Floating point exception processing method and device

Abstract

The present disclosure relates to a floating-point exception handling method and device. The floating-point exception handling method includes: if it is detected that the operand of the floating-point operation has a floating-point exception, in the process of using the operator corresponding to the operation type of the floating-point operation to perform a floating-point operation on the operand to obtain the operation result, the operand is corrected according to the number of leading zeros; if it is detected that the operand does not have a floating-point exception, the operator corresponding to the operation type of the floating-point operation is directly used to perform a floating-point operation on the operand to obtain the operation result; if the operation result overflows, the operation result is corrected. According to the floating-point exception handling method and device of the embodiment of the present application, the process of repeatedly executing the loop repair is avoided, and complex interactions between multiple modules are not required. Different processing procedures and methods are set according to whether the operand has a floating-point exception, thereby improving the flexibility of processing and thus improving the operation efficiency.

Description

Technical Field

[0001] The present disclosure relates to the field of computer technology, and in particular to a floating-point exception processing method and device. Background Art

[0002] The IEEE (Institute of Electrical and Electronics Engineering) standard for floating-point arithmetic (IEEE 754) specifies how to represent single-precision, double-precision, single-extended-precision, and double-extended-precision floating-point numbers.

[0003] IEEE 754 standard uses V = (-1) s *M*2 E The floating point number is approximately represented in the form of . And the bit representation of the floating point number is divided into three fields:

[0004] The sign s field determines whether the number is negative or positive, where s=0 indicates a positive number and s=1 indicates a negative number.

[0005] The mantissa (also called mantissa, hereinafter referred to as man) M is a binary decimal, its range is 1 to 2-ξ or 0 to 1-ξ, the mantissa segment M uses the n-bit fractional segment frac=f n-1 …f0 encoding.

[0006] The function of the exponent E is to weight the floating point number, and this weight is 2 to the power of E (which may be negative).

[0007] The IEEE 754 standard defines single-precision floating-point numbers as 32 bits long, double-precision floating-point numbers as 64 bits long, and extended double-precision floating-point numbers as 80 bits long. Bit fields can be divided into: sign field, exponent field, and mantissa field. As shown in Table 1

[0008] Table 1 Floating point number definition

[0009] Single precision S(31) exp: 8 bits (30 to 23) frac: 23 bits (22 to 0) Double precision S(63) exp: 11 digits (62 to 52) frac: 52 bits (51 to 0) Extended double precision S(79) exp: 15 digits (78 to 64) frac: 64 bits (63-0)

[0010] According to the value of the exponent field exp, the encoded value can be divided into three different cases.

[0011] Case 1: Normalized values

[0012] The most common case is when the value of the exponent field exp (exponent, abbreviated as exp) is neither all 0 nor all 1. In this case, the exponent field is interpreted as a biased representation of a signed integer. Taking single-precision floating-point numbers as an example, the exponent field exp is 8 bits and exp is an unsigned number. The range of expression is (1-254). In order to enable the exponent field exp to express signed numbers, a bias value Bias is set. For single-precision floating-point numbers, Bias = 127, E = exp-Bias, so the range of the exponent E is -126 to +127.

[0013] frac is described as a decimal value, and 0≤frac<1, and its binary representation is 0.frac. The mantissa is defined as M=1+frac, so M=1.frac. Therefore, 1≤M<2. Since the exponent E can be adjusted so that M is in the range 1≤M<2, there is no need to explicitly represent "1", which can also gain an extra bit of precision. In other words, when M is saved internally in the computer, the first bit of this number is always 1 by default (that is, the default implicit bit, hereinafter referred to as imp), so it can be discarded and only the frac part at the end is saved. When the mantissa is read, the first bit of 1 is added.

[0014] Case 2: Denormalized Values

[0015] When the value of the exponent field exp is all 0s, the number represented is denormalized. In this case, the exponent value E=1-Bias (provides a method for converting from unformatted values to formatted values). The mantissa M=frac.

[0016] Denormalized numbers have two uses:

[0017] (1) Represents the value 0. In normalized numbers, M is always ≥ 1, so it is impossible to represent 0. However, when the exponent field is all 0 and the mantissa is also all 0, the value 0 can be represented.

[0018] (2) Represents numbers close to 0.0. The values it represents are distributed close to 0.0, and this property causes the represented values to gradually overflow (underflow). Because the precision is allowed to be slowly (gradually) reduced when the result is small, the denormalized number underflows step by step.

[0019] Case 3: Special Values

[0020] There are two types:

[0021] (1) The exponent is all 1, and the decimal field is all 0. The value represented is +∞ (s=0) or -∞ (s=1). In computers, this can represent overflow results, for example, the multiplication of two very large numbers.

[0022] (2) The exponent is all 1, and the decimal field is not all 0. The value represented is NaN (Note a Number). In computers, illegal numbers can be represented, for example, when calculating the square root of -1.

[0023] For example, the binary single-precision floating-point format of the value 1.0 can be represented as 2^0*1.0, where the sign bit is 0, the exponent field is 0+127=127, and the mantissa bits are all 0. Therefore, the binary single-precision floating-point format of the value 1.0 can be represented as 0 0111 1111 000 0000 0000 0000 0000 0000 (7F00000). Summary of the Invention

[0024] In view of this, the present disclosure proposes a floating-point exception handling method and apparatus, which can correct the underflow of operation results and flexibly select the floating-point operation process for different input operands to improve operation efficiency.

[0025] In a first aspect, an embodiment of the present application provides a floating-point exception handling method for floating-point operations, the method being applied to a floating-point operation unit (FPU), the method comprising:

[0026] Detecting the operation type of the floating-point operation and whether an operand of the floating-point operation has a floating-point exception;

[0027] If a floating-point exception is detected in the operand, the number of leading zeros of the operand with the floating-point exception is determined, and in a process of performing a floating-point operation on the operand using an operator corresponding to an operation type of the floating-point operation to obtain an operation result, the operand is corrected according to the number of leading zeros;

[0028] If it is detected that the operand does not have a floating-point exception, directly using an operator corresponding to the operation type of the floating-point operation to perform a floating-point operation on the operand to obtain an operation result;

[0029] If the calculation result overflows, the calculation result is corrected.

[0030] By setting the repair of floating-point exceptions for operands within the FPU, the repeated execution of the loop repair process can be avoided, and complex interactions between multiple modules are not required, which can improve computing performance. The floating-point exception handling method according to the above embodiment of the present application can also correct the downward overflow of the operation result, and flexibly select the floating-point operation process for different input operands, thereby improving computing efficiency.

[0031] In combination with a first possible implementation manner of the first aspect, the floating-point operation is a multiplication operation, the operation result is a first multiplication result, and the first multiplication result includes a first exponent result and a first mantissa result;

[0032] In a process of performing a floating-point operation on the operand using an operator corresponding to an operation type of the floating-point operation to obtain an operation result, the operand is corrected according to the number of leading zeros, including:

[0033] A multiplier is used to calculate the first exponent result according to the exponent and the number of leading zeros of the operands of the multiplication operation, and the mantissas of the operands of the multiplication operation are multiplied to obtain the first mantissa result.

[0034] In conjunction with the first possible implementation of the first aspect, in a second possible implementation, if the operation result overflows, correcting the operation result includes:

[0035] Determining whether the first multiplication result overflows based on a relationship between the first exponent result and the minimum exponent;

[0036] If the first multiplication result overflows, calculating a first mantissa shift amount and a second exponent result according to the minimum exponent and the first exponent result;

[0037] Shifting the first mantissa result according to the first mantissa shift amount to obtain a second mantissa result;

[0038] A second multiplication result in a floating-point format is obtained by converting the second mantissa result and the second exponent result.

[0039] In conjunction with the second possible implementation manner of the first aspect, in a third possible implementation manner, calculating the first mantissa shift amount and the second exponent result according to the minimum exponent and the first exponent result includes:

[0040] Calculate a first mantissa shift amount according to the minimum exponent and the first exponent result;

[0041] A second exponent result is calculated based on the first exponent result and the first mantissa shift amount.

[0042] In conjunction with the second possible implementation manner of the first aspect, in a fourth possible implementation manner, if the operation result overflows, correcting the operation result further includes:

[0043] If the first multiplication result does not underflow, calculating a second mantissa shift amount according to the number of leading zeros of the first mantissa result and the number of leading zeros of the operand;

[0044] Shifting the first mantissa result according to the second mantissa shift amount and the number of leading zeros of the input operand to obtain a second mantissa result, and calculating a second exponent result according to the second mantissa shift amount and the first exponent result;

[0045] A second multiplication result in a floating-point format is obtained by converting the second mantissa result and the second exponent result.

[0046] The method of the embodiment of the present application reduces the number of shifts, that is, the implementation process of the calculation method according to the embodiment of the present application is more friendly to the calculation time and circuit area.

[0047] In combination with the first aspect, in a fifth possible implementation manner, the floating-point operation is a division operation, and the operation result is a first division result.

[0048] In a process of performing a floating-point operation on the operand using an operator corresponding to an operation type of the floating-point operation to obtain an operation result, the operand is corrected according to the number of leading zeros, including:

[0049] normalizing the operand according to the number of leading zeros;

[0050] A divider is used to perform a division operation on the normalized operands to obtain the first division result.

[0051] With reference to the fifth possible implementation of the first aspect, in a sixth possible implementation, the first division result includes a third exponent result and a third mantissa result;

[0052] If the operation result overflows, the operation result is corrected, including:

[0053] Determining whether the first division result overflows according to a relationship between the third exponent result and the minimum exponent;

[0054] If the first division result overflows, calculating a third mantissa shift amount based on the minimum exponent and the third exponent result, and calculating a fourth exponent result based on the third exponent result and the third mantissa shift amount;

[0055] Shifting the third mantissa result according to the third mantissa shift amount, and rounding the third mantissa result according to the rounding mode to obtain a fourth mantissa result;

[0056] A second division result in a floating-point format is obtained by converting the fourth mantissa result and the fourth exponent result.

[0057] In conjunction with the sixth possible implementation manner of the first aspect, in a seventh possible implementation manner, if the operation result overflows, correcting the operation result further includes:

[0058] If the first division result does not overflow, determining whether the third mantissa result needs to be normalized according to the number of leading zeros of the third mantissa result;

[0059] If the third mantissa result does not need to be normalized, the second division result in floating-point format is directly converted according to the third exponent result and the third mantissa result;

[0060] If the third mantissa result needs to be normalized, the third mantissa result is shifted left by one position to obtain a fourth mantissa result, the third exponent result is subtracted by 1 to obtain a fourth exponent result, and the second division result in floating-point format is obtained based on the fourth mantissa result and the fourth exponent result.

[0061] In combination with the first aspect, or any one of the first to seventh possible implementations of the first aspect, in an eighth possible implementation, the method further includes:

[0062] Before performing a floating-point operation on an operand using an operator corresponding to the operation type of the floating-point operation, the operand is bit-width expanded.

[0063] By expanding the bit width of the operands, multiple operands in the same channel can be unified into the same bit width. After the expansion, the precision of the multiple input operands is the same, and if the calculation result overflows, the wider bit width can also improve the precision of the calculation result.

[0064] In a second aspect, an embodiment of the present application provides a floating-point exception handling device, comprising: a detection module, a leading zero counter, a multiplier, and a divider.

[0065] Wherein, the detection module is connected to the leading zero counter, and the leading zero counter is connected to the multiplier and the divider respectively;

[0066] When the detection module detects that the floating-point operation is a multiplication operation or a division operation, and an operand of the floating-point operation has an exception, the leading zero counter is used to count the number of leading zeros of the operand with the floating-point exception, and the multiplier and the divider are used to correct the operand according to the number of leading zeros in the process of performing the floating-point operation to obtain an operation result;

[0067] When the detection module detects that the floating-point operation is a multiplication operation or a division operation, and there is no abnormality in the operands of the floating-point operation, the multiplier and the divider are used to directly perform the floating-point operation on the operands to obtain the operation results;

[0068] If the operation result overflows, the multiplier and the divider are further configured to correct the operation result.

[0069] By setting the repair of floating-point exceptions for operands within the FPU, the repeated execution of the loop repair process can be avoided, and complex interactions between multiple modules are not required, which can improve computing performance. The floating-point exception handling device according to the above embodiment of the present application can also correct the downward overflow of the operation result and flexibly select the floating-point operation process for different input operands, thereby improving computing efficiency.

[0070] In combination with a first possible implementation manner of the second aspect, the floating-point operation is a multiplication operation, the operation result is a first multiplication result, and the first multiplication result includes a first exponent result and a first mantissa result;

[0071] The multiplier includes a multiplication unit, which is used to calculate the first exponent result according to the exponent and the number of leading zeros of the operands, and multiply the mantissas of the operands of the multiplication operation to obtain the first mantissa result.

[0072] In combination with the first possible implementation manner of the second aspect, in a second possible implementation manner, when the detection module detects that an operand of the floating-point operation has a floating-point exception, the multiplication unit obtains the number of leading zeros of the operand from the leading zero counter;

[0073] When the detection module detects that the operands of the floating-point operation do not have a floating-point exception, the multiplication unit sets the number of leading zeros to 0.

[0074] In combination with the first possible implementation manner of the second aspect, in a third possible implementation manner, the multiplier further includes a first underflow correction unit;

[0075] The first underflow correction unit is configured to correct the first multiplication result when it is determined based on the first exponent result that the first multiplication result has overflowed.

[0076] With reference to the third possible implementation manner of the second aspect, in a fourth possible implementation manner, the first underflow correction unit is configured to determine whether the first multiplication result has overflowed according to a relationship between the first exponent result and the minimum exponent;

[0077] If the first multiplication result overflows, the first underflow correction unit calculates a first mantissa shift amount and a second exponent result based on the minimum exponent and the first exponent result, shifts the first mantissa result according to the first mantissa shift amount, and rounds the first mantissa result according to the rounding mode to obtain a second mantissa result.

[0078] In combination with the fourth possible implementation method of the second aspect, in a fifth possible implementation method, the first underflow correction unit is used to calculate the first mantissa shift number based on the minimum exponent and the first exponent result if the first multiplication result overflows, and calculate the second exponent result based on the first exponent result and the first mantissa shift number.

[0079] In combination with the fourth possible implementation manner of the second aspect, in a sixth possible implementation manner, the first underflow correction unit is further configured to, if the first multiplication result does not underflow, calculate a second mantissa shift amount based on the number of leading zeros of the first mantissa result and the number of leading zeros of the operand;

[0080] The first mantissa result is shifted according to the second mantissa shift amount and the number of leading zeros of the input operand to obtain a second mantissa result, and a second exponent result is calculated according to the second mantissa shift amount and the first exponent result.

[0081] In combination with the fourth or sixth possible implementation manner of the second aspect, in a seventh possible implementation manner, the multiplier further includes a first format conversion unit,

[0082] The first format conversion unit is configured to convert the second mantissa result and the second exponent result to obtain a second multiplication result in a floating point format.

[0083] In conjunction with an eighth possible implementation manner of the second aspect, the floating-point operation is a division operation, and the operation result is a first division result.

[0084] The divider includes a normalization unit, a division unit and a second underflow correction unit;

[0085] The normalization unit is configured to normalize the abnormal operand according to the number of leading zeros of the operand when the detection module detects that the operand of the division operation is abnormal;

[0086] The division unit is configured to perform a division operation according to the normalized operand to obtain a first division result;

[0087] The second underflow correction unit is configured to correct the first division result when it is detected that the first division result underflows.

[0088] With reference to the eighth possible implementation of the second aspect, in a ninth possible implementation, the first division result includes a third exponent result and a third mantissa result;

[0089] The second underflow correction unit is used to determine whether the first division result has underflowed according to the relationship between the third exponent result and the minimum exponent;

[0090] If the first division result overflows, calculating a third mantissa shift amount based on the minimum exponent and the third exponent result, and calculating a fourth exponent result based on the third exponent result and the third mantissa shift amount;

[0091] The third mantissa result is shifted according to the third mantissa shift amount, and the third mantissa result is rounded according to the rounding mode to obtain a fourth mantissa result.

[0092] In conjunction with the ninth possible implementation manner of the second aspect, in a tenth possible implementation manner, the second underflow correction unit is further configured to, when the first division result does not underflow, determine, based on the number of leading zeros in the third mantissa result, whether normalization processing needs to be performed on the third mantissa result;

[0093] If the third mantissa result needs to be normalized, the third mantissa result is shifted left by one position to obtain the fourth mantissa result, and the third exponent result is subtracted by 1 to obtain the fourth exponent result.

[0094] In combination with the eighth possible implementation method of the second aspect, in an eleventh possible implementation method, the division unit is also used to directly perform a division operation on the operands of the division operation to obtain a first division result when the detection module detects that there is no floating-point exception in the operands of the division operation.

[0095] In combination with the ninth or tenth possible implementation manner of the second aspect, in a twelfth possible implementation manner, the divider further includes a second format conversion unit,

[0096] The second format conversion unit is configured to convert the fourth mantissa result and the fourth exponent result to obtain a second division result in a floating-point format;

[0097] Alternatively, if the second underflow correction unit determines that the third mantissa result does not need to be normalized, the second format conversion unit is configured to directly convert the third exponent result and the third mantissa result to obtain a second division result in a floating point format.

[0098] In a thirteenth possible implementation manner of the second aspect, both the multiplier and the divider include a bit width extension unit, and the bit width extension unit is used to extend the bit width of the operand before performing a floating-point operation on the operand.

[0099] In a third aspect, an embodiment of the present application provides a processing system, including:

[0100] processor;

[0101] A memory, used to store floating-point operation instructions executable by the processor and operands corresponding to the floating-point operation instructions;

[0102] The processor is configured to implement the first aspect and any possible implementation manner of the first aspect when executing the floating-point operation instruction to process the operand.

[0103] Further features and aspects of the present disclosure will become apparent from the following detailed description of exemplary embodiments with reference to the attached drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0104] The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate exemplary embodiments, features, and aspects of the disclosure and, together with the description, serve to explain the principles of the disclosure.

[0105] Figure 1 The following illustrates an application scenario of a floating-point exception handling method in related art.

[0106] Figure 2 A block diagram of a floating-point exception handling device according to an embodiment of the present application is shown.

[0107] Figure 3 A block diagram of a floating-point exception handling device according to another embodiment of the present application is shown.

[0108] Figure 4 A flowchart of a floating-point exception handling method according to an embodiment of the present application is shown.

[0109] Figure 5a A schematic diagram illustrating bit width expansion of an exponent field according to an embodiment of the present application is shown.

[0110] Figure 5b A schematic diagram illustrating the expansion of the mantissa segment width according to an embodiment of the present application is shown.

[0111] Figure 6 A flowchart of a multiplication operation according to an embodiment of the present application is shown.

[0112] Figure 7 A flowchart of a multiplication operation according to an embodiment of the present application is shown.

[0113] Figure 8 FIG. 4 shows a block diagram of a multiplier according to an embodiment of the present application.

[0114] Figure 9 A schematic diagram illustrating an exponential adder and a unit for exponent underflow prediction according to an embodiment of the present application is shown.

[0115] Figure 10 A flowchart of a division operation according to an embodiment of the present application is shown.

[0116] Figure 11 A flowchart of a division operation according to an embodiment of the present application is shown.

[0117] Figure 12 FIG. 4 shows a block diagram of a divider according to an embodiment of the present application.

[0118] Figure 13 A schematic diagram illustrating an exponential adder and a unit for exponent underflow prediction according to an embodiment of the present application is shown.

[0119] Figure 14 FIG. 1 is a schematic diagram of a processing system 200 according to an embodiment of the present application. DETAILED DESCRIPTION

[0120] Various exemplary embodiments, features, and aspects of the present disclosure will be described in detail below with reference to the accompanying drawings. The same reference numerals in the accompanying drawings represent elements with the same or similar functions. Although various aspects of the embodiments are shown in the accompanying drawings, the drawings are not necessarily drawn to scale unless otherwise indicated.

[0121] The word “exemplary” is used exclusively herein to mean “serving as an example, example, or illustration.” Any embodiment described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other embodiments.

[0122] In addition, numerous specific details are provided in the following detailed description to better illustrate the present disclosure. Those skilled in the art will appreciate that the present disclosure can be practiced without certain specific details. In some instances, methods, means, components, and circuits well known to those skilled in the art are not described in detail in order to highlight the main points of the present disclosure.

[0123] When a processor executes instructions that use or generate denormalized numbers, an exception is triggered, requiring processing to a software module or other hardware. This exception is typically handled by representing the data in a wider format, which has sufficient precision to represent the denormalized number as a smaller normalized number. This method requires converting data between different formats, which can slow down the calculation.

[0124] The processor may also have instructions for performing single instruction multiple data (SIMD) operations on floating-point numbers. When the processor executes SIMD instructions, if the SIMD instructions use or generate non-normalized numbers, exceptions will be triggered multiple times, and the exceptions need to be processed in multiple cycles, resulting in poor computing performance. Multiple triggering of exceptions will also lead to complex interactions and non-scalability.

[0125] In order to more clearly illustrate the solution of this application, the application scenario and the technical problems to be solved are first described in detail. Figure 1 The following shows the application scenario of the floating point exception handling method in the related art. Figure 1As shown, the reservation station (RS) is provided with an MFX (Media Fixup) module, which is used to correct exceptions caused by denormalized numbers and result underflow, wherein result underflow may refer to the result of an instruction operation overflowing downward, which is the underflow mentioned above. In other words, there are mainly two types of data that need to be corrected: one is the exception caused by denormalized numbers, and the exception is masked; the other is the exception caused by result underflow, and the exception is masked. Among them, the masked exception may mean that the operand or result will not be triggered to process the exception, and internal processing is required. Internal processing may refer to handling the exception in the reservation station.

[0126] The reservation station stores instructions to be distributed, and is responsible for distributing the instructions to be distributed to the execution units. For example, in an embodiment of the present application, the reservation station can distribute floating-point operation instructions to the floating-point operation execution unit (FPU).

[0127] Figure 1 The floating-point execution unit is also used to detect floating-point exceptions. If no floating-point exception is detected in the instruction's operands or calculation results, the floating-point execution unit can set the instruction's complete status to 1 after executing the instruction and send the instruction to the re-order buffer (ROB). If the floating-point execution unit detects a floating-point exception in the instruction's operands or calculation results, the floating-point execution unit can set the instruction's complete status to 0 and send the instruction to the ROB. The floating-point execution unit can also return exception information about the detected floating-point exception to the reservation station, so that the reservation station can correct the floating-point exception based on the exception information.

[0128] The ROB stores information about instructions that need to be reordered and processes the instructions based on the information. In one possible implementation, the ROB stores instruction information in the form of table entries. Each ROB entry may include: 1) complete: indicates whether an instruction has been executed; 2) Areg: the destination register specified by the instruction in the original program, given in the form of a logical register; 3) Preg: the number of the physical register corresponding to the instruction's Areg after register renaming; 4) OPreg: the old Preg corresponding to the instruction's Areg before it is renamed to the new Preg. This value is used when the instruction encounters an exception and the state is restored; 5) PC: the PC value corresponding to this instruction. When an instruction encounters an interrupt or exception, the PC value of this instruction needs to be saved so that the program can be re-executed; 6) Exception: If an instruction encounters an exception, the type of the exception will be written here. When the instruction is to retire, the exception will be handled; 7) Type: the type of instruction will be recorded here. When the instruction retires, different types of instructions will have different actions. Therefore, the ROB can process the instruction accordingly based on the information of the instruction. For example, if the instruction has an exception and needs to be re-executed, the ROB can send the instruction (with the information of re-executing the instruction) back to the reservation station. If the instruction has been processed, it can be retired and sent to the next level.

[0129] exist Figure 1 In the application scenario shown, for SIMD instructions, since the number of floating-point exceptions that can be processed at one time by the reservation station (RS) is limited, if multiple operands of the SIMD instruction have exceptions, then it is necessary to Figure 1 The three units (RS, FPU, and ROB) shown in the figure need to execute multiple cycles to correct all exceptions, resulting in poor computing performance. Multiple triggering of exceptions also leads to complex interactions and non-scalability.

[0130] For example, assume a SIMD instruction has two operands, Source1 and Source2. Source1 and Source2 are packed single-precision floating-point numbers, and each Source contains four channels, each of which is a 32-bit single-precision floating-point number. When handling floating-point exceptions, the reservation station handles the floating-point exceptions of the operands one by one according to the following priority: Source1 > Source2, SP0 > SP1 > SP2 > SP3.

[0131] If all four channels of operand Source 1 are denormalized, the floating-point exception handling process may include:

[0132] Step 1: RS distributes SIMD instructions to FPU;

[0133] Step 2: The FPU performs a floating-point exception check and detects that all four channels of operand Source1 are denormalized numbers, indicating a floating-point exception. This triggers the instruction re-execution process, sends the SIMD instruction to the ROB, and returns the exception information to the RS.

[0134] Step 3: ROB returns the information of re-executing SIMD instructions to RS;

[0135] Step 4: RS modifies channel SP0 of operand Source1 based on the exception information and the information of re-executing the SIMD instruction. Then it returns to step 1 and distributes the instruction to the FPU.

[0136] The above process is repeated until all floating-point exceptions of the SIMD instruction operands are corrected and the execution of the SIMD instruction is completed. Then, the ROB can be retired and sent to the next level.

[0137] Therefore, if a floating-point exception occurs in all four channels of an operand, the instruction must be re-executed four times. If an instruction has three operands, and all four channels of each operand have floating-point exceptions, the FPU will trigger 12 re-executions. As the number of operands increases and the precision scales, the complexity of the operation increases exponentially, resulting in poor performance. Multiple exception triggering also leads to complex interactions and non-scalability.

[0138] Although there are adders, multipliers or dividers in the related art that support floating-point operations of non-normalized numbers, the existing above-mentioned operators are unable to correct the underflow of the operation results, and the processing flexibility is insufficient and the efficiency is low for different input operands.

[0139] In order to solve the above technical problems, the present application provides a floating-point exception handling device. Figure 2 A block diagram of a floating point exception handling device 2 according to an embodiment of the present application is shown. Figure 2 As shown, the floating point exception handling device of the present application can be located in a floating point unit FPU (Float Point Unit), which is used to detect floating point exceptions of operands and / or operation results of operation instructions (floating point operations) and correct floating point exceptions during the execution of floating point operations. For the sake of clarity, Figure 2 The example omits other components that may be included in the FPU, that is, Figure 2 This is only an example of the present application and does not limit the present application in any way.

[0140] In an embodiment of the present application, the floating-point exception handling device 2 may include: a detection module 20 , a leading zero counter 21 , a multiplier 22 , and a divider 23 .

[0141] exist Figure 2 In the example shown, the detection module 20 can be connected to the leading zero counter 21, the multiplier 22 and the divider 23, and the leading zero counter 21 is also connected to the multiplier 22 and the divider 23. It should be noted that, Figure 2 The connection method of the components shown is only an example of the present application and the present application is not limited thereto.

[0142] Figure 3 FIG. 2 shows a block diagram of a floating point exception handling device 2 according to another embodiment of the present application. Figure 3 As shown, the detection module 20 may be connected to a multiplexing circuit 24 and a leading zero counter 21 , and the multiplexing circuit is connected to a multiplier 22 and a divider 23 respectively.

[0143] The detection module 20 is used to detect the operation type of the floating-point operation and whether the operand of the floating-point operation has a floating-point exception.

[0144] In one possible implementation, the detection module 20 can be connected to the RS and receive an operation instruction sent by the RS. The operation instruction can include information about the operation type. Therefore, the operation type of the floating-point operation can be identified based on the operation instruction. In the embodiment of the present application, the operation type of the floating-point operation can include addition (subtraction), multiplication, and division (root-finding operation), but addition and subtraction are not the focus of discussion in this application. The embodiment of the present application is mainly for multiplication, division, and root-finding operations.

[0145] A floating-point exception in an input operand may mean that the input operand is a denormalized number. Since normalized numbers and denormalized numbers can be distinguished based on the value of the exponent field, the detection module 20 can detect whether the operand has a floating-point exception based on the exponent field of the operand. If the detection module 20 detects that the value of the exponent field of the floating-point operation operand is all 0, then the operand can be determined to be a denormalized number and a floating-point exception exists in the operand. If the detection module 20 detects that the value of the exponent field of the floating-point operation operand is not all 0 or 1, then the operand of the floating-point operation can be determined to be a normalized number.

[0146] If the floating-point operation is identified as an addition operation or a subtraction operation, the detection module 20 may send the operation instruction to the adder. That is, the floating-point exception handling device 2 of the embodiment of the present application may also include an adder ( Figure 2(not shown in the figure). In the embodiments of the present application, the adder can be any type of adder in the related art that supports floating-point operations on denormalized numbers, and this application is not limited thereto. For example, an adder with an NR (Near-Remote) path structure can be used, and the N path or R path can be selected for addition or subtraction based on the difference in the exponent bits of the operands and the significant bits of the mantissa.

[0147] When the detection module 20 detects that the floating-point operation is a multiplication or division operation (root operation) and the operand of the floating-point operation has a floating-point exception, the leading zero counter 21 is used to count the number of leading zeros of the operand with the floating-point exception.

[0148] When the detection module 20 detects that there is no floating point exception in the floating point operation operand, the operation instruction corresponding to the floating point operation can be directly output to the operator corresponding to the floating point operation, which can be the multiplier 22 or the divider 23 as described above. Figure 2 As shown, if the detection module 20 detects that the floating-point operation is a multiplication operation, the corresponding operation instruction can be output to the multiplier 22. If the detection module 20 detects that the floating-point operation is a division operation or a root operation, the corresponding operation instruction can be output to the divider 23. Or as shown in FIG. Figure 3 As shown, if the detection module 20 detects that there is no floating-point exception in the operand, the operation instruction corresponding to the floating-point operation can be sent to the multiplexing circuit 24, and then sent to the corresponding operator through the multiplexing circuit 24. The multiplexing circuit 24 can design a corresponding circuit connection method based on the above-mentioned logic, and the present application does not limit the specific circuit connection of the multiplexing circuit 24.

[0149] In an embodiment of the present application, the multiplier 22 and the divider 23 may be provided with a module for correcting floating-point exceptions of operands and operation results.

[0150] According to the floating-point exception handling device of the embodiment of the present application, by setting the repair of the floating-point exception of the operand inside the FPU, it is possible to avoid the repeated execution of the loop repair process and do not require complex interactions between multiple modules, which can improve computing performance. According to the floating-point exception handling device of the above embodiment of the present application, it can also correct the downward overflow of the operation result and flexibly select the floating-point operation process for different input operands, thereby improving computing efficiency.

[0151] The present application also provides a floating point exception handling method for floating point operations, which is applied to FPU, Figure 4 FIG. 1 is a flow chart showing a method for handling floating point exceptions according to an embodiment of the present application. Figure 4 As shown, the floating-point exception handling method may include:

[0152] Step S40, detecting the operation type of the floating-point operation and whether the operand of the floating-point operation has a floating-point exception;

[0153] Step S41, if it is detected that a floating-point exception exists in an operand of a floating-point operation, the number of leading zeros of the operand with the floating-point exception is determined, and in the process of performing a floating-point operation on the operand using an operator corresponding to the operation type of the floating-point operation to obtain an operation result, the operand is corrected according to the number of leading zeros; if the operation result overflows, the operation result is corrected;

[0154] Step S42: If it is detected that there is no floating-point exception in the floating-point operation operand, a floating-point operation is performed using an operator corresponding to the operation type of the floating-point operation to obtain an operation result. If the operation result overflows, the operation result is corrected.

[0155] The above step S40 can be executed by the detection module 20, which can improve the operation efficiency by detecting the operation type of the floating-point operation and whether the operand has a floating-point exception, and diverting the processing according to the detection results. The floating-point operation process can be flexibly selected for different input operands.

[0156] In one possible implementation, if it is detected that any one or more operands of the floating-point operation have a floating-point exception, then the floating-point operation operand has a floating-point exception. If it is detected that all operands of the floating-point operation are normalized numbers and none of them have a floating-point exception, then the floating-point operation operand does not have a floating-point exception.

[0157] The operator corresponding to the operation type of the floating-point operation may include a multiplier 22 and a divider 23. In the embodiment of the present application, the addition operation and subtraction operation performed by the adder are not within the scope of discussion. Therefore, the above-mentioned operation type may include multiplication operation and division operation (root-finding operation). If the operation type of the floating-point operation detected by the detection module 20 is multiplication operation, the multiplier can be used to perform the floating-point operation. If the detection module 20 detects that the operation type of the floating-point operation is division operation (root-finding operation), the divider 23 can be used to perform the floating-point operation. In the process of performing the floating-point operation, if the operand of the floating-point operation has a floating-point exception, the operator can correct the floating-point exception of the operand. If the result of the floating-point operation overflows, the operator can correct the result.

[0158] In one possible implementation, before performing a floating-point operation using an operator corresponding to the operation type of the floating-point operation, the operand may be bit-width expanded to obtain an operand with an expanded bit width, and the floating-point operation may be performed based on the operand with the expanded bit width. Bit-width expansion may refer to widening the number of bits representing a floating-point number. By performing bit-width expansion on the exponent and mantissa, multiple operands in the same channel may be unified into the same bit width. The precision of the multiple operands input after expansion is the same, and if an operation result overflows, a wider bit width can also improve the precision of the operation result.

[0159] It should be noted that if multiple channels are included, the FPU can expand the bit width of the operands input to all or part of the channels. After the bit width expansion, the number of bits of the input operands of each channel can be the same or different, and this application does not limit this.

[0160] This application provides a method for expanding the bit width, expanding the operands of floating-point operations to EP (Extend Double Precision) format, that is, expanding the operands to 80 bits. Of course, it can also be expanded to other precisions, such as double-precision format, according to the needs of actual application scenarios, and this application does not limit this. The following uses the floating-point number expanded to EP format as an example to illustrate the bit width expansion method of this application.

[0161] Because the exponent represented by IEEE 754 is biased, when expanding the exponent field, the bias value in the original format must be removed and the bias value in the expanded new format must be added.

[0162] For the exponent field of a normalized number, the value of the exponent field after bit width expansion can be calculated according to the value of the exponent field before bit width expansion using the following formula (1):

[0163] exp dest =exp sour -Bias sour +Bias dest ; (1)

[0164] Among them, exp sour It can represent the value of the exponent field of the floating point number before bit width expansion, Bias sour It can represent the bias value of the floating point format before bit width expansion. dest It can represent the offset value of the floating point format after bit width expansion, exp dest It can represent the value of the exponent field of the floating point number after bit width expansion. sour and Bias destThe specific value of is related to the format of the floating point number. For example, for SP (Single Precision) floating point numbers, Bias is (2 7 -1)=127, for DP (Double Precision) floating point numbers, Bias is (2 10 -1)=1023. For EP format, when actually executing the instruction (in the implementation process), the exponent bit is 17 bits, so the Bias is (2 16 -1).

[0165] Table 2 shows an example of extending the exponent field bit width of a normalized number according to some embodiments of the present application, where 8'h7F is taken as an example, where 8' represents a total of 8 bits, h represents hexadecimal (b represents binary), and 7F is its numerical value.

[0166] Table 2

[0167]

[0168]

[0169] Figure 5a FIG. 1 is a schematic diagram showing a method for extending the bit width of an exponent field according to an embodiment of the present application. Figure 5a As shown, if the input operand is in EP format, the value of the exponent field of the operand can be subtracted by 2. 14 -1, then add 2 16 -1, you can get the value of the exponent field after the bit width is expanded.

[0170] For normalized numbers, you can simply add zeros to the original mantissa according to the number of digits you need to increase. For example, for an SP floating-point number, if you want to expand it to EP, then add 41 zeros to the original mantissa; for a DP floating-point number, if you want to expand it to EP, then add 12 zeros to the original mantissa.

[0171] For denormalized numbers, the value of the exponent field after bit width expansion can be calculated using the following formula (2) based on the value of the exponent field before bit width expansion:

[0172] exp dest =-Bias sour +Bias dest -LZC sour ; (2)

[0173] Among them, LZC sour It can represent the number of leading zeros of the denormalized floating-point number before bit width expansion. Since the value of the exponent field of the denormalized number is 0, the value of the exponent field after bit width expansion can be calculated by expression (2).

[0174] Table 3 shows an example of the exponent field width extension of a denormalized number according to some embodiments of the present application.

[0175] Table 3

[0176] Accuracy sign exp man exp_extend[16:0] SP[31:0] sp

[31] 8'h0 sp[22:0] 17'hFFFF-8'h7F-LZC_sp DP[63:0] dp

[63] 11'h0 dp[51:0] 17'hFFFF-11'h3FF-LZC_dp EP[79:0] ep

[79] 15'h0 ep[62:0] 17'hFFFF-15'h3FFF-LZC_ep

[0177] For the mantissa field of a non-normalized number, you can also directly add 0 after the original mantissa according to the number of digits that need to be increased.

[0178] Figure 5b FIG. 1 is a schematic diagram showing the expansion of the mantissa segment width according to an embodiment of the present application. Figure 5b As shown in the figure, for an SP floating-point number (SP0), if it is to be expanded to an EP, 41 zeros are added after the original mantissa segment (0:22, a total of 23 bits); for a DP floating-point number (DP0), if it is to be expanded to an EP, 12 zeros are added after the original mantissa segment (0:51, a total of 52 bits); for an EP floating-point number, bit width expansion is not required.

[0179] It should be noted that the above method of bit width expansion is merely an example of the present application and does not limit the present application in any way.

[0180] According to the floating-point exception handling device of the embodiment of the present application, by setting the repair of the floating-point exception of the operand within the FPU, it is possible to avoid the repeated execution of the loop repair process and eliminate the need for complex interaction between multiple modules, thereby improving computing performance. In addition, different processing procedures and methods are set according to whether the operand has a floating-point exception, which can increase the flexibility of the processing and thus improve computing efficiency. The following describes the structure of the multiplier 22 and the divider 23 and the process of performing floating-point operations.

[0181] Multiplier, multiplication operation

[0182] The multiplier 22 is used to perform a multiplication operation. In one possible implementation, Figure 2 or Figure 3 As shown, the multiplier 22 may include a multiplication unit 221 and a first underflow correction unit 222, wherein the multiplication unit 221 is used to perform a multiplication operation to obtain a first multiplication result, and the first underflow correction unit 222 is used to correct the first multiplication result when it is detected that the first multiplication result overflows.

[0183] In one possible implementation, the first multiplication result may include a first exponent result and a first mantissa result. The first underflow correction unit 222 is used to determine whether the first multiplication result overflows based on the first exponent result and the minimum exponent. If the first exponent result is less than the minimum exponent, the first multiplication result overflows; if the first exponent result is not less than the minimum exponent, the first multiplication result does not overflow.

[0184] In one possible implementation, the multiplier 22 may calculate a first exponent result based on an exponent corresponding to the value of the exponent field of the operand, the number of leading zeros, and a bias value corresponding to the operation result. The exponent corresponding to the value of the exponent field of the operand may be a value obtained by subtracting a corresponding bias value from the value of the exponent field of the operand, also referred to as the exponent of the operand; and the bias value corresponding to the operation result may be a preset bias value in a floating-point format corresponding to the operation result. The first exponent result may be obtained by summing the exponents of the operands, subtracting the number of leading zeros of the operands, and then adding the bias value corresponding to the (input) operation result.

[0185] In another possible implementation, the multiplier 22 may also calculate the first exponential result based on the exponents and the number of leading zeros of the operands. For example, the first exponential result may be obtained by summing the exponents of the operands and subtracting the number of leading zeros of the operands.

[0186] The two methods for calculating the first exponent can use different minimum exponents to determine whether underflow occurs. For example, in the first implementation, the minimum exponent can be the smallest number representable by the value of the exponent field, which can be 0. In the second implementation, the minimum exponent can be the minimum value of the exponent in the corresponding format of the floating-point number. For example, for SP, the minimum exponent can be -127.

[0187] In one possible implementation, the multiplier 22 may multiply the mantissa bits of the operands to obtain a first mantissa result.

[0188] In one possible implementation, when there is a floating-point exception in the operands of the multiplication operation, if the first underflow correction unit 222 detects that the first multiplication result has overflowed, the first underflow correction unit 222 can correct the first multiplication result according to the minimum exponent; when there is no floating-point exception in the operands of the multiplication operation, the first multiplication result will not overflow, and the first mantissa result of the first multiplication result may have a carry. In this case, the first exponent result can be adjusted according to the carry bit of the first mantissa result.

[0189] The process of correcting the first multiplication result by the first underflow correction unit 222 will be described below in different cases.

[0190] (1) There is a floating-point exception in the operand of the multiplication operation

[0191] Figure 6 FIG. 1 shows a flow chart of a multiplication operation according to an embodiment of the present application. Figure 6 As shown, in this case, before performing the multiplication operation, step S60 is first performed, and the leading zero counter 21 counts the number of leading zeros of the operand with the floating point exception.

[0192] Assume that a multiplication operation includes two operands, namely operand A and operand B. The presence of a floating point exception in the operands of the multiplication operation may refer to the presence of a floating point exception in either or both operands. For operands with floating point exceptions, the leading zero counter 21 counts the number of leading zeros in the operands. For example, if operand A has a floating point exception, the leading zero counter 21 can count the number of leading zeros in operand A to obtain LZC A If there is a floating point exception in operand B, the leading zero counter 21 can calculate the number of leading zeros in operand B to obtain LZC B .

[0193] In step S61, the FPU may perform bit-width expansion on the operands of the multiplication operation to obtain expanded operands. The FPU may perform bit-width expansion on operands A and B, respectively, in the manner described above to obtain operands A' and B'. The specific manner of bit-width expansion can be found in the description above. For operands without floating-point exceptions, the bit-width expansion is implemented using a method corresponding to normalized numbers. For operands with floating-point exceptions, the bit-width expansion is implemented using a method corresponding to denormalized numbers. This description will not be repeated here.

[0194] In step S62, the multiplication unit 221 performs a multiplication operation on the expanded operand to obtain a first multiplication result. The first multiplication result may include a first exponent result and a first mantissa result. The multiplication unit 221 performs a multiplication operation on the operand A' and the operand B' to obtain a first multiplication result. The specific process of performing the multiplication operation may include: the first exponent result can be calculated based on the value of the exponent field of the expanded operand, the offset value corresponding to the expanded operand, the number of leading zeros, and the offset value corresponding to the input operand. Among them, the offset value corresponding to the input operand may refer to the offset value corresponding to the format of the input operand, that is, the offset value corresponding to the format of the operand that has not been bit-width expanded. The product of the mantissa A of operand A' and the mantissa B of operand B' is obtained to obtain the first mantissa result.

[0195] For example, the first index result = E A –LZC A +E B –LZC B +Biassour , where, during the calculation process, E A E is obtained by subtracting the corresponding bias value from ExpA. A Bias is obtained by subtracting the corresponding bias value from ExpB. sour Indicates the offset value corresponding to the format of the input operand.

[0196] In step S63 , the first underflow correction unit 222 determines whether the first exponent result is less than the minimum exponent.

[0197] If the first exponent result is less than the minimum exponent, the first underflow correction unit 222 may determine that the first multiplication result has underflowed. In other words, if the result of adding the exponent bits of the multiplication operands is less than 0, the first multiplication result has underflowed. If the first multiplication result has underflowed, step S64 may be executed, where the first underflow correction unit 222 calculates a first mantissa shift amount and a second exponent result based on the minimum exponent and the first exponent result.

[0198] For example, when the first multiplication result overflows, the first underflow correction unit 222 can add 1 to the difference between the minimum exponent and the first exponent result as the first mantissa shift number, and calculate the second exponent result based on the first mantissa shift number and the first exponent result. The second exponent result can be the sum of the first exponent result and the first mantissa shift number.

[0199] In a possible implementation, the first underflow correction unit 222 may calculate the first mantissa shift amount according to the following formula (3):

[0200] S underflow1 =MINExp-Exp1+1; (3)

[0201] Among them, S underflow1 Indicates the number of mantissa shifts when the first multiplication result overflows, MINExp indicates the minimum exponent, and Exp1 indicates the first exponent result.

[0202] In step S66 , the first underflow correction unit 222 shifts the first mantissa result according to the first mantissa shift amount and rounds the first mantissa result according to the rounding mode to obtain a second mantissa result.

[0203] Because the operands of the multiplication operation contain floating-point exceptions, the calculated first mantissa result may be a denormalized number including leading zeros. If the first multiplication result underflows, the calculated first mantissa shift amount is used to right-shift the first mantissa result. In this case, the first mantissa result may be rounded according to the rounding mode during the right shift to obtain a second mantissa result.

[0204] In one possible implementation, before step S66, the method may further include: determining an actual mantissa shift number based on a relationship between the first mantissa shift number and the number of bits in the mantissa field. The number of bits in the mantissa field may refer to the number of bits in the mantissa field in the format of the floating-point number after bit width extension. For example, the number of bits in the mantissa field of the EP floating-point number is 64, the DP is 52, and the SP is 23.

[0205] Specifically, if the first mantissa shift amount is less than the number of bits in the mantissa field, the actual mantissa shift amount is the first mantissa shift amount; if the first mantissa shift amount is greater than the number of bits in the mantissa field, the number of bits in the mantissa field is the actual mantissa shift amount.

[0206] The number of bits of the first mantissa result shifted to the right cannot exceed the number of bits of the mantissa field. Therefore, after determining the actual mantissa shift number according to the above method, step S66 can be executed. The first underflow correction unit 222 shifts the first mantissa result according to the actual mantissa shift number and rounds the first mantissa result according to the rounding mode to obtain the second mantissa result.

[0207] Compared with the theoretical approach, the method of the embodiment of the present application reduces the number of shifts. That is, the implementation process of the calculation method according to the embodiment of the present application is more friendly to the calculation time and circuit area.

[0208] If the first exponent result is not less than the minimum exponent, the first underflow correction unit 222 may determine that the first multiplication result has not underflowed. In other words, if the result of adding the exponent bits of the multiplication operands is not less than 0, the first multiplication result has not underflowed. If the first multiplication result has not underflowed, step S65 may be executed, and the first underflow correction unit 222 may calculate a second mantissa shift amount based on the number of leading zeros in the first mantissa result and the number of leading zeros in the operands.

[0209] In a possible implementation, when the first multiplication result does not underflow, the first underflow correction unit 222 may calculate a first difference between the number of leading zeros of the input operand and the number of leading zeros of the first mantissa result.

[0210] If the first difference is greater than 0, the first underflow correction unit 222 may determine the first difference as the second mantissa shift amount; if the first difference is equal to 0, the first underflow correction unit 222 does not need to calculate the second mantissa shift amount, or the second mantissa shift amount is 0.

[0211] If the first difference is greater than 0, the first underflow correction unit 222 may execute step S67, shift the first mantissa result according to the second mantissa shift amount and the number of leading zeros of the input operand to obtain a second mantissa result, and calculate a second exponent result according to the second mantissa shift amount and the first exponent result.

[0212] Specifically, the first underflow correction unit 222 may shift the first mantissa result to the left by the difference between the number of leading zeros of the input operand and the second mantissa shift number. The first exponent result is added to the second mantissa shift number to obtain the second exponent result. In another possible implementation, the second mantissa shift number may be calculated based on ExpA+ExpB-LZC. A -LZC B calculate.

[0213] If the first multiplication result does not overflow, the calculated second mantissa shift amount is used to left-shift the first mantissa result. If a carry occurs from the left side of the second mantissa result during the left shift, causing the most significant bit to be greater than 1, the left-shift process of the first mantissa result is stopped to obtain the second mantissa result, and the second exponent result is re-determined based on the carry bit.

[0214] It should be noted that, since the number of bits of the calculated first mantissa result is greater than the number of bits of the mantissa of the operand, the first mantissa result can be rounded after the left shift to obtain the second mantissa result.

[0215] After calculating and obtaining the second exponent result and the second mantissa result, the multiplier 22 may execute step S68 , where the first underflow correction unit 222 converts the second mantissa result and the second exponent result into a second multiplication result in a floating-point format.

[0216] (2) There are no floating-point exceptions for the operands of the multiplication operation

[0217] Figure 7 FIG. 1 shows a flow chart of a multiplication operation according to an embodiment of the present application. Figure 7 As shown, in this case, there is no need to calculate the number of leading zeros of the operand, thereby reducing delays and improving computational efficiency.

[0218] In step S71, the FPU may perform bit width expansion on the operands of the multiplication operation to obtain expanded operands. The specific process can be found in step S61 above and the implementation method of the bit width expansion of the normalized number, which will not be repeated here.

[0219] In step S72, the multiplication unit 221 performs a multiplication operation on the expanded operands to obtain the first multiplication result. The specific process can be found in the description of step S62. The number of leading zeros in the operands is always 0.

[0220] Since there is no floating-point exception in the operands of the floating-point operation, the first exponent result of the calculated first multiplication result is definitely greater than the minimum exponent, and the first multiplication result will not overflow. If the first multiplication result does not overflow, the first underflow correction unit 222 does not need to calculate the number of mantissa shifts, because in the case where there is no floating-point exception in the operands of the multiplication operation, the first mantissa result of the first multiplication result is definitely greater than 1, and there is no need to perform a left shift operation on the first mantissa result to normalize it. The multiplier can then execute step S73 to determine whether the first mantissa result is less than 2. If the first mantissa result is greater than 1 and less than 2, the multiplier can execute step S74 to directly convert the first exponent result and the first mantissa result into a second multiplication result in floating-point format.

[0221] However, the first mantissa result may be greater than or equal to 2, that is, a carry operation is required. In this case, in order to normalize the first multiplication result, a right shift operation needs to be performed on the first mantissa result.

[0222] Step S75, the normalization unit of the multiplier may shift the first mantissa result according to the carry bit of the first mantissa result, and round the first mantissa result according to the rounding mode to obtain a second mantissa result;

[0223] In step S76 , the multiplier may further calculate a second exponent result according to the carry bit of the first mantissa result and the first exponent result.

[0224] Finally, step S77 may be executed to convert the second mantissa result and the second exponent result into a second multiplication result in a floating-point format.

[0225] According to the multiplication operation of the above embodiment, by detecting whether there is a floating-point exception in the floating-point operation operand and dividing the processing according to the detection result, the floating-point operation process is flexibly selected for different input operands, thereby improving the operation efficiency.

[0226] The following describes an implementation of the multiplier 22 of the present application. Figure 8 FIG. 2 shows a block diagram of a multiplier 22 according to an embodiment of the present application. Figure 8 As shown, the multiplier 22 of the embodiment of the present application may include an exponent expansion unit and a mantissa expansion unit. The exponent expansion unit is used to expand the bit width of the exponent field of the operand of the multiplication operation, and the mantissa expansion unit is used to expand the bit width of the mantissa field of the operand of the multiplication operation.

[0227] After the bit width is expanded, the operation process can be performed, such as Figure 8As shown, the multiplier 22 of the embodiment of the present application may include an exponent adder and a mantissa multiplier. The exponent adder is used to perform addition and subtraction operations on the exponents of the input operands, and the mantissa multiplier is used to perform multiplication operations on the mantissas of the input operands.

[0228] In one possible implementation, Figure 8 The exponent adder and the mantissa multiplier shown may constitute the multiplication unit 221. In another possible implementation, Figure 8 The exponent expansion unit, exponent adder, mantissa expansion unit and mantissa multiplier shown in the figure constitute the multiplication unit 221. The present application does not limit the specific division method of the units or modules.

[0229] After the exponent and the mantissa of the operand of the multiplication operation are calculated respectively by the exponent adder and the mantissa multiplier, a first multiplication result can be obtained. The first multiplication result may include a first exponent result and a first mantissa result.

[0230] In one possible implementation, Figure 8 As shown, the first underflow correction unit 222 may include a unit for exponent underflow prediction and mantissa shift amount calculation, a Wallace-Tree-Adder, a normalization unit, a rounding control unit, and a plurality of multiplexers.

[0231] Among them, the unit for exponent underflow prediction and mantissa shift number calculation can predict whether underflow occurs based on the first exponent result and the minimum exponent calculated by the exponent adder, and calculate the mantissa shift number (such as Figure 6 As shown), the calculated mantissa shift number (the first mantissa shift number, or the second mantissa shift number, or the actual mantissa shift number, etc.) is sent to the mantissa normalization unit.

[0232] The Wallace tree adder is used to round the first mantissa result. The rounding process may include Round Up and Round Down, that is, rounding up and rounding down. The results of rounding up and rounding down of the first mantissa result are calculated to obtain the rounded-up mantissa and the rounded-down mantissa.

[0233] The mantissa normalization unit can perform normalization processing (left shift or right shift) on the rounded-up mantissa and the rounded-down mantissa according to the calculated mantissa shift number (the first mantissa shift number or the second mantissa shift number). The specific processing process can be found in Figure 6 Step S66 or S67 in, or see Figure 7If the rounded-up mantissa or the rounded-down mantissa is shifted right, the normalized mantissa can be rounded by +1 or +0 according to the rounding mode. The above process yields a normalized rounded-up mantissa and a rounded-down mantissa, and the rounding control unit selects one of them as the second mantissa result according to the rounding mode. The rounding mode may be the rounding mode used by the software module running on the processor.

[0234] Figure 9 FIG. 1 is a schematic diagram showing an exponential adder and a unit for exponential underflow prediction and mantissa shift number calculation according to an embodiment of the present application. Figure 9 As shown, the two adders on the left (Adder 1 and Adder 2, hereinafter referred to as the first adder and the second adder) are used to perform subtraction operations on the operands and the number of leading zeros of the operands, respectively. For example, in the example described above, the multiplication operation includes operands A and B, the value of the exponent field of operand A is ExpA, and the number of leading zeros of the mantissa can be LZC. A The exponent field of operand B has the value ExpB, and the number of leading zeros in the mantissa can be LZC. B In the embodiment of the present application, the leading zeros of operands A and B can be negated before being input to the first adder and the second adder. The first adder is used to calculate ExpA-LZC A -Bias A Get the first difference, the second adder is used to calculate ExpB-LZC B -Bias B Get the second difference, where Bias A and Bias B They are the bias values of operand A and operand B respectively. The two adders output the first difference and the second difference to the connected third adder (Adder 3), which is used to sum the first difference and the second difference and add the Bias sour Get the first exponent result of the first multiplication result.

[0235] After calculating the first exponent result, the unit for exponent underflow prediction and mantissa shift number calculation can determine whether the first multiplication result has overflowed based on the first exponent result and the minimum exponent, and can also calculate the mantissa shift number based on the first exponent result, the minimum exponent, and the number of leading zeros.

[0236] like Figure 9 As shown, in a possible implementation, a comparator ( Figure 9(not shown), the comparator may compare the calculated first exponent result Exp with the minimum exponent.

[0237] If the first exponent result is greater than the minimum exponent, then the first multiplication result does not underflow. Figure 9 As shown, the number of mantissa shifts can be set to 0.

[0238] If the first exponent result is less than the minimum exponent (MinExp), such as Figure 9 As shown, the first mantissa shift number MinExp+~Exp+1 is calculated, and the relationship between the first mantissa shift number and the number of digits in the mantissa field is determined to determine the actual mantissa shift number. Figure 9 As shown, the number of bits in the mantissa field can be 64. Specifically, if the first mantissa shift number is less than the number of bits in the mantissa field, the actual mantissa shift number is the first mantissa shift number; if the first mantissa shift number is greater than the number of bits in the mantissa field, the number of bits in the mantissa field is the actual mantissa shift number. Figure 9 In the example shown, for different input operands, it is possible to predict whether the operation result will overflow, and determine the calculation method of the mantissa shift number according to the prediction result, and obtain the mantissa shift number to shift the first mantissa result. Figure 8 As shown, if it overflows, the multiplexer connected later can also calculate the second index result based on the prediction result, the first index result and the minimum index. It should be noted that Figure 9 The example shown is merely one example of an exponent adder and a unit for exponent underflow prediction and mantissa shift amount calculation, and does not limit the present application in any way.

[0239] Application Example (Multiplication Operation)

[0240] The following is an example of the multiplication process based on a practical application.

[0241] Example 1 (operands A and B are both normalized numbers)

[0242] LZC A =0,LZC B =0, no LZC is required at this time. If normalization is detected, LZC is set directly A =0,LZC B =0.

[0243] Assume operand A is 1.25 and operand B is 2.345, and assume both are single-precision floating-point numbers. The following table illustrates the gradual evolution of each operand during the calculation.

[0244] Operand A: 0x3FA0000 (i.e. decimal 1.25)

[0245]

[0246] Operand B: 0x4016147B (i.e. decimal 2.345)

[0247]

[0248] During the implementation process, not all channels need to be expanded to 64-bit, which means that the input operands of some channels can be expanded in bit width.

[0249] Note that in this example, the LZC of the input operands are all 0.

[0250] First index result = ExpA – LZC A +ExpB–LZC B +Bias sp

[0251] =(17'hFFFF-17'hFFFF)–0+(17'h10000-17'hFFFF)–0+8'7F

[0252] =8'h1+8'7F=8'h80

[0253] Therefore, the calculated 8'h80 is greater than the minimum exponent, and therefore, the calculated multiplication result does not overflow.

[0254] First digit result = ManA * ManB

[0255] =64'hA000000000000000*64'h96143B0000000000

[0256] =128'h5dcccd20000000000000000000000000

[0257] Normalization is not necessary at this time because the result of 1.***×1.**** is still 1.*****, so the valid result is taken from the first digit.

[0258] First digit result:

[0259]

[0260] The result of the first multiplication:

[0261]

[0262] Example 2 (Operand A is a normalized number, operand B is a denormalized number)

[0263] like Figure 9As shown, the first exponent result Exp and the first mantissa result are calculated.

[0264] If the first exponent result is less than the minimum exponent, it indicates underflow. In this case, the difference between the first exponent result and the minimum exponent needs to be calculated to determine the actual number of mantissa shifts (underflow shift counter). The algorithm is as follows:

[0265] Underflow shift counter=MinExp–Exp=MinExp+~Exp+1;

[0266] If(Underflow shift counter>64)

[0267] Underflow shift counter=64;

[0268] Else Underflow=MinExp+~Exp+1.

[0269] Denormalization Example

[0270] Operand A: 0x3F7FFFFF

[0271]

[0272] Operand B: 0x00000001

[0273]

[0274] In decimal, the exponential result in the theoretical operation result = ExpA – LZC A +(ExpB–LZC B )+Bias sp=(-1)-0+(-127-22)+127=-23<0 judges underflow

[0275] If in hexadecimal, according to the implementation of the present application, the method of calculating the first exponent result is:

[0276] =(17'hFFFF-17'hFFFF–0)+((0–8’h7F+17’hFFFF–8’h12)–17’hFFFF)+8’h7F

[0277] =(17'hFFFF-17'hFFFF)+(17'hFF6A-17'hFFFF)+17'hFFFF

[0278] =-8'h23<8'h0 determines underflow

[0279] SP Exponent range: [-127+127,128+127]

[0280] SP Min(32'h0000_0001)2^(-126-23)=2^(-149)-149+Bias SP=-149+127=-22

[0281] First mantissa shift number: Underflow Shift Counter = (-22) – (-23) = 1

[0282] Underflow prediction and mantissa shift:

[0283] Mantissa intermediate result = 128'h000000ffffff0000000000000000000000

[0284] The intermediate result of the mantissa is shifted right by the first mantissa shift bit (1-bit) to obtain the mantissa result =

[0285] 128'h0000007f ffff80000000000000000000

[0286]

[0287] Second exponent result = -8'h23 + 8'h1 = -8'h22 < 0; set to 8'h0 in floating point format.

[0288] Select the result (second mantissa result) according to the rounding mode:

[0289] If rounded up: 23'h000001;

[0290] If rounded down: 23'h000000;

[0291] Exponent result: 0x0.

[0292] The final second multiplication result is 32'h00000001 (rounding mode is Round Up or Round Near) or 32'h00000000 (rounding mode is Round Down or Truncate).

[0293] Compared to theoretical approaches, the method of the embodiment of the present application reduces the number of shifts (as described above, the calculation method according to the embodiment of the present application only requires a 1-bit shift of the mantissa, while the related prior art requires a 23-bit shift). In other words, the implementation process of the calculation method according to the embodiment of the present application is more user-friendly in terms of calculation time and circuit area. In addition, two rounding situations (adding 1 to the mantissa and not adding 1) are calculated, and finally a selection is made based on the actual rounding mode, which also improves calculation efficiency.

[0294] Divider, division operation

[0295] The divider 23 is used to perform a division operation. In a possible implementation, as shown in FIG. Figure 2 or Figure 3 As shown, the divider 23 may include a normalization unit 231, a division unit 232 and a second underflow correction unit 233; wherein, the normalization unit 231 is used to normalize (normalize) the operand according to the number of leading zeros of the operand when the detection module 20 detects that there is a floating-point exception in the operand of the division operation; the division unit 232 is used to perform a division operation according to the operand or the normalized operand to obtain a first division result; the second underflow correction unit 233 is used to correct the first division result according to the minimum exponent when it is detected that the first division result overflows.

[0296] In one possible implementation, the process of expanding the bit width of the operands of the division operation can be performed after normalization and before the division operation. That is, if the operands of the division operation have a floating-point exception, the leading zero counter 21 can count the number of leading zeros in the operands with the floating-point exception, and then the normalization unit 231 can normalize the operands based on the number of leading zeros. After that, the bit width of the normalized operands is expanded, and the division operation is performed based on the operands after the bit width expansion.

[0297] For division operations, if the detection module 20 detects that there is no floating-point exception in the operands of the division operation, the normalization process can be skipped, that is, the normalization unit 231 does not need to normalize the operands, and the division unit 232 directly performs the division operation according to the operands to obtain the first division result (or, the operands can be bit-width expanded before performing the division operation). Then, the second underflow correction unit 233 is used to correct the first division result according to the minimum exponent when it is detected that the first division result overflows.

[0298] In one possible implementation, the first division result may include a third exponent result and a third mantissa result. Assume that the two operands after bit width expansion are operand A and operand B, and assume that operand A is the dividend and operand B is the divisor. The specific process of performing the division operation may include: calculating the third exponent result based on the value of the exponent field of the expanded operand, the offset value corresponding to the expanded operand, and the offset value corresponding to the input operand. For example, the third exponent result = E A -E B +Bias sour , where, during the calculation process, EA ExpA is obtained by subtracting the corresponding offset value, where ExpA is the value of the exponent field of operand A, and E B ExpB is obtained by subtracting the corresponding bias value. ExpB is the value of the exponent field of operand B. Bias sour Indicates the offset value corresponding to the format of the input operand.

[0299] In one possible implementation, when the offset values corresponding to the two expanded operands are the same, a third exponent result can be calculated based on the value of the exponent field of the expanded operand and the offset value corresponding to the input operand. For example, the third exponent result is obtained by taking the difference between the values of the exponent fields of operand A and operand B and adding the offset value corresponding to the input operand.

[0300] The specific process of performing the division operation may further include: calculating the quotient of the mantissa of the operation A and the mantissa of the operation B to obtain a third mantissa result.

[0301] The second underflow correction unit 233 is used to determine whether the first division result has overflowed under the third exponent result and the minimum exponent. If the third exponent result is less than the minimum exponent, the first division result has overflowed under the third exponent result. If the third exponent result is not less than the minimum exponent, the first division result has not overflowed under the third exponent result.

[0302] In one possible implementation, when the first division result overflows, the second underflow correction unit 233 can calculate the fourth mantissa shift number based on the minimum exponent, the third exponent result, and the number of leading zeros of the third mantissa result, where the fourth mantissa shift number is the number of bits by which the third mantissa result is shifted right.

[0303] When the first division result does not overflow, the second underflow correction unit 233 can first determine whether the third mantissa result needs to be normalized according to the number of leading zeros of the third mantissa result. Since the operands of the division operation are normalized before the calculation, the normalized operands are 1.***. At this time, the minimum result of the third mantissa result is 1.000... / 1.111...>0.1, and the maximum result of the third mantissa result is 1.111...

[0304] If the calculated third mantissa result is not less than 1, then the mantissa shift number can be directly determined to be 0, and the divider can convert the third exponent result and the third mantissa result to obtain the second division result in floating point format.

[0305] If the calculated third mantissa result is less than 1, then the third mantissa result includes only one leading zero. That is, the third mantissa result only needs to be shifted left by one position to obtain a fourth mantissa result, and the third exponent result is subtracted by 1 to obtain a fourth exponent result. The divider converts the fourth exponent result and the fourth mantissa result into a floating-point second division result.

[0306] In one possible implementation, the number of mantissa shifts required for the third mantissa result depends on the algorithm used for the division operation. The number of mantissa shifts depends on the number of zeros in the quotient calculated in the first round of the algorithm. In actual algorithms, pre-computation padding is performed on the operands to ensure that the result of the first round is greater than or equal to 1, thereby truncating subsequent calculations of zeros. In this case, the number of mantissa shifts is determined by the number of zeros in the quotient calculated in the first round.

[0307] For example, when using the SRT-r algorithm, the quotient calculated in the first round has Log2(r) bits, which is a fixed value. For example, when using SRT16, after the algorithm is fixed, the quotient calculated in each round is 4 bits.

[0308] The number of 0s in the quotient = 4 – (the logarithm of the number of digits in the quotient calculated in the first round). For example, the possible values of the quotient that can be calculated in the first round are [2,7], and the number of digits in the quotient that have 1 is [log22,log27].

[0309] The following describes the division process and divider examples.

[0310] (1) There is a floating-point exception in the operand of the division operation

[0311] Figure 10 FIG. 1 shows a flow chart of a division operation according to an embodiment of the present application. Figure 10 As shown, in this case, before executing the division operation, step S100 is first executed, and the leading zero counter 21 counts the number of leading zeros of the operands with floating point exceptions.

[0312] Assume that a division operation includes two operands, namely operand A and operand B. Assume that operand A is the dividend and operand B is the divisor. The existence of a floating point exception in the operands of the division operation may refer to the existence of a floating point exception in any one or both of the two operands. For the operands with floating point exceptions, the leading zero counter 21 counts the number of leading zeros. For example, if operand A has a floating point exception, the leading zero counter 21 can count the number of leading zeros to obtain LZC A If there is a floating point exception in operand B, the leading zero counter 21 can count the number of leading zeros to obtain LZC B .

[0313] In step S101 , the normalization unit 231 may perform normalization processing (normalization processing) on the operand according to the number of leading zeros.

[0314] In one possible implementation, the normalization unit 231 can shift the mantissa of the operand left by the same number of bits as the number of leading zeros according to the number of leading zeros, and subtract the exponent of the operand (the exponent here does not refer to the binary exponent bit, but refers to the exponent of the operand represented in floating-point format) by a value equal to the number of leading zeros.

[0315] In another possible implementation, the normalization unit 231 can also determine whether the most significant bit of the mantissa of the operand is 1. If it is not 1, the mantissa of the operand is shifted left by one position and the exponent of the operand is reduced by 1. The above process is repeated until the most significant bit of the mantissa of the operand is 1.

[0316] For example, assuming that operand A is a single-precision floating-point number, operand A is 0.001*2^(-126). The mantissa of operand A can be shifted left by three bits to obtain a mantissa 1.000. The exponent of operand A can be subtracted by 3 to obtain -129. Therefore, the normalized operand A can be expressed as 1.000*2^(-129).

[0317] In step S102 , the FPU may perform bit width expansion on the normalized operand to obtain an expanded operand.

[0318] The specific process of expanding the bit width can be found in the description above. Taking the above operand A as an example, the process of expanding from a single-precision floating-point number to an extended double-precision floating-point number is as follows:

[0319] The expanded index is: -129+(2 16 -1)=2 16 -2 7 -2;

[0320] The expanded mantissa is expanded to 64 bits by adding 0 after the original mantissa.

[0321] Therefore, the operand A after the bit width extension can be expressed in the extended double-precision floating-point number format as: 0(17'hEE6D)(64'h 0000000000000000).

[0322] In step S103, the division unit 232 performs a division operation on the expanded operands to obtain a first division result, wherein the first division result includes a third exponent result and a third mantissa result. The specific process of performing the division operation may include: calculating the third exponent result based on the value of the exponent field of the expanded operand, the offset value corresponding to the expanded operand, and the offset value corresponding to the input operand. In a possible implementation, when the offset values corresponding to the two expanded operands are the same, the third exponent result may be calculated based on the value of the exponent field of the expanded operand and the offset value corresponding to the input operand. For example, the difference between the values of the exponent fields of operands A and B is calculated, and the offset value corresponding to the input operand is added to obtain the third exponent result. The specific process of performing the division operation may also include: calculating the quotient of the mantissa belonging to operation A and the mantissa of operand B to obtain the third mantissa result.

[0323] In step S104 , the second underflow correction unit 233 determines whether the third exponent result is smaller than the minimum exponent.

[0324] If the third exponent result is less than the minimum exponent, the first underflow correction unit 233 may determine that the first division result has overflowed. In other words, if the result of adding the exponent bits of the division operands is less than 0, the first division result has overflowed. If the first division result has overflowed, in step S105, the second underflow correction unit 233 calculates a third mantissa shift amount based on the minimum exponent and the third exponent result, and calculates a fourth exponent result based on the third exponent result and the third mantissa shift amount.

[0325] For example, the second underflow correction unit 233 is used to add 1 to the difference between the minimum exponent and the third exponent result as the third mantissa shift number when the first division result overflows, and the fourth exponent result can be calculated based on the third mantissa shift number and the third exponent result. The fourth exponent result can be the sum of the third exponent result and the third mantissa shift number.

[0326] In a possible implementation, the second underflow correction unit 233 may calculate the third mantissa shift amount according to the following formula (6):

[0327] S underflow4 =MINExp-Exp3+1; (6)

[0328] Among them, S underflow4 Indicates the number of shifts to the mantissa when the result of the first division overflows, MINExp indicates the minimum exponent, and Exp3 indicates the third exponent result.

[0329] Then, step S106 is executed, where the second underflow correction unit 233 shifts the third mantissa result according to the third mantissa shift amount and rounds the third mantissa result according to the rounding mode to obtain a fourth mantissa result.

[0330] If the result of the first division overflows, the calculated third mantissa shift amount is used to right-shift the third mantissa result so that the third exponent result falls within the range of the exponent bits. In this case, the third mantissa result may be rounded according to the rounding mode during the right shift to obtain a fourth mantissa result.

[0331] In step S109 , the divider 23 converts the fourth mantissa result and the fourth exponent result to obtain a second division result in a floating-point format.

[0332] If the third exponent result is not less than the minimum exponent, the second underflow correction unit 233 can determine that the first division result has not overflowed. In other words, if the result after adding the exponent bits of the division operands is not less than 0, the first division result has not overflowed. If the first division result has not overflowed, step S106 is executed, and the second underflow correction unit 233 determines whether the third mantissa result needs to be normalized (determine whether the third mantissa result is less than 1) based on the number of leading zeros in the third mantissa result.

[0333] If the calculated third mantissa result is not less than 1, then the mantissa shift number can be directly determined to be 0, and the divider can execute step S107 to directly convert the third exponent result and the third mantissa result to obtain the second division result in floating point format.

[0334] If the calculated third mantissa result is less than 1, then the third mantissa result only includes a leading zero, that is, it is only necessary to execute step S108, shift the third mantissa result one position to the left to obtain a fourth mantissa result, and subtract 1 from the third exponent result to obtain a fourth exponent result; in step S109, the divider converts the fourth exponent result and the fourth mantissa result to obtain a second division result in floating-point format.

[0335] (2) There are no floating-point exceptions for the operands of the division operation

[0336] Figure 11 FIG. 1 shows a flow chart of a division operation according to an embodiment of the present application. Figure 11 As shown, when there is no floating point exception in the operand, there is no need to calculate the number of leading zeros in the operand, nor is there any need to perform normalization processing on the operand based on the number of leading zeros.

[0337] Before performing the division operation, step S110 may be performed first, and the FPU may perform bit width expansion on the operand of the division operation to obtain an expanded operand. For the specific process, please refer to the implementation method of the bit width expansion part above.

[0338] In step S111 , the division unit 232 performs a division operation according to the expanded operands to obtain a first division result, where the first division result includes a third exponent result and a third mantissa result.

[0339] In step S112 , the second underflow correction unit 233 determines whether the third exponent result is smaller than the minimum exponent.

[0340] If the third exponent result is less than the minimum exponent, the second underflow correction unit 233 may determine that the first division result has underflowed. If the first division result has underflowed, in step S113, the second underflow correction unit 233 calculates a third mantissa shift amount based on the minimum exponent and the third exponent result, and calculates a fourth exponent result based on the third exponent result and the third mantissa shift amount.

[0341] In step S115 , the second underflow correction unit 233 shifts the third mantissa result according to the third mantissa shift amount, and rounds the third mantissa result according to the rounding mode to obtain a fourth mantissa result.

[0342] In step S118 , the second underflow correction unit 233 converts the fourth mantissa result and the fourth exponent result to obtain a second division result in a floating-point format.

[0343] If the third exponent result is not less than the minimum exponent, the second underflow correction unit 233 may determine that the first division result has not underflowed. If the first division result has not underflowed, step S114 is executed, and the second underflow correction unit 233 determines whether the third mantissa result needs to be normalized (determines whether the third mantissa result is less than 1) based on the number of leading zeros in the third mantissa result.

[0344] If the calculated third mantissa result is not less than 1, then the mantissa shift number can be directly determined to be 0, and the divider can execute step S116 to directly convert the third exponent result and the third mantissa result to obtain the second division result in floating point format.

[0345] If the calculated third mantissa result is less than 1, then the third mantissa result only includes a leading zero, that is, it is only necessary to execute step S117, shift the third mantissa result one position to the left to obtain a fourth mantissa result, and subtract 1 from the third exponent result to obtain a fourth exponent result; in step S118, the divider converts the fourth exponent result and the fourth mantissa result to obtain a second division result in floating-point format.

[0346] The process of steps S112-S118 and Figure 10 The processes of steps S104-S109 are the same, and the specific processes can be found in the above description and will not be repeated here.

[0347] An implementation of the divider 23 is described below. Figure 12 FIG. 2 shows a block diagram of a divider 23 according to an embodiment of the present application. Figure 12 As shown, compared with the multiplier 22, the divider 23 includes an exponent adder and a mantissa shift unit for normalizing the operand, wherein the mantissa shift unit is used to shift the mantissa of the operand with the floating-point exception to the left until the most significant bit is 1, and the exponent adder for normalizing the operand is used to subtract the number of bits of the mantissa shift from the exponent of the operand with the floating-point exception.

[0348] The exponent extension unit and the mantissa extension unit in the divider 23 have the same functions as those in the multiplier 22 and are not described in detail.

[0349] By performing a shift operation and an exponent subtraction operation on the mantissa of the operand, and expanding the bit width of the exponent and mantissa of the operand, the operation with a floating-point exception can be converted into a normalized floating-point number, thereby achieving normalization processing of the operand.

[0350] The exponent adder and the mantissa shift unit, the exponent extension unit and the mantissa extension unit for normalizing the operand in the divider 23 together constitute DMFX (Denormal Media Fix up), which is the normalization unit 231 mentioned above.

[0351] The mantissa divider is used to perform a division operation on the mantissas of two operands of the division operation to obtain a mantissa of a first division result.

[0352] The units for exponent underflow prediction and mantissa shift number calculation can perform Figure 10 Part of the contents of steps S104 and S105 shown, Figure 11 Part of the contents of step S112 and step S113 in .

[0353] The mantissa normalization unit in divider 23 has the same function as the mantissa normalization unit in multiplier 22, except that a Wallace tree adder is not provided in divider 23. For the fourth mantissa result obtained after the mantissa in the first division result is normalized, the fourth digit result is directly rounded according to the rounding control, without the need to select from the rounded-up result and the rounded-down result. Of course, the divider 23 of the embodiment of the present application can also adopt the same method as that of multiplier 22, first calculating the rounded-up result and the rounded-down result based on the third digit result through the Wallace tree adder, normalizing both the rounded-up result and the rounded-down result, and then selecting one of the normalized rounded-up result and the rounded-down result as the fourth mantissa result according to the rounding control.

[0354] The multiplexer connected to the lower side of the unit for exponent underflow prediction and mantissa shift amount calculation is used to calculate the fourth exponent result based on the third exponent result, the minimum exponent and the third mantissa shift amount.

[0355] Figure 13 FIG. 1 is a schematic diagram showing a specific structure of a unit for exponential underflow prediction and mantissa shift number calculation and an exponential adder according to an embodiment of the present application. Figure 13 As shown, since the input operands have been normalized according to the number of leading zeros in the input operands, when performing a division operation, it is not necessary to calculate the exponent result based on the number of leading zeros. Figure 13 Compared to the example in Figure 9 Two less adders can be set, and the other structures are the same as Figure 9 same.

[0356] Application Example (Division Operation)

[0357] The following is an example of actual application to illustrate the process of division operation.

[0358] Example 3 (operands A and B are both normalized numbers)

[0359] Operand A: 0x3E80000 (i.e. decimal 0.25)

[0360]

[0361] Operand B: 0x3F00000 (i.e. decimal 0.5)

[0362]

[0363] Subtracting exponentials:

[0364] The third index result = (ExpA – LZC A )–(ExpB-LZCB )+Bias SP

[0365] =(17'hFFFD–17'hFFFF-0)–(17'FFFE-17'hFFFF-0)+8'h7F

[0366] =8'h7E>8'h0. Therefore, the third exponent result does not underflow.

[0367] The third digit result:

[0368] Mantissa A / Mantissa B=

[0369] 64'h8000000000000000 / 64'h8000000000000000

[0370] =64'h8000000000000000

[0371] Mantissa shift number = 0

[0372] Final result = 24'h800000

[0373] Second division result:

[0374] Sign

[31] Exponent[30:23] Imp. Mantissa[22:0] 0 01111110 1 00000000000000000000000

[0375] Second division result = 0x3f000000 (i.e. decimal 0.5)

[0376] Example 4 (Operand A is a denormalized number, operand B is a normalized number)

[0377] Operand A:0x003fffff

[0378]

[0379] Operand B: 0x40800000

[0380]

[0381] In decimal, the third exponent result = (ExpA – LZC A )–(ExpB-LZC B )+Bias SP

[0382] =(-127-1)-(2-0)+127=-3<0.

[0383] Therefore, the third exponent result did not underflow.

[0384] The same result can be obtained in hexadecimal:

[0385] Third index result = (17'hff80–17'hffff-1)–(17'h10001–17'hffff-0)+17'hffff

[0386] =(17'hff7f-17'hffff)–(17'h10001–17'hffff-0)+17'hffff

[0387] =17'hff7d

[0388] The third digit result:

[0389] Mantissa A / Mantissa B=64'hffffffc0000000000 / 64'h8000000000000000

[0390] =64'hfffffc0000000000

[0391] Mantissa shift number = 1 – (-3) = 4

[0392] Exponential intermediate result = (17'hff7d+4)–17'hffff+8'h7f=8'h1

[0393] The third mantissa result is shifted right by the mantissa shift number (4-bit) to obtain the mantissa result = 64'h0fffffc000000000

[0394] Imp Mantissa Round bit 0 00011111111111111111111 11000000

[0395] At this time, Imp=0, which is equivalent to the mantissa being 0.****, and the result is a non-normalized number.

[0396] IEEE 754 stipulates that the exponent bits of a denormalized number are all 0s, and the exponent needs to be adjusted to obtain the fourth exponent result = 8'h0.

[0397] After adjusting the exponent bits, the mantissa bits need to be shifted and rounded to get the fourth mantissa result:

[0398] Mantissa round up result 23'h001000000000000000000000

[0399] Mantissa round down result 23'h00011111111111111111111

[0400] Therefore, the round-up mantissa result = 0x00100000, and the round-down mantissa result = 0x000fffff.

[0401] According to the rounding mode, one of the above mantissa results can be selected as the fourth mantissa result, and then according to the fourth exponent result=8'h0 and the fourth mantissa result conversion, the second division result in floating point format can be obtained.

[0402] According to the floating-point exception handling method and apparatus of the above-described embodiment of the present application, by fixing the floating-point exception of the operand within the FPU, it is possible to avoid the repeated execution of the repair loop process and eliminate the need for complex interactions between multiple modules, thereby improving computing performance. Furthermore, by setting different processing flows and methods based on whether the operand has a floating-point exception, it is possible to increase processing flexibility and thus improve computing efficiency.

[0403] The floating-point exception handling method of the above embodiment of the present application can be executed by a processing system. The processing system of the embodiment of the present application can include a floating-point operation unit FPU (Float Point Unit). The FPU is used to perform floating-point operations. The FPU can include the floating-point exception handling device of the above embodiment of the present application. Floating-point operations are a high-precision operation method and are mainly used in scientific and multimedia data processing.

[0404] Figure 14 FIG2 shows a schematic diagram of a processing system 200 according to an embodiment of the present application. The processing system 200 may include a processor 201 and a memory 202 connected to the processor 201. The processor 201 may be provided with an FPU. Figure 14 Various other components of the processing system 200 are omitted in the illustrated example. With respect to the processor 201 and memory 202 in the processing system 200, the embodiments of the present application do not limit the types of the processor 201 and the memory 202. For example, the processor 201 may be a general-purpose processor such as a CPU or a GPU, or a dedicated processor composed of one or more combinations of DSP (Digital Signal Process) and Field-Programmable Gate Array (FPGA) chips. The memory 202 is used to store data. The memory 202 may be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic memory, flash memory, magnetic disk or optical disk, and the like.

[0405] The present disclosure may be a system, method and / or computer program product. The computer program product may include a computer-readable storage medium carrying computer-readable program instructions for causing a processor to implement various aspects of the present disclosure.

[0406] A computer-readable storage medium can be a tangible device that can hold and store instructions for use by an instruction execution device. A computer-readable storage medium can be, for example, but not limited to, an electrical storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination thereof. More specific examples (a non-exhaustive list) of computer-readable storage media include: a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), a static random access memory (SRAM), a portable compact disc read-only memory (CD-ROM), a digital versatile disk (DVD), a memory stick, a floppy disk, a mechanical encoding device, such as a punch card or a raised structure in a groove on which instructions are stored, and any suitable combination thereof. As used herein, a computer-readable storage medium is not to be construed as a transient signal per se, such as a radio wave or other freely propagating electromagnetic wave, an electromagnetic wave propagating through a waveguide or other transmission medium (e.g., a light pulse through a fiber optic cable), or an electrical signal transmitted through an electrical wire.

[0407] The computer-readable program instructions described herein can be downloaded from a computer-readable storage medium to each computing / processing device, or downloaded to an external computer or external storage device via a network, such as the Internet, a local area network, a wide area network, and / or a wireless network. The network can include copper transmission cables, fiber optic transmission, wireless transmission, routers, firewalls, switches, gateway computers, and / or edge servers. The network adapter card or network interface in each computing / processing device receives the computer-readable program instructions from the network and forwards the computer-readable program instructions to be stored in the computer-readable storage medium in each computing / processing device.

[0408] The computer program instructions for performing the operations of the present disclosure may be assembly instructions, instruction set architecture (ISA) instructions, machine instructions, machine-dependent instructions, microcode, firmware instructions, state setting data, or source code or object code written in any combination of one or more programming languages, including object-oriented programming languages such as Smalltalk, C++, and conventional procedural programming languages such as "C" language or similar programming languages. Computer-readable program instructions may be executed entirely on a user's computer, partially on a user's computer, as an independent software package, partially on a user's computer, partially on a remote computer, or entirely on a remote computer or server. In the case of a remote computer, the remote computer may be connected to the user's computer via any type of network, including a local area network (LAN) or a wide area network (WAN), or may be connected to an external computer (e.g., utilizing an Internet service provider to connect via the Internet). In some embodiments, an electronic circuit, such as a programmable logic circuit, a field programmable gate array (FPGA), or a programmable logic array (PLA), may be personalized by utilizing the state information of the computer-readable program instructions. The electronic circuit may execute the computer-readable program instructions, thereby realizing various aspects of the present disclosure.

[0409] Various aspects of the present disclosure are described herein with reference to flowcharts and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the present disclosure. It should be understood that each block of the flowcharts and / or block diagrams, and combinations of blocks in the flowcharts and / or block diagrams, can be implemented by computer-readable program instructions.

[0410] These computer-readable program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing device, thereby producing a machine, so that when these instructions are executed by the processor of the computer or other programmable data processing device, a device is generated that implements the functions / actions specified in one or more blocks in the flowchart and / or block diagram. These computer-readable program instructions can also be stored in a computer-readable storage medium, where these instructions cause the computer, programmable data processing device, and / or other device to operate in a specific manner. Thus, the computer-readable medium storing the instructions comprises an article of manufacture that includes instructions for implementing various aspects of the functions / actions specified in one or more blocks in the flowchart and / or block diagram.

[0411] Computer-readable program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other device so that a series of operational steps are performed on the computer, other programmable data processing apparatus, or other device to produce a computer-implemented process, thereby causing the instructions executed on the computer, other programmable data processing apparatus, or other device to implement the functions / actions specified in one or more blocks in the flowchart and / or block diagram.

[0412] The flow charts and block diagrams in the accompanying drawings show the possible architecture, functions and operations of the systems, methods and computer program products according to multiple embodiments of the present disclosure. In this regard, each box in the flow chart or block diagram can represent a part of a module, program segment or instruction, and the part of the module, program segment or instruction contains one or more executable instructions for realizing the prescribed logical function. In some alternative implementations, the functions marked in the box can also occur in a sequence different from that marked in the accompanying drawings. For example, two consecutive boxes can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each box in the block diagram and / or flow chart, and the combination of the boxes in the block diagram and / or flow chart can be implemented by a dedicated hardware-based system that performs the prescribed function or action, or can be implemented by a combination of dedicated hardware and computer instructions.

[0413] While various embodiments of the present disclosure have been described above, the foregoing description is intended to be illustrative, non-exhaustive, and not limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is selected to best explain the principles of the embodiments, their practical applications, or technical improvements to existing technologies, or to enable others skilled in the art to understand the embodiments disclosed herein.

Claims

1. A floating point exception handling method for floating point operations, characterized in that: The method is applied to a floating point arithmetic unit (FPU), and the method comprises: Detecting an operation type of the floating-point operation and determining whether an operand of the floating-point operation is a denormalized number to detect whether a floating-point exception exists in the operand; if the operand is a denormalized number, the operand has a floating-point exception; if the operand is a normalized number, the operand does not have a floating-point exception; If it is detected that the operand has a floating-point exception, the number of leading zeros of the operand with the floating-point exception is determined, the bit width of the operand is expanded, and in the process of expanding the exponent field of the operand, the offset value of the original format is removed, the offset value of the new format after expansion is added, and the number of leading zeros of the denormalized floating-point number is subtracted; after the bit width expansion, in the process of performing a floating-point operation on the operand using an operator corresponding to the operation type of the floating-point operation to obtain an operation result, the operand is corrected according to the number of leading zeros; If it is detected that the operand does not have a floating-point exception, the operand is bit-width expanded. In the process of expanding the exponent field of the operand, the bias value of the original format is removed and the bias value of the expanded new format is added according to the value of the exponent field of the floating-point number before the bit-width expansion; after the bit-width expansion, the operator corresponding to the operation type of the floating-point operation is directly used to perform a floating-point operation on the operand to obtain an operation result; when the floating-point operation is a multiplication operation, the operation result is a first multiplication result; the first multiplication result includes a first exponent result and a first mantissa result, and it is determined whether the first mantissa result is greater than 1 and less than 2; if the first mantissa result is greater than 1 and less than 2, a second multiplication result in a floating-point format is directly converted according to the first exponent result and the first mantissa result; if the first mantissa result is greater than or equal to 2, a right shift operation is performed on the first mantissa result to normalize the first multiplication result and generate a second multiplication result in a floating-point format; If the operation result overflows, the operation result is corrected, including when the floating-point operation is a multiplication operation and there is a floating-point exception in the operand of the multiplication operation, if it is detected that the first multiplication result overflows, then the first multiplication result is corrected according to the minimum exponent.

2. The method according to claim 1, characterized in that The floating-point operation is a multiplication operation, and the operation result is a first multiplication result, and the first multiplication result includes a first exponent result and a first mantissa result; In a process of performing a floating-point operation on the operand using an operator corresponding to an operation type of the floating-point operation to obtain an operation result, the operand is corrected according to the number of leading zeros, including: A multiplier is used to calculate the first exponent result according to the exponent and the number of leading zeros of the operands of the multiplication operation, and the mantissas of the operands of the multiplication operation are multiplied to obtain the first mantissa result.

3. The method according to claim 2, characterized in that If the operation result overflows, the operation result is corrected, including: Determining whether the first multiplication result overflows based on a relationship between the first exponent result and the minimum exponent; If the first multiplication result overflows, calculating a first mantissa shift amount and a second exponent result according to the minimum exponent and the first exponent result; Shifting the first mantissa result according to the first mantissa shift amount to obtain a second mantissa result; A second multiplication result in a floating-point format is obtained by converting the second mantissa result and the second exponent result.

4. The method according to claim 3, characterized in that Calculating a first mantissa shift amount and a second exponent result according to the minimum exponent and the first exponent result, comprising: Calculate a first mantissa shift amount according to the minimum exponent and the first exponent result; A second exponent result is calculated based on the first exponent result and the first mantissa shift amount.

5. The method according to claim 3, characterized in that If the operation result overflows, the operation result is corrected, further comprising: If the first multiplication result does not underflow, calculating a second mantissa shift amount according to the number of leading zeros of the first mantissa result and the number of leading zeros of the operand; Shifting the first mantissa result according to the second mantissa shift amount and the number of leading zeros of the input operand to obtain a second mantissa result, and calculating a second exponent result according to the second mantissa shift amount and the first exponent result; A second multiplication result in a floating-point format is obtained by converting the second mantissa result and the second exponent result.

6. The method according to claim 1, further characterized in that: The floating-point operation is a division operation, and the operation result is a first division result. In a process of performing a floating-point operation on the operand using an operator corresponding to an operation type of the floating-point operation to obtain an operation result, the operand is corrected according to the number of leading zeros, including: normalizing the operand according to the number of leading zeros; A divider is used to perform a division operation on the normalized operands to obtain the first division result.

7. The method according to claim 6, characterized in that The first division result includes a third exponent result and a third mantissa result; If the operation result overflows, the operation result is corrected, including: Determining whether the first division result overflows according to a relationship between the third exponent result and the minimum exponent; If the first division result overflows, calculating a third mantissa shift amount based on the minimum exponent and the third exponent result, and calculating a fourth exponent result based on the third exponent result and the third mantissa shift amount; Shifting the third mantissa result according to the third mantissa shift amount, and rounding the third mantissa result according to the rounding mode to obtain a fourth mantissa result; A second division result in a floating-point format is obtained by converting the fourth mantissa result and the fourth exponent result.

8. The method according to claim 7, characterized in that If the operation result overflows, the operation result is corrected, further comprising: If the first division result does not overflow, determining whether the third mantissa result needs to be normalized according to the number of leading zeros of the third mantissa result; If the third mantissa result does not need to be normalized, the second division result in floating-point format is directly converted according to the third exponent result and the third mantissa result; If the third mantissa result needs to be normalized, the third mantissa result is shifted left by one position to obtain a fourth mantissa result, the third exponent result is subtracted by 1 to obtain a fourth exponent result, and the second division result in floating-point format is obtained based on the fourth mantissa result and the fourth exponent result.

9. A floating point exception handling device, characterized in that: include: detection module, leading zero counter, multiplier and divider, Wherein, the detection module is connected to the leading zero counter, and the leading zero counter is connected to the multiplier and the divider respectively; When the detection module detects that the floating-point operation is a multiplication operation or a division operation, and the operand of the floating-point operation is a non-normalized number and therefore a floating-point exception exists, the leading zero counter is used to count the number of leading zeros of the operand with the floating-point exception, and the multiplier and the divider both include a bit width expansion unit, and the bit width expansion unit is used to expand the bit width of the operand before performing the floating-point operation on the operand, and in the process of expanding the exponent field of the operand, remove the offset value of the original format, add the offset value of the new format after expansion, and subtract the number of leading zeros of the non-normalized floating-point number; after the bit width expansion, the multiplier and the divider are used to correct the operand according to the number of leading zeros in the process of performing the floating-point operation to obtain the operation result; When the detection module detects that the floating-point operation is a multiplication operation or a division operation, and there is no floating-point exception in the operand of the floating-point operation, the bit width expansion unit of the multiplier and the divider is used to expand the bit width of the operand before the floating-point operation is performed on the operand. In the process of expanding the exponent field of the operand, the bias value of the original format is removed and the bias value of the expanded new format is added according to the value of the exponent field of the floating-point number before the bit width expansion; after the bit width expansion, it is used to directly perform a floating-point operation on the operand to obtain an operation result; when the floating-point operation is a multiplication operation, the operation result is a first multiplication result; the first multiplication result includes a first exponent result and a first mantissa result, and it is determined whether the first mantissa result is greater than 1 and less than 2; if the first mantissa result is greater than 1 and less than 2, a second multiplication result in a floating-point format is directly converted according to the first exponent result and the first mantissa result; if the first mantissa result is greater than 1 and less than 2, the first mantissa result is right-shifted to normalize the first multiplication result to generate a second multiplication result in a floating-point format; If the operation result overflows, the multiplier and divider are also used to correct the operation result, including when the floating-point operation is a multiplication operation and there is a floating-point exception in the operand of the multiplication operation, if it is detected that the first multiplication result overflows, then the first multiplication result is corrected according to the minimum exponent.

10. The device according to claim 9, characterized in that The floating-point operation is a multiplication operation, and the operation result is a first multiplication result, and the first multiplication result includes a first exponent result and a first mantissa result; The multiplier includes a multiplication unit, which is used to calculate the first exponent result according to the exponent and the number of leading zeros of the operands, and multiply the mantissas of the operands of the multiplication operation to obtain the first mantissa result.

11. The device according to claim 10, characterized in that When the detection module detects that the operand of the floating-point operation has a floating-point exception, the multiplication unit obtains the number of leading zeros of the operand from the leading zero counter; When the detection module detects that the operands of the floating-point operation do not have a floating-point exception, the multiplication unit sets the number of leading zeros to 0.

12. The device according to claim 10, characterized in that The multiplier further includes a first underflow correction unit; The first underflow correction unit is configured to correct the first multiplication result when it is determined based on the first exponent result that the first multiplication result has overflowed.

13. The device according to claim 12, characterized in that The first underflow correction unit is configured to determine whether the first multiplication result has underflowed according to a relationship between the first exponent result and the minimum exponent; If the first multiplication result overflows, the first underflow correction unit calculates a first mantissa shift amount and a second exponent result based on the minimum exponent and the first exponent result, shifts the first mantissa result according to the first mantissa shift amount, and rounds the first mantissa result according to the rounding mode to obtain a second mantissa result.

14. The device according to claim 13, characterized in that The first underflow correction unit is configured to calculate a first mantissa shift amount according to the minimum exponent and the first exponent result, and calculate a second exponent result according to the first exponent result and the first mantissa shift amount if the first multiplication result underflows.

15. The device according to claim 13, characterized in that The first underflow correction unit is further configured to calculate a second mantissa shift amount according to the number of leading zeros of the first mantissa result and the number of leading zeros of the operand if the first multiplication result does not underflow; The first mantissa result is shifted according to the second mantissa shift amount and the number of leading zeros of the input operand to obtain a second mantissa result, and a second exponent result is calculated according to the second mantissa shift amount and the first exponent result.

16. The device according to claim 13 or 15, characterized in that The multiplier further includes a first format conversion unit, The first format conversion unit is configured to convert the second mantissa result and the second exponent result to obtain a second multiplication result in a floating point format.

17. The device according to claim 9, characterized in that The floating-point operation is a division operation, and the operation result is a first division result. The divider includes a normalization unit, a division unit and a second underflow correction unit; The normalization unit is configured to normalize the abnormal operand according to the number of leading zeros of the operand when the detection module detects that the operand of the division operation is abnormal; The division unit is configured to perform a division operation according to the normalized operand to obtain a first division result; The second underflow correction unit is configured to correct the first division result when it is detected that the first division result underflows.

18. The device according to claim 17, characterized in that The first division result includes a third exponent result and a third mantissa result; The second underflow correction unit is used to determine whether the first division result has underflowed according to the relationship between the third exponent result and the minimum exponent; If the first division result overflows, calculating a third mantissa shift amount based on the minimum exponent and the third exponent result, and calculating a fourth exponent result based on the third exponent result and the third mantissa shift amount; The third mantissa result is shifted according to the third mantissa shift amount, and the third mantissa result is rounded according to the rounding mode to obtain a fourth mantissa result.

19. The device according to claim 18, characterized in that The second underflow correction unit is further configured to determine whether normalization processing needs to be performed on the third mantissa result according to the number of leading zeros of the third mantissa result when the first division result does not underflow; If the third mantissa result needs to be normalized, the third mantissa result is shifted left by one position to obtain the fourth mantissa result, and the third exponent result is subtracted by 1 to obtain the fourth exponent result.

20. The device according to claim 17, wherein The division unit is further configured to directly perform a division operation on the operands of the division operation to obtain a first division result when the detection module detects that there is no floating-point exception in the operands of the division operation.

21. The device according to claim 18 or 19, characterized in that The divider further includes a second format conversion unit, The second format conversion unit is configured to convert the fourth mantissa result and the fourth exponent result to obtain a second division result in a floating-point format; Alternatively, if the second underflow correction unit determines that the third mantissa result does not need to be normalized, the second format conversion unit is configured to directly convert the third exponent result and the third mantissa result to obtain a second division result in a floating point format.

22. A processing system, characterized in that include: processor; A memory, used to store floating-point operation instructions executable by the processor and operands corresponding to the floating-point operation instructions; The processor is configured to implement the method according to any one of claims 1 to 8 when executing the floating-point operation instruction to process the operand.

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