A fault-tolerant mapping method for nano-CMOS circuits with optimized delay

Abstract

The present invention discloses a nano-CMOS circuit fault-tolerant mapping method capable of optimizing delay. Aiming at the problems of poor delay performance, poor solution speed and quality existing in the nano-CMOS circuit that uses the existing fault-tolerant mapping method to realize the correct logical function, a nano-CMOS circuit fault-tolerant mapping method capable of optimizing delay is provided under the mapping constraint of the defective nano-CMOS circuit. The fault-tolerant mapping method of the present invention optimizes the mapping process of the traditional nano-CMOS circuit, adds a logic-level division technology for the logic circuit to be mapped and a physical-level pre-planning technology with the original input as the object, maps the logic circuit to the pre-planned area in the nano-CMOS circuit in the unit of the path tree using two mapping modes to optimize the delay of each path, and improves the mapping success rate by finding available defective units, and optimizes the delay performance of the delay mapping circuit on the basis of quickly eliminating the influence of defects on the logical function of the nano-CMOS circuit.

Description

Technical Field

[0001] The invention relates to the field of integrated circuits, and in particular to a nanometer CMOS circuit fault-tolerant mapping method capable of optimizing delay. Background Art

[0002] With the reduction of the line width of the manufacturing process, silicon-based CMOS integrated circuits have entered the nanoscale size. The quantum effect of the microscopic world has an increasing impact on signal integrity. The delay on the interconnection line has gradually replaced the delay of CMOS devices and become an important factor affecting the myocardial infarction of CMOS integrated circuits. Such technical difficulties have made people hope that the hybrid process combining nanotechnology and CMOS technology can meet the current development needs. Among them, in 2005, Likharev and his colleagues proposed the CMOS / nanowire / molecular hybrid (CMOL) circuit technology that combines CMOS and nanowire layers. It is considered to be one of the most representative post-CMOS technologies that can continue Moore's Law. The nano-CMOS circuit structure mixes MOS tubes in traditional processes and nano-devices and nano-wires in nano-manufacturing processes, so it has rich logical functions and the advantages of high density and low power consumption. At present, the nano-CMOS circuit structure has been successfully applied to memristor-designed memories, CMOLFPGAs and neural network circuits.

[0003] Nano CMOS circuit is a hybrid circuit based on nano cross array structure: the top is two layers of vertically crossed nanowires, each layer of nanowires is arranged in parallel, and a programmable nano device (nano diode) is arranged at the intersection of the crossed nanowires; the bottom is a CMOS inverter, which is connected to the nanowire layer through an interface pin. The interface pin is located at the center of each nanowire and can transmit the signal on the nanowire to the CMOS inverter. Figure 1The figure shows a cross-sectional view of the nano-CMOS circuit structure. Each input nanowire transmits the signal to the CMOS inverter through the interface pin, and after inversion, the signal can be transmitted through the interface pin and the output nanowire. Then, through the programmable nanodiode configured in a low-resistance state, the signal realizes the line OR logic on the input nanowire, and the NOR logic and NOT logic (i.e., NOR logic and NOT logic) can be realized in the nano-CMOS circuit. Based on the CMOS inverter, the nano-CMOS circuit can be divided into multiple nano-CMOS units, each of which contains a CMOS inverter, two interface pins connected to the inverter, two periodically broken input and output nanowires, and nano-diodes periodically arranged on the input nanowire. Through numerous nano-diodes, any nano-CMOS unit can be connected to a finite number of nearby M=2r(r-1)-1 units. However, due to errors in the manufacturing process of the nano-CMOS circuit and the programming voltage of the produced nano-diodes, the defect rate of the nano-CMOS circuit can reach 10% to 20%, which is much higher than the 10% in the traditional CMOS circuit. -9 ~10 -7 The presence of defects has a huge impact on the connection range of units in nanometer CMOS circuits.

[0004] It is generally believed that in nano-CMOS circuits, due to the configuration voltage being too low or the irregular breakage of the nanowire, the number of other nano-CMOS cells that the CMOS inverter in the nano-CMOS cell can connect to is reduced, and this defect is called a stuck-at-open defect. Figure 2 (a) in the figure shows a schematic diagram of a normally-on defect of a nanodiode in a 3×2 nano-CMOS circuit structure. Nanodiode ① has a normally-on defect, and the circle represents the nanodiode and interface pin that are normally programmed to be in the on state. Figure 2 As can be seen from (a) in Figure 1, the nanodiode ① on the input nanowire of unit C is normally open, and ① is connected to the output nanowire of unit B, resulting in the output signal of unit B being unable to be transmitted to unit C. Originally, unit C can realize the logic: g3 = g1 + g2, but due to the existence of the normally open defect, it will realize: g3 = g2. Figure 2 From the equivalent path diagram in (b), it can be seen that the normally-open defect not only affects the logical correctness but also changes the signal path.

[0005] Because the configuration voltage is too high, the programmable nanodiode is constantly turned on (in the low-resistance "ON" state), causing the two intersecting nanowires connected to the nanodiode to constantly transmit in a directional manner. This defect is called the nanodiode normally closed defect (stuck-at-close in nanodevice). Figure 3(a) shows a schematic diagram of the normally closed defect of nanodiodes in a 4×3 nano-CMOS circuit structure. The units marked ①, ②, and ③ all contain normally closed defect nanodiodes. Figure 3 As can be seen from (a) in the figure, the nanodiode ① on the input nanowire of unit C is normally closed, and ① is connected to the output nanowire of unit B, causing unit B to constantly transmit the output signal to unit C in a directional manner. Originally, unit C can realize the logic: g3=g1, but due to the existence of the normally closed defect, it will realize: g3=g1+g2. Similarly, for unit E, the defective nanodiode ③ contained in it is connected to unit G, so E will realize E=G=g5, and at the same time, the normally closed defective nanodiode ② of unit D is connected to the output nanowire of unit E, that is, the logic value realized on E will be transmitted to unit D. Since the input and output nanowires of E are both connected to the defective nanodiodes, E will become a bridge connecting units G and D, and realize the logic D=g4+g5 related to G on unit D. From Figure 3 From the equivalent path diagram in (b), it can be seen that the normally closed defect not only affects the logical correctness, but also changes the number of logic gates in the equivalent path due to the addition of an additional connecting path, thus there is a possibility of deteriorating the delay of the mapping circuit.

[0006] Fault-tolerant mapping on nano-CMOS circuits is to match NOR logic gates to nano-CMOS units one by one, and implement functions without defects on nano-CMOS circuits. It is generally divided into: random initialization mapping (not considering defects and only implementing the connectivity constraints of mapped logic gates); heuristic iterative search fault-tolerant mapping (considering defects). The fault-tolerant mapping step is carried out on all logic gates and connecting edges at the same time, and there is a possibility of adding additional units in the signal transmission path. Figure 4 (a) in FIG. 5 shows an example of tolerating normally-open defects in two ways. Figure 4 In (a), the black arrow indicates the first fault tolerance method: reconfiguration. By swapping the logic gate g1 mapped on unit B to the non-defective unit D, the signal can be prevented from passing through the defective nanodiode ①. The equivalent path after fault tolerance is shown in Figure 4 As shown in (b) in the figure, this operation ensures the correct logical function while also ensuring the same number of units in the path. Figure 4 The dotted lines in (a) of the figure show the second fault-tolerance method: inverter pair insertion. Due to the complex connection between logic gates, some high fan-in / fan-out logic gates are difficult to be fault-tolerant using reconfiguration methods. In this case, using a pair of inverters to replicate input signals to expand the connected domain is an effective solution. By turning on nanodiodes ④ and ⑤, unit F can implement a logical function equivalent to g1. At this time, turning on nanodiode ⑥ allows the g1 signal copied to unit F to be transmitted normally to unit C, realizing the correct logic g3=g1+g2. The equivalent path after fault tolerance is as follows: Figure 4As shown in (b), since a pair of inverters are inserted between the original connection edge e(g1,g3), it means that the logic level of g1 is increased by two levels. If the margin S(e(g1,g3)) of the connection edge e(g1,g3) is less than 3, it will inevitably lead to the deterioration of the delay of the mapping circuit.

[0007] Figure 5 (a) in the figure is a traditional fault tolerance example for the erroneous logic caused by two normally closed defects. For the short circuit defect caused by a single normally closed defect, considering that there is no logical connection relationship between logic gates g2 and g3, a reconfiguration method is selected to remap g2 to the defect-free unit H, so that g3 can achieve the correct logical function. The equivalent connection relationship after fault tolerance is as follows: Figure 5 As shown in (b), remapping can maintain the original signal path while ensuring the correct logic.

[0008] For the propagation paths caused by multiple normally closed defects, the false path principle needs to be used to block the error signal. Select an unmapped unit I to invert the error signal, so that units G and I form g5 and g5 as a pair of complementary signals, which are transmitted to unit E together. Then the logic implemented on unit E becomes E=g5+g5=0, and the influence of the error signal g5 is eliminated in the input signal of unit D. The equivalent connection relationship after fault tolerance is as follows Figure 5 As shown in (b) in the figure. Note that although the false path eliminates the erroneous logic, the transmission path from unit E to unit D still exists, and the premise for unit E to achieve the output of the 0 signal is that the complementary signal of g5 is correctly generated. Therefore, the signal arrival time of the 0 signal is higher than that of g5 and g5, which means that the logic level of g6 is: L(g6)>L(0)>L(g5)+1. If S(e(g5,g6))<3, this blocking method will affect the logic level of g6, thereby worsening the delay of the mapping circuit.

[0009] At present, in the practical development of nano-CMOS circuits, there are very few considerations for both defect tolerance and performance optimization. Considering that delay is an important indicator for measuring the performance of integrated circuits, how to map logic circuits to defective nano-CMOS circuits, reduce the number of additional occupied units while ensuring the impact of defects on the logical function of the mapped circuit, and optimize the delay of the mapped circuit are key issues related to the development of the practical process of nano-integrated circuits. Summary of the invention

[0010] The technical problem to be solved by the present invention is to provide a nano-CMOS circuit fault-tolerant mapping method that can optimize the delay under the mapping constraints of defective nano-CMOS circuits, aiming at the problems of poor delay performance, poor solution speed and quality in nano-CMOS circuits that use existing fault-tolerant mapping methods to achieve correct logical functions. The fault-tolerant mapping method of the present invention optimizes the mapping process of traditional nano-CMOS circuits, adds a logical-level division technology for logical circuits to be mapped and a physical-level pre-planning technology based on original inputs, maps the logical circuits to the pre-planned areas in the nano-CMOS circuits in units of path trees using two mapping modes to optimize the delay of each path, and improves the mapping success rate by finding available defective units, and optimizes the delay performance of the delay mapping circuit on the basis of quickly eliminating the influence of defects on the logical functions of the nano-CMOS circuits.

[0011] The technical solution adopted by the present invention to solve the above technical problems is: a nano-CMOS circuit fault tolerance mapping method capable of optimizing delay, comprising the following steps:

[0012] Step 1: For a to-be-mapped or non-logic circuit including M original inputs PI and N original outputs PO, the maximum number of logic gates experienced in all paths from any original input PI of the logic circuit to logic gate g is defined as the logic level of logic gate g, denoted as L(g), and the signal arrival time of logic gate g can be quantified as this value; the maximum number of logic gates experienced in all original outputs PO of the logic circuit is defined as the delay CD of the logic circuit; the maximum number of logic gates experienced in all paths from any original output PO of the logic circuit to logic gate g is defined as the inverse logic level of logic gate g, denoted as IL(g); the difference between the delay CD of the logic circuit and the inverse logic level IL(g) of logic gate g is defined as the signal completion time of logic gate g, denoted as RL(g);

[0013] Step 2: The logical connection edge between two logic gates g and g' that are connected is represented as e(g,g'), where g' is the output logic gate of g and g is the input logic gate of g'; the difference between the signal completion time of logic gate g' and the signal arrival time of its input logic gate g is defined as the margin of the logical connection edge e(g,g'), which is recorded as S(e(g,g'))=RL(g')-L(g), which represents the minimum number of logic gates that can be inserted into the logical connection edge e(g,g') and cause circuit delay degradation;

[0014] If the margin of any logical connection edge e(g,g') is equal to 1, that is, S(e(g,g'))=1, the logical connection edge is defined as a critical edge; if the margin of any logical connection edge e(g,g') is equal to 2, that is, S(e(g,g'))=2, the logical connection edge is defined as a sub-critical edge; if the margin of any logical connection edge e(g,g') is neither equal to 1 nor equal to 2, the logical connection edge is defined as a general connection edge; if any logic gate g satisfies L(g)=RL(g), the logic gate is defined as a critical gate; if any logic gate g satisfies RL(g)-L(g)=1, the logic gate is defined as a sub-critical gate;

[0015] Step 3: Define the path tree as a sub-logic network consisting of n logic gates, each input of the sub-logic network consists of a PI or logic gate, and the output of the sub-logic network is a PO, which is defined as the root logic gate;

[0016] The path tree with PO as the root logic gate is called PO path tree; the path tree with the logic level of the root logic gate equal to CD is defined as the critical path tree, the path tree with the logic level of the root logic gate equal to CD-1 is defined as the sub-critical path tree, and the path tree with the logic level of the root logic gate less than CD-1 is defined as the general path tree;

[0017] Step 4: The correlation between the logic gate g and its output logic gate g', OutputCriticality(g,g'), depends on the margin of the logical connection edge e(g,g'):

[0018]

[0019] Assign logic gate g to PO i The cost of the path tree generated Partitioncost (PO i ) is defined as not existing in PO i The correlation degree of the output logical connection edge in the path tree |E differ (PO i )|with the existence in PO i The correlation degree E of the output logical connection edge in the path tree same (PO i )|Difference:

[0020] Patitioncost(PO i )=|E differ (PO i )|-|E same (PO i )| (2)

[0021] Among them, |E differ (PO i )| indicates that the output of logic gate g is assigned to POi Path tree and logic gate g is not assigned to PO i In the case of a path tree, the sum of the associations of the corresponding output logical connection edges; |E same (PO i )| indicates that the logic gate g and its output logic gate g' are assigned to PO i In the case of a path tree, the sum of the associations of the corresponding output logical connection edges;

[0022] Step 5: For the to-be-mapped OR-NO logic circuit containing M original inputs PI and N original outputs PO, a breadth search algorithm is used to calculate the probability that any logic gate g is assigned to different POs by using equations (1) and (2). i The cost of the path tree, select the PO corresponding to the minimum cost i Path tree, assigning logic gate g to the PO i Path tree: traverse all logic gates in the NOR logic circuit in the order from output to input, and complete the division of N path trees;

[0023] Step 6: Signal tightness ST of any original input PI to any original output PO PIPO The earliest signal arrival time of the longest path in the original input PI added to the PO path tree is expressed. The earliest signal arrival time can be quantified as the logic level of the logic gate in the longest path:

[0024] ST PIPO =CD-minL(g|g∈LongestPath(PO)&PI∈In(g)) (3)

[0025] Among them, g∈LongestPath(PO) means that the logic gate g is located on the longest path in the PO path tree, and PI∈In(g) means that the signal of the original input PI can be transmitted to the logic gate g;

[0026] Step 7: Among the K path trees, select the PO containing the most logic gates. k The original input PI with the highest signal density in the critical path tree i Construct a one-dimensional array for the center;

[0027] According to PO k The critical path tree contains m PI pairs PO k In the order of decreasing signal density, m PIs are added to the one-dimensional array in a divergent manner from the center of the one-dimensional array to both ends, where m <M;

[0028] For the remaining K-1 path trees, the signal density of the PIs contained in the K-1 path trees to the root logic gates PO of the path trees is calculated in batches according to the descending order of the logic level of the root logic gates; the PIs in each batch are added to both ends of the one-dimensional array in the descending order of signal density;

[0029] Mapping the sorted M PIs to defect-free nano-CMOS cells at the boundary of the nano-CMOS circuit;

[0030] Step 8: Prioritize the mapping of logic gates within the sub-critical path tree and the critical path tree according to the increasing order of logic level:

[0031] Step 8-1: Traverse all logic gates on any logic level L1 in the sub-critical path tree and the critical path tree, and for any logic gate g i , judge g in turn i The input logic gate g i " and output logic gate g i 'Whether there is a connected domain intersection between the mapped nano-CMOS units, if there is a connected domain intersection ∨ (C i ), then go to step 10; if there is no connected domain intersection, then the logic gate g i Randomly map to g i "The mapped unit is connected to an unmapped nano-CMOS unit in the domain;

[0032] Step 8-2: loop step 8-1, traverse all logic levels in the sub-critical path tree and the critical path tree, until all logic gates on all logic levels in the sub-critical path tree and the critical path tree are mapped, and go to step 11;

[0033] Step 9: If the mapping of logic gates in the sub-critical path tree and the critical path tree has been completed, hierarchical mapping of logic gates on the logic level in the general path tree is performed according to the increasing order of logic level:

[0034] Step 9-1: Traverse all logic gates on any logic level L2 in the general path tree, for any logic gate g j , judge g in turn j The input logic gate g j " and output logic gate g j 'Whether there is a connected domain intersection between the mapped nano-CMOS units, if there is a connected domain intersection ∨ (C j ), then go to step 10; if there is no connected domain intersection, then the logic gate g j Randomly map to g j "The mapped unit is connected to an unmapped nano-CMOS unit in the domain;

[0035] Step 9-2: loop step 9-1, traverse all logic levels in the general path tree, until all logic gates on all logic levels in the general path tree are mapped, and go to step 11;

[0036] Step 10: Find a mappable unit in the connected domain intersection ∨(C) for the logic gate g to be mapped:

[0037] For the logic gate g to be mapped, if there is a normally closed defective unit A in the intersection of the connected domains ∨(C), then for the unit B with a normally closed defect between the normally closed defective unit A, determine whether there is a connection relationship between the logic gate mapped on the unit B and the logic gate g; if there is no connection relationship, the normally closed defective unit A is discarded, and any nano-CMOS unit without a normally closed defect in ∨(C) is selected as the mappable unit of the logic gate g; if there is a connection relationship, the normally closed defective unit A is used as the mappable unit of the logic gate g, and a low logic level complementary signal is used for defect isolation;

[0038] If there is no normally closed defective unit in the connected domain intersection ∨(C), then any nano-CMOS unit without normally closed defect in ∨(C) is selected as the mappable unit of logic gate g;

[0039] Step 11: Determine whether there are errors in the currently mapped logic gates, and use the bad function to calculate:

[0040]

[0041] in:

[0042] r represents the radius of the connected domain, g and g' represent the mapped logic gates, and there is a logical connection edge between g' and g;

[0043] c i and p(g) denotes a nano-CMOS cell, where p(g) is the cell mapped by logic gate g;

[0044] It represents the sum of the cases where there are normally closed defects between all units in the connected domain of the unit p(g) mapped by the logic gate g and p(g); if there is a normally closed defect, then Represents the sum of the average fan-in and fan-out of the logic gates of the logic circuit;

[0045] It represents the sum of the cases where the connectivity constraint is not satisfied between the mapped logic gates g and the units mapped by g'; if the connectivity constraint is violated and the logical connection edge between the logic gates g' and g is a secondary critical edge or a critical edge, then If the connectivity constraint is violated and the logical connection edge between logic gates g' and g is a general connection edge, then U g',g =1;

[0046] After all logic gates have been mapped and judged, go to step 12;

[0047] Step 12: Use the taboo search algorithm to perform neighborhood disturbance fault tolerance on the logic gates in the sub-critical path tree and the critical path tree for 200 iterations; perform neighborhood disturbance fault tolerance on the logic gates in the general path tree for 50 iterations;

[0048] For the selected fault-tolerant mapping unit, search for replaceable nano-CMOS units within the connected domain of the mapped nano-CMOS unit; establish a unit set as a candidate table for storing all replacement units; calculate the cost value of each candidate unit in the candidate table after exchange, and select the unit with the smallest cost value for exchange. The cost function is expressed as;

[0049]

[0050] in:

[0051] badness g represents the bad function value of logic gate g;

[0052] p(g) represents the mapping unit of logic gate g; wire p(g) is the length of the interconnection line between the logic gate g and the unit mapped by its output logic gate;

[0053] N represents the total number of mapped logic gates;

[0054] When the number of iterations is reached or there is no erroneous mapping in the mapping result, the taboo search algorithm stops perturbing. If the erroneous mapping still exists, the inverter pair insertion method is used to expand the connected domain of the unconnectable path for fault tolerance, and then go to step 13;

[0055] Step 13: Update the connection relationship for the mapping result;

[0056] Starting from the mapping unit of the original input PI, along the directional signal path connected by the conductive nanodiodes between the units, one mapping unit in the nano-CMOS circuit corresponds to a NOR logic gate, and the conductive nanodiodes between the units correspond to the logic connection edges. The mapping result is updated to an equivalent circuit composed of logic gates.

[0057] For the logic gates in the equivalent circuit, the margins of the logic levels and logic connection edges are calculated; if the margins of the logic levels and logic connection edges of each logic gate change after the calculation, and there are newly added sub-critical gates or critical gates, then the path tree where the newly added sub-critical gates or critical gates are located is updated accordingly and added as a sub-critical path tree or a critical path tree, and for the newly added sub-critical path tree or critical path tree, go to step 8 to perform priority mapping; if the margins of the logic levels and logic connection edges of each logic gate do not change after the calculation, go to step 9 to perform hierarchical mapping.

[0058] Compared with the prior art, the present invention has the following advantages:

[0059] 1. The nano-CMOS circuit fault-tolerant mapping method capable of optimizing delay of the present invention combines the logic circuit partitioning technology, and firstly divides the logic circuit into a path tree according to the logic gates and logic connection edges according to the degree of delay influence on the mapped or non-logic circuit, and adds the logic circuit partitioning technology suitable for delay performance optimization on the basis of the traditional optimization only in the mapping process;

[0060] 2. The auxiliary pre-planning technology of the present invention sorts the input of each path tree, pre-plans the mappable area for each path tree, and sets the mappable area at the physical level, thereby increasing the space for optimizing the mapping performance;

[0061] 3. In nano-CMOS circuits with known defect distribution, the utilization conditions of each unit are analyzed, and the idea of ​​path-by-path hierarchical mapping is adopted. Two mapping modes, namely priority mapping and hierarchical mapping, are used in the mapping from the logical level to the physical level to achieve the matching of the fault-tolerant method with the logical connection edges with different margins. While improving the unit utilization, the number of units that affect the mapping circuit path and the mapping area are reduced, ensuring the optimization of the mapping performance;

[0062] 4. In the mapping of normally closed defective cells, different from the traditional method of randomly selecting defect blocking signals, the present invention uses specific low-logic-level logic gates to form complementary signals for defect blocking in the mapping process of any defective cell, i.e., a directional mapping method, which has a certain improvement effect on the number of cells in the signal transmission path in the mapped nano-CMOS circuit;

[0063] 5. The present invention improves the fault-tolerant mapping process of traditional nano-CMOS circuits. The conversion of the representation form of the logic circuit to be mapped and the change of the specific mapping ideas are all conducive to the optimization of the delay of the mapping circuit. At the same time, more defective units are used to improve the mapping success rate, simplify the circuit fault tolerance complexity, and achieve the optimization of the delay performance of the mapped nano-CMOS circuit on the basis of ensuring the correctness of the logical function. BRIEF DESCRIPTION OF THE DRAWINGS

[0064] Figure 1 This is a cross-sectional view of the nano-CMOS circuit structure;

[0065] Figure 2 (a) is a schematic diagram of the normally-on defect of a nanodiode in a 3×2 nano-CMOS circuit structure;

[0066] Figure 2 (b) in Figure 2 Equivalent path diagram of the mapping result of the nano-CMOS circuit shown in (a);

[0067] Figure 3 (a) is a schematic diagram of the normally closed defect of a nano diode in a 4×3 nano CMOS circuit structure;

[0068] Figure 3 (b) in Figure 3 Equivalent path diagram of the mapping result of the nano-CMOS circuit shown in (a);

[0069] Figure 4 (a) is a schematic diagram of two fault-tolerance methods for a 3×2 normally-on defect nano-CMOS circuit;

[0070] Figure 4 (b) is the equivalent path diagram of two fault tolerance methods for a 3×2 normally-on defect nano-CMOS circuit;

[0071] Figure 5 (a) is a schematic diagram of two fault-tolerance methods for a 4×3 normally-off defect nano-CMOS circuit;

[0072] Figure 5 (b) is an equivalent path diagram of two fault-tolerance methods for a 4×3 normally-off defect nano-CMOS circuit;

[0073] Figure 6 This is the schematic diagram of the s27 circuit in the ISCAS'89 benchmark circuit;

[0074] Figure 7 (a) is for Figure 6 Schematic diagram of the directed fault tolerance method for a normally-off defect nano-CMOS circuit of size 4×3;

[0075] Figure 7 (b) in Figure 6 The equivalent path diagram of the directed fault tolerance method for a 4×3 size normally-off defect nano-CMOS circuit is shown. DETAILED DESCRIPTION

[0076] The present invention is further described in detail below with reference to the accompanying drawings.

[0077] Embodiment 1: Figure 6 Taking the s27 circuit in the ISCAS'89 benchmark circuit as an example, the method of the present invention is used to perform fault-tolerant mapping.

[0078] According to the topological sorting, the s27 circuit contains 7 original inputs, 3 original outputs O0, O1, O2, and 12 logic gates. According to the original outputs O0, O1, O2, 3 path trees PO0, PO1, and PO2 can be established. The logic gates g corresponding to O1 and O2 are 18 and g 19The logic level is the highest, L(g 18 )=L(g 19 )=7, so there are two critical path trees, g 11 , g 18 and g 19 are the root logic gates of the three path trees respectively. The division method of the three path trees includes the following steps:

[0079] Step ①: Calculate the logic gate g located in L6 using the breadth search algorithm in descending order of logic level 17 The correlation degree with its output logic gate, where it is calculated according to formula (1) According to formula (2), we can get the value of logic gate g 17 The costs assigned to the path trees PO0, PO1 and PO2 are: Patitioncost(O0) = |E differ (O0)|-|E same (O0)|=1-0=1,Patitioncost(O1)=Patitioncost(O2)=|E differ (O2)|-|E same (O2)|=0-1=-1;

[0080] So the logic gate g 17 You can choose to allocate it in either PO1 or PO2 path tree. Here, choose to allocate it to PO1.

[0081] Step ②: Similarly, in L5, L4, L3 and L2, place the logic gate with a unique output logic gate in the path tree where its output logic gate is located;

[0082] Step ③: In L1, logic gate g8 has two output logic gates g 11 and g 13 , the corresponding logical connection edge margins are S(e(g8,g 11 ))=RL(g 11 )-L(g8)=7-1=6、S(e(g8,g 13 ))=2, then the correlation degree of the two output logical connection edges can be calculated according to formula (1) as Then assign logic gate g8 to g 11 The cost of the path tree PO0 can be calculated according to formula (2): Assign to g 13 The cost of the path tree PO1 is calculated as Therefore, the case with the lowest cost is selected, and logic gate g8 is assigned to path tree PO1;

[0083] Step ④: Logic gate g10 There is an output logic gate g 19 , So the logic gate g 10 Can be assigned to logic gate g 19 In the path tree PO2;

[0084] The other logic gates in L1 and the original inputs i1-i4, i6-i7 have only one output logic gate. These logic gates and the original inputs are directly configured in the path tree where their output logic gates are located;

[0085] Step ⑤: In L0, i5 has two output logic gates g 12 and g 10 , calculate the association degree of its output logical connection edge according to formula (1): According to formula (2), the cost of assigning i5 to path trees PO1 and PO2 is: Select to assign i5 to path tree PO1;

[0086] At this point, the path tree is split and the logic circuit is split into {i2,i3,i4,i5,i6,i7,g9,g8,g 12 ,g 13 ,g 14 ,g 15 ,g 16 ,g 17 ,g 18}、{i1,g 11} and {g 10 ,g 19}Three path trees.

[0087] The path tree with the most logic gates in the s27 circuit is the PO1 path tree, in which the longest path is the solid line from i4 to g. 18 The original input PIs are sorted and pre-mapped for the segmented logic circuits, and the influence of each original input PI on the PO path is determined according to formula (3), which specifically includes the following steps:

[0088] Step ⑥: Calculate each PI to g according to formula (3) 18 The degree of signal impact:

[0089] i4, i6 and i7 have only one logic output gate, and their output logic gates g9, g 14 and g 17 All are in the longest path, so i4, i6 and i7 have no effect on g 18 The signal influence degrees are and

[0090] i1 has no signal connection with the PO1 path tree, so it has no influence. i5 has two output logic gates, which are located in different path trees. When calculating its influence on the PO1 path tree, we only need to calculate its output logic gate g on the longest path. 12 The inverse logic level:

[0091] The direct output logic gate of i2 and i3 is g8 which is not in the longest path. The output logic gate of g8 is g 13 In the longest path, so g 13 is the longest path logic gate that can receive the i2 and i3 signals,

[0092] Step 7: Create a one-dimensional array [*,i4,*] centered on the PI with the largest signal correlation, and record each PI in the one-dimensional array in descending order of signal density, then we have [*,i2,i3,i4,i5,i6,i7];

[0093] Step ⑧: For the unsorted i1 and the PO0 path tree to which i1 belongs, the longest path of the PO0 path tree is {i1, g 11}, where g 11 It can also receive output signals from i2 and i3, so i1 should be arranged on the side of i2 and i3, and the final PI sorting order is: [i0,i1,i2,i3,i4,i5,i6,i7].

[0094] Special utilization and fault tolerance strategies need to be adopted for defective cells in sub-path mapping to prevent delay degradation. Figure 7 (a) is for Figure 6 The schematic diagram of the directional fault tolerance method for the normally closed defect nano CMOS circuit of size 4×3 is shown. Figure 7 (b) in Figure 6 The equivalent path diagram of the directed fault tolerance method for a 4×3 size normally-off defect nano-CMOS circuit is shown. Figure 7 The nano-CMOS circuit structure shown in (a) includes 12 nano-CMOS units, of which units A and C are mapped by logic gates g1 and g3 respectively. Units J, H, F, G, and D are mapped by i2, g2, g4, g5, and g6 respectively. The input nanowire of unit D can receive the output signal g4 of unit F through the programmable nanodiode, but the normally closed defective nanodiode ② will turn on the short-circuit path from unit E to unit D, and at the same time, the normally closed defective nanodiode ③ will turn on the short-circuit path from unit G to unit E, so there is a propagation path from unit G to unit D. If the defect propagation signal cannot be correctly blocked, the logical correctness and delay of the mapping circuit cannot be guaranteed. For Figure 7The directional fault tolerance method for normally-off defect nano-CMOS circuit shown in (a) includes the following steps:

[0095] Step ⑨: Record the logic level of the logic gate g6 mapped by the nano-CMOS unit D at the output end of the propagation path;

[0096] Step ⑩: Find whether there is a complementary signal with a logic level lower than g6 in the input connection domain of the nano-CMOS unit E. If there is an existing complementary signal (such as unit J and unit H), directly turn on the nano-diodes ④ and ⑤ so that unit J and unit H serve as the direct input of unit E; if there is no complementary signal, select any logic gate with a logic level lower than g6, invert its signal to form a new complementary signal, and use the new complementary signal as the input of unit E, so as to block the error signal g5 without affecting the logic delay of g6.

Claims

1. A nanometer CMOS circuit fault-tolerant mapping method capable of optimizing delay, characterized in that: The following steps are involved: Step 1: For a to-be-mapped or non-logic circuit including M original inputs PI and N original outputs PO, the maximum number of logic gates passed through in all paths from any original input PI of the logic circuit to logic gate g is defined as the logic level of logic gate g, denoted as L(g), and the signal arrival time of logic gate g can be quantified as this value; the maximum number of logic gates passed through in all original outputs PO of the logic circuit is defined as the delay CD of the logic circuit; The maximum number of logic gates in all paths from any original output PO of the logic circuit to the logic gate g is defined as the inverse logic level of the logic gate g, recorded as IL(g); the difference between the delay CD of the logic circuit and the inverse logic level IL(g) of the logic gate g is defined as the signal completion time of the logic gate g, recorded as RL(g); Step 2: The logical connection edge between two logic gates g and g' that are connected is represented as e(g,g'), where g' is the output logic gate of g and g is the input logic gate of g'; the difference between the signal completion time of logic gate g' and the signal arrival time of its input logic gate g is defined as the margin of the logical connection edge e(g,g'), which is recorded as S(e(g,g'))=RL(g')-L(g), which represents the minimum number of logic gates that can be inserted into the logical connection edge e(g,g') and cause circuit delay degradation; If the margin of any logical connection edge e(g,g') is equal to 1, that is, S(e(g,g'))=1, the logical connection edge is defined as a critical edge; if the margin of any logical connection edge e(g,g') is equal to 2, that is, S(e(g,g'))=2, the logical connection edge is defined as a sub-critical edge; if the margin of any logical connection edge e(g,g') is neither equal to 1 nor equal to 2, the logical connection edge is defined as a general connection edge; if any logic gate g satisfies L(g)=RL(g), the logic gate is defined as a critical gate; if any logic gate g satisfies RL(g)-L(g)=1, the logic gate is defined as a sub-critical gate; Step 3: Define the path tree as a sub-logic network consisting of n logic gates, each input of the sub-logic network consists of a PI or logic gate, and the output of the sub-logic network is a PO, which is defined as the root logic gate; The path tree with PO as the root logic gate is called PO path tree; The path tree whose root logic gate has a logic level equal to CD is defined as a critical path tree, the path tree whose root logic gate has a logic level equal to CD-1 is defined as a sub-critical path tree, and the path tree whose root logic gate has a logic level less than CD-1 is defined as a general path tree; Step 4: The correlation degree OutputCriticality(g,g') between the logic gate g and its output logic gate g' depends on the margin of the logical connection edge e(g,g'): Assign logic gate g to PO i The cost of the path tree generated Partitioncost (PO i ) is defined as not existing in PO i The correlation degree of the output logical connection edge in the path tree |E differ (PO i )|with the existence in PO i The correlation degree of the output logical connection edge in the path tree |E same (PO i )|Difference: Partition cost(PO i )=|E differ (PO i )|-|E same (PO i )| (2) Among them, |E differ (PO i )| indicates that the output of logic gate g is assigned to PO i Path tree and logic gate g is not assigned to PO i In the case of a path tree, the sum of the associations of the corresponding output logical connection edges; |E same (PO i )| indicates that the logic gate g and its output logic gate g' are assigned to PO i In the case of a path tree, the sum of the associations of the corresponding output logical connection edges; Step 5: For the to-be-mapped OR-NO logic circuit containing M original inputs PI and N original outputs PO, a breadth search algorithm is used to calculate the probability that any logic gate g is assigned to different POs by using equations (1) and (2). i The cost of the path tree, select the PO corresponding to the minimum cost i Path tree, assigning logic gate g to the PO i Path tree: traverse all logic gates in the NOR logic circuit in the order from output to input, and complete the division of N path trees; Step 6: Signal tightness ST of any original input PI to any original output PO PIPO The earliest signal arrival time of the longest path in the original input PI added to the PO path tree is expressed. The earliest signal arrival time can be quantified as the logic level of the logic gate in the longest path: ST PIPO =CD-minL(g|g∈LongestPath(PO)&PI∈In(g)) (3) Among them, g∈LongestPath(PO) means that the logic gate g is located on the longest path in the PO path tree, and PI∈In(g) means that the signal of the original input PI can be transmitted to the logic gate g; Step 7: Among the K path trees, select the PO containing the most logic gates. k The original input PI with the highest signal density in the critical path tree i Construct a one-dimensional array for the center; According to PO k The critical path tree contains m PI pairs PO k In the order of decreasing signal density, m PIs are added to the one-dimensional array in a divergent manner from the center of the one-dimensional array to both ends, where m <M; For the remaining K-1 path trees, the signal density of the PIs contained in the K-1 path trees to the root logic gates PO of the path trees is calculated in batches according to the descending order of the logic level of the root logic gates; the PIs in each batch are added to both ends of the one-dimensional array in the descending order of signal density; Mapping the sorted M PIs to defect-free nano-CMOS cells at the boundary of the nano-CMOS circuit; Step 8: Prioritize the mapping of logic gates within the sub-critical path tree and the critical path tree according to the increasing order of logic level: Step 8-1: Traverse all logic gates on any logic level L1 in the sub-critical path tree and the critical path tree, and for any logic gate g i , judge g in turn i The input logic gate g i " and output logic gate g i 'Whether there is a connected domain intersection between the mapped nano-CMOS units, if there is a connected domain intersection ∨ (C i ), then go to step 10; if there is no connected domain intersection, then the logic gate g i Randomly map to g i "The mapped unit is connected to an unmapped nano-CMOS unit in the domain; Step 8-2: loop step 8-1, traverse all logic levels in the sub-critical path tree and the critical path tree, until all logic gates on all logic levels in the sub-critical path tree and the critical path tree are mapped, and go to step 11; Step 9: If the mapping of logic gates in the sub-critical path tree and the critical path tree has been completed, hierarchical mapping of logic gates on the logic level in the general path tree is performed according to the increasing order of logic level: Step 9-1: Traverse all logic gates on any logic level L2 in the general path tree, for any logic gate g j , judge g in turn j The input logic gate g j " and output logic gate g j 'Whether there is a connected domain intersection between the mapped nano-CMOS units, if there is a connected domain intersection ∨ (C j ), then go to step 10; if there is no connected domain intersection, then the logic gate g j Randomly map to g j "The mapped unit is connected to an unmapped nano-CMOS unit in the domain; Step 9-2: loop step 9-1, traverse all logic levels in the general path tree, until all logic gates on all logic levels in the general path tree are mapped, and go to step 11; Step 10: Find a mappable unit in the connected domain intersection ∨(C) for the logic gate g to be mapped: For the logic gate g to be mapped, if there is a normally closed defective unit A in the intersection of the connected domains ∨(C), then for the unit B with a normally closed defect between the normally closed defective unit A, determine whether there is a connection relationship between the logic gate mapped on the unit B and the logic gate g; if there is no connection relationship, the normally closed defective unit A is discarded, and any nano-CMOS unit without a normally closed defect in ∨(C) is selected as the mappable unit of the logic gate g; if there is a connection relationship, the normally closed defective unit A is used as the mappable unit of the logic gate g, and a low logic level complementary signal is used for defect isolation; If there is no normally closed defective unit in the connected domain intersection ∨(C), then any nano-CMOS unit without normally closed defect in ∨(C) is selected as the mappable unit of logic gate g; Step 11: Determine whether there are errors in the currently mapped logic gates, and use the bad function to calculate: in: r represents the radius of the connected domain, g and g' represent the mapped logic gates, and there is a logical connection edge between g' and g; c i and p(g) denotes a nano-CMOS cell, where p(g) is the cell mapped by logic gate g; It represents the sum of the cases where there are normally closed defects between all units in the connected domain of the unit p(g) mapped by the logic gate g and p(g); if there is a normally closed defect, then Represents the sum of the average fan-in and fan-out of the logic gates of the logic circuit; It represents the sum of the cases where the connectivity constraint is not satisfied between the mapped logic gates g and the units mapped by g'; if the connectivity constraint is violated and the logical connection edge between the logic gates g' and g is a secondary critical edge or a critical edge, then If the connectivity constraint is violated and the logical connection edge between logic gates g' and g is a general connection edge, then U g',g =1; After all logic gates have been mapped and judged, go to step 12; Step 12: Use the taboo search algorithm to perform neighborhood disturbance fault tolerance on the logic gates in the sub-critical path tree and the critical path tree for 200 iterations; perform neighborhood disturbance fault tolerance on the logic gates in the general path tree for 50 iterations; For the selected fault-tolerant mapping unit, search for replaceable nano-CMOS units within the connected domain of the mapped nano-CMOS unit; establish a unit set as a candidate table for storing all replacement units; calculate the cost value of each candidate unit in the candidate table after exchange, and select the unit with the smallest cost value for exchange. The cost function is expressed as; in: badness g represents the bad function value of logic gate g; p(g) represents the mapping unit of logic gate g; wire p(g) is the length of the interconnection line between the logic gate g and the unit mapped by its output logic gate; N represents the total number of mapped logic gates; When the number of iterations is reached or there is no erroneous mapping in the mapping result, the taboo search algorithm stops perturbing. If the erroneous mapping still exists, the inverter pair insertion method is used to expand the connected domain of the unconnectable path for fault tolerance, and then go to step 13; Step 13: Update the connection relationship for the mapping result; Starting from the mapping unit of the original input PI, along the directional signal path connected by the conductive nanodiodes between the units, one mapping unit in the nano-CMOS circuit corresponds to a NOR logic gate, and the conductive nanodiodes between the units correspond to the logic connection edges. The mapping result is updated to an equivalent circuit composed of logic gates. For the logic gates in the equivalent circuit, the margins of the logic levels and logic connection edges are calculated; if the margins of the logic levels and logic connection edges of each logic gate change after the calculation, and there are newly added sub-critical gates or critical gates, then the path tree where the newly added sub-critical gates or critical gates are located is updated accordingly and added as a sub-critical path tree or a critical path tree, and for the newly added sub-critical path tree or critical path tree, go to step 8 to perform priority mapping; if the margins of the logic levels and logic connection edges of each logic gate do not change after the calculation, go to step 9 to perform hierarchical mapping.

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