Semiconductor structure and method for forming the same

Abstract

A semiconductor structure and a method for forming the same, the method comprising: providing a layer to be etched, the surface of the layer to be etched having a liner layer; forming a plurality of mutually separate first mask structures on the surface of the liner layer; using the first mask structure as a mask, etching the layer to be etched and the liner layer, forming a groove in the layer to be etched, and making the first mask structure form a first initial layer to be removed; performing a modification process on the first initial layer to be removed to form a first layer to be removed; and etching and removing the liner layer and the first layer to be removed. The semiconductor structure formed by the method has good performance.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a semiconductor structure and a method for forming the same. Background Art

[0002] With the advancement of semiconductor manufacturing technology, in order to achieve faster computing speed, larger data storage capacity and more functions, many different methods are used in the existing technology to reduce the feature size (CD) of semiconductor devices to increase the integration density of semiconductor chips. At present, Self-Aligned-Double-Patterning (SADP) and Self-Aligned-Quadra Patterning (SAQP) are gradually being accepted and applied as a solution.

[0003] However, the current graphic accuracy of the self-aligned multiple imaging technology is still not high enough, resulting in a poor etching effect in the process of manufacturing semiconductor chips, and thus being unable to meet the demand for higher integration density of semiconductor chips, while also reducing the yield of manufacturing semiconductor devices. Summary of the invention

[0004] The technical problem solved by the present invention is to remove the residues formed in the self-aligned double imaging technology and the self-aligned quadruple imaging technology, avoid the influence of the residues on the pattern accuracy during the manufacturing process, and improve the etching effect and the yield rate of manufacturing semiconductor devices.

[0005] To solve the above technical problems, an embodiment of the present invention provides a semiconductor structure, including: providing a layer to be etched, wherein the surface of the layer to be etched has a liner layer; forming a plurality of mutually discrete first mask structures on the surface of the liner layer; using the first mask structure as a mask, etching the layer to be etched and the liner layer, forming a groove in the layer to be etched, and making the first mask structure form a first initial layer to be removed; performing a modification process on the first initial layer to be removed to form a first layer to be removed; and etching away the liner layer and the first layer to be removed.

[0006] Optionally, the etching process for removing the first layer to be removed has a first etching rate for the material of the first layer to be removed, the etching process for removing the first layer to be removed has a second etching rate for the material of the first initial layer to be removed, and the first etching rate is greater than the second etching rate.

[0007] Optionally, the first mask structure includes a first mask layer located on the surface of the liner layer and a second mask layer located on the surface of the liner layer, and a thickness of the first mask layer is greater than a thickness of the second mask layer.

[0008] Optionally, while etching the layer to be etched and the pad layer, the first mask structure is etched until the surface of the pad layer at the bottom of the second mask layer is exposed, and a first initial layer to be removed is formed on the surface of the pad layer; the method for forming the first mask structure includes: forming a plurality of mutually discrete first sacrificial layers on the surface of the pad layer; forming a first mask structure material layer on the surface of the first sacrificial layer and the surface of the pad layer exposed between the plurality of first sacrificial layers; forming a first protective layer on the first mask structure material layer formed on the surface of the pad layer; after forming the first protective layer, etching the first mask structure material layer to form the first mask structure; after forming the first mask structure, removing the first protective layer and the first sacrificial layer.

[0009] Optionally, the method for forming the first protective layer includes: forming a first protective material layer on a first mask structure material layer formed on the surface of the liner layer; and etching the first protective material layer to form the first protective layer.

[0010] Optionally, the first mask structure further includes: the second mask layer and two first mask layers respectively located on both sides of the second mask layer, and the second mask layer connects the two first mask layers.

[0011] Optionally, it also includes: after forming the first layer to be removed and before removing the liner layer and the first layer to be removed, forming a second protective layer on the exposed surface of the layer to be etched, the surface of the second protective layer is higher than or flush with the contact surface between the layer to be etched and the liner layer.

[0012] Optionally, the method for forming the second protective layer in the groove includes: using a spin coating process to form an initial second protective layer in the groove, on the exposed surface of the liner layer and on the surface of the first layer to be removed, and etching back the initial second protective layer until the surface of the initial second protective layer is higher than or flush with the surface of the layer to be etched to form the second protective layer; after removing the liner layer and the first layer to be removed, removing the second protective layer.

[0013] Optionally, the layer to be etched includes: a first layer to be etched and a second layer to be etched, the second layer to be etched has a liner layer on its surface, and the first layer to be etched has the second layer to be etched on its surface.

[0014] Optionally, the method for forming the groove also includes: when etching the layer to be etched and the liner layer, etching the second layer to be etched of the layer to be etched until the surface of the first layer to be etched is exposed; the method for forming the semiconductor structure also includes: after removing the liner layer and the first layer to be removed, etching the first layer to be etched using the second layer to be etched as a mask.

[0015] Optionally, the material of the layer to be removed has one or more of nitrogen-hydrogen bonds, hydrogen-oxygen bonds, or helium-nitrogen bonds.

[0016] Optionally, the material of the first layer to be removed includes one or more of a Si-NH group, a Si-OH group, and a Si-HeN group.

[0017] Optionally, the material of the first mask structure includes one of silicon nitride and silicon nitride oxide.

[0018] Optionally, the modification process is a plasma treatment process.

[0019] Optionally, when the material of the first mask structure includes one of silicon nitride or silicon oxynitride, the parameters of the plasma treatment process include: the gas includes a process gas, and the process gas includes one or more of H2 or He.

[0020] Optionally, the gas further includes a carrier gas, and the carrier gas includes one or both of argon or helium.

[0021] Optionally, the process of removing the liner layer and the first layer to be removed is a wet etching process.

[0022] Optionally, when the material of the liner layer is silicon dioxide, the parameters of the wet etching process include: the solution is a hydrofluoric acid solution.

[0023] Correspondingly, an embodiment of the present invention further provides a semiconductor structure formed by any of the above methods.

[0024] Compared with the prior art, the technical solution of the embodiment of the present invention has the following beneficial effects:

[0025] In the formation method of the embodiment of the present invention, since the first initial layer to be removed is formed after the modification treatment, the first layer to be removed can be removed at the same time as the liner layer. Therefore, the first initial layer to be removed that eventually falls off and remains on the surface of the layer to be etched after the liner layer is removed is reduced, thereby reducing the contamination of the layer to be etched by the first initial layer to be removed, reducing the defects of the semiconductor structure or the reduction of the pattern accuracy caused by the contamination, and improving the yield rate and etching effect.

[0026] Furthermore, since the first etching rate is greater than the second etching rate, the first layer to be etched can be removed faster than the first initial layer to be removed, thereby obtaining a better removal effect.

[0027] Furthermore, since the second protective layer is formed and covers the surface of the layer to be etched, when the liner layer and the first layer to be removed are removed, the exposed surface portion of the layer to be etched is prevented from being removed together, thereby maintaining the graphic accuracy of the layer to be etched.

[0028] Furthermore, since one or more of H2 or He is used as the process gas, when the material of the first initial layer to be removed includes silicon nitride or silicon nitride oxide, the first layer to be removed can be formed by bombarding the first initial layer to be removed with hydrogen ions or helium ions. At this time, after being processed by the plasma process, compared with the first initial layer to be removed, the material of the first layer to be removed obtains higher energy and improves activity, and is therefore more likely to undergo a chemical reaction and be removed.

[0029] Furthermore, since the hydrofluoric acid solution can corrode silicon dioxide and materials having one or more of nitrogen-hydrogen bonds, hydrogen-oxygen bonds, or helium-nitrogen bonds, the hydrofluoric acid solution is used as the acid solution of the wet etching process to simultaneously remove the liner layer and the first layer to be removed. This reduces the first initial layer to be removed that eventually falls off and remains on the surface of the layer to be etched after the liner layer is removed, thereby reducing the contamination of the layer to be etched by the first initial layer to be removed, reducing the defects of the semiconductor structure or the reduction of the pattern accuracy caused by the contamination, and improving the yield rate and etching effect.

[0030] The semiconductor device in the embodiment of the present invention, due to the use of the above-mentioned formation method, obtains a semiconductor device with better etching effect, more precise pattern, fewer defects and higher yield. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Figures 1 to 5 It is a schematic cross-sectional structure diagram of a pattern forming process of a self-aligned multiple patterning technology;

[0032] Figures 6 to 16 is a schematic cross-sectional structure diagram of a semiconductor structure forming process in an embodiment of the present invention;

[0033] Fig.17 It is a schematic cross-sectional structure diagram of a semiconductor structure forming process in another embodiment of the present invention. DETAILED DESCRIPTION

[0034] As described in the background art, it is necessary to improve the pattern accuracy of the current self-aligned multiple imaging technology.

[0035] Figures 1 to 5 The present invention is a schematic diagram of the cross-sectional structure of a pattern forming process of a self-aligned multiple patterning technology.

[0036] Please refer to Figure 1, a liner layer 120 is provided on the layer to be etched 110, a sacrificial material layer (not shown) is formed on the surface of the liner layer 120, and the sacrificial material layer is etched to form a plurality of separate sacrificial layers 130;

[0037] Please refer to Figure 2 A mask material layer (not shown) is deposited on the surface of the liner layer 120 and the surface of the sacrificial layer 130, and the mask material layer is etched to form a mask structure 151. Figure 2 Two mask structures 151 are schematically drawn;

[0038] Please refer to Figure 3 The mask structure 151 includes a first portion 151a and a second portion 151b, wherein the second portion 151b connects two first portions 151a on both sides, and the thickness of the first portion 151a is greater than the thickness of the second portion 151b;

[0039] Please refer to Figure 4 , removing the sacrificial layer 130;

[0040] Please refer to Figure 5 , etching the to-be-etched layer 110 and the liner layer 120 using the mask structure 151 as a mask until the surface of the liner layer 120 at the bottom of the second portion 151 b is exposed to form a patterned etching layer 111;

[0041] However, in the process of forming the etching layer 111, due to the large thickness of the first part 151a, the first part 151a was not completely consumed in the etching process, so residues were formed on the surface of the pad layer 120. After the pad layer 120 was removed, the residues would remain on the surface of the etching layer 111.

[0042] At this time, the residue will become a pollutant, reduce the pattern accuracy of the etching layer, and affect the etching effect; it will also cause defects in the semiconductor structure, resulting in reduced reliability of the semiconductor device or making the semiconductor device become waste, reducing the yield of the semiconductor device.

[0043] To solve the above problems, the technical solution of the present invention provides a semiconductor structure and a method for forming the same, which can remove residues generated during the formation of the semiconductor structure, ensure the pattern accuracy during the pattern transfer process, improve the etching effect, reduce the defects of the semiconductor structure, and improve the reliability and yield of semiconductor devices.

[0044] In order to make the above-mentioned objects, features and beneficial effects of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0045] Figures 6 to 16It is a schematic cross-sectional structure diagram of the semiconductor structure forming process in an embodiment of the present invention.

[0046] Please refer to Figure 6 , providing a layer 200 to be etched, wherein the layer 200 to be etched includes a region A and a region B, and a liner layer 210 is provided on a surface of the layer 200 to be etched.

[0047] In this embodiment, the layer to be etched 200 is a substrate, and the material of the substrate is silicon.

[0048] In another embodiment, the etched layer 200 is a semiconductor substrate, and the material of the semiconductor substrate includes silicon carbide, silicon germanium, a multi-component semiconductor material composed of group III-V elements, silicon on insulator (SOI) or germanium on insulator. Among them, the multi-component semiconductor material composed of group III-V elements includes InP, GaAs, GaP, InAs, InSb, InGaAs or InGaAsP.

[0049] In another embodiment, the layer to be etched 200 includes a first layer to be etched (not shown) and a second layer to be etched (not shown). The second layer to be etched is formed on the surface of the first layer to be etched, and the pad layer is formed on the surface of the second layer to be etched. The first layer to be etched is a semiconductor substrate, and the material of the semiconductor substrate includes silicon carbide, silicon germanium, a multi-element semiconductor material composed of group III-V elements, silicon on insulator (SOI) or germanium on insulator; wherein the multi-element semiconductor material composed of group III-V elements includes InP, GaAs, GaP, InAs, InSb, InGaAs or InGaAsP. The second layer to be etched includes an interconnect wiring layer, an interlayer dielectric layer, a gate material layer or a hard mask layer formed on the first layer to be etched; the material of the interconnect wiring layer includes at least one of tungsten, tungsten silicide, aluminum, titanium and titanium nitride; the material of the interlayer dielectric layer includes a low dielectric constant (k) material or an ultra-low k material; the material of the gate material layer includes one of polysilicon and aluminum; the material of the hard mask layer includes at least one of oxide, undoped silicon glass, silicon on glass, SiON, SiN, SiBN, BN and high-k material, or the hard mask layer is a metal hard mask layer, such as TiO2, titanium nitride, etc.

[0050] In this embodiment, the material of the liner layer 210 is silicon dioxide; the method of forming the liner layer 210 on the surface of the to-be-etched layer 200 is chemical vapor deposition, physical vapor deposition or oxidation process.

[0051] In this embodiment, a plurality of first mask structures are subsequently formed on a portion of the surface of the liner layer 210 in the region A, and the plurality of first mask structures are separated from each other; a plurality of second mask structures are formed on a portion of the surface of the liner layer 210 in the region B, and the plurality of second mask structures are separated from each other. For details on the method of forming the plurality of first mask structures and the plurality of second mask structures, please refer to Figures 7 to 11 .

[0052] Please refer to Figure 7 , forming a first sacrificial material layer (not shown) on the surface of the liner layer 210; etching the first sacrificial material layer using different photolithography patterns in the region A and the region B to form a plurality of mutually discrete first sacrificial layers 220 and a plurality of mutually discrete second sacrificial layers 320.

[0053] In this embodiment, the method of forming the first sacrificial material layer includes chemical vapor deposition, physical vapor deposition or oxidation process. The method of etching the first sacrificial material layer includes dry etching process or wet etching process.

[0054] In this embodiment, the material of the first sacrificial layer 220 and the second sacrificial layer 320 is silicon.

[0055] Please refer to Figure 8 After forming the first sacrificial layer 220 and the second sacrificial layer 320 , a first mask structure material layer 230 is formed to cover the surface of the exposed portion of the liner layer 210 in the region A and the region B, the surface of the first sacrificial layer 220 , and the surface of the second sacrificial layer 320 .

[0056] In this embodiment, the method for forming the first mask structure material layer 230 is a deposition process. For example, the first mask structure material layer 230 covering the surface of the liner layer 210 exposed in the region A and the region B, the surface of the first sacrificial layer 220 and the surface of the second sacrificial layer 320 is formed by an atomic layer deposition process (ALD).

[0057] Please continue to refer to Figure 8 A first protective layer 240 is formed on the surface of the first mask structure material layer 230 , and the first protective layer 240 is located on the surface of the first mask structure material layer 230 formed on the surface of the liner layer 210 portion in the region A.

[0058] In this embodiment, the material of the first protective layer 240 is silicon; the method for forming the first protective layer 240 includes: depositing a first protective material layer (not shown) on the surface of the first mask structure material layer 230 formed on the surface of the liner layer 210; etching the first protective material layer to form the first protective layer 240.

[0059] In this embodiment, the method for etching the first protective material layer is a dry etching process. Specifically, the dry etching process is a plasma etching process.

[0060] In another embodiment, the method for etching the first protective material layer is a wet etching process. Specifically, an etching solution having excellent selectivity to the material of the first protective layer 240 is selected for the wet etching process. For example, when the material of the first protective layer 240 is silicon, an inorganic alkali or an organic alkali solution is used as the etching solution. The inorganic alkali can be KOH, NaOH, NH4OH, etc., and the organic alkali can be a tetramethylammonium hydroxide (TMAH) solution or EDP (including ethylenediamine, hydroquinone and water), etc.

[0061] In this embodiment, in a direction parallel to the surface of the substrate 210, a plurality of the first sacrificial layers 220 (eg Figure 7 The minimum spacing dimension between the side surfaces is D1, and the minimum spacing dimension between the side surfaces of the second sacrificial layer 320 is D2. Figure 7 As shown), D2 is greater than D1.

[0062] Please refer to Fig. 9 and Fig.10 , Fig.10 yes Fig. 9 FIG. 1 is an enlarged schematic diagram of the first mask structure. After forming the first protective layer 240, the first mask structure material layer 230 (eg, Figure 8 As shown in FIG. 1 , a plurality of first mask structures 250 are formed in the region A, and a plurality of second mask structures 350 are formed in the region B.

[0063] Each of the first mask structures 250 includes two first mask layers 251 and one second mask layer 252. The first mask layer 251 and the second mask layer 252 are both located on the liner layer 210 (eg Fig. 9 As shown in the figure, the two first mask layers 251 are respectively located on both sides of the one second mask layer 252, and the second mask layer 252 connects the two first mask layers 251.

[0064] In this embodiment, the material of the first mask structure 250 and the second mask structure 350 includes one of silicon nitride and silicon oxynitride. The method of etching the first mask structure material layer 230 includes: a dry etching process or a wet etching process.

[0065] In another embodiment, the first mask structure material layer 230 is etched by an anisotropic dry etching process to selectively remove the first mask structure material layer 230 in the horizontal direction and retain the first mask structure material layer 230 in the vertical direction to form a plurality of first mask structures 250 and the second mask structure 350 .

[0066] In this embodiment, in a direction perpendicular to the pad layer 210, a dimension from the surface of the first mask layer 251 to the surface of the pad layer 210 is a first thickness H1, and a dimension from the surface of the second mask layer 252 to the surface of the pad layer 210 is a second thickness H2, and the first thickness H1 is greater than the second thickness H2.

[0067] In this embodiment, since one second mask layer 252 connects two first mask layers 251, the first mask structure 250 has a larger width in the direction parallel to the surface of the pad layer 210 than the second mask structure 350, and thus when the to-be-etched layer 200 is subsequently etched using the first mask structure 250 as a mask, an etched pattern with a larger line width can be formed in the region A, while an etched pattern with a smaller line width can be formed in the region B. In a simple way, etched layer patterns with different feature sizes can be simultaneously formed on the same to-be-etched layer, which satisfies the design requirements for different line widths of the etched patterns and saves man-hours to reduce manufacturing costs.

[0068] exist Fig. 9 Based on Fig.11 After forming the first mask structure 250 and the second mask structure 350 , the first protection layer 240 , the first sacrificial layer 220 , and the second sacrificial layer 320 are removed.

[0069] In this embodiment, since the materials of the first protective layer 240 , the first sacrificial layer 220 , and the second sacrificial layer 320 are all silicon, the first protective layer 240 , the first sacrificial layer 220 , and the second sacrificial layer 320 can be removed at the same time.

[0070] In another embodiment, the materials of the first sacrificial layer 220 , the second sacrificial layer 320 , and the first protective layer 240 are different, and thus the first sacrificial layer 220 , the second sacrificial layer 320 , and the first protective layer 240 are removed respectively.

[0071] In this embodiment, the method of removing the first protection layer 240 , the first sacrificial layer 220 , and the second sacrificial layer 320 includes a dry etching process or a wet etching process.

[0072] In this embodiment, since the first protection layer 240 , the first sacrificial layer 220 , and the second sacrificial layer 320 are removed at the same time, the time for forming the semiconductor structure can be reduced, thereby reducing the manufacturing cost.

[0073] Please refer to Fig.12 After forming the first mask structure 250 and the second mask structure 350, the first mask structure 250 is used as a mask to etch the layer 200 to be etched and the liner layer 210 in the area A, a groove 260 is formed in the layer 200 to be etched in the area A, and the first mask structure 250 forms a first initial layer to be removed 270; at the same time, the second mask structure 350 is used as a mask to etch the layer 200 to be etched and the liner layer 210 in the area B, a groove 360 ​​is formed in the layer 200 to be etched in the area B, and the second mask structure 350 forms a second initial layer to be removed 370.

[0074] In another embodiment, when the layer to be etched 200 includes the first layer to be etched and the second layer to be etched formed on the surface of the first layer to be etched, the second layer to be etched and the liner layer 210 are etched using the first mask structure 250 and the second mask structure 350 as masks until the surface of the first layer to be etched is exposed to form the grooves 260 and 360. After the liner layer 210, the first layer to be removed and the second layer to be removed are subsequently removed, the first layer to be etched is etched using the etched second layer to be etched as a mask.

[0075] In this embodiment, while etching the layer to be etched 200 and the liner layer 210, the first mask structure 250 and the second mask structure 350 are etched until the surface of the liner layer 210 at the bottom of the second mask layer 252 is exposed, so as to form the first initial layer to be removed 270 on the surface of the liner layer 210 in the region A, and simultaneously form the second layer to be removed 370 on the surface of the liner layer 210 in the region B. The method of etching the layer to be etched 200, the liner layer 210, the first mask structure 250 and the second mask structure 350 includes a dry etching process and a wet etching process.

[0076] In this embodiment, since the etched layer 200, the pad layer 210, the first mask structure 250 and the second mask structure 350 are etched simultaneously, the steps in manufacturing the semiconductor structure are reduced, the time required for manufacturing the semiconductor structure is shortened, and the manufacturing cost is reduced.

[0077] In another embodiment, after etching the layer to be etched 200 and the liner layer 210, the first mask structure 250 is etched to form the first initial layer to be removed 270 in the region A, and at the same time, the second mask structure 350 is etched to form the second initial layer to be removed 370 in the region B. The method of etching the layer to be etched 200, the liner layer 210, the first mask structure 250, and the second mask structure 350 includes a dry etching process and a wet etching process.

[0078] In another embodiment, since the first mask structure 250 and the second mask structure 350 are etched after etching the layer to be etched 200 and the pad layer 210, the etching degree of the layer to be etched 200, the pad layer 210, the first mask structure 250 and the second mask structure 350 can be more accurately controlled by controlling the etching parameters, thereby improving the graphic accuracy of the groove 260 and the groove 360.

[0079] Please refer to Fig.13 , the first initial layer to be removed 270 (such as Fig.12 as shown) and the second initial layer to be removed 370 (as shown Fig.12 As shown in the figure, a modification process is performed to form a first layer to be removed 271 in the region A and a second layer to be removed 371 in the region B.

[0080] Since the first initial layer to be removed 270 and the second initial layer to be removed 370 are modified to form the first layer to be removed 271 and the second layer to be removed 371, the first layer to be removed 271 and the second layer to be removed 371 can be removed at the same time as the liner layer 210 is removed. Therefore, the first initial layer to be removed 270 and the second initial layer to be removed 370 that eventually fall off and remain on the surface of the layer to be etched 200 after the liner layer 210 is removed are reduced, thereby reducing the contamination of the first initial layer to be removed 270 and the second initial layer to be removed 370 on the layer to be etched 200, reducing the defects of the semiconductor structure or the reduction of the pattern accuracy caused by the contamination, and improving the yield rate and etching effect.

[0081] In this embodiment, the modification process is a plasma treatment process. Specifically, the parameters of the plasma treatment process include: the gas includes a process gas, and the process gas is pure H2, pure He or a mixed gas of H2 and He.

[0082] In this embodiment, the material of the first layer to be removed 271 includes one or more of a Si—NH group, a Si—OH group, and a Si—HeN group.

[0083] In another embodiment, the gas further includes a carrier gas, and the carrier gas includes one or both of argon gas and helium gas.

[0084] In this embodiment, the H2 and He become hydrogen ions and helium ions after ionization and are bombarded to the first initial layer to be removed 270 and the second initial layer to be removed 370. The hydrogen ions and helium ions with higher energy enter the first initial layer to be removed 270 and the second initial layer to be removed 370, interrupt the chemical bonds of the materials of the first initial layer to be removed 270 and the second initial layer to be removed 370, that is, the chemical bonds of the silicon nitride or silicon nitride oxide, and re-bond with the nitrogen ions and silicon ions in the materials of the first initial layer to be removed 270 and the second initial layer to be removed 370 to form one or more of Si-NH groups, Si-OH groups and Si-HeN groups, forming the first layer to be removed 271 and the second layer to be removed 371. Since the Si-NH groups, Si-OH groups and Si-HeN groups have higher energy and greater activity than silicon nitride or silicon nitride oxide, they are more likely to undergo chemical reactions and be removed.

[0085] Please refer to Fig.14 After forming the first layer to be removed 271 and the second layer to be removed 371 , a second protective layer 280 is formed on the exposed surface of the layer to be etched 200 , and the surface of the second protective layer 280 is higher than or flush with the contact surface between the layer to be etched 200 and the liner layer 210 .

[0086] In this embodiment, the method for forming the second protective layer 280 on the exposed surface of the layer to be etched 200 includes: using a spin coating process to form an initial second protective layer (not shown) on the exposed surface of the layer to be etched 200, the exposed surface of the pad layer 210, the exposed surface of the first layer to be removed 271, and the exposed surface of the second layer to be removed 371, and etching back the initial second protective layer until the surface of the initial second protective layer is higher than or flush with the contact surface between the layer to be etched 200 and the pad layer 210, so as to form the second protective layer 280.

[0087] In this embodiment, since the second protective layer 280 is formed and the second protective layer covers the surface of the layer to be etched 200, when the liner layer 210, the first layer to be removed 271 and the second layer to be removed 371 are subsequently removed, the exposed surface portion of the layer to be etched 200 is avoided from being removed together, thereby maintaining the graphic accuracy of the layer to be etched 200.

[0088] In this embodiment, the second protection layer 280 is an organic material containing carbon.

[0089] In this embodiment, since the second protective layer 280 is an organic material containing carbon elements, the organic material has better fluidity and ductility. Therefore, in the spin coating process, the initial second protective layer can more evenly and quickly cover the groove 260, the exposed surface of the pad layer 210, the exposed surface of the first layer to be removed 271 and the exposed surface of the second layer to be removed 371.

[0090] Please refer to Fig.15 After forming the second protection layer 280 , the liner layer 210 , the first layer to be removed 271 , and the second layer to be removed 371 are removed by etching.

[0091] In this embodiment, the process of removing the liner layer 210, the first layer to be removed 271 and the second layer to be removed 371 is a wet etching process. Specifically, the parameters of the wet etching process include: the solution is a hydrofluoric acid solution.

[0092] In this embodiment, the wet etching process has a first etching rate for the material of the first layer to be removed 271 and the second layer to be removed 371, and the wet etching process has a second etching rate for the material of the first initial layer to be removed 230, and the first etching rate is greater than the second etching rate. Since the first etching rate is greater than the second etching rate, the first layer to be removed 271 and the second layer to be removed 371 can be removed faster than the first initial layer to be removed 270, thereby obtaining a better removal effect.

[0093] In this embodiment, since the hydrofluoric acid solution can corrode silicon dioxide and materials including Si-NH groups, Si-OH groups or Si-HeN groups, the hydrofluoric acid solution is used as the etching solution of the wet etching process to simultaneously remove the liner layer 210, the first layer to be removed 271 and the second layer to be removed 371. This reduces the first initial layer to be removed 270 and the second layer to be removed 371 that eventually fall off and remain on the surface of the layer to be etched 200 after the liner layer 210 is removed, thereby reducing the contamination of the layer to be etched 200 by the first initial layer to be removed 270 and the second layer to be removed 371, reducing the defects of the semiconductor structure or the reduction of the pattern accuracy caused by the contamination, and improving the yield rate and etching effect.

[0094] Please refer to Fig.16In this embodiment, after removing the liner layer 210, the first to-be-removed layer 271 and the second to-be-removed layer 371, the second protective layer 280 is removed to form the first etching layer 201 in the region A and the second etching layer 203 in the region B. The method of removing the second protective layer 280 includes a dry etching process or a wet etching process.

[0095] Fig.17 It is a schematic cross-sectional structure diagram of a semiconductor structure forming process in another embodiment of the present invention.

[0096] Please refer to Fig.17 In another embodiment, the layer to be etched 200 includes region A but not region B, so the first etched layer 201 is formed after the layer to be etched 200 is processed but not the second etched layer 203. The method of forming the first etched layer 201 is the same as the method in this embodiment and will not be described in detail.

[0097] In another embodiment, the first etching layer 201 is formed without forming the second etching layer 203 , which can correspond to the situation where only one etching layer pattern line width size is required on the same layer to be etched.

[0098] An embodiment of the present invention further provides a semiconductor device, comprising: a semiconductor structure formed by the above-mentioned forming method.

[0099] Accordingly, in this embodiment, due to the adoption of the above-mentioned formation method, a semiconductor device with better etching effect, more precise pattern, fewer defects and higher yield is obtained.

[0100] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that: include: Providing a layer to be etched, wherein the surface of the layer to be etched has a liner layer; forming a plurality of mutually discrete first mask structures on the surface of the liner layer; Using the first mask structure as a mask, etching the layer to be etched and the liner layer, forming a groove in the layer to be etched, and making the first mask structure form a first initial layer to be removed; Performing a modification process on the first initial layer to be removed to increase material activity, thereby forming a first layer to be removed; The liner layer and the first to-be-removed layer are removed by etching at the same time.

2. The method for forming a semiconductor structure according to claim 1, wherein: The etching process for removing the first layer to be removed has a first etching rate for the material of the first layer to be removed, the etching process for removing the first layer to be removed has a second etching rate for the material of the first initial layer to be removed, and the first etching rate is greater than the second etching rate.

3. The method for forming a semiconductor structure according to claim 1, wherein: The first mask structure includes a first mask layer located on the surface of the liner layer and a second mask layer located on the surface of the liner layer, and the thickness of the first mask layer is greater than the thickness of the second mask layer.

4. The method for forming a semiconductor structure according to claim 3, characterized in that: While etching the layer to be etched and the liner layer, etching the first mask structure until the surface of the liner layer at the bottom of the second mask layer is exposed, and forming a first initial layer to be removed on the surface of the liner layer; The method for forming the first mask structure includes: forming a plurality of mutually independent first sacrificial layers on the surface of the pad layer; forming a first mask structure material layer on the surface of the first sacrificial layer and on the surface of the pad layer exposed between the plurality of first sacrificial layers; forming a first protective layer on the first mask structure material layer formed on the surface of the pad layer; after forming the first protective layer, etching the first mask structure material layer to form the first mask structure; after forming the first mask structure, removing the first protective layer and the first sacrificial layer.

5. The method for forming a semiconductor structure according to claim 4, characterized in that: The method for forming the first protective layer comprises: forming a first protective material layer on a first mask structure material layer formed on the surface of the liner layer; and etching the first protective material layer to form the first protective layer.

6. The method for forming a semiconductor structure according to claim 3, wherein: The first mask structure further includes: the second mask layer and two first mask layers respectively located on both sides of the second mask layer, and the second mask layer connects the two first mask layers.

7. The method for forming a semiconductor structure according to claim 1, wherein: Also includes: After forming the first layer to be removed and before removing the liner layer and the first layer to be removed, a second protective layer is formed on the exposed surface of the layer to be etched, wherein the surface of the second protective layer is higher than or flush with the contact surface between the layer to be etched and the liner layer.

8. The method for forming a semiconductor structure according to claim 7, characterized in that: The method for forming the second protective layer in the groove includes: using a spin coating process to form an initial second protective layer in the groove, on the exposed surface of the liner layer and on the surface of the first layer to be removed, and etching back the initial second protective layer until the surface of the initial second protective layer is higher than or flush with the surface of the layer to be etched to form the second protective layer; after removing the liner layer and the first layer to be removed, removing the second protective layer.

9. The method for forming a semiconductor structure according to claim 1, wherein: The layer to be etched comprises: a first layer to be etched and a second layer to be etched, the surface of the second layer to be etched has a liner layer, and the surface of the first layer to be etched has the second layer to be etched.

10. The method for forming a semiconductor structure according to claim 9, characterized in that: The method for forming the groove also includes: when etching the layer to be etched and the liner layer, etching the second layer to be etched of the layer to be etched until the surface of the first layer to be etched is exposed; the method for forming the semiconductor structure also includes: after removing the liner layer and the first layer to be removed, etching the first layer to be etched using the second layer to be etched as a mask.

11. The method for forming a semiconductor structure according to claim 1, wherein: The material of the layer to be removed has one or more of nitrogen-hydrogen bonds, hydrogen-oxygen bonds, or helium-nitrogen bonds.

12. The method for forming a semiconductor structure according to claim 11, characterized in that: The material of the first mask structure includes one of silicon nitride and silicon oxynitride.

13. The method for forming a semiconductor structure according to claim 12, wherein: The material of the first layer to be removed includes one or more of a Si-NH group, a Si-OH group, and a Si-HeN group.

14. The method for forming a semiconductor structure according to claim 11, wherein: The modification process is a plasma treatment process.

15. The method for forming a semiconductor structure according to claim 14, wherein: When the material of the first mask structure includes one of silicon nitride and silicon oxynitride, the parameters of the plasma treatment process include: the gas includes a process gas, and the process gas includes one or more of H2 or He.

16. The method for forming a semiconductor structure according to claim 15, characterized in that: The gas further includes a carrier gas, and the carrier gas includes one or both of argon gas and helium gas.

17. The method for forming a semiconductor structure according to claim 11, characterized in that: The process of removing the liner layer and the first layer to be removed is a wet etching process.

18. The method for forming a semiconductor structure according to claim 17, wherein: When the material of the liner layer is silicon dioxide, the parameters of the wet etching process include: the solution is a hydrofluoric acid solution.

19. A semiconductor structure formed by the method according to any one of claims 1 to 18.

Images