Optoelectronic active device and method for producing an optoelectronic active device

Abstract

An active optoelectronic device includes: a silicon-on-insulator (SOI) substrate, the SOI substrate including a silicon substrate layer, a buried oxide (BOX) layer on top of the silicon substrate layer, an SOI layer on top of the BOX layer, and a substrate cavity, the substrate cavity extending through the SOI layer, the BOX layer, and into the silicon substrate layer, such that the base of the substrate cavity is formed by a portion of the silicon substrate layer; an active optoelectronic waveguide including an active optoelectronic stack within the substrate cavity; and a buffer region within the substrate cavity below the active optoelectronic waveguide, the buffer region including a Ge layer and a GaAs layer.

Description

[0001] This application claims priority to U.S. Application No. 62 / 671,830, filed May 15, 2018, the contents and elements of which are incorporated herein by reference for all purposes. Field of the Invention

[0002] The present invention relates to the integration of photonic components on an SOI platform using a buffer region, and particularly (but not exclusively) to the integration of components utilizing III-V materials onto an SOI substrate. Background Art

[0003] Electro-absorption modulators (III-V EAMs) formed from III-V materials are used to modulate light in optical systems.

[0004] Silicon-on-insulator (SOI) wafers can be used as substrates on which optical components and / or circuits can be formed. However, monolithic integration of III-V EAMs on SOI substrates has not been successful due to the lattice mismatch between Si and III-V materials.

[0005] In view of the above considerations, the present invention has been designed. Summary of the invention

[0006] In a first aspect, the present invention may provide an optoelectronic active device, comprising: a silicon-on-insulator (SOI) substrate, the SOI substrate comprising a silicon base layer, a buried oxide (BOX) layer on top of the silicon base layer, a SOI layer on top of the BOX layer, and a substrate cavity, the substrate cavity extending through the SOI layer, the BOX layer and into the silicon base layer, such that a base of the substrate cavity is formed by a portion of the silicon base layer; an optoelectronic active waveguide, the optoelectronic active waveguide comprising an optoelectronic active stack within the substrate cavity; and a buffer region, the buffer region being below the optoelectronic active waveguide within the substrate cavity, the buffer region comprising a Ge layer and a GaAs layer.

[0007] The buffer region allows for better integration of the optoelectronic active waveguide with the SOI substrate since it modifies the lattice structure on which the waveguide is formed. This device with the buffer region can be used as a template on which optoelectronic active and / or passive waveguides can be formed.

[0008] The buffer region may include a graded InAlAs layer. The buffer region may include an InGaAs or InP layer. The buffer region may include an InGaAs or InP layer on top of a graded InAlAs layer on top of a GaAs layer on top of a Ge layer.

[0009] The Ge layer may have a thickness of 1000nm+ / -20%, and / or the GaAs layer may have a thickness of 1000nm+ / -20%, and / or the graded InAlAs layer may have a thickness of 1300nm+ / -30%, and / or the InGaAs or InP layer may have a thickness of 500nm to 1000nm.

[0010] The buffer region may be composed of an intrinsic or unintentionally doped (UID) material. The buffer region may be epitaxially grown onto the base of the substrate cavity. The epitaxial growth of the buffer region on the base of the substrate cavity improves the integration of the buffer region with the silicon base layer at the base of the substrate cavity. The epitaxially grown layers may be detectable by microscopy and / or SEM in view of the formed structure.

[0011] The optoelectronically active stack may be located directly on top of the buffer region. The optoelectronically active stack may be epitaxially grown on the buffer region. The epitaxial growth of the optoelectronically active stack on the buffer region improves the integration of the stack with the buffer region.

[0012] The interface between the optoelectronic active stack and the buffer region may be positioned deeper in the substrate cavity than the interface between the silicon base layer and the BOX layer in the SOI substrate, so that a portion of the optoelectronic active stack may be positioned at the same height as a portion of the silicon base layer.

[0013] The optoelectronic active stack may include a III-V semiconductor layer. Due to the presence of the buffer region, the III-V semiconductor may be monolithically integrated with the SOI. The stack may be a III-V EPI stack, and the III-V EPI stack may include MQW and / or bulk III-V materials.

[0014] The optoelectronic active stack may include a multiple quantum well region.

[0015] The optoelectronic active stack may form an electro-absorption modulator (EAM). The EAM may be a III-V EAM and / or the EAM may include a device utilizing a quantum confined Stark effect (QCSE) and / or a Franz-Keldysh (FK) effect. The optoelectronic active waveguide may be configured such that the optical properties of the optoelectronic active waveguide can be modified according to the QCSE effect or the FK effect.

[0016] The optoelectronic active device may include a channel between the optoelectronic active stack and the sidewalls of the substrate cavity; wherein the channel may be filled with a liner and a filling material, the liner and the filling material having a refractive index similar to or greater than the refractive index of the material forming the sidewalls of the substrate cavity, thereby forming a bridge waveguide in the channel between the SOI layer and the optoelectronic active stack. The filling material may be amorphous silicon or silicon germanium (SiGe), and the liner may be formed of silicon nitride (Si3N4). The bottom surface of the filling material may be aligned with the top surface of the BOX layer.

[0017] A top surface of the optoelectronic active stack may be positioned higher than a top surface of the SOI layer such that a portion of the optoelectronic active stack protrudes from the substrate cavity.

[0018] The optoelectronic active device may include a silicon nitride (Si3N4) layer on top of the SOI layer, the top surface of the silicon nitride having a height above the SOI substrate equal to the height of the portion of the optoelectronic active stack protruding from the substrate cavity, so that the top surface of the silicon nitride layer is aligned with the top surface of the optoelectronic active stack.

[0019] The optoelectronic active device may include: a first electrode contact on a first doped region, the first doped region forming the bottommost layer of the optoelectronic active stack; an isolation cavity in the first doped region; an insulating material, the insulating material being located on a side surface of the optoelectronic active stack and extending into and lining the isolation cavity in the first doped region; and a second electrode contact on a second doped region, the second doped region forming the top layer of the optoelectronic active stack, the contact extending from the second doped region along the insulating material and into the isolation cavity in the first doped region.

[0020] The composition of the optoelectronically active device and the nature and / or height of the layers may be detectable using an optical microscope and / or a SEM.

[0021] In a second aspect, the present invention may provide a method for producing an optoelectronic active device, the method comprising the following steps: providing a silicon-on-insulator (SOI) substrate, the SOI substrate comprising a silicon base layer, a buried oxide (BOX) layer on top of the silicon base layer, and a silicon-on-insulator (SOI) layer on top of the BOX layer; etching a substrate cavity through the BOX layer and into the silicon base layer in a portion of the silicon-on-insulator (SOI) substrate through the SOI layer; forming a buffer region within the substrate cavity, the step of forming the buffer region comprising epitaxially growing a Ge layer and epitaxially growing a GaAs layer; epitaxially growing an optoelectronic active stack within the substrate cavity and on top of the buffer region; etching the optoelectronic active stack to form an optoelectronic active waveguide; and etching the SOI substrate to form an SOI waveguide, the SOI waveguide being configured to guide light waves through the optoelectronic active waveguide.

[0022] The step of forming a buffer region in the substrate cavity may include epitaxially growing a graded InAlAs layer. The step of forming a buffer region in the substrate cavity may include epitaxially growing an InGaAs or InP layer.

[0023] The step of forming a buffer region in the substrate cavity may include: epitaxially growing a Ge layer on a portion of the silicon base layer forming the base of the substrate cavity; then epitaxially growing a GaAs layer on the Ge layer; then epitaxially growing a graded InAlAs layer on the GaAs layer; and then epitaxially growing an InGaAs or InP layer on the graded InAlAs layer.

[0024] The interface between the optoelectronic active stack and the buffer region may be positioned deeper in the substrate cavity than an interface between the silicon base layer and the BOX layer in the SOI substrate, such that a portion of the optoelectronic active stack is positioned at the same height as a portion of the silicon base layer.

[0025] The method may include the following steps: before etching the substrate cavity, depositing a silicon nitride layer on the SOI substrate so that the top surface of the silicon nitride has a first height above the SOI substrate, wherein after growing the optoelectronic active stack, a portion of the optoelectronic active stack protrudes from the substrate cavity to a height equal to the first height so that the top surface of the silicon nitride layer is aligned with the top surface of the optoelectronic active stack.

[0026] The method may include depositing silicon nitride on sidewalls of the substrate cavity prior to epitaxially growing the buffer region.

[0027] The epitaxially grown optoelectronic active stack may have facets in a region adjacent to the sidewalls of the substrate cavity; and the method may include the following steps: etching the region to remove the facets and create a channel between the sidewalls and the stack; and filling the channel with a filling material having a refractive index similar to or greater than the refractive index of the material forming the sidewalls, so that the filling material forms a bridge waveguide in the channel between the SOI waveguide and the optoelectronic active stack.

[0028] The epitaxially grown optoelectronic active stack may have facets in a region adjacent to the sidewalls of the substrate cavity; and the method may include the following steps: etching the region to remove the facets and create a channel between the sidewalls and the stack; lining the channel with a liner to provide a lined channel; and filling the lined channel with a fill material having a refractive index similar to the refractive index of the material forming the sidewalls, so that the fill material forms a bridge waveguide in the channel between the SOI waveguide and the optoelectronic active stack.

[0029] The liner may be formed of silicon nitride. The filler material may be amorphous silicon or silicon germanium (SiGe).

[0030] The step of etching the region, thereby removing the facets and creating the channel between the sidewalls and the stack may include any of: etching through the optoelectronic active stack and etching into the buffer region so that the base of the channel is formed by a portion of the buffer region; or etching into the optoelectronic active stack so that the base of the channel is formed by a portion of the optoelectronic active stack.

[0031] The step of etching the region to remove the facets and create the channel between the sidewalls and the stack may include etching to a position lower than the interface between the silicon base layer and the BOX layer in the SOI substrate so that the top surface of the liner at the base of the channel is at the same height as the top surface of the BOX layer.

[0032] The method may include the following steps: depositing a first electrode contact on a first doped region, the first doped region forming a bottom layer of the optoelectronic active stack; etching an isolation cavity in the first doped region; depositing an insulating material on a side surface of the optoelectronic active stack and in the isolation cavity in the first doped region to line the isolation cavity, thereby electrically isolating the isolation cavity from the optoelectronic active stack; and depositing a second electrode contact on a second doped region, the second doped region forming a top layer of the optoelectronic active stack, the contact extending into the isolation cavity in the first doped region.

[0033] The method may include the step of etching an amorphous silicon layer from a region above the SOI substrate and proximate to the cavity, followed by the step of performing chemical mechanical planarization of the SiO2 layer above the optoelectronic active stack.

[0034] In this application, the orientation of components and layers is discussed relative to the substrate as the base of the device. The height of a layer or waveguide is measured in a direction away from the silicon base layer or away from the base of a substrate cavity. The top surface of a layer or waveguide is the surface farthest from the base of a silicon base layer or a substrate cavity, and the bottom surface of a layer or waveguide is the surface closest to the bottom of a silicon base layer or a substrate cavity. For example, the height of an SOI layer is measured from the bottom surface of the SOI layer to the top surface of the SOI layer in a direction perpendicular to the interface between the silicon base layer and the BOX layer. The term "below" indicates a base closer to a silicon base layer or a substrate cavity. The depth of a substrate cavity refers to the distance from the base of a substrate cavity in a direction opposite to the height. The deeper a layer is in a cavity, the closer the layer is to the base of a substrate cavity.

[0035] The top of the stack may have a height greater than the height of the SOI layer, so that the stack may protrude above the top of the substrate cavity. Such a stack is still considered to be within the cavity as long as a portion of the optoelectronically active stack is at the same height above the silicon substrate layer as the SOI layer. In this way, light from an input waveguide in the SOI layer may enter the optoelectronically active stack, and light may leave the stack to enter an output waveguide in the SOI layer.

[0036] The present invention includes any combination of the described aspects and preferred features unless such a combination is expressly impermissible or explicitly avoided. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] Embodiments and experiments illustrating the principles of the present invention will now be discussed with reference to the accompanying drawings, in which:

[0038] Figure 1 Shown is a top view of a monolithic III-V EAM on a Si substrate.

[0039] Figure 2 Shows Figure 1 Cross-sectional view of the EAM version, the EAM is AlInGaAs MQW or bulk InGaAsP EAM on 1μm SOI platform, the cross-sectional view is along Figure 1 The line A-A'.

[0040] Figure 3 Shown along Figure 1 Line B-B' Figure 2 Cross-sectional view of the EAM.

[0041] Figure 4 Shows Figure 1 A cross-sectional view of a version of the EAM. The EAM is an InGaNAs MQWEAM on a 1μm SOI platform. The cross-sectional view is taken along Figure 1 The line A-A'.

[0042] Figure 5 Shown along Figure 1 Cross-sectional view of the InGaNAs MQW EAM on the 1μm SOI platform along line BB’.

[0043] Figure 6 Shown along Figure 1 The line C-C' Figure 1 Cross-sectional view of the EAM.

[0044] Figure 7 Shown along Figure 1 Line D-D' Figure 1 Cross-sectional view of the EAM.

[0045] Figures 8A to 8V Steps in a method of making an EAM are shown.

[0046] FIG. 9A to FIG. 9U Steps in a method of making an EAM are shown. DETAILED DESCRIPTION

[0047] Various aspects and embodiments of the present invention will now be discussed with reference to the accompanying drawings. Other aspects and embodiments will be apparent to those skilled in the art. All documents mentioned herein are incorporated herein by reference.

[0048] Figure 1A top view of a III-V MQW / bulk waveguide EAM 2 on a SOI substrate 1 is shown in FIG. An input SOI waveguide 3 provides a path for light to enter the waveguide of the EAM 2, and an output SOI waveguide 4 provides a path for light to leave the EAM 2. Electrodes 6 and 7 provide connections for electronics that can be used to apply a bias across the optoelectronic active stack of the EAM to modulate light in the EAM. There is an amorphous silicon region 5 between the input waveguide 3 and the EAM, and another amorphous silicon region 5 between the EAM and the output waveguide 4. Region 5 forms a fill material and can provide a bridge waveguide between the input waveguide and the output waveguide as well as the optoelectronic active stack. The amorphous silicon region 5 is surrounded by a Si3N4 liner. The amorphous silicon can be replaced by SiGe.

[0049] Figure 2 and Figure 3 Shows Figure 1 An example of an EAM is shown. The EAM is formed on an SOI platform 1 comprising a silicon base layer 8 , a buried oxide layer 9 and an SOI layer 10 . Figure 2 The EAM shown is on a 1 μm SOI platform with the SOI layer 10 having a height of 1 μm, but in other embodiments other platform sizes and SOI layer heights may be used. The silicon base layer may be a (100) silicon substrate with a 6 degree bevel angle.

[0050] The substrate cavity extends through the SOI layer 10, through the BOX layer 9 and into the silicon base layer 8. The base of the cavity is formed in the silicon base layer 8.

[0051] An optoelectronic active stack is formed in the substrate cavity. In this example, the stack is formed by an N-doped InP layer 12, an AlInGaAs layer 14, a P-doped InP layer, and a P-doped InGaAs layer 15. The AlInGaAs layer 14 may be a multi-quantum well layer or a bulk layer. The top of the stack has a height greater than the height of the SOI layer 10, so that the stack protrudes above the top of the substrate cavity. Other layers may be added to the stack, one or more layers may be omitted from the stack, and / or other layers may replace one or more layers in the stack. The layers may be reordered.

[0052] The P-doped and N-doped layers surround the intrinsic or uid AlInGaAs layer 14, forming a vertical PIN junction in the stack. A bias voltage can be applied across the PIN junction to create a modulation region.

[0053] The EAM also has a buffer region 11 below the optoelectronically active waveguide. The buffer region 11 consists of a Ge layer 21, a GaAs layer 20, a graded InAlAs layer 19, and an InGaAs or InP layer 18 in this example. The InGaAs or InP layer 18 is on top of the graded InAlAs layer 19, which is on top of the GaAs layer 20 and the GaAs layer 20 is on top of the Ge layer 21. Other layers may be added to the buffer region, one or more layers may be omitted from the buffer region and / or other layers may replace one or more layers in the buffer region. The layers may be reordered.

[0054] The buffer region 11 is at the base of the substrate cavity. The optoelectronic active stack is on the buffer region 11 .

[0055] The N-doped InP layer 12 is on top of the buffer region 11, the AlInGaAs layer 14 is on top of the N-doped InP layer 12, the P-doped InP layer is on top of the AlInGaAs layer 14 and the P-doped InGaAs layer 15 is on top of the P-doped InP layer. In other embodiments, the layers may be reversed so that one or more P-doped layers are positioned lower (closer to the base of the substrate cavity) than the AlInGaAs layer 14 and one or more N-doped layers are positioned higher than the AlInGaAs layer 14. In other embodiments, other doped and undoped or unintentionally doped layers may form the optoelectronic active stack.

[0056] Electrode 6 contacts the lower doped layer of the photovoltaic active stack, and electrode 7 contacts the upper doped layer of the photovoltaic active stack. Figure 2 and Figure 3 In the embodiment of the present invention, electrode 6 contacts the N-doped InP layer 12 of the optoelectronic active stack, and electrode 7 contacts the P-doped InGaAs layer 15 of the optoelectronic active stack. In other embodiments, electrode 6 may contact the P-doped layer, and electrode 7 may contact the N-doped layer.

[0057] On top of the SOI layer 10 there is a Si3N4 layer 16, and on the Si3N4 layer 16 there is a SiO2 layer 17. An amorphous silicon region 5 is between the input waveguide 3 and the optoelectronic active stack, and between the optoelectronic active stack and the output waveguide 4. The amorphous silicon region 5 is surrounded by a Si3N4 liner. Si3N4 is a silicon-rich silicon nitride with a refractive index of 2.7.

[0058] Table 1 shows an example of layer heights and compositions for this embodiment for an MQW EAM utilizing QCSE. Additional layers containing GaAsN and GaAs are included between the AlGaAs layer and the InGaNAs layer. Additional layers containing GaAsN and GaAs are also included between the InGaNAs layer and the AlGaAs layer.

[0059] Another example of the height and composition of the layers used in this embodiment is shown in Table 2 for an EAM realized with bulk family materials utilizing the FK effect. The use of the FK effect is superior to the use of the QCSE because the FK effect is polarization independent. The InGaAsP layer in Table 2 can be composed of Figure 2 and Figure 3 The AlInGaAs shown is replaced by InGaNAs. The example has an additional layer containing InGaAsP between the P-doped InP layer and the P-doped InGaAs layer.

[0060] exist Figure 4 and Figure 5 Along the Figure 1 Lines AA' and BB' show another embodiment. Except for the composition of the buffer region 11 and the composition of the photovoltaic active stack, this embodiment is similar to Figure 2 and Figure 3 The embodiments shown are identical.

[0061] The optoelectronic active stack is formed by an N-doped GaAs layer 22, an N-doped AlGaAs layer 23, an InGaNAs layer 24, a P-doped AlGaAs layer 25, and a P-doped GaAs layer 26. The P-doped GaAs layer 26 is on top of the P-doped AlGaAs layer 25, the P-doped AlGaAs layer 25 is on top of the InGaNAs layer 24, and the InGaNAs layer 24 is on top of the N-doped AlGaAs layer 23. Other layers may be added to the stack, one or more layers may be omitted from the stack, and / or other layers may replace one or more layers in the stack. The layers may be reordered. The InGaNAs layer 24 may have an MQW structure.

[0062] The P-doped and N-doped layers surround the intrinsic or uid InGaNAs layer 24, forming a vertical PIN junction in the stack. A bias voltage can be applied across the PIN junction to create a modulation region.

[0063] The optoelectronically active stack is on top of the buffer region 11 .

[0064] The buffer region 11 is formed by a Ge layer 21 and a GaAs layer 20. The Ge layer 21 is on the base of the substrate cavity, and the GaAs layer 20 is on the Ge layer. Other layers may be added to the buffer region, one or more layers may be omitted from the buffer region, and / or other layers may replace one or more layers in the buffer region. The layers may be reordered.

[0065] Table 3 shows an example of the height of the layers in this embodiment for an MQW EAM utilizing QCSE. As shown by this example, the layers discussed in this application may be composed of sublayers that may differ in their dopant content. For example, in Table 3, the InP layer is formed by three sublayers (layers 6, 7, 8) each having a different silicon doping level. In addition, as illustrated by this example, additional layers may be included in the stack and / or in the buffer region. In the example of Table 3, an additional layer containing InGaAsP is also included between the corresponding InP layer and the AlInGaAs layer. The InGaAsP layer is also added between the P-doped InP layer and the P-doped InGaAs layer. The n / u / p column describes the doping of the layer. The uid marking in the table indicates that the layer may be unintentionally doped, and although no dopant is actively applied to the layer, there may be some residual doping due to the thinness of the layer and the adjacent layers that are doped.

[0066] Figure 6 Shown through Figure 1 1 and shows the input waveguide 3. The waveguide is a rib waveguide formed in the SOI layer 10. The Si3N4 layer 16 is on top of the ridge of the rib waveguide. The SiO2 layer is formed above the waveguide and the Si3N4 layer.

[0067] Figure 7 Shown through Figure 1 2 and shows the amorphous silicon region 5. In this region of the device, the Si3N4 layer 27 is on top of the silicon base layer 8, the amorphous silicon layer 5 is on top of the Si3N4 layer 27 and a rib waveguide is formed in the amorphous silicon 5, the rib waveguide of the amorphous silicon is aligned with the optoelectronic active stack and the input waveguide. The Si3N4 layer 16 is on top of the ridge of the rib waveguide. A SiO2 layer is formed above the waveguide and the Si3N4 layer.

[0068] like Figure 7 The same structure shown is provided between the optoelectronic active stack and the output waveguide, wherein a rib waveguide of amorphous silicon is aligned with the optoelectronic active stack and the output waveguide.

[0069] Figure 2 and Figure 3 The devices shown can be referenced as follows Figures 8A to 8VA similar method can be used to form by replacing the appropriate layers in the buffer region and the stack. Figure 4 and Figure 5 The embodiment shown.

[0070] A Si3N4 layer 16 is deposited on the SOI substrate. The top surface of the Si3N4 layer 16 may have a height above the silicon base layer 8 that matches the desired height of the top surface of the optoelectronic active stack when the stack is deposited in the substrate cavity.

[0071] like Fig. 8A As shown, a substrate cavity 28 is etched in the substrate. The cavity extends through the Si3N4 layer 16, through the SOI layer 10, through the BOX layer 9 and into the silicon base layer 8. The distance to which the cavity extends in the silicon base layer can be selected so that the center mode of the silicon waveguide in the SOI layer is aligned with the center mode of the optoelectronic active stack to be deposited.

[0072] Then, if Figure 8B As shown, 20 nm of Si3N4 is deposited on the sidewalls of the substrate cavity. This can be achieved by anisotropic etching.

[0073] Polycrystalline III-V (polymer) is deposited on the Si3N4 layer 16, and the buffer region and the photovoltaic active stack are grown by epitaxial growth on the base of the substrate cavity. The layers forming the buffer region and the stack are as follows Figure 8C Shown is faceting at the edge of the cavity.

[0074] A SiO2 layer is deposited on the device over the optoelectronic active stack and the polymer. Etching is performed on the region surrounding the substrate cavity, such as Fig.8D As shown, the SiO2 layer remains on the stack and the polymer, and the SiO2 remains between the etched area and the substrate cavity. Chemical mechanical polishing (CMP) is then used to remove the remaining polymer, so that Fig. 8E As shown, about 20 nm SiO2 is left on the top surface of the stack.

[0075] like Fig.8F As shown, SiO2 is then deposited as a hard mask on the device and patterned using photoresist 29 to prepare for etching the faceted regions of the stack at the edges of the cavity. The faceted edges of the stack are then etched using the SiO2 hard mask to form channels and remove defects from the faceted edge regions. Figure 8GAs shown, etching removes the facet edges of the P-doped InGaAs layer 15, the P-doped InP layer 13, and the AlInGaAs layer 14. Etching also removes the upper portion of the facet edges of the N-doped InP layer 12. Etching forms two channels, one channel at the edge of the substrate cavity adjacent to the input waveguide, and one channel at the edge of the substrate cavity adjacent to the output waveguide.

[0076] like Figure 8H As shown, silicon-rich Si3N4_h is then deposited on the device. Si3N4_h forms a layer 30 on the SiO2 layer and forms a layer in the base of each of the channels at the edge of the substrate cavity. Si3N4_h is also deposited on the sidewalls of the channel, where the thickness at the sidewalls is between 230nm and 260nm. Si3N4_h has a refractive index of 2.7.

[0077] like Fig.8I As shown, amorphous silicon is then deposited to fill the channel and form a layer on the Si3N4_h. SiO2 is then deposited on the amorphous silicon in the region above the channel, and the amorphous silicon is then etched from the region surrounding the channel, leaving the amorphous silicon in and above the channel.

[0078] like Figure 8K As shown, CMP is then used to remove SiO2, reduce the height of the remaining amorphous silicon, remove the Si3N4_h layer 30 and reduce the height of the SiO2 layer on the stack to about 100 nm.

[0079] The amorphous silicon is then etched so that the top surface of the amorphous silicon has the same height as the top surface of the SOI layer 10 (see Figure 8L ).like Figure 8M and Figure 8N As shown, Si3N4 is then deposited and polished using CMP to the height of the SiO2 layer on the stack.

[0080] SiO2 and Si3N4 hard masks are then deposited to form waveguides in the stack (see Fig.8O ). Next, the mask is patterned using a photoresist to give Figure 8P The desired waveguide shape shown in FIG. Figure 1 Cross-sectional views along directions BB' and CC' are shown.

[0081] like Figure 8QAs shown, a rib waveguide is formed in the stack by etching a groove through the P-doped InGaAs layer 15, the P-doped InP layer 13 and the AlInGaAs layer 14. The groove also extends into the upper part of the N-doped InP layer 12. The ridge of the rib waveguide is formed by the stack between the etched grooves. The Si3N4 layer is not etched in this step.

[0082] like Figure 8R As can be seen in Figure 1, a SiO2 layer is then deposited on the device and a photoresist is added to the area above the optoelectronic active stack. The SiO2 layer on the input and output waveguide regions is then etched away to expose the Si3N4 hard mask. Figure 8S As shown, the Si3N4 and SOI are then further etched using a SiO2 hard mask to form a rib waveguide in each of the input and output waveguide regions.

[0083] Figure 8T An isolation cavity is shown, which is etched through the N-doped InP layer to the InGaAs or InP layer, so that the top electrode can be better isolated from the lower N-doped region to reduce parasitic capacitance. The isolation cavity is lined with an insulator such as SiO2. Figure 8U In the present invention, an insulator liner is deposited in the trenches and contacts are opened at each of these locations by removing portions of the SiO2 layer at the lower (N-doped) and upper (P-doped) layers of the photovoltaic active stack.

[0084] like Figure 8V Metallization is then used to form electrodes 6 and 7 at the contact points as shown.

[0085] You can refer to the following methods FIG. 9A to FIG. 9U To form another embodiment on a 3 μm SOI platform.

[0086] The substrate is a SOI substrate, wherein the SOI layer has a height of 3 μm. A SiO2 layer is deposited on the SOI layer, and a substrate cavity 29 is formed in the substrate. The cavity extends through the SiO2 layer, the SOI layer 10, the BOX layer 9 and into the silicon base layer 8. The distance to which the cavity extends in the silicon base layer can be selected so that the central mode of the silicon waveguide in the SOI layer is aligned with the central mode of the optoelectronic active stack to be deposited.

[0087] Then, if Fig. 9B As shown, 20 nm of Si3N4 is deposited on the sidewalls of the substrate cavity. This can be achieved by anisotropic etching.

[0088] The polymer is deposited on the Si3N4 layer 16 and the buffer region and the photovoltaic active stack are grown by epitaxial growth on the base of the substrate cavity. The layers forming the buffer region and the stack are as follows Fig. 9C and Fig.9D Shown is faceting at the edge of the cavity.

[0089] The buffer region 11 in this embodiment consists of a Ge layer 21 on the base of the substrate cavity, a GaAs layer 20 on the Ge layer 21, a graded InAlAs layer 19 on the GaAs layer 20, and an InGaAs or InP layer 18 on the graded InAlAs layer 19. The optoelectronic active stack includes a lower InP layer 31, an InGaAsP layer 33, and an upper InP layer 32. When deposited, the layers may be undoped and may be doped later in the process. The bottom surface of the InGaAsP layer 33 may have a height equal to the height of the bottom surface of the SOI layer.

[0090] Other layers may be added to the stack / buffer region, one or more layers may be omitted from the stack / buffer region, and / or other layers may replace one or more layers in the stack / buffer region. The layers may be reordered.

[0091] A SiO2 layer is deposited on the device over the optoelectronic active stack and the polymer. Etching is performed on the region surrounding the substrate cavity, such as Fig.9D As shown, the SiO2 layer remains on the stack and the polymer, and the SiO2 remains between the etched area and the substrate cavity. Chemical mechanical polishing (CMP) is then used to remove the remaining polymer, so that Fig.9E As shown, about 20 nm SiO2 is left on the top surface of the stack.

[0092] like Fig.9F As shown, SiO2 is then deposited as a hard mask on the device and patterned using photoresist 29 to prepare for etching the faceted regions of the stack at the edges of the cavity. The faceted edges of the stack are then etched using the SiO2 hard mask to form channels and remove defects from the faceted edge regions. Figure 9G As shown, etching removes the faceted edges of the upper InP layer 32, the InGaAsP layer 33, and the lower InP layer 31. Etching also removes the upper portion of the faceted edges of the InGaAs or InP layer 18. The etching forms two channels, one channel at the edge of the substrate cavity adjacent to the input waveguide, and one channel at the edge of the substrate cavity adjacent to the output waveguide.

[0093] like Figure 9HAs shown, silicon-rich Si3N4_h is then deposited on the device. Si3N4_h forms a layer 30 on the SiO2 layer and forms a layer in the base of each of the channels at the edge of the substrate cavity. Si3N4_h is also deposited on the sidewalls of the channel, where the thickness at the sidewalls is between 230nm and 260nm. Si3N4_h has a refractive index of 2.7.

[0094] like Fig.9I As shown, amorphous silicon is then deposited to fill the channel and form a layer on the Si3N4_h. SiO2 is then deposited on the amorphous silicon in the region above the channel, and the amorphous silicon is then etched from the region surrounding the channel, leaving the amorphous silicon in and above the channel.

[0095] like Figure 9K As shown, CMP is then used to remove SiO2, reduce the height of the remaining amorphous silicon, remove the Si3N4_h layer 30 and reduce the height of the SiO2 layer on the stack to about 20 nm.

[0096] The SiO2 layer is then patterned using a photoresist 29 to prepare a pattern that gives Figure 9L The desired waveguide shape shown is a waveguide, wherein the desired waveguide shape is included in Figure 1 Cross-sectional views along directions BB' and CC' are shown.

[0097] like Figure 9M As shown, a rib waveguide is formed in the stack by etching grooves through the upper InP layer 32, the InGaAsP layer 33 and the lower InP layer 31. The grooves also extend into the upper part of the InGaAs or InP layer 18. The ridge of the rib waveguide is formed by the stack between the etched grooves. At the same time, the SiO2 layer and the SOI layer 10 are etched to form a rib waveguide. Figure 9M The rib waveguides visible in the C-C' view form the input waveguide and the output waveguide.

[0098] A SiO2 layer of approximately 20-50 nm thickness is then deposited on the device to protect the device. Except for the SiO2 layer at the base of the first trench in the etched trenches, the sidewalls of the first trench at the ridge of the waveguide, and a portion of the top surface of the ridge of the waveguide, as shown in FIG. Fig.9O Photoresist is added to cover the device as shown. The first sidewalls of the upper InP layer 32 and the slab portion of the waveguide below the trench are then N-doped by silicon ion implantation. The rest of the device is not doped due to the presence of the photoresist.

[0099] The exposed portion is then covered with photoresist, and SiO2 is exposed at the base of another second trench, the sidewall of the second trench on the ridge of the waveguide, and a portion of the top surface of the ridge waveguide. Figure 9P It can be seen that the second sidewall of the upper InP layer 32, the slab portion of the waveguide below this trench, is then P-doped by Be or Zn ion implantation. The exposed portion is covered again with photoresist.

[0100] The photoresist on a portion of SiO2 at the base of the first trench is removed. Then, the photoresist is further removed by Figure 9Q Visible silicon ion implantation is used to dope a portion of the slab below the first trench to form an N+ doped region in the slab of the waveguide. The exposed portion is again covered with photoresist. The N+ region has a greater N doping concentration than the rest of the N doped region.

[0101] The photoresist on a portion of SiO2 at the base of the second trench is removed. Then, the photoresist is further removed by Figure 9R Be ions are implanted to dope a portion of the slab below the second trench to form a P+ doped region in the slab of the waveguide. The photoresist is then removed. The P+ region has a greater P doping concentration than the rest of the P doped region.

[0102] The order of the doping steps can be rearranged according to practical needs.

[0103] like Figure 8S As shown, 500 nm of SiO2 is then deposited on the device, and a rapid thermal annealing (RTA) is performed at 700°C to 850°C.

[0104] Then, the portion of the SiO2 layer above the N+ region and the P+ region is removed to form a contact hole ( Figure 9T ), and if Figure 9U The contact vias are shown metallized.

[0105] exist Figure 9U The resulting EAM device is shown in . The EAM is formed on a SOI platform 1 comprising a silicon base layer 8 , a buried oxide layer 9 and a SOI layer 10 . Figure 9U The EAM shown is on a 3 μm SOI platform with a height of 3 μm for the SOI layer 10, but in other embodiments other platform sizes may be used. The silicon base layer may be a (100) silicon substrate with a 6 degree bevel angle.

[0106] The substrate cavity extends through the SOI layer 10, through the BOX layer 9 and into the silicon base layer 8. The base of the cavity is formed in the silicon base layer 8.

[0107] The optoelectronic active stack is formed in the substrate cavity. The stack is formed by a lower InP layer 31, an InGaAsP layer 33 and an upper InP layer 32. The InGaAsP layer 33 and the upper InP layer are N-doped on one side and P-doped on the opposite side (e.g. Figure 9U The slab region of the rib waveguide formed in the stack is formed by a portion of the lower InP layer 31 and the InGaAsP layer 33. The slab is N-doped on a portion of one side and P-doped on a portion of the opposite side (as shown in FIG. Figure 9U The top surface of the stack has a height equal to the height of the top surface of the SOI layer 10 so that the stack does not protrude above the top of the substrate cavity.

[0108] In this embodiment, a PIN junction is formed horizontally between a P-doped region and an N-doped region on either side of the optoelectronic active stack.

[0109] The buffer region 11 below the optoelectronic active stack is composed of a Ge layer 21 on the base of the substrate cavity, a GaAs layer 20 on the Ge layer 21, a graded InAlAs layer 19 on the GaAs layer 20, and an InGaAs or InP layer 18 on the graded InAlAs layer 19. The buffer region 11 is on the base of the substrate cavity. The optoelectronic active stack is on the buffer region 11.

[0110] Other layers may be added to the stack / buffer region, one or more layers may be omitted from the stack / buffer region, and / or other layers may replace one or more layers in the stack / buffer region. The layers may be reordered.

[0111] Electrode 6 contacts an N+ doped region of the plane of the optoelectronic active stack, and electrode 7 contacts a P+ doped region of the plane of the optoelectronic active stack.

[0112] Like in the embodiment described above, the amorphous silicon region 5 is between the input waveguide 3 and the optoelectronic active stack, and between the optoelectronic active stack and the output waveguide 4. The amorphous silicon region 5 is surrounded by Si3N4.

[0113] Examples of the heights and compositions of the layers used in this embodiment are shown for an EAM realized on a 3 μm SOI platform with bulk III-V materials utilizing the FK effect in Table 4. The InGaSaP layers may be replaced by AlInGaAs layers.

[0114] surface:

[0115] Table 1: EAM EPI stack with InGaNAs MQW (QCSE)

[0116]

[0117] Table 2: EAM EPI stacks using bulk III-V materials via the FK effect

[0118]

[0119] Table 3: EAM EPI stack with AlInGaAs MQW (QCSE)

[0120]

[0121] Table 4: EAM EPI stacks using 3 μm bulk III-V materials via FK effect

[0122]

[0123] The features disclosed in the preceding description, or in the appended claims or in the drawings, expressed in their specific form or in terms of means for performing the disclosed functions, or methods or processes for obtaining the disclosed results, may, where appropriate, be used alone or in any combination of such features to implement the invention in diverse forms.

[0124] Although the present invention has been described in conjunction with the exemplary embodiments described above, many equivalent modifications and variations will be apparent to those skilled in the art when this disclosure is given. Therefore, the exemplary embodiments of the present invention set forth above should be considered to be illustrative rather than restrictive. Various changes may be made to the described embodiments without departing from the spirit and scope of the present invention.

[0125] To avoid any doubt, any theoretical explanations provided herein are provided for the purpose of enhancing the reader's understanding. The inventors do not wish to be bound by any of these theoretical explanations.

[0126] Any section headings used herein are for organizational purposes only and are not to be construed as limiting the subject matter described.

[0127] Throughout this specification, including the appended claims, unless the context requires otherwise, the words "comprise" and "comprising" and variations such as "comprises", "comprising" and "including", will be understood to imply the inclusion of stated integers or steps, or groups of integers or steps, but not the exclusion of any other integers or steps, or groups of integers or steps.

[0128] It must be noted that the singular forms "a / an" and "the" as used in this specification and the appended claims include plural references unless the context clearly indicates otherwise. Ranges may be expressed herein as from "about" one particular value, and / or to "about" another particular value. When such a range is expressed, another embodiment includes from a particular value and / or to another particular value. Similarly, when a value is expressed as an approximation by using the antecedent "about," it will be understood that the particular value forms another embodiment. The term "about" with respect to a numerical value is optional and means, for example, + / - 10%.

Claims

1. An optoelectronic active device, comprising: a silicon-on-insulator substrate comprising a silicon base layer, a buried oxide layer on top of the silicon base layer, a silicon-on-insulator layer on top of the buried oxide layer, and a substrate cavity extending through the silicon-on-insulator layer, the buried oxide layer and into the silicon base layer such that a base of the substrate cavity is formed by a portion of the silicon base layer; an optoelectronically active waveguide, the optoelectronically active waveguide comprising an optoelectronically active stack within the substrate cavity; as well as a buffer region, the buffer region being located below the optoelectronic active waveguide in the substrate cavity, the buffer region comprising a Ge layer and a GaAs layer; Wherein, the buffer region comprises a gradient InAlAs layer; and / or Wherein, the buffer region includes an InGaAs or InP layer.

2. The optoelectronic active device according to claim 1, wherein: In the case where the buffer region comprises a graded InAlAs layer and the buffer region comprises an InGaAs or InP layer, the InGaAs or InP layer is located on top of the graded InAlAs layer, the graded InAlAs layer is located on top of the GaAs layer, and the GaAs layer is located on top of the Ge layer.

3. The optoelectronic active device according to claim 1, wherein the Ge layer has a thickness of 1000nm+ / -20%, and / or the GaAs layer has a thickness of 1000nm+ / -20%, and / or the graded InAlAs layer has a thickness of 1300nm+ / -30%, and / or the InGaAs or InP layer has a thickness of 500nm to 1000nm.

4. The optoelectronic active device of claim 1, wherein the buffer region is composed of an intrinsic or unintentionally doped material.

5. The optoelectronic active device of claim 1, wherein the buffer region is epitaxially grown onto the base of the substrate cavity.

6. The optoelectronically active device of claim 1, wherein the optoelectronically active stack is located directly on top of the buffer region. 7 . The optoelectronic active device according to claim 6 , wherein the optoelectronic active stack is epitaxially grown on the buffer region.

8. An optoelectronic active device according to any one of claims 6 or 7, wherein the interface between the optoelectronic active stack and the buffer region is positioned in the substrate cavity deeper than the interface between the silicon base layer and the buried oxide layer in the silicon-on-insulator substrate, so that a portion of the optoelectronic active stack is positioned at the same height as a portion of the silicon base layer.

9. The optoelectronic active device of claim 1, wherein the optoelectronic active stack comprises a III-V semiconductor layer.

10. The optoelectronic active device of claim 1, wherein the optoelectronic active stack comprises a multi-quantum well region.

11. The optoelectronic active device of claim 1, wherein the optoelectronic active stack forms an electro-absorption modulator (EAM).

12. The optoelectronic active device according to claim 1, wherein the optoelectronic active waveguide is configured such that an optical property of the optoelectronic active waveguide can be modified according to a QCSE effect or a FK effect.

13. The optoelectronic active device of claim 1, further comprising a channel between the optoelectronic active stack and the sidewall of the substrate cavity; The channel is filled with liner and filler materials having a refractive index similar to or greater than the refractive index of the material forming the sidewalls of the substrate cavity, thereby forming a bridge waveguide in the channel between the silicon-on-insulator layer and the optoelectronic active stack.

14. The optoelectronic active device according to claim 13, wherein the filling material is amorphous silicon or silicon germanium (SiGe), and the liner is formed of silicon nitride (Si3N4).

15. An optoelectronic active device according to claim 13 or 14, wherein a bottom surface of the filling material is aligned with a top surface of the buried oxide layer.

16. The optoelectronic active device of claim 1, wherein a top surface of the optoelectronic active stack is positioned higher than a top surface of the silicon-on-insulator layer such that a portion of the optoelectronic active stack protrudes from the substrate cavity.

17. The optoelectronic active device of claim 16, further comprising a silicon nitride (Si3N4) layer on top of the silicon-on-insulator layer, the top surface of the silicon nitride having a height above the silicon-on-insulator substrate equal to the height of the portion of the optoelectronic active stack protruding from the substrate cavity, such that the top surface of the silicon nitride layer is aligned with the top surface of the optoelectronic active stack.

18. The optoelectronic active device according to claim 1, further comprising: a first electrode contact on a first doped region, the first doped region forming a lowermost layer of the optoelectronic active stack; an isolated cavity in the first doped region; an insulating material disposed on a side surface of the optoelectronic active stack and extending into and lining the isolation cavity in the first doped region; as well as A second electrode contact is provided on a second doped region, the second doped region forming a top layer of the optoelectronic active stack, the contact extending from the second doped region along the insulating material and into the isolation cavity in the first doped region.

19. A method of producing an optoelectronic active device, the method comprising the steps of: providing a silicon-on-insulator substrate comprising a silicon base layer, a buried oxide layer on top of the silicon base layer, and a silicon-on-insulator layer on top of the buried oxide layer; etching a substrate cavity in a portion of the silicon-on-insulator substrate through the silicon-on-insulator layer, through the buried oxide layer and into the silicon base layer; Forming a buffer region in the substrate cavity, wherein the step of forming the buffer region comprises epitaxially growing a Ge layer and epitaxially growing a GaAs layer; epitaxially growing an optoelectronic active stack within the substrate cavity and on top of the buffer region; etching the optoelectronically active stack to form an optoelectronically active waveguide; as well as etching the silicon-on-insulator substrate to form a silicon-on-insulator waveguide configured to guide light waves through the optoelectronically active waveguide; Wherein, the step of forming a buffer region in the substrate cavity further comprises epitaxially growing a graded InAlAs layer; and / or Wherein, the step of forming a buffer region in the substrate cavity further comprises epitaxially growing an InGaAs or InP layer.

20. The method of producing an optoelectronic active device according to claim 19, wherein the step of forming a buffer region in the substrate cavity comprises: epitaxially growing the Ge layer on a portion of the silicon base layer forming the base of the substrate cavity; then epitaxially growing the GaAs layer on the Ge layer; and then epitaxially growing the graded InAlAs layer on the GaAs layer; and then An InGaAs or InP layer is epitaxially grown on the graded InAlAs layer.

21. The method of producing an optoelectronic active device according to claim 19, wherein The interface between the optoelectronic active stack and the buffer region is positioned deeper in the substrate cavity than the interface between the silicon base layer and the buried oxide layer in the silicon-on-insulator substrate, so that a portion of the optoelectronic active stack is positioned at the same height as a portion of the silicon base layer.

22. The method of producing an optoelectronic active device according to claim 19, further comprising the following steps: Before etching the substrate cavity, depositing a silicon nitride layer on the silicon-on-insulator substrate such that a top surface of the silicon nitride has a first height above the silicon-on-insulator substrate, After the optoelectronic active stack is grown, a portion of the optoelectronic active stack protrudes from the substrate cavity by a height equal to the first height, so that the top surface of the silicon nitride layer is aligned with a top surface of the optoelectronic active stack.

23. The method of producing an optoelectronic active device according to claim 19, further comprising depositing silicon nitride on the sidewalls of the substrate cavity prior to epitaxially growing the buffer region.

24. The method of producing an optoelectronic active device according to claim 19, wherein the epitaxially grown optoelectronic active stack has facets in a region adjacent to a sidewall of the substrate cavity; the method further comprising the steps of: etching the region to remove the facets and create a channel between the sidewalls and the stack; as well as The channel is filled with a fill material having a refractive index similar to or greater than a refractive index of a material forming the sidewalls such that the fill material forms a bridge waveguide in the channel between the silicon-on-insulator waveguide and the optoelectronic active stack.

25. The method of producing an optoelectronic active device according to claim 19, wherein the epitaxially grown optoelectronic active stack has facets in regions adjacent to the sidewalls of the substrate cavity; the method further comprising the following steps: etching the region to remove the facets and create a channel between the sidewalls and the stack; lining the passage with a liner to provide a lined passage; as well as The lined channel is filled with a fill material having a refractive index similar to that of the material forming the sidewalls such that the fill material forms a bridge waveguide in the channel between the silicon-on-insulator waveguide and the optoelectronic active stack.

26. A method of producing an optoelectronic active device according to claim 25, wherein the liner is formed of silicon nitride.

27. A method of producing an optoelectronic active device according to any one of claims 25 to 26, wherein the filling material is amorphous silicon or silicon germanium (SiGe).

28. A method of producing an optoelectronic active device according to any one of claims 24 to 26, wherein the step of etching the region to remove the facets and create the channel between the sidewalls and the stack comprises any of the following: (i) etching through the optoelectronic active stack and into the buffer region such that the base of the channel is formed by a portion of the buffer region; or (ii) etching into the optoelectronically active stack such that the base of the channel is formed by a portion of the optoelectronically active stack.

29. The method of producing an optoelectronic active device according to claim 27, wherein the step of etching the region to remove the facets and create the channel between the sidewalls and the stack comprises: Etching to a position lower than an interface between the silicon base layer and the buried oxide layer in the silicon-on-insulator substrate so that a top surface of the liner at the base of the channel is at the same height as a top surface of the buried oxide layer.

30. The method of producing an optoelectronic active device according to claim 19, further comprising the following steps: depositing a first electrode contact on a first doped region, the first doped region forming a bottom layer of the optoelectronic active stack; etching an isolation cavity in the first doped region; depositing an insulating material on side surfaces of the optoelectronic active stack and in the isolation cavity in the first doped region to line the isolation cavity and thereby electrically isolate the isolation cavity from the optoelectronic active stack; as well as A second electrode contact is deposited on a second doped region, the second doped region forming a top layer of the optoelectronic active stack, the contact extending into the isolation cavity in the first doped region.

31. The method of producing an optoelectronic active device according to claim 19, further comprising the following steps: An amorphous silicon layer is etched from a region above the silicon-on-insulator substrate and proximate to the cavity, followed by the step of performing a chemical mechanical planarization of the SiO2 layer above the optoelectronic active stack.

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