Light detection device, method for manufacturing light detection device, and electronic apparatus

Abstract

Provided is a light detection device in which an oxide film is formed on the bottom of a fin of a transistor in a bulk substrate without using an SOI substrate. The light detection device includes a first substrate portion and a second substrate portion. The first substrate portion has pixels that photoelectrically convert incident light. The second substrate portion is bonded to a surface of the first substrate portion opposite to a light incident surface. The second substrate portion has a plurality of elements constituting a readout circuit configured to output a pixel signal based on a charge output from the pixel. A pattern of an insulating film is formed on a bonding surface of the second substrate part that is bonded to the first substrate part.

Description

Technical Field

[0001] The technology according to the present invention (the present technology) relates to a light detecting device, a method for manufacturing the light detecting device, and an electronic device including the light detecting device. Background Art

[0002] For example, Patent Documents 1 and 2 disclose a light detection device having a three-dimensional structure. This structure increases the element density in the stacking direction by stacking multiple semiconductor substrates, each containing elements such as transistors. This three-dimensional structure not only allows the use of a single plane, but also increases the number of elements on a plane by stacking two or three planes. Even with miniaturized pixels, it is possible to ensure sufficient area for the photoelectric converter and pixel transistors.

[0003] Fin-type field-effect transistors (FFETs) are known as transistors, in which a portion of the gate electrode is embedded in a semiconductor substrate. To improve the characteristics of these FFETs, a structure has been proposed in which the bulk substrate is replaced with an SOI (silicon on insulator) substrate and an oxide film is placed at the bottom of the fin. [Citation List] [Patent Document]

[0004] [Patent Document 1] Japanese Patent Application Laid-Open No. JP2018-50057 [Patent Document 2] International Application Publication No. WO 2020 / 105713 Summary of the Invention [Technical problems to be solved]

[0005] In the fin-type field-effect transistor using the SOI substrate described above, since the fin is formed on the oxide film, there is no leakage, etc., and excellent characteristics can be obtained. However, the use of the SOI substrate complicates the process.

[0006] The present invention is designed in view of the above situation and aims to provide a light detection device having an oxide film at the bottom of a transistor fin in a bulk substrate without using an SOI substrate, a method for manufacturing the light detection device, and an electronic device. [Technical solutions to technical problems]

[0007] One aspect of the present invention is a light detection device comprising a first substrate portion and a second substrate portion. The first substrate portion has pixels that perform photoelectric conversion on incident light. The second substrate portion is bonded to a surface of the first substrate portion opposite the light incident surface and has a plurality of elements that constitute a readout circuit configured to output pixel signals based on the charge output from the pixels. An insulating film pattern is formed on the bonding surface of the second substrate portion that bonds to the first substrate portion.

[0008] Another aspect of the present invention is a method for manufacturing a light detection device, the manufacturing method comprising: preparing a first substrate portion and a second substrate portion, the first substrate portion having pixels for performing photoelectric conversion on incident light, the second substrate portion having a plurality of elements for constituting a readout circuit, the readout circuit being constructed to output a pixel signal based on the charge output from the pixel; forming a pattern of an insulating film on a bonding surface of the second substrate portion bonded to the first substrate portion; and bonding the first substrate portion and the second substrate portion after forming the pattern of the insulating film.

[0009] Yet another aspect of the present invention is an electronic device including a light detecting device, the light detecting device comprising: a first substrate portion having pixels that perform photoelectric conversion on incident light; and a second substrate portion bonded to a surface of the first substrate portion opposite the light incident surface and having a plurality of elements constituting a readout circuit configured to output pixel signals based on the charge output from the pixels. An insulating film pattern is formed on a surface of the second substrate portion bonded to the first substrate portion. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 : is a schematic diagram showing a configuration example of a light detection device according to a first embodiment of the present invention. Figure 2 It shows Figure 1 A circuit diagram showing an example of the configuration of a pixel unit of a light detection device shown. Figure 3 is used to form Figure 2 The cross-sectional view of the first substrate and the second substrate of the pixel unit is shown. Figure 4 FIG. 1 is a partial longitudinal cross section showing an example of the semiconductor structure of the light detecting device according to the first embodiment of the present invention. Figure 5A is a plan view showing one example of the semiconductor structure of the light detecting device according to the first embodiment of the present invention. Figure 5B is a plan view showing another example of the semiconductor structure of the light detecting device according to the first embodiment of the present invention. Figure 6A 1 is a cross-sectional view showing steps of a method for manufacturing the light detecting device according to the first embodiment of the present invention. Figure 6B 2 is a cross-sectional view showing steps of the method for manufacturing the light detecting device according to the first embodiment of the present invention. Figure 6C 3 is a cross-sectional view showing steps of a method for manufacturing the light detecting device according to the first embodiment of the present invention. Figure 6D 4 is a cross-sectional view showing steps of the method for manufacturing the light detecting device according to the first embodiment of the present invention. Figure 6E 5 is a cross-sectional view showing steps of the method for manufacturing the light detecting device according to the first embodiment of the present invention. Figure 6F 1 is a cross-sectional view (part 6) showing steps of the method for manufacturing the light detecting device according to the first embodiment of the present invention. Figure 6G 7 is a cross-sectional view showing steps of the method for manufacturing the light detecting device according to the first embodiment of the present invention. Figure 6H 8 is a cross-sectional view showing steps of a method for manufacturing the light detecting device according to the first embodiment of the present invention. Figure 7 1 is a cross-sectional view for explaining a state in which misalignment of element separation portions is prevented by a through-contact region according to the first embodiment of the present invention. Figure 8A 1 is a cross-sectional view showing steps of a method for manufacturing a light detecting device according to a modification of the first embodiment of the present invention. Figure 8B 2 is a cross-sectional view showing steps of a method for manufacturing a light detecting device according to a modification of the first embodiment of the present invention. Figure 9A 1 is a cross-sectional view showing steps of a method for manufacturing a light detecting device according to a second embodiment of the present invention. Figure 9B 2 is a cross-sectional view showing steps of a method for manufacturing a light detecting device according to a second embodiment of the present invention. Figure 9C 3 is a cross-sectional view showing steps of a method for manufacturing a light detecting device according to a second embodiment of the present invention. Figure 9D 4 is a cross-sectional view showing steps of a method for manufacturing a light detecting device according to a second embodiment of the present invention. Figure 10A: is a cross-sectional view (one of) illustrating steps of a method for manufacturing a light detecting device according to a third embodiment of the present invention. Figure 10B 2 is a cross-sectional view showing steps of a method for manufacturing a light detecting device according to a third embodiment of the present invention. Figure 10C 3 is a cross-sectional view showing steps of a method for manufacturing a light detecting device according to a third embodiment of the present invention. Figure 11 FIG. 1 is a partial longitudinal cross section showing an example of a semiconductor structure of a light detecting device according to a modification of the third embodiment of the present invention. Figure 12A 4 is a cross-sectional view (one of) illustrating steps of a method for manufacturing a light detecting device according to a fourth embodiment of the present invention. Figure 12B 2 is a cross-sectional view showing steps of a method for manufacturing a light detecting device according to a fourth embodiment of the present invention. Figure 12C 3 is a cross-sectional view showing steps of a method for manufacturing a light detecting device according to a fourth embodiment of the present invention. Figure 13 : is a block diagram showing a configuration example of an imaging device as an electronic device to which the present technology is applied. Figure 14 An example of a schematic configuration of an endoscopic surgery system to which the present technology is applied is shown. Figure 15 It shows Figure 14 A block diagram showing an example of the functional configuration of a camera head and CCU is shown. Figure 16 is a block diagram showing an example of a schematic configuration of a vehicle control system to which the present technology is applied. Figure 17 It shows Figure 16 1 and 2 are explanatory diagrams showing examples of installation positions of the vehicle exterior information detection unit and the imaging unit. DETAILED DESCRIPTION

[0011] Embodiments of the present invention will be described below with reference to the accompanying drawings. In the following description with reference to the accompanying drawings, identical or similar parts are represented by identical or similar reference numerals, and repeated descriptions are omitted. However, it should be noted that the accompanying drawings are schematic, and the relationship between thickness and planar dimensions and the thickness ratio of each device and each component may differ from the actual relationship and ratio. Therefore, the specific thickness and dimensions should be determined in consideration of the following description. Furthermore, it goes without saying that each of the accompanying drawings also includes parts having different dimensional relationships and ratios.

[0012] In this specification, "first conductivity type" refers to one of p-type and n-type, and "second conductivity type" refers to one of p-type and n-type that is different from the "first conductivity type." Furthermore, semiconductor regions represented by the symbols "n" and "p" with "+" or "-" appended indicate that the semiconductor regions have relatively higher and relatively lower impurity concentrations, respectively, compared to semiconductor regions represented by the symbols "n" and "p" without "+" or "-." However, this does not necessarily mean that semiconductor regions with the same symbol "n" have exactly the same impurity concentrations.

[0013] Furthermore, it should be understood that the definitions of directions such as upward and downward in the following description are provided for simplicity only and are not intended to limit the technical concept of the present invention. For example, it is obvious that when an object is observed after being rotated 90 degrees, up and down are switched and described as left and right, and when the object is observed after being rotated 180 degrees, up and down are described as reversed. The beneficial effects described herein are merely exemplary and not limiting, and other beneficial effects may also occur.

[0014] <First embodiment> (Overall Structure of the Light Detection Device) Figure 1 : is a schematic diagram showing a configuration example of a light detection device according to a first embodiment of the present invention.

[0015] like Figure 1 As shown, the light detection device 1 includes a first substrate 10, a second substrate 20, and a third substrate 30. The three substrates are bonded to each other. The first substrate 10, the second substrate 20, and the third substrate 30 are stacked in sequence.

[0016] The first substrate 10 has a plurality of sensor pixels 12 for performing photoelectric conversion, disposed on a first semiconductor substrate 11. The plurality of sensor pixels 12 are arranged in a matrix in a pixel region 13 of the first substrate 10. The second substrate 20 has a readout circuit 22 disposed on the second semiconductor substrate 21 for reading pixel signals based on the charge output from the sensor pixels 12. One readout circuit 22 is provided for every four sensor pixels 12. The second substrate 20 has a plurality of pixel drive lines 23 extending in the row direction and a plurality of vertical signal lines 24 extending in the column direction.

[0017] The third substrate 30 includes a logic circuit 32 for processing pixel signals, which is disposed on a third semiconductor substrate 31. The logic circuit 32 includes, for example, a vertical drive circuit 33, a column signal processing circuit 34, a horizontal drive circuit 35, and a system control circuit 36. The logic circuit 32 (specifically, the horizontal drive circuit 35) outputs an output voltage Vout to the outside for each sensor pixel 12. In the logic circuit 32, for example, a low-resistance region composed of silicide formed using a self-aligned silicide (SAL) process employing CoSi2, NiSi, or the like may be formed on the surface of the impurity diffusion region in contact with the source and drain electrodes.

[0018] The vertical drive circuit 33 sequentially selects a plurality of sensor pixels 12, for example, in rows. The column signal processing circuit 34 performs, for example, correlated double sampling (CDS) processing on the pixel signals output from each sensor pixel 12 in the row selected by the vertical drive circuit 33. For example, the column signal processing circuit 34 extracts the signal level of the pixel signal through CDS processing and stores pixel data corresponding to the amount of light received by each sensor pixel 12. The horizontal drive circuit 35 sequentially outputs the pixel data stored in the column signal processing circuit 34 to the outside. The system control circuit 36 ​​controls the driving of each block in the logic circuit 32 (the vertical drive circuit 33, the column signal processing circuit 34, and the horizontal drive circuit 35).

[0019] (Example of a pixel unit circuit configuration) Figure 2 is a circuit diagram showing a configuration example of the pixel unit PU of the light detection device 1 . like Figure 2 As shown, one pixel unit PU includes four sensor pixels 12 and one readout circuit 22. In other words, one readout circuit 22 is shared among the four sensor pixels 12, and outputs of the four sensor pixels 12 are input to the shared readout circuit 22.

[0020] Each sensor pixel 12 includes: a photodiode PD as a photoelectric conversion element; and a transfer transistor TR electrically connected to the photodiode PD.

[0021] The readout circuit 22 includes a floating diffusion FD, an amplifier transistor AMP, a reset transistor RST, and a selection transistor SEL. Note that the selection transistor SEL may be omitted as needed.

[0022] In the following description, when it is necessary to distinguish four sensor pixels 12 connected to one readout circuit 22 from each other, as shown in FIG. Figure 2 As shown in FIG. 1 , these sensor pixels 12 are referred to as sensor pixels 121 to 124. Similarly, the photodiodes PD and transfer transistors TR included in the sensor pixels 121 to 124 are also referred to as photodiodes PD1 to PD4 and transfer transistors TR1 to TR4. When there is no need to distinguish the four sensor pixels 12, the photodiodes PD, and the transfer transistors TR from one another, their subscripts are omitted.

[0023] The photodiode PD performs photoelectric conversion to generate charge corresponding to the amount of light received. The cathode of the photodiode PD is electrically connected to the source of the transfer transistor TR, and the anode of the photodiode PD is electrically connected to a reference potential line (e.g., ground). The drain of the transfer transistor TR is electrically connected to the floating diffusion FD, and the gate electrode of the transfer transistor TR is electrically connected to the pixel drive line 23.

[0024] The input terminal of the readout circuit 22 is the floating diffusion FD, and the source of the reset transistor RST is electrically connected to the floating diffusion FD. A predetermined power supply voltage VDD is supplied to the drain of the reset transistor RST and the drain of the amplifier transistor AMP. The gate electrode of the reset transistor RST is electrically connected to the pixel drive line 23 ( Figure 1 ). The source of the amplifier transistor AMP is electrically connected to the drain of the selection transistor SEL, and the gate electrode of the amplifier transistor AMP is electrically connected to the source of the reset transistor RST. The source of the selection transistor SEL serves as an output terminal of the readout circuit 22 and is electrically connected to the vertical signal line 24. The gate electrode of the selection transistor SEL is electrically connected to the pixel drive line 23 (refer to Figure 1 ).

[0025] Figure 2 The wiring L1 to wiring L9 in FIG. 1 correspond to the wiring L1 to wiring L9 to be described later. Figure 3 The wiring L1 to the wiring L9 in. When the transfer transistor TR turns on in response to a control signal supplied to its gate electrode via the pixel drive line 23 and the wiring L9, it transfers the charge from the photodiode PD to the floating diffusion FD. The floating diffusion FD temporarily holds the charge output from the photodiode PD via the transfer transistor TR. The reset transistor RST resets the potential of the floating diffusion FD to a predetermined potential. When the reset transistor RST turns on, the potential of the floating diffusion FD is reset to the power supply voltage VDD.

[0026] The amplifier transistor AMP generates a pixel signal with a voltage corresponding to the charge held in the floating diffusion FD. Together with a load MOS transistor (not shown) acting as a constant current source, the amplifier transistor AMP forms a source-follower circuit and outputs a pixel signal with a voltage corresponding to the level of charge generated in the photodiode PD. When the select transistor SEL is turned on, the amplifier transistor AMP amplifies the potential of the floating diffusion FD and outputs pixel information with a voltage corresponding to this potential to the column signal processing circuit 34 via the vertical signal line 24. The select transistor SEL controls the output timing of the pixel signal from the readout circuit 22. When the select transistor SEL is turned on, a pixel signal with a voltage corresponding to the level of charge held in the floating diffusion FD can be output.

[0027] The transfer transistor TR, the reset transistor RST, the amplifier transistor AMP, and the selection transistor SEL include, for example, N-type MOSFETs (Metal Oxide Semiconductor Field Effect Transistors).

[0028] (Example of a stacked pixel unit structure) Figure 3 1 is a cross-sectional view of the first substrate 10 and the second substrate 20 on which the pixel unit PU is formed. Figure 3 The cross-sectional view shown is a schematic diagram, but is not intended to strictly and accurately show the actual structure. In order to easily explain the structure of the pixel unit PU included in the light detection device 1 on paper, Figure 3 The illustrated cross-sectional view includes a portion where the positions of the transistor and the impurity diffusion layer in the horizontal direction are intentionally changed.

[0029] For example, in Figure 3 In the figure, the high-concentration n-type layer (n-type diffusion layer) 51, which forms part of the floating diffusion FD, the gate electrode TG of the transfer transistor TR, and the high-concentration p-type layer (p-type diffusion layer) 52 are arranged in a lateral direction. However, in actual structures, the high-concentration n-type layer 51, the gate electrode TG, and the high-concentration p-type layer 52 may be arranged in a vertical direction on the paper. In this case, one of the high-concentration n-type layer 51 and the high-concentration p-type layer 52 is arranged near the front of the paper, while the other is arranged in the back of the paper, across the gate electrode TG.

[0030] like Figure 3As shown, in the light detection device 1, a first substrate 10 and a second substrate 20 are stacked to form a stacked body. The first substrate 10 includes a first semiconductor substrate 11, and the second substrate 20 is stacked on the front surface 11a side of the first semiconductor substrate 11. In other words, the second substrate 20 is attached to the first substrate 10 in a face-to-back manner.

[0031] On the front surface 11a side of the first semiconductor substrate 11, a transfer transistor TR is provided for each sensor pixel 12. The source of the transfer transistor TR is a high-concentration n-type layer 51. The high-concentration n-type layer 51 provided for each sensor pixel 12 is electrically connected to each other via wiring L2 and constitutes a floating diffusion FD.

[0032] The back side of the first substrate 10, opposite the front side 11a, serves as a light incident surface. Therefore, the photodetection device 1 is a back-illuminated solid-state imaging device having a color filter and an on-chip lens on the back side, which serves as the light incident surface. For example, a color filter and an on-chip lens are provided for each sensor pixel 12.

[0033] The first semiconductor substrate 11 included in the first substrate 10 is composed of, for example, a silicon substrate. A p-type layer 53 (hereinafter referred to as the p-well 53) serving as a well layer is provided in and near a portion of the front surface 11a of the first semiconductor substrate 11. An n-type layer 54 constituting the photodiode PD is provided in a region deeper than the p-well 53. The gate electrode TG of the transfer transistor TR extends from the front surface 11a of the first semiconductor substrate 11 through the p-well 53 to a depth within the n-type layer 54 serving as the photodiode PD. A reference potential (e.g., ground potential: 0 V) ​​is supplied to the high-concentration p-type layer 52, serving as a contact of the p-well 53, via wiring L1, setting the potential in the p-well 53 to the reference potential.

[0034] A pixel isolation layer 55 is provided in the first semiconductor substrate 11 to electrically isolate adjacent sensor pixels 12. The pixel isolation layer 55 has, for example, a DTI (Deep Trench Isolation) structure and extends in the depth direction of the first semiconductor substrate 11. The pixel isolation layer 55 is made of, for example, silicon oxide. In the first semiconductor substrate 11, a p-type layer 56 and an n-type layer 57 are provided between the pixel isolation layer 55 and the photodiode PD (n-type layer 54). The p-type layer 56 is formed on the pixel isolation layer 55 side, and the n-type layer 57 is formed on the photodiode PD side.

[0035] An interlayer insulating film 58 is provided on the front surface 11a side of the first semiconductor substrate 11. The interlayer insulating film 58 is, for example, one of a silicon oxide film (SiO), a silicon nitride film (SiN), a silicon oxynitride film, and a silicon carbonitride film, or a stacked film composed of two or more of these films.

[0036] For example, the second semiconductor substrate 21 included in the second substrate 20 is formed of a silicon substrate. The second semiconductor substrate 21 has a front surface 21a facing the first substrate 10 and a back surface 21b located on the opposite side to the front surface 21a. Figure 3 , the front surface 21a is the lower surface, and the back surface 21b is the upper surface.

[0037] The second semiconductor substrate 21 includes, for example, a p-type layer 71 (hereinafter referred to as a p-well 71 ) as a well layer. An amplifier transistor AMP, a selection transistor SEL, and a reset transistor RST are formed on the back surface 21 b side of the second semiconductor substrate 21 .

[0038] An element isolation portion 72 is formed between the amplifier transistor AMP and the reset transistor RST. A high-concentration p-type layer 73, serving as a contact to the p-well 71, is formed between the select transistor SEL and the reset transistor RST. An element isolation portion 72 is also formed between the select transistor SEL and the high-concentration p-type layer 73, and between the reset transistor RST and the high-concentration p-type layer 73. The element isolation portion 72 has, for example, an STI (Shallow Trench Isolation) structure. A reference potential (e.g., ground potential: 0 V) ​​is supplied to the high-concentration p-type layer 73 via wiring L1, setting the potential of the p-well 71 to the reference potential.

[0039] The amplifier transistor AMP includes a gate electrode AG, a high-concentration n-type layer 74 serving as a drain, and a high-concentration n-type layer 75 serving as a source (hereinafter referred to as a source portion 75). The gate electrode AG of the amplifier transistor AMP has a structure partially buried in the depth direction from the substrate surface (back surface 21b) of the second semiconductor substrate 21.

[0040] The reset transistor RST includes a gate electrode RG, a high-concentration n-type layer 76 serving as a drain (hereinafter referred to as the drain portion 76 ), and a high-concentration n-type layer 77 serving as a source (hereinafter referred to as the source portion 77 ). The select transistor SEL includes a gate electrode SG, a high-concentration n-type layer 78 serving as a drain, and a high-concentration n-type layer 79 serving as a source.

[0041] The gate electrode AG of the amplifier transistor AMP is connected to the high-concentration n-type layer 51 provided for each sensor pixel 12 in the first semiconductor substrate 11 via a wiring L2. Furthermore, the gate electrode AG of the amplifier transistor AMP is connected to the source portion 77 of the reset transistor RST via a wiring L3. The floating diffusion portion FD is composed of the high-concentration n-type layer 51 of each sensor pixel 12, the source portion 77 of the reset transistor RST, and the wirings L2 and L3.

[0042] The high-concentration n-type layer 74, which serves as the drain electrode of the amplifier transistor AMP, and the drain portion 76 of the reset transistor RST are connected via wiring L4. A predetermined power supply voltage VDD is supplied to the high-concentration n-type layer 74 and the drain portion 76 via wiring L4. Alternatively, the high-concentration n-type layer 74 and the drain portion 76 may be connected via separate wiring. In this case, the drive voltages for the amplifier transistor AMP and the reset transistor RST are set separately.

[0043] The source portion 75 of the amplifier transistor AMP and the high-concentration n-type layer 78 serving as the drain of the select transistor SEL are connected via a wiring L5. The source portion 75 and the high-concentration n-type layer 78 can be connected via the wiring L5 or, by devising a layout without using the wiring L5, can be connected so that the high-concentration n-type layer 78 of the second semiconductor substrate 21 is shared.

[0044] The gate electrode RG of the reset transistor RST is connected to the pixel drive line 23 via the wiring L6 , and a drive signal for controlling the reset transistor RST is supplied from the vertical drive circuit 33 .

[0045] The gate electrode SG of the selection transistor SEL is connected to the pixel drive line 23 via the wiring L7, and a drive signal for controlling the selection transistor SEL is supplied from the vertical drive circuit 33. The high-concentration n-type layer 79 serving as the source of the selection transistor SEL is connected to the vertical signal line 24 ( Figure 2 ), and a pixel signal having a voltage corresponding to the charge held in the floating diffusion FD is output to the vertical signal line 24 via the wiring L8.

[0046] The gate electrode TG of the transfer transistor TR is connected to the pixel drive line 23 via the wiring L9 , and a drive signal for controlling the transfer transistor TR is supplied from the vertical drive circuit 33 .

[0047] The second substrate 20 includes an insulating film 81 that covers the front surface 21a, a portion of the back surface 21b, and the side surfaces of the second semiconductor substrate 21. For example, the insulating film 81 is a laminated film formed of one of SiO, SiN, SiON, and SiCN, or at least two of these. The interlayer insulating film 58 of the first substrate 10 and the interlayer insulating film 81 of the second substrate 20 are bonded to each other to form an interlayer insulating layer 82.

[0048] The wiring L1 to wiring L9 can be made of any metal material or conductive semiconductor material. For example, the portion extending in the stacking direction of the first substrate 10 and the second substrate 20 can be made of tungsten (W), while the portion extending in a direction perpendicular to the stacking direction (e.g., horizontally) can contain copper (Cu) or a Cu alloy containing Cu as a main component.

[0049] <Comparative Example of First Embodiment> In a two-stage pixel structure in which pixel transistors such as the amplifier transistor AMP are formed on different substrates, the pixel transistors are fin-type field-effect transistors. To improve the characteristics of this fin-type field-effect transistor, a structure has been proposed in which the bulk substrate is replaced with an SOI substrate and an oxide film is provided at the bottom of the fin.

[0050] The above structure improves the characteristics of FinFETs by forming the fins on an oxide film. This reduces leakage and achieves excellent characteristics. However, the use of an SOI substrate complicates the process. Furthermore, since the transistor channel is formed on the SOI substrate, high-quality control of film thickness and crystal quality is required.

[0051] <Solution of the First Embodiment> To address the above-mentioned problem, a first embodiment of the present invention has a structure in which an oxide film is provided on the bottom of the fin in a bulk substrate without using an SOI substrate. Figure 4 FIG is a partial longitudinal cross section showing an example of the semiconductor structure of the light detecting device 1 according to the first embodiment of the present invention. Figure 4 In, with Figure 3 The same parts are denoted by the same reference numerals, and detailed descriptions thereof are omitted.

[0052] As a specific structure, such as Figure 4 As shown in FIG. 1 , a process is adopted as follows: before bonding the second substrate 20 to the first substrate 10, an element separation portion 72 is formed in the area of ​​the second semiconductor substrate 21 that will become the bottom of the fin, and an oxide film is buried in the element separation portion 72. Then, the first substrate 10 and the second substrate 20 are bonded to each other. Next, the same process as that of a conventional bulk substrate is performed to form a structure that becomes an oxide film at the bottom of the fin. In addition, the element separation portion 72 can be as shown in FIG. Figure 5A As shown, it is formed in a strip shape on the second semiconductor substrate 21, or it can be formed as Figure 5B The element separation portion 72 is formed in an island shape. Alternatively, the element separation portion 72 may be formed in a mesh shape or the like.

[0053] On the second semiconductor substrate 21, three element isolation portions 72-1, 72-2, and 72-3 are formed. Figure 4The element isolation portion 72-1 is arranged in the direction indicated by the arrow X. Among these element isolation portions, the element isolation portion 72-1 is formed by a back STI portion 72a formed on the bonding surface side (the back side of the second substrate 20) bonded to the first substrate 10 and a back STI portion 72a extending from the back STI portion 72a to the side opposite to the bonding surface (on the back side of the second substrate 20). Figure 4 The element isolation portions 72-2 and 72-3 each consist of a back-side STI portion 72a and three front-side STI portions 72b1, 72b2, and 72b3.

[0054] A planar field effect transistor 41 is formed on the element isolation portion 72-1. The planar field effect transistor 41 is composed of a gate electrode 41a that bridges the two front STI portions 72b1 and 72b2 of the element isolation portion 72-1, a channel portion 41b provided between the two front STI portions 72b1 and 72b2, and a gate oxide film 41c provided between the gate electrode 41a and the channel portion 41b. The channel portion 41b is connected to the Figure 4 The source and drain portions are arranged in the direction indicated by the arrow Y.

[0055] A fin field-effect transistor 42 is formed on the element isolation portion 72-2. The fin field-effect transistor 42 is composed of a gate electrode 42a formed by digging into three front-side STI portions 72b1, 72b2, and 72b3, element forming portions (fin portions) 42b1 and 42b2 that protrude from the element isolation portion 72-2 and are arranged side by side at predetermined intervals, a gate oxide film 42c1 provided between the gate electrode 42a and the fin portion 42b1, and a gate oxide film 42c2 provided between the gate electrode 42a and the fin portion 42b2.

[0056] That is, the gate electrode 42a and the gate oxide film 42c1 are provided over the top and side surfaces of the fin portion 42b1. In addition, the gate electrode 42a and the gate oxide film 42c2 are provided over the top and side surfaces of the fin portion 42b2. Therefore, due to the thickness of the gate oxide films 42c1 and 42c2 provided on the top surfaces of the fin portions 42b1 and 42b2, and the thickness of the gate oxide films 42c1 and 42c2 provided on the side surfaces of the fin portions 42b1 and 41b2, the gate electrode 42a can simultaneously apply a gate voltage to the top and side surfaces of each of the fin portions 42b1 and 42b2. In addition, the fin portions 42b1 and 42b2 are connected to the Figure 4 The source and drain portions are arranged in the direction indicated by the arrow Y.

[0057] A fin field-effect transistor 43 is formed on the element isolation portion 72-3. The fin field-effect transistor 43 is composed of a gate electrode 43a formed by digging into two front-side STI portions 72b1 and 72b2, a fin portion 43b protruding from the back-side STI portion 72a of the element isolation portion 72-3, and a gate oxide film 43c provided between the gate electrode 43a and the fin portion 43b.

[0058] That is, the gate electrode 43a and the gate oxide film 43c are provided over the top and side surfaces of the fin portion 43b. Therefore, due to the thickness of the gate oxide film 43c provided on the top and side surfaces of the fin portion 43b, the gate electrode 43a can apply a gate voltage to both the top and side surfaces of the fin portion 43b. In addition, the fin portion 43b is connected to the Figure 4 The source and drain portions are arranged in the direction indicated by the arrow Y.

[0059] The gate electrodes 41a, 42a, and 43a are connected to contacts 83. Therefore, gate voltages are applied to the gate electrodes 41a, 42a, and 43a through the contacts 83, respectively.

[0060] In addition, in the second semiconductor substrate 21, a contact penetration region 211 is formed between the element isolation portion 72-1 and the element isolation portion 72-2. Furthermore, a contact penetration region 212 is formed between the element isolation portions 72-2 and 72-3. Through-contacts 84 are formed through the contact penetration regions 211 and 212, respectively. The through-contacts 84 penetrate the interlayer insulating film 81 stacked on the second semiconductor substrate 21, the contact penetration regions 211 and 212, and the interlayer insulating film 58 stacked on the first semiconductor substrate 11, and reach the high-concentration n-type layer or high-concentration p-type layer formed in the first semiconductor substrate 11. Furthermore, the through-contacts 84 are also connected to the gate electrode TG of the transfer transistor TR. Furthermore, insulating films 85 and 86 are formed on the bonding surfaces of both the first substrate 10 and the second substrate 20 .

[0061] (Method of Manufacturing Photodetection Device 1) Figures 6A to 6HThe following are cross-sectional views illustrating the manufacturing steps of the light detecting device 1 according to the first embodiment of the present invention. The light detecting device 1 is manufactured using various devices, such as a film-forming device (including a chemical vapor deposition (CVD) device and a sputtering device), an ion implantation device, a heat treatment device, an etching device, a chemical mechanical polishing (CMP) device, and a lamination device. Hereinafter, these devices are collectively referred to as the manufacturing device.

[0062] First, the second substrate 20 made of silicon (Si) is prepared. In the manufacturing apparatus, the element separation portions 72-1, 72-2, and 72-3 ( Figure 6A After forming the element separation portions 72-1, 72-2, and 72-3, an insulating film 85 is formed ( Figure 6B As the insulating film 85, a silicon oxide film, a silicon nitride film, or a multilayer film formed of a silicon oxide film material and a silicon nitride film material can be used. Note that the silicon surface can be oxidized using a thermally grown oxide film. Since the second substrate 20 will be bonded to the first substrate 10 in the next step, the surface of the insulating film 85 can be flattened by CMP or etch-back processing at this time.

[0063] Next, the manufacturing apparatus turns the second substrate 20 upside down and attaches the second substrate 20 to the first substrate 10 ( Figure 6C ). At this time, the manufacturing apparatus first flattens the front surface of the first substrate 10. Then, the manufacturing apparatus forms an insulating film 86 on the front surface of the first substrate 10. As the insulating film 86, a silicon nitride film or the like can be used.

[0064] After attaching the first substrate 10 and the second substrate 20 to each other, the manufacturing apparatus reduces the thickness of the second substrate 20 to form a second semiconductor substrate 21 having a desired thickness, and then forms a digging portion 87 by digging from the back surface 21b of the second semiconductor substrate 21, and forms the channel portion 41b of the planar field effect transistor 41, the fin portions 42b1 and 42b2 of the fin field effect transistor 42, and the fin portion 43b of the fin field effect transistor 43 ( Figure 6D ).

[0065] Next, the manufacturing apparatus forms a dug portion 88 ( Figure 6E At this time, silicon etching is performed on the first substrate 10 at the formation positions of the contact penetration regions 211 and 212 .

[0066] Then, the manufacturing apparatus buries the insulating film in the excavated portion 87, thereby forming the front-side STI portions 72b1, 72b2, and 72b3 of the element isolation portions 72-1, 72-2, and 72-3, and buries the insulating film in the excavated portion 88, thereby forming the contact penetration regions 211 and 212 ( Figure 6F ). Therefore, if Figure 7 As shown, even if there is a certain degree of misalignment, it can be ignored and the fin portions 42b1 and 42b2 will not be damaged.

[0067] Then, if Figure 6G As shown, the manufacturing apparatus forms excavated portions 89 by excavating from the back surface 21b of the second semiconductor substrate 21 at the locations where gate electrodes 42a of FinFET 42 and 43a of FinFET 43 are to be formed. In other words, a portion of the front-side STI portions 72b1 and 72b3 of the element isolation portion 72-2 and the insulating film (oxide film) of the front-side STI portion 72b2 are etched away (removed), and the insulating film of the front-side STI portions 72b1 and 72b2 of the element isolation portion 72-3 is also partially etched away. Thereafter, the manufacturing apparatus performs a cleaning process (not shown) on the processing damage and then forms an insulating film 99 including gate oxide films 41c, 42c1, 42c2, and 43c on the back surface 21b of the second semiconductor substrate 21. Gate oxide films 41c, 42c1, 42c2, and 43c can be fabricated separately, thereby forming oxide films having various thicknesses. Typically, transistors with thick gate oxide films operate in high-voltage systems, and transistors with thin gate oxide films operate in low-voltage systems. The thickness of the gate oxide film 41c of the planar field-effect transistor 41, the thickness of the gate oxide films 42c1 and 42c2 of the fin-type field-effect transistor 42, and the thickness of the gate oxide film 43c of the fin-type field-effect transistor 43 may be equal to or different from each other. Two fin portions 42b1 and 42b2 are provided for the fin-type field-effect transistor 42, and one fin portion 43b is provided for the fin-type field-effect transistor 43. However, the number of fin portions is not limited thereto.

[0068] Then, if Figure 6HAs shown, the manufacturing apparatus buries metal, polysilicon, or the like within the excavated portion 89 to perform gate processing, forming gate electrodes 42a and 43a for the fin-type field-effect transistors 42 and 43. Simultaneously, the gate electrode 41a of the planar field-effect transistor 41 is formed on the top surface of the gate oxide film 41c. Next, after forming sidewalls (not shown), the manufacturing apparatus forms an interlayer insulating film 81 stacked on the back surface 21b of the second semiconductor substrate 21. Furthermore, the manufacturing apparatus forms a contact 83 penetrating the interlayer insulating film 81. Simultaneously, a through-contact 84 is formed by penetrating the interlayer insulating film 81, the contact penetration regions 211 and 212, and the interlayer insulating film 58 stacked on the first semiconductor substrate 11.

[0069] <Actions and Effects According to the First Embodiment> As described above, according to the first embodiment, unlike SOI substrates having a single silicon film thickness, the thickness of the silicon film can be varied depending on the device used to achieve superior characteristics. Therefore, element separation portions 72-1, 72-2, and 72-3 are formed on the bonding surface of the second substrate 20, which is a bulk substrate, to the first substrate 10. The first substrate 10 and the second substrate 20 are then bonded together, thereby forming silicon films having different thicknesses. Furthermore, by controlling the impurity distribution, the difference can be increased, thereby reducing damage below the transistor layer and the influence of interface conditions on characteristics.

[0070] Furthermore, according to the first embodiment, the fin-type field-effect transistor 42 is formed in the second substrate 20, and the gate electrode 42a of the fin-type field-effect transistor 42 can apply a gate voltage to the top and side surfaces of each of the fin portions 42b1 and 42b2 simultaneously in three directions, thereby realizing a transistor with high drive capability. Furthermore, the fin-type field-effect transistor 43 is formed in the second substrate 20, and the gate electrode 43a of the fin-type field-effect transistor 43 can apply a gate voltage to the top and side surfaces of the fin portion 43b simultaneously in three directions, thereby realizing a transistor with high drive capability.

[0071] Furthermore, according to the first embodiment, different types of transistors such as a planar field effect transistor 41 having a thick gate oxide film 41 c and high breakdown voltage, and fin field effect transistors 42 and 43 can be formed on the second substrate 20 .

[0072] <Modification of the First Embodiment> Figure 8A and Figure 8B 1A is a cross-sectional view showing steps of a method for manufacturing the light detecting device 1A according to a modification of the first embodiment of the present invention. Figure 8A and Figure 8B In, with Figure 6G and Figure 6H The same parts are denoted by the same reference numerals, and detailed descriptions thereof are omitted.

[0073] like Figure 8A As shown, the manufacturing apparatus forms excavated portions 89 by excavating from the back surface 21b of the second semiconductor substrate 21 at the locations where gate electrodes 42a of FinFET 42 and 43a of FinFET 43 are to be formed. In other words, all of the insulating film (oxide film) of the front-side STI portions 72b1, 72b2, and 72b3 of the element isolation portion 72-2 is etched away (removed), and all of the insulating film of the front-side STI portions 72b1 and 72b2 of the element isolation portion 72-3 is etched away. Thereafter, the manufacturing apparatus performs a cleaning process (not shown) on the process-damaged portions, and then forms an insulating film 99 including gate oxide films 41c, 42c1, 42c2, and 43c on the back surface 21b of the second semiconductor substrate 21.

[0074] Then, if Figure 8B As shown, the manufacturing apparatus buries metal, polysilicon, or the like in the excavated portion 89 to perform gate processing, and forms gate electrodes 42a and 43a for the fin-type field-effect transistors 42 and 43. Simultaneously, the gate electrode 41a of the planar field-effect transistor 41 is formed on the top surface of the gate oxide film 41c. The manufacturing apparatus then forms the interlayer insulating film 81 stacked on the back surface 21b of the second semiconductor substrate 21. The manufacturing apparatus then forms a contact 83 that penetrates the interlayer insulating film 81. Simultaneously, a through-contact 84 is formed that penetrates the interlayer insulating film 81, the contact penetration regions 211 and 212, and the interlayer insulating film 58 stacked on the first semiconductor substrate 11.

[0075] <Functions and Effects According to Modification Example of First Embodiment> As described above, also in the modification of the first embodiment, the same operations and effects as those in the first embodiment can be obtained.

[0076] <Second embodiment> 9A to 9D 1B is a cross-sectional view showing steps of a method for manufacturing the light detecting device 1B according to the second embodiment of the present invention. 9A to 9D In, with Figures 6A to 6H The same parts are denoted by the same reference numerals, and detailed descriptions thereof are omitted.

[0077] In the manufacturing apparatus, the element isolation portions 72-1, 72-2, and 72-3 are formed on the top surface 20a of the second substrate 20, and a spacer film 91 ( Figure 9A (1)). Figure 9A As shown in (2), the liner film 91 includes a nitride film liner 911 and an oxide film liner 912 .

[0078] After forming the element isolation portions 72-1, 72-2, and 72-3, the manufacturing apparatus forms an insulating film 85. Next, the manufacturing apparatus inverts the second substrate 20 and bonds it to the first substrate 10. At this point, the manufacturing apparatus first flattens the front surface of the first substrate 10. Then, the manufacturing apparatus forms an insulating film 86 on the front surface of the first substrate 10.

[0079] After attaching the first substrate 10 and the second substrate 20 to each other, the manufacturing apparatus reduces the thickness of the second substrate 20 to form a second semiconductor substrate 21 having a desired thickness, and then forms a digging portion 87 by digging from the back surface 21b of the second semiconductor substrate 21, and forms the channel portion 41b of the planar field effect transistor 41, the fin portions 42b1 and 42b2 of the fin field effect transistor 42, and the fin portion 43b of the fin field effect transistor 43 ( Figure 9B ).

[0080] Next, the manufacturing apparatus forms a dug portion 88 ( Figure 9C At this time, silicon etching is performed on the first substrate 10 at the formation positions of the contact penetration regions 211 and 212 .

[0081] Then, the manufacturing apparatus buries the insulating film in the excavated portion 87, thereby forming the front-side STI portions 72b1, 72b2, and 72b3 of the element isolation portions 72-1, 72-2, and 72-3, and buries the insulating film in the excavated portion 88, thereby forming the contact penetration regions 211 and 212 ( Figure 9D ).

[0082] <Functions and Effects According to the Second Embodiment> As described above, according to the second embodiment, by forming the liner film 91 in each of the element separation portions 72-1, 72-2, and 72-3, it can function as a stopper for silicon etching from the back surface 21b of the second semiconductor substrate 21 while also improving moisture resistance. Furthermore, according to the second embodiment, the liner film 91 is composed of two types of insulating films: the nitride film liner 911 and the oxide film liner 912. This can achieve the effect of a stopper film during processing after the first substrate 10 and the second substrate 20 are bonded to each other, thereby improving processing accuracy.

[0083] <Third embodiment> Figures 10A to 10C 1C are cross-sectional views showing steps of a method for manufacturing a light detecting device 1C according to a third embodiment of the present invention. Figures 10A to 10C In, with Figures 6A to 6H The same parts are denoted by the same reference numerals, and detailed descriptions thereof are omitted.

[0084] like Figure 10A As shown, in the manufacturing apparatus, the element isolation portions 72-1 and 72-2 are formed on the top surface, that is, the front surface 20a, of the second substrate 20, and the element isolation portion 92 is formed so as to be deeper than the element isolation portions 72-1 and 72-2 in the thickness direction of the second semiconductor substrate 21. Specifically, the back surface STI portion 92a of the element isolation portion 92 is thicker than the back surface STI portion 72a of the element isolation portions 72-1 and 72-2.

[0085] After forming the element isolation portions 72-1, 72-2, and 92, the manufacturing apparatus forms an insulating film 85. The manufacturing apparatus then inverts the second substrate 20 and bonds it to the first substrate 10. At this point, the manufacturing apparatus first flattens the front surface of the first substrate 10. The manufacturing apparatus then forms an insulating film 86 on the front surface of the first substrate 10.

[0086] After attaching the first substrate 10 and the second substrate 20 to each other, the manufacturing apparatus reduces the thickness of the second substrate 20 to form a second semiconductor substrate 21 having a desired thickness, and then forms a digging portion 87 by digging from the back surface 21b of the second semiconductor substrate 21, thereby forming the channel portion 41b of the planar field-effect transistor 41, the fin portions 42b1 and 42b2 of the fin-type field-effect transistor 42, and the fin portion 44b of the fin-type field-effect transistor 44. The fin portion 44b of the fin-type field-effect transistor 44 is shorter than the fin portions 42b1 and 42b2 of the fin-type field-effect transistor 42.

[0087] Then, if Figure 10B As shown, the manufacturing apparatus forms a dug portion 88 by digging from the back surface 21b of the second semiconductor substrate 21 at the locations where the contact penetration regions 211 and 212 are to be formed for allowing the through-contact 84 to penetrate into the first substrate 10. At this time, silicon etching is performed on the first substrate 10 at the locations where the contact penetration regions 211 and 212 are to be formed.

[0088] Then, if Figure 10C As shown, the manufacturing apparatus buries an insulating film in the excavated portion 87, thereby forming the front-side STI portions 72b1 and 72b2 of the element isolation portions 72-1 and 72-2, and the first front-side STI portions 92b1 and 92b2 and the second front-side STI portion 92c of the element isolation portion 92. Furthermore, the manufacturing apparatus buries an insulating film in the excavated portion 88, thereby forming the contact penetration regions 211 and 212. Furthermore, a liner film 91 may be formed corresponding to the element isolation portions 72-1, 72-2, and 92.

[0089] <Functions and Effects According to the Third Embodiment> As described above, according to the third embodiment, elements having different silicon film thicknesses can be formed on the second substrate 20 depending on the type of element to be formed. Therefore, devices meeting various requirements can be formed on the second substrate 20.

[0090] <Modification of the Third Embodiment> Figure 11 FIG. 1 is a partial longitudinal cross section showing an example of a semiconductor structure of a light detecting device 1D according to a modification of the third embodiment of the present invention. Figure 11 In, with Figure 4 The same parts are denoted by the same reference numerals, and detailed descriptions thereof are omitted.

[0091] As a specific structure, such as Figure 11 As shown in FIG. 1 , before the second substrate 20 is bonded to the first substrate 10, an element isolation portion 93 having regions with different thicknesses is formed in the region of the second semiconductor substrate 21 that will become the bottom of the fin. The element isolation portion 93 is composed of a first back surface STI portion 93a and a second back surface STI portion 93b formed on the bonding surface side (the back surface 21a side of the second semiconductor substrate 21) bonded to the first substrate 10, and a first back surface STI portion 93a and a second back surface STI portion 93b extending from the first back surface STI portion 93a toward the side opposite to the bonding surface (the back surface 21a side of the second semiconductor substrate 21). Figure 11 The first front-side STI portion 93c protruding from the second back-side STI portion 93b toward the side opposite to the bonding surface (in the direction indicated by the arrow Z in FIG. Figure 11 The first front-side STI portion 93c is formed by a second front-side STI portion 93d protruding in the direction indicated by the arrow Z. The first back-side STI portion 93a is thinner than the second back-side STI portion 93b. The first front-side STI portion 93c is thicker than the second front-side STI portion 93d.

[0092] A fin field-effect transistor 45 is formed on the first back-side STI portion 93a of the element isolation portion 93. The fin field-effect transistor 45 comprises a gate electrode 45a formed by digging into the first front-side STI portion 93c, a fin portion 45b protruding from the first back-side STI portion 93a, and a gate oxide film 45c provided between the gate electrode 45a and the fin portion 45b. The fin field-effect transistor 45 functions as a low-noise transistor having a secured effective gate width W, for example.

[0093] Fin-type field-effect transistors 46-1 and 46-2 are formed on the second back-side STI portion 93b of the element isolation portion 93. Each of fin-type field-effect transistors 46-1 and 46-2 consists of a gate electrode 46a formed by digging into the second front-side STI portion 93d, a fin portion 46b protruding from the second back-side STI portion 93b, and a gate oxide film 46c provided between the gate electrode 46a and the fin portion 46b. Fin-type field-effect transistors 46-1 and 46-2 are used as switching transistors for a more miniaturized mode, for example.

[0094] Planar field-effect transistors 47 and 48 are formed in the region of the second semiconductor substrate 21 excluding the element isolation portion 93. Planar field-effect transistor 47 includes a gate electrode 47a, a channel portion 47b, and a gate oxide film 47c disposed between gate electrode 47a and channel portion 47b. Planar field-effect transistor 48 includes a gate electrode 48a, a channel portion 48b, and a gate oxide film 48c disposed between gate electrode 48a and channel portion 48b. Channel portion 48b has an area wider than that of channel portion 47b. These planar field-effect transistors 47 and 48 are used as, for example, high-voltage-resistant transistors including thick gate oxide films 47c and 48c.

[0095] <Functions and Effects According to Modification of Third Embodiment> As described above, according to the modified example of the third embodiment, by varying the depth of the element isolation portion 93, an effective gate width W can be ensured in the first back-side STI portion 93a, thereby realizing a low-noise transistor. In the second back-side STI portion 93b, a switching transistor can be realized in a more miniaturized mode.

[0096] <Fourth embodiment> 12A to 12C 1 is a cross-sectional view showing steps of a method for manufacturing a light detecting device 1E according to a fourth embodiment of the present invention. 12A to 12C In, with Figures 6A to 6H The same parts are denoted by the same reference numerals, and detailed descriptions thereof are omitted.

[0097] In the manufacturing apparatus, the element isolation sections 72-1, 72-2, and 72-3 are formed on the top surface, or front surface 20a, of the second substrate 20, and impurities are implanted into the element isolation sections 72-2 and 72-3 for forming the fin-type field-effect transistors 42 and 49. After forming the element isolation sections 72-1, 72-2, and 72-3, the manufacturing apparatus forms an insulating film 85. Next, the manufacturing apparatus turns the second substrate 20 upside down and attaches it to the first substrate 10. At this point, the manufacturing apparatus first flattens the front surface of the first substrate 10. Then, the manufacturing apparatus forms an insulating film 86 on the front surface of the first substrate 10.

[0098] After attaching the first substrate 10 and the second substrate 20 to each other, the manufacturing apparatus reduces the thickness of the second substrate 20 to form a second semiconductor substrate 21 having a desired thickness, and then forms a digging portion 87 by digging from the back surface 21b of the second semiconductor substrate 21, and forms the channel portion 41b of the planar field effect transistor 41, the fin portions 42b1 and 42b2 of the fin field effect transistor 42, and the fin portions 49b1 and 49b2 of the fin field effect transistor 49 ( Figure 12A At this time, a doped layer 94-1 containing impurities is formed between the back STI portion 72a of the element isolation portion 72-2 and the fin portion 42b1, and a doped layer 94-2 containing impurities is formed between the back STI portion 72a of the element isolation portion 72-2 and the fin portion 42b2. Furthermore, a doped layer 95-1 containing impurities is formed between the back STI portion 72a of the element isolation portion 72-3 and the fin portion 49b1, and a doped layer 95-2 containing impurities is formed between the back STI portion 72a of the element isolation portion 72a and the fin portion 49b2.

[0099] Next, the manufacturing apparatus forms a dug portion 88 ( Figure 12B At this time, silicon etching is performed on the first substrate 10 at the formation positions of the contact penetration regions 211 and 212 .

[0100] Then, the manufacturing apparatus buries the insulating film in the excavated portion 87 to form the front-side STI portions 72b1, 72b2, and 72b3 of the element isolation portions 72-1, 72-2, and 72-3, and buries the insulating film in the excavated portion 88 to form the contact penetration regions 211 and 212 ( Figure 12C ).

[0101] <Functions and Effects According to Fourth Embodiment> As described above, according to the fourth embodiment, a doping layer 94-1 is formed between the element isolation portion 72-2 and the fin portion 42b1, and a doping layer 94-2 is formed between the element isolation portion 72-2 and the fin portion 42b2, thereby reducing the influence of the interface between the fin portions 42b1, 42b2 and the back STI portion 72a. In addition, the fourth embodiment describes an example in which impurities are implanted to form the doped layers 94-1, 94-2, 95-1, and 95-2 before the first substrate 10 and the second substrate 20 are bonded together. However, impurities may be implanted from the front surface 20a of the second substrate 20 after the first substrate 10 and the second substrate 20 are bonded together.

[0102] (Other embodiments) The present technology has been described above in the form of the first to fourth embodiments, the modified example of the first embodiment, and the modified example of the third embodiment. However, it should not be understood that the description and drawings constituting a part of the present invention limit the present technology. According to the gist of the technical contents disclosed in the first to fourth embodiments, the modified example of the first embodiment, and the modified example of the third embodiment, it is obvious to those skilled in the art that various alternative embodiments, examples, and application technologies all fall within the scope of the present technology. In addition, within the scope that no contradiction arises, the structures disclosed in the first to fourth embodiments, the modified example of the first embodiment, and the modified example of the third embodiment can be appropriately combined. For example, the structures disclosed in different embodiments can be combined, or the structures disclosed in different modified examples of the same embodiment can be combined.

[0103] <Application Examples of Electronic Equipment> The above-described light detection device can be applied to various electronic devices, for example, imaging devices such as digital cameras and digital video cameras, cellular phones having an imaging function, or any other devices having an imaging function. Figure 13 : is a block diagram showing a configuration example of an imaging device as an electronic device to which the present technology is applied.

[0104] Figure 13 The illustrated imaging device 2201 includes an optical system 2202, a shutter device 2203, a solid-state imaging element 2204 as a light detection device, a control circuit 2205, a signal processing circuit 2206, a monitor 2207, and two memories 2208, and can capture still images and moving images.

[0105] The optical system 2202 includes one or more lenses, guides light from a subject (incident light) to the solid-state imaging element 2204 , and forms an image on a light-receiving surface of the solid-state imaging element 2204 . The shutter device 2203 is arranged between the optical system 2202 and the solid-state imaging element 2204 , and controls a light irradiation period and a light shielding period of the solid-state imaging element 2205 under the control of the control circuit 2205 .

[0106] The solid-state imaging element 2204 includes a package containing the solid-state imaging element. The solid-state imaging element 2204 accumulates signal charge for a certain period of time based on light formed on a light-receiving surface via the optical system 2202 and the shutter device 2203. The signal charge accumulated in the solid-state imaging element 2204 is transferred in response to a drive signal (timing signal) supplied from the control circuit 2205.

[0107] The control circuit 2205 outputs a drive signal for controlling the transfer operation of the solid-state imaging element 2204 and the shutter operation of the shutter device 2203 to drive the solid-state imaging element 2205 and the shutter device 2203 .

[0108] The signal processing circuit 2206 performs various signal processing on the signal charge output from the solid-state imaging element 2204. An image (image data) obtained by the signal processing performed by the signal processing circuit 2206 is supplied to the monitor 2207 for display or supplied to the memory 2208 for storage (recording). In the imaging device 2201 having this configuration, the light detection device 1A, 1B, 1C, or 1D can be applied instead of the above-described solid-state imaging element 2204 .

[0109] <Application Examples of Endoscopic Surgery Systems> The technology according to the present invention (the present technology) can be applied to various products. For example, the technology according to the present invention can be applied to an endoscopic surgery system.

[0110] Figure 14 : is a diagram showing an example of a schematic configuration of an endoscopic surgery system to which the technology according to the present invention (present technology) can be applied. Figure 14 The figure shows a surgeon (doctor) 11131 performing a surgical operation on a patient 11132 on a bed 11133 using an endoscopic surgery system 11000. As shown, endoscopic surgery system 11000 includes an endoscope 11100; other surgical instruments 11110, such as a pneumoperitoneum tube 11111 and an energy treatment instrument 11112; a support arm 11120 for supporting endoscope 11100; and a trolley 11200 equipped with various instruments used for endoscopic surgery.

[0111] Endoscope 11100 includes: a lens barrel 11101 having a predetermined length from its distal end to be inserted into a body cavity of a patient 11132; and a camera head 11102 connected to the proximal end of lens barrel 11101. In the illustrated example, endoscope 11100 is configured as a rigid endoscope having a rigid lens barrel 11101. Endoscope 11100 may also be configured as a flexible endoscope having a flexible lens barrel.

[0112] The distal end of the lens barrel 11101 has an opening, into which the objective lens is embedded. A light source device 11203 is connected to the endoscope 11100. Light generated by the light source device 11203 is guided to the distal end of the lens barrel 11101 by a light guide extending within the lens barrel 11101. This light is then directed through the objective lens to an observation object in the body cavity of the patient 11132. The endoscope 11100 can be a direct-viewing endoscope, an oblique-viewing endoscope, or a side-viewing endoscope.

[0113] The camera head 11102 houses an optical system and an imaging element. Light reflected from the observation object (observation light) is focused onto the imaging element through the optical system. The imaging element performs photoelectric conversion on the observation light, generating an electrical signal corresponding to the observation light, i.e., an image signal corresponding to the observed image. This image signal is transmitted as RAW data to the camera control unit (CCU) 11201.

[0114] The CCU 11201 is composed of a central processing unit (CPU) or a graphics processing unit (GPU), and comprehensively controls the operations of the endoscope 11100 and the display device 11202. The CCU 11201 also receives image signals from the camera head 11102 and performs various image processing, such as development processing (demosaicing), on the image signals to display an image based on the image signals. The display device 11202 displays an image based on an image signal that has been image-processed by the CCU 11201 under the control of the CCU 11201 .

[0115] The light source device 11203 is composed of, for example, a light source such as a light emitting diode (LED), and supplies irradiation light to the endoscope 11100 when imaging a surgical site or the like. The input device 11204 is an input interface for the endoscopic surgery system 11000. The user can input various information or commands to the endoscopic surgery system 11000 via the input device 11204. For example, the user can input commands such as commands for changing the imaging conditions of the endoscope 11100 (e.g., the type of irradiation light, magnification, or focal length).

[0116] The treatment instrument control device 11205 controls the driving of the energy treatment instrument 11112 for cauterizing or incising tissue or sealing blood vessels. The pneumoperitoneum device 11206 injects gas into the body cavity of the patient 11132 via the pneumoperitoneum tube 11111 to inflate the cavity, thereby ensuring the field of view of the endoscope 11100 and the surgeon's working space. The recorder 11207 is a device capable of recording various information related to the surgery. The printer 11208 is a device capable of printing various information related to the surgery in various formats, such as text, images, and charts.

[0117] For example, the light source device 11203 that supplies illumination light to the endoscope 11100 for capturing images of the surgical site can be configured as a white light source composed of an LED, a laser light source, or a combination thereof. When the white light source is configured as a combination of RGB laser light sources, the output intensity and output timing of each color (wavelength) can be controlled with high precision, enabling the light source device 11203 to adjust the white balance of the captured image. In this case, by illuminating the observation object with laser light from each of the RGB laser light sources in a time-division manner and controlling the drive of the imaging element of the camera head 11102 in synchronization with this illumination timing, images corresponding to each of the RGB colors can be captured in a time-division manner. This method enables the acquisition of color images even when the imaging element does not have a color filter.

[0118] Furthermore, the light source device 11203 can be controlled so that the intensity of the light output changes at predetermined intervals. By controlling the driving of the imaging element of the camera head 11102 in synchronization with the timing of the light intensity change, images are acquired in a time-division manner, and the acquired images are synthesized, thereby generating an image with a high dynamic range that is free of any so-called black or white spots.

[0119] The light source device 11203 can be configured to supply light in a predetermined wavelength band compatible with special light observation. In special light observation, for example, narrowband light observation (narrowband imaging) is performed by illuminating light with a narrower wavelength band than that used in conventional observation (i.e., white light) by exploiting the wavelength dependence of light absorption in body tissue. This allows for high-contrast imaging of specific tissues, such as blood vessels in the mucosal surface layer, with high contrast. Alternatively, special light observation can be performed using fluorescence observation, where images are obtained by emitting excitation light to generate fluorescence. Fluorescence images can be obtained by illuminating body tissue with excitation light and observing the fluorescence from the tissue (autofluorescence observation), or by locally injecting an agent, such as indocyanine green (ICG), into the tissue and illuminating the tissue with excitation light corresponding to the agent's fluorescence wavelength. The light source device 11203 can be configured to supply narrowband light and / or excitation light compatible with this type of special light observation.

[0120] Figure 15 It shows Figure 14 A block diagram showing an example of the functional configuration of the camera head 11102 and the CCU 11201 is shown. The camera head 11102 includes a lens unit 11401, an imaging unit 11402, a driving unit 11403, a communication unit 11404, and a camera head control unit 11405. The CCU 11201 includes a communication unit 11411, an image processing unit 11412, and a control unit 11413. The camera head 11102 and the CCU 11201 are communicably connected to each other via a transmission cable 11400.

[0121] The lens section 11401 is an optical system provided at a connection portion with the lens barrel 11101. Observation light taken in from the distal end of the lens barrel 11101 is guided to the camera head 11102 and enters the lens section 11401. The lens section 11401 is constructed as a combination of a plurality of lenses including a zoom lens and a focus lens.

[0122] The imaging unit 11402 includes an imaging element. The imaging element used to constitute the imaging unit 11402 can be a single element (so-called single-board type) or multiple elements (so-called multi-board type). When the imaging unit 11402 is constructed as a multi-board type, for example, image signals corresponding to RGB are generated by each imaging element, and these image signals can be synthesized to obtain a color image. Alternatively, the imaging unit 11402 can be constructed to have a pair of imaging elements, which are used to obtain right-eye image signals and left-eye image signals for three-dimensional (3D) display. By performing 3D display, the surgeon 11131 can more accurately grasp the depth of biological tissue in the surgical site. When the imaging unit 11402 is constructed as a multi-board type, multiple systems of lens units 11401 can also be provided corresponding to the respective imaging elements.

[0123] The imaging unit 11402 does not necessarily need to be provided in the camera head 11102. For example, the imaging unit 11402 may be provided inside the lens barrel 11101 and immediately behind the objective lens. The driving section 11403 includes an actuator and causes the zoom lens and focus lens of the lens section 11401 to move a predetermined distance along the optical axis under the control of the camera head control section 11405. Thus, the magnification and focus of the image captured by the imaging section 11402 can be appropriately adjusted.

[0124] The communication section 11404 is configured as a communication device for exchanging various information with the CCU 11201. The communication section 11404 transmits the image signal acquired from the imaging section 11402 to the CCU 11201 via the transmission cable 11400 as RAW data.

[0125] The communication unit 11404 receives a control signal for controlling the driving of the camera head 11102 from the CCU 11201, and supplies the control signal to the camera head control unit 11405. For example, the control signal includes information related to imaging conditions such as information specifying the frame rate of the captured image, information specifying the exposure value during imaging, and / or information specifying the magnification and focus of the captured image.

[0126] The above-mentioned imaging conditions such as the frame rate, exposure value, magnification, and focus can be appropriately specified by the user, or can be automatically set based on the acquired image signal by the control unit 11413 of the CCU 11201. In the latter case, the endoscope 11100 has a so-called automatic exposure (AE) function, a so-called automatic focus (AF) function, and a so-called automatic white balance (AWB) function.

[0127] The camera head control section 11405 controls the driving of the camera head 11102 based on a control signal received from the CCU 11201 via the communication section 11404 . The communication unit 11411 includes a communication device for transmitting and receiving various information to and from the camera head 11102. The communication unit 11411 receives an image signal transmitted from the camera head 11102 via the transmission cable 11400.

[0128] The communication unit 11411 transmits a control signal for controlling the driving of the camera head 11102 to the camera head 11102. The image signal and the control signal can be transmitted by electrical communication, optical communication, or the like. The image processing unit 11412 performs various image processing on the image signal transmitted from the camera head 11102 as RAW data.

[0129] The control unit 11413 performs various controls related to imaging of the surgical site and the like by the endoscope 11100 and display of the captured image obtained by imaging the surgical site. For example, the control unit 11413 generates a control signal for controlling the driving of the camera head 11102.

[0130] Furthermore, based on the image signal processed by the image processing unit 11412, the control unit 11413 causes the display device 11202 to display a captured image of the surgical site, etc. In this case, the control unit 11413 can use various image recognition technologies to identify various objects in the captured image. For example, the control unit 11413 can detect the edge shape and color of objects contained in the captured image to identify surgical instruments such as forceps, specific biological sites, bleeding, and mist during the use of the energy treatment device 11112. When the control unit 11413 causes the display device 11202 to display the captured image, it can use the recognition results to superimpose various surgical support information on the image of the surgical site. When this superimposed display of surgical support information is presented to the surgeon 11131, the burden on the surgeon 11131 can be reduced, allowing the surgeon 11131 to perform the surgery reliably.

[0131] The transmission cable 11400 connecting the camera head 11102 and the CCU 11201 is an electrical signal cable supporting electrical signal communication, an optical fiber supporting optical communication, or a composite cable thereof. Although wired communication is performed using the transmission cable 11400 in the illustrated example, wireless communication may also be performed between the camera head 11102 and the CCU 11201 .

[0132] Thus, an example of an endoscopic surgery system to which the technology according to the present invention can be applied has been described. The technology according to the present invention can be applied to, for example, the endoscope 11100, the imaging unit 11402 of the camera head 11102, the image processing unit 11412 of the CCU 11201, etc. in the above-mentioned configuration. Specifically, Figure 1 The light detection device 1A can be applied to the imaging unit 10402. Here, an endoscopic surgery system has been described as an example. The technology according to the present invention can also be applied to other systems such as a microscope surgery system.

[0133] <Application examples for mobile objects> The technology according to the present invention (the present technology) can be applied to a variety of products. For example, the technology according to the present invention can be implemented as a device equipped on any type of mobile object, such as automobiles, electric vehicles, hybrid vehicles, motorcycles, bicycles, personal mobility vehicles, aircraft, drones, ships, and robots.

[0134] Figure 16 is a block diagram showing a schematic configuration example of a vehicle control system as an example of a moving body control system to which the technology according to the present invention can be applied. The vehicle control system 12000 includes a plurality of electronic control units interconnected via a communication network 12001. Figure 16 In the illustrated example, vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an exterior information detection unit 12030, an interior information detection unit 12040, and an integrated control unit 12050. Integrated control unit 12050 also includes a microcomputer 12051, an audio / video output unit 12052, and an in-vehicle network interface (I / F) 12053.

[0135] The drive system control unit 12010 controls the operation of devices related to the vehicle's drive system according to various programs. For example, the drive system control unit 12010 functions as a control device for the following devices: a drive force generating device such as an internal combustion engine or a drive motor for generating vehicle drive force; a drive force transmission mechanism for transmitting the drive force to the wheels; a steering mechanism for adjusting the vehicle's steering angle; and a braking device for generating vehicle braking force.

[0136] The body system control unit 12020 controls the operation of various devices installed on the vehicle body according to various programs. For example, the body system control unit 12020 functions as a controller for the following devices: the keyless entry system; the smart key system; the power windows; and various lights such as the headlights, backup lights, brake lights, turn signals, and fog lights. In this case, the body system control unit 12020 can receive radio waves transmitted from a portable device that replaces the key or signals from various switches. The body system control unit 12020 receives these radio waves or signals and controls the vehicle's door locks, power windows, and lights.

[0137] The vehicle exterior information detection unit 12030 detects information outside the vehicle in which the vehicle control system 12000 is installed. For example, the vehicle exterior information detection unit 12030 is connected to the imaging unit 12031. The vehicle exterior information detection unit 12030 causes the imaging unit 12031 to capture images of the vehicle exterior and receive the captured images. Based on the received images, the vehicle exterior information detection unit 12030 can perform object detection processing or distance detection processing for objects such as people, vehicles, obstacles, signs, and text on the road surface.

[0138] The imaging unit 12031 is an optical sensor that receives light and outputs an electrical signal corresponding to the amount of light received. The imaging unit 12031 can also output the electrical signal as an image or as distance measurement information. The light received by the imaging unit 12031 can be visible light or non-visible light such as infrared light.

[0139] The in-vehicle information detection unit 12040 detects information about the interior of the vehicle. For example, a driver state detection unit 12041 for detecting the driver's state is connected to the in-vehicle information detection unit 12040. The driver state detection unit 12041 includes, for example, a camera that captures the driver's image. Based on the detection information input from the driver state detection unit 12041, the in-vehicle information detection unit 12040 can calculate the driver's level of fatigue or concentration, or determine whether the driver is dozing off.

[0140] Microcomputer 12051 can calculate control target values ​​for the driving force generating device, steering mechanism, or braking device based on information outside or inside the vehicle acquired by vehicle exterior information detection unit 12030 or vehicle interior information detection unit 12040, and can output control commands to drive system control unit 12010. For example, microcomputer 12051 can perform coordinated control to implement advanced driver assistance system (ADAS) functions, including collision avoidance or impact mitigation, vehicle-to-vehicle distance-based following driving, speed maintenance, vehicle collision warning, and lane departure warning.

[0141] In addition, the microcomputer 12051 controls the driving force generating device, steering mechanism or braking device based on the information around the vehicle obtained by the external information detection unit 12030 or the internal information detection unit 12040, and is able to perform collaborative control such as automatic driving that enables autonomous driving without relying on the driver's operation.

[0142] In addition, based on the information outside the vehicle acquired by the vehicle exterior information detection unit 12030, the microcomputer 12051 can output a control command to the body system control unit 12020. For example, the microcomputer 12051 can execute cooperative control aimed at preventing glare, for example, by controlling the headlights to switch from high beam to low beam, based on the position of a preceding vehicle or an oncoming vehicle detected by the vehicle exterior information detection unit 12030.

[0143] The audio / image output unit 12052 transmits an output signal of at least one of sound and image to an output device capable of visually or auditorily notifying information to passengers or the outside of the vehicle. Figure 16 In the example of FIG, as the output device, an audio speaker 12061, a display portion 12062, and an instrument panel 12063 are shown. For example, the display portion 12062 may include at least one of an onboard display and a head-up display.

[0144] Figure 17 12031 is a diagram showing an example of the installation position of the camera unit 12031. exist Figure 17 , the vehicle 12100 includes cameras 12101 , 12102 , 12103 , 12104 , and 12105 as the camera 12031 .

[0145] For example, the cameras 12101, 12102, 12103, 12104, and 12105 are located at locations such as the front nose, side mirrors, rear bumper, trunk, and upper portion of the windshield inside the vehicle 12100. The camera 12101 located at the front nose and the camera 12105 located at the upper portion of the windshield inside the vehicle primarily capture images in front of the vehicle 12100. The cameras 12102 and 12103 located at the side mirrors primarily capture images of the two sides of the vehicle 12100. The camera 12104 located at the rear bumper or trunk primarily captures images of the rear of the vehicle 12100. The images captured by the cameras 12101 and 12105 are primarily used to detect vehicles ahead, pedestrians, obstacles, traffic lights, traffic signs, lanes, and the like.

[0146] Figure 17The figure shows an example of the imaging ranges of the imaging units 12101 to 12104. The imaging range 12111 represents the imaging range of the imaging unit 12101 located at the front nose, the imaging ranges 12112 and 12113 represent the imaging ranges of the imaging units 12102 and 12103 located at the side mirrors, respectively, and the imaging range 12114 represents the imaging range of the imaging unit 12104 located at the rear bumper or trunk door. For example, by superimposing the image data captured by the imaging units 12101 to 12104, a bird's-eye view image of the vehicle 12100 as viewed from above can be obtained.

[0147] At least one of the imaging units 12101 to 12104 may have a function of obtaining distance information. For example, at least one of the imaging units 12101 to 12104 may be a stereo camera including a plurality of imaging elements, or an imaging element having pixels for phase difference detection.

[0148] For example, based on the distance information obtained from imaging units 12101 to 12104, microcomputer 12051 can determine the distance to each three-dimensional object within imaging ranges 12111 to 12114 and the temporal change in that distance (relative speed to vehicle 12100). It can then identify as a preceding vehicle the closest three-dimensional object in the path of vehicle 12100, specifically one traveling in the same direction as vehicle 12100 at a predetermined speed (e.g., 0 km / h or higher). Furthermore, microcomputer 12051 can set a predetermined inter-vehicle distance to the preceding vehicle and execute automatic braking control (including follow-up stop control) and automatic acceleration control (including follow-up start control). This allows for cooperative control aimed at achieving, for example, autonomous driving, independent of driver input.

[0149] For example, based on the distance information obtained from the imaging units 12101 to 12104, the microcomputer 12501 can classify and extract 3D object data regarding 3D objects into two-wheeled vehicles, ordinary vehicles, large vehicles, pedestrians, and other 3D objects such as utility poles. This 3D object data can then be used to perform automatic obstacle avoidance. For example, the microcomputer 12051 identifies obstacles around the vehicle 12100 as observable by the driver of the vehicle 12100 and observable by the driver of the vehicle 12100. Furthermore, the microcomputer 12051 determines a collision risk, indicating the risk of collision with each obstacle. If the collision risk exceeds a set value and a collision is possible, a warning is output to the driver via the audio speaker 12061 or display unit 12062, or the drive system control unit 12010 initiates forced deceleration or evasive steering, thereby enabling driving assistance to avoid collisions.

[0150] At least one of the imaging units 12101 to 12104 may be an infrared camera that detects infrared light. For example, the microcomputer 12051 can identify pedestrians by determining whether a pedestrian exists in images captured by the imaging units 12101 to 12104. This pedestrian identification is performed, for example, by extracting feature points from the images captured by the imaging units 12101 to 12104, which are infrared cameras; and performing pattern matching on a series of feature points representing the outline of an object to determine whether the object is a pedestrian. When the microcomputer 12051 determines that a pedestrian exists in the images captured by the imaging units 12101 to 12104 and identifies the pedestrian, the audio / image output unit 12052 controls the display unit 12062 to display a square outline superimposed on the identified pedestrian for emphasis. Furthermore, the audio / image output unit 12052 can control the display unit 12062 to display an icon representing the pedestrian at a desired location.

[0151] So far, an example of a vehicle control system to which the technology according to the present invention can be applied has been described. The technology according to the present invention is applicable to the camera unit 12031 and the like in the above-mentioned configuration. Specifically, the technology can be applied to Figure 1 The light detection device 1 in.

[0152] The present invention may also include the following technical solutions. (1) A light detection device, comprising: a first substrate portion having pixels for photoelectrically converting incident light; and a second substrate portion bonded to a surface of the first substrate portion opposite to the light incident surface and having a plurality of elements constituting a readout circuit configured to output a pixel signal based on the charge output from the pixel; Here, an insulating film pattern is formed on a bonding surface of the second substrate portion to be bonded to the first substrate portion. (2) The light detection device according to (1), wherein: The insulating film formed on the second substrate portion is composed of a plurality of films. (3) The light detection device according to (1), wherein: The second substrate portion includes an element separation portion for separating the plurality of elements from each other. (4) The light detection device according to (3), wherein: The element separation portion is formed at a plurality of locations on the second substrate portion, and These element separation portions have different depths. (5) The light detection device according to (3), wherein: A stopper film is formed on the element isolation portion. (6) The light detection device according to (1), wherein: The element is a transistor. (7) The light detection device according to (6), wherein: The transistor includes multiple gate oxide film thicknesses. (8) The light detection device according to (1), wherein: The plurality of transistors formed in the second substrate portion have different channel depths. (9) The light detection device according to (6), wherein: The second substrate portion includes an element separation portion for separating the plurality of transistors from each other and a plurality of element formation portions protruding from the element separation portion and arranged side by side at predetermined intervals, and At least some of the transistors formed in the second substrate portion are fin-type field-effect transistors, and the gate oxide film and gate electrode of each of the fin-type field-effect transistors are arranged over the top and side surfaces of each of the element forming portions. (10) The light detection device according to (9), wherein: The second substrate portion forms a doping layer between the element isolation portion and the element formation portion. (11) The light detection device according to (9), wherein: At least some of the transistors formed in the second substrate portion are fin-type field-effect transistors, the gate oxide film and the gate electrode of each of the fin-type field-effect transistors being provided over the top surface portion and the side surface portion of each of the element forming portions, and Other transistors among the plurality of transistors formed in the second substrate portion are planar field effect transistors. (12) A method for manufacturing a light detection device, the method comprising: preparing a first substrate portion having pixels that photoelectrically convert incident light, and a second substrate portion having a plurality of elements constituting a readout circuit configured to output pixel signals based on charges output from the pixels; forming an insulating film pattern on a bonding surface of the second substrate portion to be bonded to the first substrate portion; and After the insulating film is patterned, the first substrate portion and the second substrate portion are bonded. (13) An electronic device comprising a light detection device, wherein the light detection device comprises: a first substrate portion having pixels for photoelectrically converting incident light; and a second substrate portion bonded to a surface of the first substrate portion opposite to the light incident surface and having a plurality of elements constituting a readout circuit configured to output a pixel signal based on the charge output from the pixel; Here, an insulating film pattern is formed on a bonding surface of the second substrate portion to be bonded to the first substrate portion. [Reference Signs List]

[0153] 1. 1A, 1B, 1C, 1D, 1E: Light detection device 10: First substrate 11: First semiconductor substrate 11a: Front 12: Sensor pixels 13: Pixel area 14: Fins 20: Second substrate 21: Second semiconductor substrate 21a: Front 21b: Back 22: Readout circuit 23: Pixel drive line 24: Vertical signal line 30: The third substrate 31: Third semiconductor substrate 32: Logic Circuits 33: Vertical drive circuit 34: Column signal processing circuit 35: Horizontal drive circuit 36: System control circuit 51: High concentration n-type layer (n-type diffusion layer) 52: High concentration p-type layer (p-type diffusion layer) 53: p-well 54: n-type layer 55: Pixel separation layer 56: p-type layer 57: n-type layer 58, 82: Interlayer insulation film 71: p-well 72: Component separation layer 73: High concentration p-type layer 74, 76: Drain 75, 77: Source 78: High concentration n-type layer 79: High concentration n-type layer 41: Planar field-effect transistor 41a: Gate electrode 41b: Channel 41c: Gate oxide film 42: Fin field-effect transistor 42a: Gate electrode 42b1, 42b2: Element forming portion (fin portion) 42c1, 42c2: Gate oxide film 43: Fin field-effect transistor 43a: Gate electrode 43b: Fin 43c: Gate oxide film 44: FinFET 44b: Fin 45: Fin field-effect transistor 45a: Gate electrode 45b: Fin 45c: Gate oxide film 46-1: FinFET 46-2: FinFET 46a: Gate electrode 46b: Fin 46c: Gate oxide film 47: Planar Field Effect Transistor 47a: Gate electrode 47b: Channel 47c: Gate oxide film 48: Planar Field Effect Transistor 48a: Gate electrode 48b: Channel 48c: Gate oxide film 49: Fin field-effect transistor 49b1, 49b2: fins 72, 72-1, 72-2, 72-3: Component separation unit 72a: Back STI part 72b1, 72b2, 72b3: Front STI 83: Contact 84: Through contact 85, 86: Insulating film 87, 88, 89: Excavation Department 91: Cushioning film 92, 93: Component separation 92a: Back STI part 92b1, 93c: First front STI part 92b2, 93d: First front STI part 92c: Second front STI part 93a: First backside STI portion 93b: Second backside STI portion 94-1, 94-2, 95-1, 95-2: Doped layers 211, 212: Contact penetration area 911: Nitride film liner 912: Oxide film liner 2201: Camera 2202: Optical System 2203: Shutter mechanism 2204: Solid-state imaging element 2205: Control Circuit 2206: Signal Processing Circuit 2207: Monitor 2208: Memory 10402: Camera Department 11000: Endoscopic surgical system 11100: Endoscope 11101: Lens tube 11102: Camera head 11110: Surgical instruments 11111: pneumoperitoneum tube 11112: Energy management equipment 11120: Support arm device 11131: Surgeon (Doctor) 11132: Patient 11133: Hospital bed 11200: Trolley 11201: Camera Control Unit (CCU) 11202: Display device 11203: Light source device 11204: Input device 11205: Disposal equipment control device 11206: Pneumoperitoneum device 11207: Recorder 11208: Printer 11400: Transmission Cable 11401: Lens unit 11402, 12031: Camera Department 11403: Drive unit 11404, 11411: Ministry of Communications 11405: Camera head control unit 11412: Image Processing Department 11413: Control Department 12000: Vehicle Control Systems 12001: Communication Network 12010: Drive system control unit 12020: Body system control unit 12030: External vehicle information detection unit 12040: In-vehicle information detection unit 12041: Driver status detection unit 12050: Integrated control unit 12051: Microcomputer 12052: Audio / image output unit 12061: Audio speakers 12062: Display unit 12063: Dashboard 12100: Vehicle 12101, 12102, 12103, 12104, 12105: Camera Department 12111, 12112, 12113, 12114: Camera range

Claims

1. A light detection device comprising: A first substrate portion having pixels for photoelectrically converting incident light; and a second substrate portion bonded to a surface of the first substrate portion opposite to the light incident surface and having a plurality of elements constituting a readout circuit configured to output a pixel signal based on the charge output from the pixel; Here, an insulating film pattern is formed on a bonding surface of the second substrate portion to be bonded to the first substrate portion.

2. The light detection device according to claim 1, wherein The insulating film formed on the second substrate portion is composed of a plurality of films.

3. The light detection device according to claim 1, wherein The second substrate portion includes an element separation portion for separating the plurality of elements from each other.

4. The light detection device according to claim 3, wherein The element separation portion is formed at a plurality of locations on the second substrate portion, and These element separation portions have different depths.

5. The light detection device according to claim 3, wherein A stopper film is formed on the element isolation portion. The light detection device according to claim 1 , wherein: The element is a transistor.

7. The light detection device according to claim 6, wherein The transistor includes multiple gate oxide film thicknesses.

8. The light detection device according to claim 1, wherein The plurality of transistors formed in the second substrate portion have different channel depths.

9. The light detection device according to claim 6, wherein The second substrate portion includes an element separation portion for separating the plurality of transistors from each other and a plurality of element formation portions protruding from the element separation portion and arranged side by side at predetermined intervals, and At least some of the transistors formed in the second substrate portion are fin-type field-effect transistors, and the gate oxide film and gate electrode of each of the fin-type field-effect transistors are arranged over the top and side surfaces of each of the element forming portions.

10. The light detection device according to claim 9, wherein The second substrate portion forms a doping layer between the element isolation portion and the element formation portion.

11. The light detection device according to claim 9, wherein At least some of the transistors formed in the second substrate portion are fin-type field-effect transistors, the gate oxide film and the gate electrode of each of the fin-type field-effect transistors being provided over the top surface portion and the side surface portion of each of the element forming portions, and Other transistors among the plurality of transistors formed in the second substrate portion are planar field effect transistors.

12. A method for manufacturing a light detection device, the method comprising: preparing a first substrate portion having pixels that photoelectrically convert incident light, and a second substrate portion having a plurality of elements constituting a readout circuit configured to output pixel signals based on charges output from the pixels; forming an insulating film pattern on a bonding surface of the second substrate portion bonded to the first substrate portion; as well as After the insulating film is patterned, the first substrate portion and the second substrate portion are bonded.

13. An electronic device comprising a light detection device, wherein the light detection device comprises: A first substrate portion having pixels for photoelectrically converting incident light; and a second substrate portion bonded to a surface of the first substrate portion opposite to the light incident surface and having a plurality of elements constituting a readout circuit configured to output a pixel signal based on the charge output from the pixel; Here, an insulating film pattern is formed on a bonding surface of the second substrate portion to be bonded to the first substrate portion.

Images