Connection interface conversion chip, connection interface conversion device and operating method

Abstract

A connection interface conversion chip, a connection interface conversion device, and an operating method are disclosed. The connection interface conversion chip includes a USB interface circuit, a DP interface circuit, a USB core circuit, and a switching circuit. The USB interface circuit is adapted to be coupled to a USB connector. The DP interface circuit is adapted to be coupled to a DP connector. In a first operating mode, at least one USB signal pair received by the USB connector passes through the USB interface circuit, where the DP data is decoded by the USB core circuit and then transmitted to the DP connector by the DP interface circuit. In a second operating mode, the DP data received by the USB connector passes through the USB interface circuit, the switching circuit, and the DP interface circuit before being transmitted to the DP connector.

Description

Technical Field

[0001] This invention relates to an electronic circuit, and more particularly to a connection interface conversion chip, a connection interface conversion device, and an operating method. Background Technology

[0002] The host and device use the same transmission interface to transmit data between them. When the transmission interface used by the host is different from that used by the device, a connection interface converter is required between the host and the device, or a connection interface converter chip is configured in the device. For example, suppose the host's transmission interface is Universal Serial Bus (USB), and the device's transmission interface is DisplayPort (DP). The connection interface converter (connection interface converter chip) can provide interface conversion functionality to transmit data from the host's USB Type-C connector (also known as a USB-C connector) to the DP connector of the DP device, and / or transmit data from the DP connector of the DP device to the host's USB-C connector.

[0003] The USB-C connector of the interface conversion device connects to the host's USB-C connector. The first side of the USB-C connector has a first transmitting pin (TX pin) pair and a first receiving pin (RX pin) pair, while the second side has a second transmitting pin pair and a second receiving pin pair. When the host's USB-C connector operates in USB 3.2 mode, when the USB-C plug is inserted face up, the first transmitting pin pair and the first receiving pin pair can be used as the USB 3.2 communication channel, while the second transmitting pin pair and the second receiving pin pair are idle. Conversely, when the USB-C plug is inserted face down, the first transmitting pin pair and the first receiving pin pair are idle, while the second transmitting pin pair and the second receiving pin pair can be used as the USB 3.2 communication channel.

[0004] The host can operate in Display Port Alternate Mode (DP ALT Mode) compliant with USB specifications (e.g., USB 3.2). When the host operates in ALT Mode, the idle transmit and receive pin pairs in the host's USB-C connector can be used to transmit DP compliant data, and the Side Band Use (SBU) pins in the host's USB-C connector can be used to transmit DP compliant AUX channel signals.

[0005] When the host's USB-C connector operates in USB 4.0 specification, the first transmit pin pair and the first receive pin pair on the first side of the USB-C connector, as well as the second transmit pin pair and the second receive pin pair on the second side of the USB-C connector, can be used as USB 4.0 communication channels. When the host's USB-C connector transmits signals compliant with the USB 4.0 specification, the SBU pins of the host's USB-C connector are used to transmit USB-compliant sideband signals. When the host's USB-C connector operates in USB 4.0 specification, the host can use the USB 4.0 compliant DisplayPort Tunneling protocol to encode DP data compliant with the DP specification and AUX channel signals in the USB 4.0 signal stream.

[0006] The DP connector of the interface converter is connected to the DP connector of the DP device. Regardless of whether the host's USB-C connector is operating in ALT mode or USB 4.0, the interface converter (interface converter chip) must be able to process the signals from the host's USB-C connector in order to transmit DP data from the host to the DP device.

[0007] It should be noted that the content of the "Prior Art" paragraph is used to help understand the present invention. Some (or all) of the content disclosed in the "Prior Art" paragraph may not be known to those skilled in the art. The content disclosed in the "Prior Art" paragraph does not mean that the content was known to those skilled in the art before the present invention application. Summary of the Invention

[0008] This invention provides a connection interface conversion chip, a connection interface conversion device, and an operating method, which can process signals from a Universal Serial Bus (USB) connector, regardless of whether the USB connector signal is a DisplayPort (DP) Alternate Mode (ALT Mode) signal conforming to USB specifications (e.g., USB 3.2 specifications) or a DisplayPort Tunneling (DP Tunneling) protocol conforming to USB 4.0.

[0009] In one embodiment of the present invention, the aforementioned connection interface conversion chip includes a USB interface circuit, a DP interface circuit, a USB core circuit, and a switching circuit. The USB interface circuit is adapted to be coupled to a USB connector. The DP interface circuit is adapted to be coupled to a DP connector. The USB core circuit is coupled to both the USB interface circuit and the DP interface circuit. The switching circuit is coupled to both the USB interface circuit and the DP interface circuit. In a first operating mode, at least one USB signal pair received by the USB connector passes through the USB interface circuit, where the DP data is decoded by the USB core circuit and then transmitted to the DP connector via the DP interface circuit. In a second operating mode, the DP data received by the USB connector passes through the USB interface circuit, the switching circuit, and the DP interface circuit before being transmitted to the DP connector.

[0010] In one embodiment of the present invention, the aforementioned connection interface conversion device includes a USB connector, a DP connector, and a connection interface conversion chip. The connection interface conversion chip includes a USB interface circuit, a DP interface circuit, a USB core circuit, and a switching circuit. The USB interface circuit is adapted to be coupled to the USB connector. The DP interface circuit is adapted to be coupled to the DP connector. The USB core circuit is coupled to both the USB interface circuit and the DP interface circuit. The switching circuit is coupled to both the USB interface circuit and the DP interface circuit. In a first operating mode, at least one USB signal pair received by the USB connector passes through the USB interface circuit, where the DP data is decoded by the USB core circuit and then transmitted to the DP connector via the DP interface circuit. In a second operating mode, the DP data received by the USB connector passes through the USB interface circuit, the switching circuit, and the DP interface circuit before being transmitted to the DP connector.

[0011] In one embodiment of the present invention, the above-mentioned operation method includes: in a first operation mode, at least one USB signal pair received by the USB connector is decoded into DP data by the USB core circuit through the USB interface circuit, and then transmitted to the DP connector by the DP interface circuit; and in a second operation mode, the DP data received by the USB connector is transmitted to the DP connector through the USB interface circuit, the switching circuit and the DP interface circuit.

[0012] Based on the above, the embodiments of the present invention configure the switching circuit in the connection interface conversion chip. When the signal from the USB connector is a signal conforming to the USB specification's ALT mode, the switching circuit can receive the DP data from the USB connector through the USB interface circuit, and / or the USB core circuit can receive the USB signal from the USB connector through the USB interface circuit. Then, the switching circuit can transmit the DP data to the DP connector through the DP interface circuit. When the signal from the USB connector is a USB signal conforming to the USB 4.0 DisplayPort Tunneling Protocol, the USB core circuit can receive the USB signal from the USB connector through the USB interface circuit and decode the USB signal to obtain DP data. Then, the USB core circuit can transmit the DP data to the DP connector through the DP interface circuit. That is, the switching circuit does not need to process high-bandwidth USB 4.0 signals, so the cost of the switching circuit can be reduced as much as possible. The connection interface conversion chip (connection interface conversion device) can process the signal from the USB connector, regardless of whether the signal from the USB connector is an ALT mode signal or a signal conforming to the USB 4.0 DisplayPort Tunneling Protocol.

[0013] To make the above features and advantages of the present invention more apparent and understandable, specific embodiments are described below in conjunction with the accompanying drawings. Attached Figure Description

[0014] Figure 1 This is a schematic diagram of a circuit block for an interface conversion device connected between a host and a device, as illustrated in an embodiment of the present invention.

[0015] Figure 2 To illustrate according to an embodiment of the present invention Figure 1 The circuit block diagram of the connection interface conversion chip is shown in the figure.

[0016] Figure 3 This is a flowchart illustrating an operation method of a connection interface conversion chip according to an embodiment of the present invention.

[0017] Figure 4 To illustrate according to an embodiment of the present invention Figure 2 The circuit block diagram of the USB interface circuit is shown in the figure.

[0018] Figure 5 To illustrate according to an embodiment of the present invention Figure 2 The circuit block diagram of the switching circuit and DP interface circuit is shown in the figure.

[0019] [Symbol Explanation]

[0020] 20: Host

[0021] 21, 110: Universal Serial Bus (USB) connector

[0022] 30: Display Port (DP) device

[0023] 31, 120: DP connector

[0024] 100: Connection interface conversion device

[0025] 130: Power Delivery (PD) Controller

[0026] 200: Connection interface conversion chip

[0027] 210: USB interface circuit

[0028] 211~214: Interface Circuits

[0029] 215, 218: Drivers

[0030] 216, 217: Receiver

[0031] 220: USB core circuit

[0032] 230: Switching circuit

[0033] 231-238: Equalizer

[0034] 240: DP interface circuit

[0035] 241_1~241_8: Pre-driver

[0036] 242_1~242_4: Drivers

[0037] B1~B4: Buffers

[0038] CCa, CCb: Configuration Channel (CC) pins

[0039] DP0, DP1, DP2, DP3: Channel pin pairs

[0040] RX1, RX2: Receive pin pair

[0041] S310~S340: Steps

[0042] TX1, TX2: Sending pin pairs Detailed Implementation

[0043] The term "coupled (or connected)" as used throughout this application (including the claims) may refer to any direct or indirect means of connection. For example, if the text describes a first device coupled (or connected) to a second device, it should be interpreted as the first device being directly connected to the second device, or the first device being indirectly connected to the second device through other devices or some means of connection. The terms "first," "second," etc., used throughout this application (including the claims) are used to name elements or distinguish different embodiments or scopes, and are not intended to limit the upper or lower limit of the number of elements, nor to limit the order of elements. Furthermore, wherever possible, elements / components / steps using the same reference numerals in the drawings and embodiments represent the same or similar parts. Elements / components / steps using the same reference numerals or the same terms in different embodiments can be referred to mutually in the relevant descriptions.

[0044] Figure 1 This is a circuit block diagram illustrating a connection interface conversion device 100 connected between a host 20 and a device 30, according to an embodiment of the present invention. The connection interface conversion device 100 has a DisplayPort (DP) connector 120. The DP connector 120 may include channel pin pairs DP0, DP1, DP2, and DP3 as specified in the DP standard. The DP connector 120 may be connected (or directly connected) to the DP connector 31 of the DP device 30 via a cable. The DP connector 31 may include channel pin pairs DP0, DP1, DP2, and DP3 as specified in the DP standard. The connection interface conversion device 100 may act as a source device, while the DP device 30 may act as a sink device. Depending on the application requirements, the DP device 30 may be a display or other DP device.

[0045] The interface conversion device 100 also includes a Universal Serial Bus (USB) connector 110. The USB connector 110 may be a USB Type-C connector (also known as a USB-C connector). The USB connector 110 may include the transmit pin (TX pin) pair TX1, receive pin (RX pin) pair RX1, transmit pin pair TX2, receive pin pair RX2, and configuration channel (CC) pin CCa as specified in the USB specification. The CC pin CCa may include the CC1 pin and / or CC2 pin as specified in the USB specification.

[0046] USB connector 110 can be connected (or directly connected) to USB connector 21 of host 20 via a cable. USB connector 21 can be a USB-C connector. USB connector 21 can include transmit pin pair TX1, receive pin pair RX1, transmit pin pair TX2, receive pin pair RX2, and configuration channel (CC) pin CCb as specified in the USB specification. The CC pin CCb can include CC1 pin and / or CC2 pin as specified in the USB specification. Depending on the application requirements, host 20 can be a personal computer, a laptop computer, or other electronic device with a USB-C connector.

[0047] The interface conversion device 100 also includes an interface conversion chip 200 and a power delivery (PD) controller 130. The CC pin CCa of the USB connector 110 is coupled to the PD controller 130. When the USB connector 21 of the host 20 is connected to the USB connector 110, the PD controller 130 can detect the connection configuration of the USB connector 110 via the CC pin CCa. For example, based on the detection result of the CC pin CCa, the PD controller 130 can determine whether the USB plug (not shown) of the host 20 is inserted into the USB connector 110 face up or face down.

[0048] Depending on the application scenario, host 20 may be an electronic device supporting the USB 4.0 specification, or host 20 may be an electronic device supporting the Display Port Alternate Mode (DP ALT Mode, hereinafter referred to as ALT mode) of the USB specification (e.g., USB 3.2 specification). PD controller 130 can also exchange configuration information with host 20 via CC pin CCa. Therefore, based on the configuration information of CC pin CCa, PD controller 130 can determine whether host 20 connected to USB connector 110 is an electronic device supporting the USB 4.0 specification or an electronic device running ALT mode. The related operations of PD (Power Delivery) control and CC pin are specified in the USB specification, and will not be described in detail here. PD controller 130 can provide connection configuration signals to connection interface conversion chip 200 according to the configuration information of CC pin CCa, and connection interface conversion chip 200 dynamically determines the operation in the first operating mode, the second operating mode, and / or other modes based on the connection configuration signals provided by PD controller 130. For example, the first operating mode includes DisplayPort Tunneling (DP Tunneling) protocol compliant with USB 4.0 specifications, while the second operating mode includes DisplayPort Alternate Mode (ALT mode) compliant with USB specifications.

[0049] Depending on the application scenario, the host 20 may be an electronic device supporting the USB 4.0 specification. That is, the signals transmitted by the USB connector 21 of the host 20 conform to the USB 4.0 specification. When the USB connector 21 of the host 20 operates in the USB 4.0 specification, the transmit pin pair TX1, receive pin pair RX1, transmit pin pair TX2, and receive pin pair RX2 of the USB connector 21 can all be used as USB 4.0 communication channels. Therefore, the transmit pin pair TX1 and transmit pin pair TX2 of the USB connector 21 can transmit USB 4.0 signal streams to the receive pin pair RX1 and receive pin pair RX2 of the USB connector 110 of the connection interface adapter 100. When the USB connector 21 of the host 20 transmits signals conforming to the USB 4.0 specification, the host 20 can use the DisplayPort Tunneling Protocol conforming to the USB 4.0 specification to encode DP data conforming to the DP specification and AUX channel signals in the USB 4.0 signal stream.

[0050] When the USB connector 21 of the host 20 operates in USB 4.0 mode, the interface conversion chip 200 can correspondingly operate in a first operating mode. In the first operating mode (USB 4.0 mode), the interface conversion chip 200 can decode at least one USB signal pair (differential signal) received by the receive pin pair RX1 and receive pin pair RX2 of the USB connector 110 to generate DP data conforming to the DP specification. Therefore, the interface conversion chip 200 can output the DP data to the DP device 30 through at least one of the channel pin pairs DP0, DP1, DP2, and DP3 of the DP connector 120.

[0051] Depending on the application scenario, host 20 may be an electronic device supporting DisplayPort Alternate Mode (ALT mode) of USB specifications (e.g., USB 3.2). When host 20's USB connector 21 operates in USB 3.2 mode, one set of transmission channels of USB connector 21 can be used as USB 3.2 communication channels, while another set of transmission channels is idle. For example, when the transmit pin pair TX1 and receive pin pair RX1 of USB connector 21 are used as USB 3.2 communication channels, the transmit pin pair TX2 and receive pin pair RX2 of USB connector 21 are idle. When the host operates in ALT mode, the idle transmit and receive pin pairs in host 20's USB connector 21 can be used to transmit DP data conforming to the DP specification.

[0052] When the USB connector 21 of the host 20 is operating in ALT mode, the interface conversion chip 200 can correspondingly operate in the second operating mode. In the second operating mode (ALT mode), when the USB plug (not shown) is inserted into the USB-C connector with its front side facing up, the interface conversion chip 200 can perform bidirectional USB communication with the host 20 through the transmit pin pair TX1 and receive pin pair RX1 of the USB connector 110, and the host 20 can transmit DP data conforming to the DP specification to the interface conversion chip 200 through at least one of the transmit pin pair TX2 and receive pin pair RX2 of the USB connector 110. Conversely, when the USB plug (not shown) is inserted into the USB-C connector with its back side facing up, the interface conversion chip 200 can perform bidirectional USB communication with the host 20 through the transmit pin pair TX2 and receive pin pair RX2 of the USB connector 110, and the host 20 can transmit DP data conforming to the DP specification to the interface conversion chip 200 through at least one of the transmit pin pair TX1 and receive pin pair RX1 of the USB connector 110. Therefore, the interface conversion chip 200 can output DP data to the DP device 30 through at least one of the channel pin pairs DP0, DP1, DP2 and DP3 of the DP connector 120.

[0053] Therefore, the interface conversion device 100 is applicable to interface conversion between different specifications of host 20 and DP device 30. The interface conversion device 100 (interface conversion chip 200) can process signals from USB connector 110, regardless of whether the signal transmitted from host 20 to USB connector 110 is a signal of the first operating mode (a signal conforming to the USB 4.0 DisplayPort Tunneling protocol) or a signal of the second operating mode (ALT mode).

[0054] Figure 2 To illustrate according to an embodiment of the present invention Figure 1 The circuit block diagram of the connection interface conversion chip 200 shown is illustrated in the figure. Figure 2In the illustrated embodiment, the interface conversion chip 200 includes a USB interface circuit 210, a USB core circuit 220, a switching circuit 230, and a DP interface circuit 240. The USB interface circuit 210 is adapted to be coupled to a USB connector 110. For example, the USB interface circuit 210 is adapted to be coupled to at least the transmit pin pair TX1, receive pin pair RX1, transmit pin pair TX2, and receive pin pair RX2 of the USB connector 110. The DP interface circuit 240 is adapted to be coupled to a DP connector 120. For example, the DP interface circuit 240 is adapted to be coupled to at least the channel pin pair DP0, channel pin pair DP1, channel pin pair DP2, and channel pin pair DP3 of the DP connector 120. The USB core circuit 220 is coupled to both the USB interface circuit 210 and the DP interface circuit 240. The switching circuit 230 is coupled to both the USB interface circuit 210 and the DP interface circuit 240. Figure 2 The USB connector 110, DP connector 120, PD controller 130, and connection interface conversion chip 200 shown can be referenced. Figure 1 Related explanations.

[0055] Figure 3 This is a flowchart illustrating an operation method of a connection interface conversion chip according to an embodiment of the present invention. Please refer to... Figure 1 , Figure 2 and Figure 3 In step S310, the PD controller 130 can detect the signal of the CC pin CCa of the USB connector 110 and exchange configuration information with the host 20 via the CC pin CCa. Therefore, based on the configuration information of the CC pin CCa, the PD controller 130 and / or the connection interface conversion chip 200 can determine whether the host 20 connected to the USB connector 110 is an electronic device that supports the USB 4.0 specification or an electronic device running ALT mode. According to design requirements, the USB core circuit 220 can perform the judgment operation in step S320, that is, the USB core circuit 220 can determine whether the signal of the USB connector 110 is an ALT mode signal or a DisplayPort Tunneling (DP Tunneling) protocol signal based on the connection configuration signal provided by the PD controller 130.

[0056] When the signal from USB connector 110 is determined to be an ALT mode signal (the determination result in step S320 is "ALT mode signal"), the interface conversion chip 200 can operate in the second operating mode. When the signal from USB connector 110 is a USB-compliant ALT mode signal, the switching circuit 230 can receive the DP data from USB connector 110 via USB interface circuit 210, and / or the USB core circuit 220 can receive the USB signal from USB connector 110 via USB interface circuit 210. Then, the switching circuit 230 can transmit the DP data to DP connector 120 via DP interface circuit 240. Therefore, in the second operating mode (ALT mode), the DP data received by USB connector 110 is transmitted to DP connector 120 via USB interface circuit 210, switching circuit 230, and DP interface circuit 240 (step S330).

[0057] In other words, in the second operating mode (ALT mode), the USB data output by the USB core circuit 220 is transmitted to the transmit pin pair (e.g., transmit pin pair TX1) of the USB connector 110 via the USB interface circuit 210, while the USB data received from the host 20 by the receive pin pair (e.g., receive pin pair RX1) of the USB connector 110 is transmitted to the USB core circuit 220 via the USB interface circuit 210. Therefore, the USB core circuit 220 can perform bidirectional USB communication with the host 20 through the USB interface circuit 210 and the USB connector 110. DP data received by at least one of the other transmit pin pair (e.g., transmit pin pair TX2) and the other receive pin pair (e.g., receive pin pair RX2) of the USB connector 110 is transmitted via the USB interface circuit 210, the switching circuit 230, and the DP interface circuit 240 to at least one of the channel pin pairs DP0, DP1, DP2, and DP3 of the DP connector 120.

[0058] In some application scenarios, the USB core circuit 220 may not need to perform bidirectional USB communication with the host 20 in ALT mode. That is, the USB core circuit 220 may not use the transmit pin pair TX1, receive pin pair RX1, transmit pin pair TX2, and receive pin pair RX2 of the USB connector 110. In such cases, the transmit pin pair TX1, receive pin pair RX1, transmit pin pair TX2, and receive pin pair RX2 of the USB connector 110 can all be used to transmit DP data. Therefore, in the second operating mode (ALT mode), the DP data received by the transmit pin pair TX1, receive pin pair RX1, transmit pin pair TX2, and receive pin pair RX2 of the USB connector 110 can be transmitted to the channel pin pair DP0, channel pin pair DP1, channel pin pair DP2, and channel pin pair DP3 of the DP connector 120 through the USB interface circuit 210, the switching circuit 230, and the DP interface circuit 240.

[0059] When the signal from USB connector 110 is determined to be a USB 4.0 DisplayPort Tunneling (DP Tunneling) protocol signal (the determination result in step S320 is "DP Tunneling signal"), the interface conversion chip 200 can operate in the first operating mode. When the signal from USB connector 110 is a USB signal conforming to the USB 4.0 DisplayPort Tunneling protocol, the USB core circuit 220 can receive the USB signal pair from USB connector 110 via USB interface circuit 210 and decode the USB signal pair to obtain DP data. Then, the USB core circuit 220 can transmit the DP data to DP connector 120 via DP interface circuit 240 (step S340). In other words, in the first operating mode, the USB signal pairs received by the receiving pin pair RX1 and the receiving pin pair RX2 of the USB connector 110 will pass through the USB interface circuit 210, be decoded by the USB core circuit 220 to obtain DP data, and then be transmitted by the DP interface circuit 240 to at least one of the channel pin pairs DP0, DP1, DP2 and DP3 of the DP connector 120.

[0060] Therefore, in the first operating mode (USB 4.0 mode), the USB signal pairs received by the USB connector 110 pass through the USB interface circuit 210, are decoded into DP data by the USB core circuit 220, and then transmitted to the DP connector 120 by the DP interface circuit 240. At this time (first operating mode), the switching circuit 230 can be disabled according to design requirements to save power. The switching circuit 230 does not need to process high-bandwidth USB 4.0 signals, therefore the cost of the switching circuit 230 can be minimized.

[0061] Figure 4To illustrate according to an embodiment of the present invention Figure 2 The circuit block diagram of the USB interface circuit 210 shown is illustrated in the figure. Figure 4 In the illustrated embodiment, the USB interface circuit 210 includes interface circuits 211, 212, 213, and 214, a driver 215, a receiver 216, a receiver 217, a driver 218, buffers B1, B2, B3, and B4. Depending on design requirements, interface circuit 211 may include a parallel-in-serial-out (PISO) interface circuit and / or other circuitry. USB data output from the USB core circuit 220 can be transmitted to the input of interface circuit 211. The differential input pair of driver 215 is coupled to the differential output pair of interface circuit 211 to receive differential signals (USB data). The differential output pair of driver 215 is adapted to be coupled to the transmit pin pair TX1 of USB connector 110.

[0062] The differential input pair of receiver 216 is adapted to be coupled to the receive pin pair RX1 of USB connector 110. The differential output pair of receiver 216 is coupled to the differential input pair of interface circuit 212. The output of interface circuit 212 is coupled to the input of USB core circuit 220. Depending on design requirements, interface circuit 212 may include clock and data recovery (CDR) circuitry, serial-in-parallel-out (SIPO) interface circuitry, and / or other circuitry. Interface circuit 212 can adjust the equalization (EQ) parameters of receiver 216 according to the current signal quality. Interface circuit 212 can also provide the EQ parameters to USB core circuit 220.

[0063] The differential input pair of receiver 217 is adapted to be coupled to the receive pin pair RX2 of USB connector 110. The differential output pair of receiver 217 is coupled to the differential input pair of interface circuit 213. The output of interface circuit 213 is coupled to the input of USB core circuit 220. Depending on design requirements, interface circuit 213 may include CDR circuitry, SIPO interface circuitry, and / or other circuitry. Interface circuit 213 can adjust the EQ parameters of receiver 217 according to the current signal quality. Interface circuit 213 can also provide the EQ parameters to USB core circuit 220.

[0064] Depending on design requirements, interface circuit 214 may include PISO interface circuitry and / or other circuitry. USB data output from USB core circuitry 220 can be transmitted to the input of interface circuitry 214. The differential input pair of driver 218 is coupled to the differential output pair of interface circuitry 214 to receive differential signals (USB data). The differential output pair of driver 218 is adapted to be coupled to the transmit pin pair TX2 of USB connector 110.

[0065] The differential input pair of buffer B1 is adapted to be coupled to the first transmit pin pair TX1 of USB connector 110. The differential output pair of buffer B1 is coupled to switching circuit 230. The differential input pair of buffer B2 is adapted to be coupled to the first receive pin pair RX1 of USB connector 110. The differential output pair of buffer B2 is coupled to switching circuit 230. The differential input pair of buffer B3 is adapted to be coupled to the receive pin pair RX2 of USB connector 110. The differential output pair of buffer B3 is coupled to switching circuit 230. The differential input pair of buffer B4 is adapted to be coupled to the transmit pin pair TX2 of USB connector 110. The differential output pair of buffer B4 is coupled to switching circuit 230.

[0066] In the first operating mode (USB 4.0 mode), the USB core circuit 220 can disable buffers B1, B2, B3, and B4. In the second operating mode (ALT mode), the USB core circuit 220 can enable at least one of buffers B1, B2, B3, and B4. For example, assuming the USB core circuit 220 uses the transmit pin pair TX1 and receive pin pair RX1 of the USB connector 110 for bidirectional USB communication with the host 20, the USB core circuit 220 can disable buffers B1 and B2 and enable buffers B3 and B4 in the second operating mode (ALT mode). Assuming the USB core circuit 220 uses the transmit pin pair TX2 and receive pin pair RX2 of the USB connector 110 for bidirectional USB communication with the host 20, the USB core circuit 220 can disable buffers B3 and B4 and enable buffers B1 and B2 in the second operating mode (ALT mode).

[0067] In some application scenarios, the USB core circuit 220 may not require bidirectional USB communication with the host 20 in ALT mode; that is, the USB core circuit 220 may not use the transmit pin pair TX1, receive pin pair RX1, transmit pin pair TX2, and receive pin pair RX2 of the USB connector 110. In such cases, the USB core circuit 220 can enable buffers B1, B2, B3, and B4 in the second operating mode (ALT mode). In other modes (neither USB 4.0 mode nor ALT mode), the USB core circuit 220 can disable buffers B1, B2, B3, and B4.

[0068] Figure 5 To illustrate according to an embodiment of the present invention Figure 2 The circuit block diagram of the switching circuit 230 and the DP interface circuit 240 is shown in the figure. Figure 5 In the illustrated embodiment, the switching circuit 230 includes equalizers 231, 232, 233, 234, 235, 236, 237, and 238. Based on the equalization (EQ) parameters determined by the USB interface circuit 210, the USB core circuit 220 can correspondingly control / adjust the EQ parameters of equalizers 231 to 238.

[0069] The differential input pair of equalizer 231 is coupled to the differential output pair of buffer B4. The differential input pair of equalizer 232 is coupled to the differential output pair of buffer B1. The differential input pair of equalizer 233 is coupled to the differential output pair of buffer B3. The differential input pair of equalizer 234 is coupled to the differential output pair of buffer B2. The differential input pair of equalizer 235 is coupled to the differential output pair of buffer B2. The differential input pair of equalizer 236 is coupled to the differential output pair of buffer B3. The differential input pair of equalizer 237 is coupled to the differential output pair of buffer B1. The differential input pair of equalizer 238 is coupled to the differential output pair of buffer B4.

[0070] exist Figure 5In the illustrated embodiment, the DP interface circuit 240 includes pre-drivers 241_1, 241_2, 241_3, 241_4, 241_5, 241_6, 241_7, 241_8, driver 242_1, driver 242_2, driver 242_3, and driver 242_4. The differential input pair of pre-driver 241_1 is coupled to the differential output pair of equalizer 231. The differential input pair of pre-driver 241_2 is coupled to the differential output pair of equalizer 232. The differential input pair of pre-driver 241_3 is coupled to the differential output pair of equalizer 233. The differential input pair of pre-driver 241_4 is coupled to the differential output pair of equalizer 234. The differential input pair of pre-driver 241_5 is coupled to the differential output pair of equalizer 235. The differential input pair of pre-driver 241_6 is coupled to the differential output pair of equalizer 236. The differential input pair of pre-driver 241_7 is coupled to the differential output pair of equalizer 237. The differential input pair of pre-driver 241_8 is coupled to the differential output pair of equalizer 238.

[0071] The differential input pair of driver 242_1 is coupled to the differential output pair of pre-driver 241_1 and the differential output pair of pre-driver 241_2. The differential output pair of driver 242_1 is adapted to be coupled to the channel pin pair DP0 of DP connector 120. The differential input pair of driver 242_2 is coupled to the differential output pair of pre-driver 241_3 and the differential output pair of pre-driver 241_4. The differential output pair of driver 242_2 is adapted to be coupled to the channel pin pair DP1 of DP connector 120. The differential input pair of driver 242_3 is coupled to the differential output pair of pre-driver 241_5 and the differential output pair of pre-driver 241_6. The differential output pair of driver 242_3 is adapted to be coupled to the channel pin pair DP2 of DP connector 120. The differential input pair of driver 242_4 is coupled to the differential output pair of pre-driver 241_7 and the differential output pair of pre-driver 241_8. The differential output pair of driver 242_4 is adapted to be coupled to the channel pin pair DP3 of DP connector 120.

[0072] In the first operating mode (USB 4.0 mode), the USB core circuit 220 can disable buffers B1-B4, equalizers 231-238, and pre-drivers 241_1-241_8. In the second operating mode (ALT mode), when the USB-C plug (not shown) is inserted into the USB connector 110 with its front side facing up, the USB core circuit 220 can disable equalizers 232, 241_2, 234, 241_4, 236, 241_6, 238, and 241_8. When the USB-C plug (not shown) is inserted into the USB connector 110 with its back side facing up, the USB core circuit 220 can disable equalizers 231, 241_1, 233, 241_3, 235, 241_5, 237, and 241_7.

[0073] With equalizers 232, 234, 236, and 238 disabled, the USB core circuit 220 can enable at least one of equalizers 231, 233, 235, and 237 in the second operating mode (ALT mode). For example, assuming the USB core circuit 220 uses the transmit pin pair TX1 and receive pin pair RX1 of the USB connector 110 to perform bidirectional USB communication with the host 20, the USB core circuit 220 can disable buffers B1 and B2, equalizers 235 and 237, pre-drivers 241_5 and 241_7, and enable buffers B3 and B4, equalizers 231 and 233, pre-drivers 241_1 and 241_3 in the second operating mode (ALT mode). Assuming that the USB core circuit 220 uses the transmit pin pair TX2 and the receive pin pair RX2 of the USB connector 110 to perform bidirectional USB communication with the host 20, the USB core circuit 220 can disable buffer B3, buffer B4, equalizer 231, equalizer 233, pre-driver 241_1 and pre-driver 241_3 and enable buffer B1, buffer B2, equalizer 235, equalizer 237, pre-driver 241_5 and pre-driver 241_7 in the second operating mode (ALT mode).

[0074] With equalizers 231, 233, 235, and 237 disabled, the USB core circuit 220 can enable at least one of equalizers 232, 234, 236, and 238 in the second operating mode (ALT mode). For example, assuming the USB core circuit 220 uses the transmit pin pair TX1 and receive pin pair RX1 of the USB connector 110 to perform bidirectional USB communication with the host 20, the USB core circuit 220 can disable buffers B1 and B2, equalizers 232 and 234, pre-drivers 241_2 and 241_4, and enable buffers B3 and B4, equalizers 236 and 238, pre-drivers 241_6 and 241_8 in the second operating mode (ALT mode). Assuming that the USB core circuit 220 uses the transmit pin pair TX2 and the receive pin pair RX2 of the USB connector 110 to perform bidirectional USB communication with the host 20, the USB core circuit 220 can disable buffer B3, buffer B4, pre-driver 241_1, pre-driver 241_3, equalizer 236, equalizer 238, pre-driver 241_6 and pre-driver 241_8 and enable buffer B1, buffer B2, equalizer 232, equalizer 234, pre-driver 241_2 and pre-driver 241_4 in the second operating mode (ALT mode).

[0075] In some application scenarios, the USB core circuit 220 may not need to perform bidirectional USB communication with the host 20 in ALT mode. That is, the USB core circuit 220 may not use the transmit pin pair TX1, receive pin pair RX1, transmit pin pair TX2, and receive pin pair RX2 of the USB connector 110. When the USB core circuit 220 does not use the transmit pin pair TX1, receive pin pair RX1, transmit pin pair TX2, and receive pin pair RX2, and when equalizers 232, 234, 236, and 238 are disabled, the USB core circuit 220 can enable buffers B1, B2, B3, B4, equalizers 231, 233, 235, 237, predrivers 241_1, 241_3, 241_5, and 241_7 in the second operating mode (ALT mode). When the USB core circuit 220 does not use the transmit pin pair TX1, receive pin pair RX1, transmit pin pair TX2 and receive pin pair RX2, and when equalizers 231, 233, 235 and 237 are disabled, the USB core circuit 220 can enable buffers B1, B2, B3, B4, equalizers 232, 234, 236 and 238, pre-drivers 241_2, 241_4, 241_6 and 241_8 in the second operating mode (ALT mode).

[0076] In other modes (neither USB 4.0 mode nor ALT mode), the USB core circuit 220 may disable buffers B1, B2, B3, B4, equalizers 231 to 238, and pre-drivers 241_1 to 241_8.

[0077] Depending on different design requirements, the implementation of the above-mentioned USB interface circuit 210, USB core circuit 220, switching circuit 230 and / or DP interface circuit 240 blocks can be hardware, firmware, software, or a combination of the above three.

[0078] In hardware terms, the aforementioned blocks of the USB interface circuit 210, USB core circuit 220, switching circuit 230, and / or DP interface circuit 240 can be implemented as logic circuits on an integrated circuit. The functions of the aforementioned USB interface circuit 210, USB core circuit 220, switching circuit 230, and / or DP interface circuit 240 can be implemented as hardware using hardware description languages ​​(such as Verilog HDL or VHDL) or other suitable programming languages. For example, the functions of the aforementioned USB interface circuit 210, USB core circuit 220, switching circuit 230, and / or DP interface circuit 240 can be implemented as various logic blocks, modules, and circuits in one or more controllers, microcontrollers, microprocessors, application-specific integrated circuits (ASICs), digital signal processors (DSPs), field-programmable gate arrays (FPGAs), and / or other processing units.

[0079] In software and / or firmware form, the functions of the USB interface circuit 210, USB core circuit 220, switching circuit 230, and / or DP interface circuit 240 can be implemented as programming codes. For example, the USB interface circuit 210, USB core circuit 220, switching circuit 230, and / or DP interface circuit 240 can be implemented using general programming languages ​​(such as C, C++, or assembly language) or other suitable programming languages. The programming codes can be recorded / stored in a recording medium, which may include, for example, read-only memory (ROM), storage devices, and / or random access memory (RAM). A computer, central processing unit (CPU), controller, microcontroller, or microprocessor can read and execute the programming codes from the recording medium to achieve the relevant functions. As the recording medium, a "non-transitory computer-readable medium" can be used, such as tape, disk, card, semiconductor memory, programmable logic circuits, etc. Furthermore, the program can also be provided to the computer (or CPU) via any transmission medium (communication network or broadcast radio waves, etc.). The communication network is, for example, the Internet, wired communication, wireless communication, or other communication media.

[0080] In summary, the above embodiments configure the switching circuit 230 within the interface conversion chip 200. When the signal from the USB connector 110 is a USB-compliant ALT mode signal, the switching circuit 230 can receive the DP data from the USB connector 110 via the USB interface circuit 210, and / or the USB core circuit 220 can receive the USB signal from the USB connector 110 via the USB interface circuit 110. Then, the switching circuit 230 can transmit the DP data to the DP connector 120 via the DP interface circuit 240. When the signal from the USB connector 110 is a USB signal compliant with the USB 4.0 Display Port Tunneling (DP Tunneling) protocol, the USB core circuit 220 can receive at least one USB signal pair from the USB connector 110 via the USB interface circuit 210 and decode the USB signal pair to obtain DP data. Then, the USB core circuit 220 can transmit the DP data to the DP connector 120 via the DP interface circuit 240. That is, the switching circuit 230 does not need to process high-bandwidth USB 4.0 signals, so the cost of the switching circuit 230 can be reduced as much as possible. The interface conversion chip 200 (interface conversion device 100) can process the signals of the USB connector 110, regardless of whether the signals of the USB connector 110 are ALT mode signals or signals conforming to the USB 4.0 DisplayPort Tunneling Protocol.

[0081] Although the present invention has been disclosed above with reference to embodiments, it is not intended to limit the present invention. Those skilled in the art can make some modifications and refinements without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the scope defined in the appended claims.

Claims

1. A connection interface conversion chip, comprising: A Universal Serial Bus (USB) interface circuit, suitable for coupling to a Universal Serial Bus connector; Display port interface circuitry, suitable for coupling to a display port connector; A Universal Serial Bus (USB) core circuit is coupled to the USB interface circuit and the display port interface circuit. as well as The switching circuit is coupled to the universal serial bus interface circuit and the display port interface circuit. In the first operating mode, at least one Universal Serial Bus (USB) signal pair received by the USB connector will pass through the USB interface, be decoded by the USB core circuit to obtain display port data, and then be transmitted to the display port connector by the display port interface circuit. as well as In the second operating mode, the display port data received by the Universal Serial Bus connector is transmitted to the display port connector through the Universal Serial Bus interface circuit, the switching circuit, and the display port interface circuit. When operating in the second operating mode, the second operating mode only allows the switching circuit to transmit the display port data between the universal serial bus interface circuit and the display port interface circuit; The first operating mode includes a DisplayPort Tunneling Protocol compliant with the USB 4.0 specification, while the second operating mode includes a DisplayPort Alternate Mode compliant with the USB specification. The connection interface conversion chip dynamically determines the operation in the first operation mode and the second operation mode based on the connection configuration signal provided by the power transmission controller via the configuration channel pin.

2. The connection interface conversion chip as claimed in claim 1, wherein the universal serial bus connector includes a USB-C connector.

3. The connection interface conversion chip as claimed in claim 1, wherein the Universal Serial Bus interface circuit is adapted to be coupled to at least a first transmit pin pair, a first receive pin pair, a second transmit pin pair and a second receive pin pair of the Universal Serial Bus connector, and the display port interface circuit is adapted to be coupled to at least a first channel pin pair, a second channel pin pair, a third channel pin pair and a fourth channel pin pair of the display port connector.

4. The connection interface conversion chip as described in claim 3, wherein in the first operating mode, the universal serial bus signal pairs received by the first receiving pin pair and the second receiving pin pair of the universal serial bus connector will pass through the universal serial bus interface circuit, and the display port data will be decoded by the universal serial bus core circuit, and then transmitted by the display port interface circuit to at least one of the first channel pin pair, the second channel pin pair, the third channel pin pair and the fourth channel pin pair of the display port connector.

5. The connection interface conversion chip as described in claim 3, wherein in the second operating mode, the display port data received by the first transmit pin pair, the first receive pin pair, the second transmit pin pair, and the second receive pin pair of the Universal Serial Bus connector will be transmitted to the first channel pin pair, the second channel pin pair, the third channel pin pair, and the fourth channel pin pair of the display port connector through the Universal Serial Bus interface circuit, the switching circuit, and the display port interface circuit.

6. The connection interface conversion chip as claimed in claim 3, wherein in the second operating mode, the first SATA data output by the SATA core circuit is transmitted to the first transmit pin pair of the SATA connector via the SATA interface circuit, the second SATA data received by the first receive pin pair of the SATA connector is transmitted to the SATA core circuit via the SATA interface circuit, and the display port data received by at least one of the second transmit pin pair and the second receive pin pair of the SATA connector is transmitted to at least one of the first channel pin pair, the second channel pin pair, the third channel pin pair, and the fourth channel pin pair of the display port connector via the SATA interface circuit, the switching circuit, and the display port interface circuit.

7. The connection interface conversion chip as described in claim 3, wherein the universal serial bus interface circuit comprises: A first driver having a differential output pair adapted to be coupled to the first transmit pin pair of the universal serial bus connector; A first receiver has a differential input pair adapted to be coupled to the first receiver pin pair of the universal serial bus connector; The second driver has a differential output pair adapted to be coupled to the second transmit pin pair of the universal serial bus connector; The second receiver has a differential input pair adapted to be coupled to the second receiver pin pair of the universal serial bus connector; A first buffer having a differential input pair adapted to be coupled to the first transmit pin pair of the universal serial bus connector; The second buffer has a differential input pair adapted to be coupled to the first receive pin pair of the universal serial bus connector; The third buffer has a differential input pair adapted to be coupled to the second receive pin pair of the universal serial bus connector; as well as The fourth buffer has a differential input pair adapted to be coupled to the second transmit pin pair of the universal serial bus connector.

8. The connection interface conversion chip as claimed in claim 7, wherein the first buffer, the second buffer, the third buffer and the fourth buffer are disabled in the first operating mode.

9. The connection interface conversion chip of claim 7, wherein at least one of the first buffer, the second buffer, the third buffer, and the fourth buffer is enabled in the second operating mode.

10. The connection interface conversion chip as claimed in claim 7, wherein the switching circuit comprises: The first equalizer has a differential input pair coupled to the differential output pair of the fourth buffer; The second equalizer has a differential input pair coupled to the differential output pair of the first buffer; The third equalizer has a differential input pair coupled to the differential output pair of the third buffer; The fourth equalizer has a differential input pair coupled to the differential output pair of the second buffer; The fifth equalizer has a differential input pair coupled to the differential output pair of the second buffer; The sixth equalizer has a differential input pair coupled to the differential output pair of the third buffer; The seventh equalizer has a differential input pair coupled to the differential output pair of the first buffer; as well as The eighth equalizer has a differential input pair coupled to the differential output pair of the fourth buffer.

11. The connection interface conversion chip as claimed in claim 10, wherein the first equalizer, the second equalizer, the third equalizer, the fourth equalizer, the fifth equalizer, the sixth equalizer, the seventh equalizer, and the eighth equalizer are disabled in the first operating mode.

12. The connection interface conversion chip as claimed in claim 10, wherein in the second operating mode, the first equalizer, the third equalizer, the fifth equalizer and the seventh equalizer are disabled, or the second equalizer, the fourth equalizer, the sixth equalizer and the eighth equalizer are disabled.

13. The connection interface conversion chip as described in claim 10, wherein... In this second operating mode, and when the first, third, fifth, and seventh equalizers are disabled, the second, fourth, sixth, and eighth equalizers are enabled; and In the second operating mode, and when the second, fourth, sixth, and eighth equalizers are disabled, the first, third, fifth, and seventh equalizers are enabled.

14. The connection interface conversion chip as described in claim 10, wherein... In this second operating mode, and when the first, third, fifth, and seventh equalizers are disabled, the second and fourth equalizers are disabled, and the sixth and eighth equalizers are enabled; and In the second operating mode, and when the second, fourth, sixth, and eighth equalizers are disabled, the first and third equalizers are enabled, and the fifth and seventh equalizers are disabled.

15. The connection interface conversion chip as described in claim 10, wherein the display port interface circuit comprises: A first pre-driver has a differential input pair coupled to a differential output pair of the first equalizer; The second pre-driver has a differential input pair coupled to the differential output pair of the second equalizer; The third pre-driver has a differential input pair coupled to the differential output pair of the third equalizer; The fourth pre-driver has a differential input pair coupled to the differential output pair of the fourth equalizer; The fifth pre-driver has a differential input pair coupled to the differential output pair of the fifth equalizer; The sixth pre-driver has a differential input pair coupled to the differential output pair of the sixth equalizer; The seventh pre-driver has a differential input pair coupled to the differential output pair of the seventh equalizer; The eighth pre-driver has a differential input pair coupled to the differential output pair of the eighth equalizer; A third driver has a differential input pair coupled to a differential output pair of the first pre-driver and a differential output pair of the second pre-driver, wherein the differential output pair of the third driver is adapted to be coupled to the first channel pin pair of the display port connector; A fourth driver has a differential input pair coupled to a differential output pair of the third pre-driver and a differential output pair of the fourth pre-driver, wherein the differential output pair of the fourth driver is adapted to be coupled to the second channel pin pair of the display port connector. The fifth driver has a differential input pair coupled to a differential output pair of the fifth pre-driver and a differential output pair of the sixth pre-driver, wherein the differential output pair of the fifth driver is adapted to be coupled to the third channel pin pair of the display port connector; as well as The sixth driver has a differential input pair coupled to a differential output pair of the seventh pre-driver and a differential output pair of the eighth pre-driver, wherein the differential output pair of the sixth driver is adapted to be coupled to the fourth channel pin pair of the display port connector.

16. A connection interface conversion device, comprising: Universal Serial Bus connector; Display port connector; as well as The connection interface conversion chip includes: A Universal Serial Bus (USB) interface circuit, suitable for coupling to the USB connector; Display port interface circuitry, adapted to be coupled to the display port connector; The Universal Serial Bus (USB) core circuitry is coupled to the USB interface circuitry and the display port interface circuitry; and The switching circuit is coupled to the universal serial bus interface circuit and the display port interface circuit. In the first operating mode, at least one Universal Serial Bus (USB) signal pair received by the USB connector passes through the USB interface circuit, where the USB core circuit decodes the display port data, and then the display port interface circuit transmits it to the display port connector; and In the second operating mode, the display port data received by the Universal Serial Bus connector is transmitted to the display port connector via the Universal Serial Bus interface circuit, the switching circuit, and the display port interface circuit. When operating in the second operating mode, the second operating mode only allows the switching circuit to transmit the display port data between the universal serial bus interface circuit and the display port interface circuit; The first operating mode includes a DisplayPort Tunneling Protocol compliant with the USB 4.0 specification, while the second operating mode includes a DisplayPort Alternate Mode compliant with the USB specification. The connection interface conversion chip dynamically determines the operation in the first operation mode and the second operation mode based on the connection configuration signal provided by the power transmission controller via the configuration channel pin.

17. A method of operating a connection interface conversion chip, the connection interface conversion chip comprising a Universal Serial Bus (USB) interface circuit, a display port interface circuit, a USB core circuit, and a switching circuit, wherein the USB interface circuit is adapted to be coupled to a USB connector, the display port interface circuit is adapted to be coupled to a display port connector, and the method of operating the chip comprises: In the first operating mode, at least one Universal Serial Bus (USB) signal pair received by the USB connector is decoded by the USB core circuit to obtain display port data through the USB interface circuit, and then transmitted to the display port connector by the display port interface circuit. as well as In the second operating mode, the display port data received by the Universal Serial Bus connector is transmitted to the display port connector via the Universal Serial Bus interface circuit, the switching circuit, and the display port interface circuit. When operating in the second operating mode, the second operating mode only allows the switching circuit to transmit the display port data between the universal serial bus interface circuit and the display port interface circuit; The first operating mode includes a DisplayPort Tunneling Protocol compliant with the USB 4.0 specification, while the second operating mode includes a DisplayPort Alternate Mode compliant with the USB specification. The connection interface conversion chip dynamically determines the operation in the first operation mode and the second operation mode based on the connection configuration signal provided by the power transmission controller via the configuration channel pin.

18. The method of operating the interface conversion chip as claimed in claim 17, wherein the universal serial bus connector includes a USB-C connector.

19. The method of operating the interface conversion chip as claimed in claim 17, wherein the Universal Serial Bus interface circuit is adapted to be at least coupled to a first transmit pin pair, a first receive pin pair, a second transmit pin pair and a second receive pin pair of the Universal Serial Bus connector, and the display port interface circuit is adapted to be at least coupled to a first channel pin pair, a second channel pin pair, a third channel pin pair and a fourth channel pin pair of the display port connector.

20. The method of operating the interface conversion chip as described in claim 19, further comprising: In this first operating mode, the universal serial bus signal pairs received by the first and second receiving pin pairs of the universal serial bus connector are passed through the universal serial bus interface circuit, and the display port data is decoded by the universal serial bus core circuit. Then, the display port interface circuit transmits the data to at least one of the first, second, third, and fourth channel pin pairs of the display port connector.

21. The method of operating the interface conversion chip as described in claim 19, further comprising: In this second operating mode, the display port data received by the first transmit pin pair, the first receive pin pair, the second transmit pin pair, and the second receive pin pair of the Universal Serial Bus connector are transmitted through the Universal Serial Bus interface circuit, the switching circuit, and the display port interface circuit to the first channel pin pair, the second channel pin pair, the third channel pin pair, and the fourth channel pin pair of the display port connector.

22. The method of operating the interface conversion chip as described in claim 19, further comprising: In this second operating mode, the first universal serial bus data output by the universal serial bus core circuit is transmitted to the first transmit pin pair of the universal serial bus connector through the universal serial bus interface circuit. In this second operating mode, the second universal serial bus data received by the first receiving pin of the universal serial bus connector is transmitted to the universal serial bus core circuit through the universal serial bus interface circuit. as well as In this second operating mode, the display port data received by at least one of the second transmit pin pair and the second receive pin pair of the Universal Serial Bus connector is transmitted through the Universal Serial Bus interface circuit, the switching circuit and the display port interface circuit to at least one of the first channel pin pair, the second channel pin pair, the third channel pin pair and the fourth channel pin pair of the display port connector.

Images