Low warpage fan-out processing method and production of substrates therefor

Abstract

A low warpage fan-out processing method and production of substrates thereof are provided. The method of fan-out processing includes: providing or obtaining a fused glass laminate or wafer having a core layer and first and second cladding layers, the core layer including a core glass having a core glass coefficient of thermal expansion α 芯体 , the first and second cladding layers each including a cladding glass having a cladding glass coefficient of thermal expansion α 包层 , wherein α 包层 < α 芯体 ; securing an integrated circuit device to the first cladding layer of the laminate or wafer; forming a fan-out layer on or over the integrated circuit device; and removing some of the second cladding layer to reduce warpage of the laminate or wafer having the integrated circuit device and the fan-out layer thereon. Also disclosed is a method of producing a laminate or wafer having a selected CTE.

Description

[0001] Cross Reference to Related Applications

[0002] This application claims priority under 35 U.S.C. § 119 to U.S. Provisional Application No. 62 / 868,997, filed June 30, 2019; U.S. Provisional Application No. 62 / 881,359, filed July 31, 2019; and U.S. Provisional Application No. 62 / 893,865, filed August 30, 2019, the contents of each of which are incorporated herein by reference in their entirety. TECHNICAL FIELD

[0003] The present disclosure relates to methods for low warpage fan-out processing, in particular, to methods for fan-out processing using a fusion lamination glass substrate having a core layer between a first clad layer and a second clad layer, the method including forming a fan-out layer supported on the first clad layer and removing at least some (thinning) of the second clad layer, and to methods for making a lamination glass substrate useful for the processing, the lamination glass substrate having a desired coefficient of thermal expansion. BACKGROUND

[0004] In recent years, fan-out wafer level packaging (FO-WLP) and fan-out panel level packaging (FO-PLP) have gained wide attention in the IC packaging technology field for their high heterogeneous integration capability, small form factor, and reduced system total cost. With the mass adoption of TSMC’s “InFO” (integrated fan-out) FO-WLP solution, fan-out packaging has transitioned from core fan-out applications (e.g., baseband, power management, and RF transceiver) to more advanced high-density fan-out applications, e.g., APE.

[0005] Today, the biggest challenges for fan-out packaging include (1) warpage in processing and (2) die shift.

[0006] To keep warpage in processing within specification, a carrier with an optimized coefficient of thermal expansion (CTE) is desired. The precise CTE that is desired depends on many factors, including chip design, layout of reconstituted wafer / panel, and RDL / bump processes. Manufacturers are seeking glass substrates that achieve CTEs at 0.1 ppm / °C increment intervals over a large range.

[0007] The Corning laminated fusion draw glass process potentially offers the ability to produce a continuous CTE spectrum of glass by varying the core to cladding thickness ratio of the fused laminated sheet and / or by varying the composition of the core and / or cladding of the sheet. However, the cost of varying the composition and / or thickness ratio in small increments is high and some ratios and compositions are outside the capability of the laminated fusion draw glass process or machine. A practical and cost effective way to manufacture fine pitch glass carriers with selectable CTE is desired.

[0008] Furthermore, even if starting with a carrier substrate that is a perfect match to the CTE of the packaged circuit, there can be significant warpage during the fan-out process (defined as the process of manufacturing a fan-out package) because the effective CTE of the layers bonded to the carrier (all on one side of the carrier) and the stresses developed in these layers after deposition are constantly changing with each successive process, such as bonding, EMC curing, lapping, multiple alternating polymer and copper deposition, bump plating and ball attach. The desired CTE of the carrier is usually selected so that the warpage developed at any point during the entire process can fall within an acceptable range; however, the warpage is not minimized at each step or steps, respectively.

[0009] To reduce warpage throughout the process, a stiffer or thicker carrier must be used. However, these solutions can not be feasible due to the technology used or manufacturing limitations. For example, glass-ceramics can seem like a good alternative to glass due to their high Young's modulus, but they usually have a relatively low CTE and transparency can also be an issue as laser debonding has become a commonly used adhesive method in die fan-out packaging. Currently, laser debonding typically requires >70% transparency in the visible light. Also, newer technologies can require some transparency even in the deep UV range. Similarly, a thicker glass carrier can certainly reduce warpage. However, a thicker glass means more weight, thus requiring a more powerful vacuum chuck and, more importantly, higher stresses are developed in the semiconductor layers. Therefore, there is a maximum thickness that manufacturers are willing or able to accept. An alternative approach to warpage minimization throughout all or several steps is needed. SUMMARY

[0010] According to some aspects of the disclosure, a method is provided that includes providing or obtaining a fused glass laminate sheet having a core layer and first and second cladding layers, the core layer having a core thickness t 芯体 and including a core glass coefficient of thermal expansion a 芯体 , a core glass Poisson's ratio v 芯体a core glass having a core glass elasticity Ecore, the first cladding layer (34) and the second cladding layer (36) each having a thickness tcladding and comprising a cladding glass having a cladding glass coefficient of thermal expansion a 包层 , a cladding glass Poisson's ratio v 包层 , and a cladding glass elasticity E 包层 . The method further includes the step of selecting or specifying a desired effective coefficient of thermal expansion a 有效 that is greater than

[0011]

[0012] and less than a 芯体 .

[0013] The method further includes thinning the first cladding layer and the second cladding layer to produce a thinned first cladding layer and a thinned second cladding layer, each having a thinned thickness t 薄化 , the t 薄化 is in the following range:

[0014] from

[0015] to

[0016]

[0017] where P is 0.1, 0.05, 0.02, 0.01, or even 0.005. The method can relatively economically produce a carrier substrate having any desired CTE in the following range:

[0018] from

[0019] to a 芯体 .

[0020] In further embodiments of the method, the core layer consists essentially of the core glass. In further embodiments, the first cladding layer and the second cladding layer each consist essentially of the cladding glass.

[0021] In further embodiments, the step of providing or obtaining a fused glass laminate includes producing the fused glass laminate using a fusion draw machine.

[0022] In other embodiments, the step of thinning the first cladding layer and the second cladding layer includes etching the first cladding layer and the second cladding layer.

[0023] In yet other embodiments, the step of thinning the first cladding layer and the second cladding layer includes polishing the first cladding layer and the second cladding layer.

[0024] According to further embodiments, the method further comprises the step of: cutting the fused glass laminate sheet to form one or more wafers.

[0025] According to further embodiments, the method comprises the step of: cutting the fused glass laminate sheet to form one or more panels.

[0026] According to further embodiments, the cutting comprises laser cutting.

[0027] According to further embodiments, the cutting comprises laser cutting using a Bessel beam.

[0028] According to further aspects of the disclosure, a method of fan-out processing comprises: providing or obtaining a fused glass laminate sheet or wafer (12) having a core layer (32) comprising a core glass having a core glass coefficient of thermal expansion a 芯体 , and first and second cladding layers (34, 36) each comprising a cladding glass having a cladding glass coefficient of thermal expansion a 包层 , wherein a 包层 < a 芯体 ; securing an integrated circuit device (42) to the first cladding layer (34) of the laminate sheet or wafer; forming a fan-out layer (46) on or over the integrated circuit device (42); and removing some of the second cladding layer (36) to reduce warpage of the sheet or wafer having the integrated circuit device and fan-out layer thereon.

[0029] According to embodiments of the method, the core layer consists essentially of the core glass. Similarly, according to embodiments, the second cladding layers each consist essentially of the cladding glass.

[0030] According to embodiments, the step of providing or obtaining a fused glass laminate sheet or wafer comprises: producing the fused glass laminate using a fusion draw machine.

[0031] According to embodiments, the step of thinning the first cladding layer comprises: etching the first cladding layer.

[0032] According to embodiments, the step of thinning the first cladding layer comprises: polishing or grinding the first cladding layer.

[0033] According to embodiments, the method further comprises: selecting an effective CTE of the laminate sheet or wafer to be within 20%, or within 10%, of an ideal CTE for die bonding and filling processes only.

[0034] According to embodiments, the method further comprises: forming additional fan-out layers on or over the first fan-out layer, and removing more of the first cladding layer.

[0035] According to embodiments, the step of selecting an effective CTE of the laminate or wafer further comprises: providing or obtaining a fused glass laminate having a core layer (32) and first and second cladding layers (34, 36), the core layer (32) having a core thickness t 芯体 and including a core glass having a core glass coefficient of thermal expansion a 芯体 , a core glass Poisson's ratio v 芯体 , and a core glass elasticity E 芯体 , the first and second cladding layers (34, 36) each having a thickness t 包层 and including a cladding glass having a cladding glass coefficient of thermal expansion a 包层 , a cladding glass Poisson's ratio v 包层 , and a cladding glass elasticity E 包层 , selecting a desired effective coefficient of thermal expansion a 有效 that is greater than

[0036]

[0037] and less than a 芯体 , and thinning the first and second cladding layers (34, 36) to produce a thinned first cladding layer and a thinned second cladding layer each having a thickness t 薄化 , the t 薄化 is in the following range:

[0038] from

[0039] to where P is 0.1, 0.05, 0.02, 0.01, or even 0.005.

[0040] Additional features and advantages are set forth in the detailed description which follows, and in part will become apparent to those skilled in the art on examination of the following or can be learned by practice of various embodiments of the present disclosure as described herein.

[0041] It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are intended to provide a further explanation of the nature and advantages of the present disclosure as claimed.

[0042] The accompanying drawings, which are included to provide a further understanding of the principles of the disclosure and are incorporated in and constitute a part of this specification, illustrate embodiments of the disclosure and together with the description serve to explain the principles of the disclosure. The drawings illustrate one or more embodiment(s) and, together with the description, serve to explain the principles and operations of the disclosure. It will be appreciated that the various features of the disclosure disclosed in this specification and in the accompanying drawings can be used in any combination and all combinations. As non-limiting examples, various features of the disclosure can be combined with each other according to the following embodiments. BRIEF DESCRIPTION OF DRAWINGS

[0043] The following is a description of the figures in the accompanying drawings. The drawings are not necessarily to scale, with certain features and certain views of the drawings being shown exaggerated in scale or in schematic for purposes of illustration and description.

[0044] In the drawings:

[0045] Figure 1 is a perspective view of a fused glass laminate sheet for use in the methods of the disclosure;

[0046] Figure 2 is a cross-sectional view of a sheet or portion of a sheet of Figure 1

[0047] Figure 3 is a cross-sectional view of a sheet or portion of a sheet of Figure 2

[0048] Figure 4 is a flow chart of an embodiment of a method according to some methods of the disclosure;

[0049] Figure 5 is a cross-sectional view illustrating an embodiment of a step of a method of Figure 4

[0050] Figure 6 is a flow chart of an embodiment of additional method steps optionally used in conjunction with a method of Figure 4 DETAILED DESCRIPTION

[0051] Other features and advantages will be readily appreciated as the same becomes better understood by the following detailed description, taken in connection with the accompanying drawings, in which:

[0052] ​​​​As used herein, the term "and / or," when used in a list of two or more items, means that any one of the listed items can be employed by itself, or any combination of two or more of the listed items can be employed. For example, if a composition is described as containing components A, B, and / or C, the composition can contain A alone; B alone; C alone; A and B in combination; A and C in combination; B and C in combination; or A, B, and C in combination.

[0053] In this document, relative terms such as first and second, top and bottom, and the like can be used for illustrative purposes and are in no way meant to denote or imply a necessary relationship or order between or among entities or actions.

[0054] Modifications of the disclosure will occur to those skilled in the art and to those who make or use the disclosure. Therefore, it is understood that the embodiments shown and described herein are merely for illustrative purposes and are not intended to limit the scope of the disclosure, which is defined by the following claims as interpreted according to the principles of patent law, including the doctrine of equivalents. The embodiments shown and described herein are merely for illustrative purposes and are not intended to limit the scope of the disclosure, which is defined by the following claims as interpreted according to the principles of patent law, including the doctrine of equivalents.

[0055] For purposes of the present disclosure, the term "connected" (or "coupled") generally means the coupling of two members directly or indirectly to one another. Such coupling can be stationary or moveable in nature. Such coupling can be achieved with the two members moving relative to one another, with the two members moving relative to a third member, with the two members moving relative to one another and relative to a third member, or with the two members moving relative to one another and relative to a third member. Such coupling can be permanent in nature or releasable in nature or releasable in nature unless otherwise stated. Such coupling can be direct or through any other intermediate structures.

[0056] As used herein, the term "about" means quantities, dimensions, formulas, parameters, and other quantities and characteristics are not exact and are not required to be exact, but can be approximated and / or larger or smaller, as reflection tolerances, conversion factors, rounding, measurement errors, and other factors known to those of skill in the art, as required. When the term "about" is used to describe a range of values or endpoints, it is understood that the disclosure includes the specific value or endpoint referred to. Whether the numerical values or endpoints of the ranges in the specification are recited using "about" or not, the numerical values or endpoints of the ranges are intended to include both implementations: one modified with "about" and one not modified with "about." It is also understood that each endpoint of a range is important when related to the other endpoint and independent of the other endpoint.

[0057] The terms "substantial," "substantially," "essentially," "essentially all," and variations thereof as used herein are intended to note that a described feature is equal or approximately equal to a value or description. For example, a "substantially planar" surface is intended to denote a surface that is planar or approximately planar. In addition, "substantially" is intended to denote that two values are equal or approximately equal. In some embodiments, "substantially" can denote values within about 10% of each other, such as within about 5% of each other, or within about 2% of each other.

[0058] Directional terms, such as "upper," "lower," "right," "left," "front," "back," "top," and "bottom," are used with respect to the orientation of the figures as drawn to facilitate description of one embodiment or variation over another. These terms are used only to reflect relative orientation and not to denote absolute orientation.

[0059] As used herein, the terms "the," "a," or "an," mean "at least one," and should not be limited to "only one" unless explicitly indicated to the contrary. Thus, for example, reference to "an element" includes embodiments having two or more such elements, unless the context clearly indicates otherwise.

[0060] Reference Figures 1-3 The present disclosure provides a method to eliminate or reduce in-process warpage in fan-out packaging processes by using a laminated glass sheet or wafer 12 as a carrier and slightly reducing the thickness of the backside cladding. Specifically, first, two compatible compositions with different CTE (coefficient of thermal expansion) values (which can be slightly different and / or vastly different) are selected, and the core CTE is higher than the cladding CTE. Note that for the purposes of the present disclosure, the CTE determination is defined as the average linear coefficient of thermal expansion (CTE) of the glass material as described by the dilatometer method according to ASTM E228. After the production of the laminated sheet 12, for example, after the production of the laminated sheet 12 by Corning's laminated fusion draw technology, there are definite residual stresses in the cladding and core. The stresses are compressive in the cladding and tensile in the core.

[0061] As Figure 1 shown, the laminated sheet or wafer (defined as a wafer-shaped laminated sheet) 12 includes a core layer 32 and first and second cladding layers 34 and 36. The outer surface 22 of the first cladding layer 34 is used to attach one or more semiconductor devices for making fan-out electrical connections / interconnections. The outer surface 24 of the second cladding layer 36 (the "backside" of the laminated sheet or wafer 12) is thinned to reduce warpage during the fan-out processing described below.

[0062] As Figure 2As shown, the first cladding layer 34 and the second cladding layer 36 are under compression, and thus generate compressive resistance (restoring force) in the direction generally indicated by the arrows on layers 34 and 36, while the core layer 32 is under tension, and thus generates tensile resistance (restoring force) in the direction generally indicated by the arrows on layer 32.

[0063] like Figure 3 As shown, one or more additional layers 40—including electronic devices and one or more dielectric layers (e.g., polyimide, polybenzoxazole, benzocyclobutene, etc.) and copper traces—are deposited on the first cladding 34. Since the one or more dielectric layers, and especially the copper traces, typically have a higher CTE than the laminate or wafer 12 (and the initial portion of the one or more additional layers 40), and also because these dielectric and metal layers are deposited at high temperatures, the stresses resulting upon cooling in the one or more additional layers are tensile stresses, and the one or more additional layers generate restoring forces in the approximate direction of the arrows shown on layer 40. To balance the various restoring forces and reduce the warpage of the overall structure, the second cladding is thinned, for example, by etching, polishing, grinding, or a combination thereof, or by other suitable means, resulting in a thinned second cladding 36a. Thus, flatness or low warpage can be restored after the deposition of one or more fan-out layers.

[0064] The implementation of this process is as follows: Figure 4 The flowchart is represented as process 50, which has steps 60, 70, and 80 as shown. In step 60, a fused glass laminate is provided or obtained, having a core layer and a first cladding layer and a second cladding layer. The core layer has a core thickness t. 芯体 It includes a core glass having a core glass thermal expansion coefficient α. 芯体 Poisson's ratio ν of the core glass 芯体 and core glass elasticity E 芯体 The first and second cladding layers each have a thickness t. 包层 And includes a cladding glass having a coefficient of thermal expansion α. 包层 , Poisson's ratio of cladding glass ν 包层 and the elasticity of the cladding glass E 包层 In step 70, a structure (e.g., a fan-out structure) is then constructed on one of the layers of the laminate (in this specification, on the first layer), which, as a whole, causes the laminate to bend away from the first layer (to become convex at the surface of the first layer). In step 80, the second layer is thinned to produce a thickness t. 薄化 The thinned second cladding layer makes the surface of the first cladding layer essentially flat again.

[0065] exist Figure 4In a more specific form of the method, a fan-out processing method is provided and includes: (1) providing or obtaining a fused glass laminate or wafer 12 having a core layer 32 including a core glass having a core glass coefficient of thermal expansion a 芯体 包层 ; a first cladding layer 34 and a second cladding layer 36 each including a cladding glass having a cladding glass coefficient of thermal expansion a 包层 芯体 ; (2) securing an integrated circuit device 42 to the first cladding layer 34 of the laminate or wafer; (3) forming a fan-out layer 46 on or over the integrated circuit device 42; and (4) removing some of the second cladding layer 36 to reduce warpage of the laminate or wafer having the integrated circuit device and fan-out layer thereon. Figure 5 An illustrative cross-sectional view of the method is shown.

[0066] In Figure 5 , the glass laminate or wafer 12 has a core layer 32 and first and second cladding layers 34 and 36, and the effective CTE of the laminate 12 is selected so that no warpage, or very little downward (frown) warpage, is produced after die bonding (securing the integrated circuit component 42) and filling the space between the die (integrated circuit component) with epoxy 44 (epoxy molding compound or "EMC") and curing the epoxy and then lapping it to flatten it. When one or more fan-out layers 46 (RDL or redistribution layers) are then deposited on and / or over the integrated circuit component 42, upward warpage (smile) is produced. By etching a very thin layer of the bottom side (non-deposited side) of the laminate (etching the surface 24 of the second cladding layer 36), the upward warpage in this process can be reduced or eliminated, or even a little downward (frown) warpage is produced again if further processing is desired.

[0067] It is desirable to select the effective CTE of the laminate to begin with to be close to the optimized CTE for the manufacturing process up to the process through die bonding and EMC (epoxy molding compound) curing / lapping. The main factors include EMC modulus / CTE / cure temperature, die shape factor, and die footprint. The effective CTE of the laminate thus selected is lower than the effective CTE of the laminate that would be optimal throughout the fan-out process. The ability to start with a lower effective CTE provides an advantage in one aspect because it is often difficult to obtain a glass that has both a high CTE (e.g., greater than 9-10 ppm / °C or higher) and high stiffness, and thus it is also difficult to obtain such a glass laminate.

[0068] According to further embodiments, selecting a particular effective CTE of the laminate or wafer can further include a method 100 including as Figure 6 ​​the steps shown in the flowchart of FIG. 1 1 0-130, or more specifically, comprising the steps of: (1 ) providing or obtaining a fusion glass laminate having a core layer (32) and first and second cladding layers (34, 36), the core layer (32) having a core thickness t 芯体 and comprising a core glass having a core glass coefficient of thermal expansion a 芯体 , a core glass Poisson's ratio v 芯体 , and a core glass elasticity E 芯体 , the first and second cladding layers (34, 36) each having a thickness t 包层 and comprising a cladding glass having a cladding glass coefficient of thermal expansion a 包层 , a cladding glass Poisson's ratio v 包层 , and a cladding glass elasticity Ecladding, (2) selecting a desired effective coefficient of thermal expansion aeff that is greater than

[0069]

[0070] and less than a 芯体 , and

[0071] thinning the first and second cladding layers (34, 36) to produce a thinned first cladding layer and a thinned second cladding layer, each having a thickness t 薄化 , the t 薄化 is in the following range:

[0072] from

[0073] to

[0074]

[0075] where P is 0.1, 0.05, 0.02, 0.01, or even 0.005.

[0076] In other embodiments of the method shown in FIG. 1 1 0-130, the core layer consists essentially of the core glass. In further embodiments, the first and second cladding layers each consist essentially of the cladding glass. Figure 6 In further embodiments, the step of providing or obtaining a fusion glass laminate comprises producing the fusion glass laminate using a fusion draw machine.

[0077] In other embodiments, the step of thinning the first and second cladding layers comprises etching the first and second cladding layers.

[0078] In other embodiments, the step of thinning the first and second cladding layers comprises polishing the first and second cladding layers.

[0079]

[0080] ​According to further embodiments, the method further comprises the step of cutting the fused glass laminate sheet to form one or more dies.

[0081] According to further embodiments, the method comprises the step of cutting the fused glass laminate sheet to form one or more panels.

[0082] According to further embodiments, the cutting comprises laser cutting.

[0083] According to further embodiments, the cutting comprises laser cutting using a Bessel beam.

[0084] Since the selected starting effective CTE of the laminate is optimized only for die bonding and EMC curing / polishing in the method of Figure 4 or 5, the warpage generated during these steps is less. A flat or only slightly curved downward (away from the processing side) (frown) as shown in Figure 5 can be achieved by careful selection of the starting CTE.

[0085] In the case where each additional layer is deposited after die bonding and EMC curing / polishing, the effective CTE of the layers above the carrier generally remains increasing because both the dielectric layer(s) (e.g., polyimide, polybenzoxazole, benzocyclobutene, etc.) and the copper traces have a higher CTE than the EMC. Since these additional layers are deposited at high temperature, the resulting stress upon cooling is a tensile stress in the additional layers, resulting in warping towards the processing side (smile). If this warping is not compensated, the carrier and device layers together will remain curved upward (towards the processing side) and can exceed the process specification. However, according to the methods and processes disclosed herein, the upward warping after die bonding and EMC curing / polishing is compensated by etching and / or polishing the bottom side of the carrier.

[0086] During the entire fan-out deposition / package process, the die / panel needs to go through many chambers for different process steps. Between transfers, the die / panel is released from the vacuum chuck and mechanical / chemical etching / polishing can be performed on the bottom side of the carrier while the impact on the deposition / package process is minimized. The number of etching / polishing steps will be determined by the process specification and / or RDL (redistribution layer) requirements.

[0087] In current commercial practice, glass carriers are typically recycled multiple times. In the present method, optionally, after each use, the top (deposition) side can be etched to reduce the thickness of the first cladding layer and to restore the carrier to a flat shape. This can be combined with a cleaning step already in place. Since only a very thin cladding layer (1-2 um) is etched off during the entire cycle, the carrier thickness will not decrease significantly, and even after multiple uses, the pre-use effective CTE of the recycled carrier laminate will only change (decrease) slowly. If desired, the initial effective CTE of a carrier laminate intended for multiple uses can be chosen to be slightly higher than the ideal CTE for a die bonding and EMC curing / polishing step only, thereby facilitating an increased number of viable cycles. If multiple cycles are not viable, the ability to tightly control warpage is expected to outweigh the disadvantage of reduced or non-cyclicality for high-end packaging requiring very small lithography line widths (<1 um).

[0088] While illustrative implementations and embodiments have been given for the purpose of disclosure, this description is not meant to limit the scope of the present disclosure and the appended claims in any way. Therefore, modifications and variations of the implementations and embodiments described herein can be made without departing from the spirit or various principles of the present disclosure. All such variations and modifications are intended to be included herein within the scope of the present disclosure and the appended claims.

Claims

1. A method of fan-out processing, the method comprising: A fused glass laminate or wafer is provided or obtained that includes a core layer, a first cladding layer, and a second cladding layer, the core layer having a core layer thickness t 芯体 and including a core glass having a core glass coefficient of thermal expansion α 芯体 , a core glass Poisson's ratio ν 芯体 , and a core glass elasticity E 芯体 , the first cladding layer and the second cladding layer each including a cladding layer thickness t 包层 and each including a cladding glass having a cladding glass coefficient of thermal expansion α 芯体 less than the core glass coefficient of thermal expansion α 包层 , a cladding glass Poisson's ratio ν 包层 , and a cladding glass elasticity E 包层 ​ Selecting a desired effective coefficient of thermal expansion of a fused glass laminate or wafer α 有效 , the α 有效 greater than and less than α 芯体 and thinning the first cladding layer and the second cladding layer to produce a thinned first cladding layer and a thinned second cladding layer, each of the thinned first cladding layer and the thinned second cladding layer having a thickness t 薄化 , the t 薄化 in the following ranges: From to where P is one of 0.1, 0.05, 0.02, 0.01, or 0.005; securing an integrated circuit device to the first cladding layer; forming a first fan-out layer on or over the integrated circuit device; and removing some of the second cladding layer to reduce warpage of the fused glass laminate or wafer having the integrated circuit device and the fan-out layer.

2. The method of claim 1, wherein, The core layer consists of core glass.

3. The method of claim 2, wherein, The first cladding layer and the second cladding layer each consist of cladding glass.

4. The method of claim 1, wherein, The step of providing or obtaining the fused glass laminate or wafer includes producing the fused glass laminate using a fusion draw machine.

5. The method of claim 1, wherein, The step of removing some of the second cladding layer includes etching the second cladding layer.

6. The method of claim 1, wherein, The step of removing some of the second cladding layer includes polishing or grinding the second cladding layer.

7. The method of claim 1, wherein, The effective coefficient of thermal expansion of the selected fused glass laminate or wafer is within 20% of the ideal CTE for securing the integrated circuit device.

8. The method of claim 7, wherein, The effective coefficient of thermal expansion of the selected fused glass laminate or wafer is within 10% of the ideal CTE for securing the integrated circuit device.

9. The method of claim 1, further comprising: forming additional fan-out layers on or over the first fan-out layer, and removing more of the second cladding layer.

Images