Three-dimensional semiconductor memory device

Abstract

A three-dimensional semiconductor memory device is provided, including: a substrate including a first connection region and a second connection region in a first direction and a cell array region between the first connection region and the second connection region; and a first block structure on the substrate. The first block structure has a first width on the cell array region, the first block structure has a second width on the first connection region, and the first block structure has a third width on the second connection region. The first width, the second width, and the third width are parallel to a second direction intersecting the first direction, and the first width is smaller than the second width and larger than the third width.

Description

[0001] This patent application claims priority to Korean Patent Application No. 10-2019-0085270, filed on July 15, 2019, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference. TECHNICAL FIELD

[0002] Embodiments of the inventive concept relate to a three-dimensional (3D) semiconductor device, and more particularly, to a 3D semiconductor memory device having improved integration density. BACKGROUND

[0003] To provide excellent performance and low manufacturing costs, semiconductor devices have been highly integrated. The integration density of a semiconductor device directly affects the cost of the semiconductor device, leading to a demand for highly integrated semiconductor devices. The integration density of a typical two-dimensional (2D) or planar semiconductor device can be determined mainly by the area occupied by a unit memory cell. Accordingly, the integration density of a typical 2D or planar semiconductor device can be affected by a technology of forming a fine pattern. However, because a higher-priced apparatus is required to form a fine pattern, the integration density of a 2D semiconductor device is still limited, although it continues to increase. Accordingly, a three-dimensional (3D) semiconductor memory device has been developed to overcome the above limitations. The 3D semiconductor memory device can include memory cells arranged three-dimensionally. SUMMARY

[0004] Embodiments of the inventive concept can provide a three-dimensional (3D) semiconductor memory device configured to improve and / or capable of improving integration density.

[0005] In one aspect, a 3D semiconductor memory device can include a substrate including a first connection region and a second connection region arranged along a first direction and a cell array region between the first connection region and the second connection region, and a first block structure on the substrate. The first block structure can have a first width on the cell array region, the first block structure can have a second width on the first connection region, and the first block structure can have a third width on the second connection region. The first width, the second width, and the third width can be parallel to a second direction crossing the first direction, and the first width can be smaller than the second width and can be greater than the third width.

[0006] In another aspect, a 3D semiconductor memory device can include: first, second, and third block structures located on a substrate and spaced apart from each other in a first direction; a first block separation region separating the first and second block structures from each other; and a second block separation region separating the second and third block structures from each other. The first block separation region can be spaced apart from the second block separation region, and at least one of the first and second block separation regions can have a stepped shape when viewed in a plan view.

[0007] In still another aspect, a 3D semiconductor memory device can include: a substrate including first and second connection regions in a first direction and a cell array region located between the first and second connection regions; and a first block structure located on the substrate. The first block structure can include first lower electrodes located at a lowest position and first upper electrodes located at a highest position. The first upper electrodes can be spaced apart from each other in a second direction crossing the first direction and can have a linear shape extending in the first direction. Each of the first upper electrodes can have a first width parallel to the second direction. The first lower electrodes can include protrusions protruding laterally from sidewalls of an outermost one of the first upper electrodes on one of the first and second connection regions. The protrusions can have a second width parallel to the second direction. The second width can be in a range of one to three times the first width.

[0008] In still another aspect, a 3D semiconductor memory device can include: a substrate including first and second connection regions in a first direction and a cell array region located between the first and second connection regions; and first and second block structures located on the substrate and spaced apart from each other in a second direction crossing the first direction by a block separation region. The block separation region can have a step shape, a diagonal line shape, or a stepped shape on one of the first and second connection regions when viewed in a plan view. BRIEF DESCRIPTION OF DRAWINGS

[0009] The inventive concept will become more apparent in view of the attached drawings and accompanying detailed description.

[0010] Figure 1 is a schematic diagram illustrating a three-dimensional (3D) semiconductor memory device according to some embodiments of the inventive concept.

[0011] Figure 2 is a schematic block diagram illustrating a cell array of a 3D semiconductor memory device according to some embodiments of the inventive concept.

[0012] Figure 3 is a schematic circuit diagram illustrating a 3D semiconductor memory device according to some embodiments of the inventive concept.

[0013] Figure 4 is a plan view showing an electrode structure of a 3D semiconductor memory device according to some embodiments of the inventive concept.

[0014] Figure 5 is a perspective view showing an electrode structure of a 3D semiconductor memory device according to some embodiments of the inventive concept.

[0015] Figure 6 is a perspective view showing Figure 5 a second block structure of a 3D semiconductor memory device.

[0016] Figure 7 is a plan view showing a portion of the second block structure of the 3D semiconductor memory device. Figure 4

[0017] Figures 8A-8D is a plan view showing a structure of some electrodes of the 3D semiconductor memory device. Figure 6

[0018] is a cross-sectional view taken along line A-A’ of Figure 9 Figure 7

[0019] Figures 10A-10C is a plan view showing a 3D semiconductor memory device according to some embodiments of the inventive concept.

[0020] Figures 11A-11D is a plan view showing an end portion in a 3D semiconductor memory device according to some embodiments of the inventive concept.

[0021] Figure 12A and Figure 12B is a plan view showing an end portion in a 3D semiconductor memory device according to some embodiments of the inventive concept. DETAILED DESCRIPTION

[0022] In the following, embodiments of the inventive concept will be described in more detail with reference to the appended drawings.

[0023] Figure 1 is a schematic diagram showing a three-dimensional (3D) semiconductor memory device according to some embodiments of the inventive concept.

[0024] Referring to Figure 1 , the 3D semiconductor memory device can include a cell array region CAR and a peripheral circuit region. The peripheral circuit region can include a row decoder region ROW DCR, a page buffer region PBR, a column decoder region COL DCR, and / or a control circuit region (not shown). In some embodiments, a connection region CNR can be provided between the cell array region CAR and the row decoder region ROW DCR.

[0025] ​​​A memory cell array including a plurality of memory cells can be disposed in a cell array region CAR. In some embodiments, the memory cell array can include three-dimensionally arranged memory cells, word lines, and / or bit lines. The word lines and the bit lines can be electrically connected to the memory cells.

[0026] A row decoder for selecting a word line of the memory cell array can be disposed in a row decoder region ROW DCR, and an interconnect structure can be disposed in a connection region CNR. The interconnect structure can include contact plugs and interconnect lines electrically connecting the memory cell array to the row decoder. The row decoder can select a word line from among the word lines of the memory cell array in response to an address signal. The row decoder can provide a first word line voltage and a second word line voltage to the selected word line and the unselected word lines, respectively, in response to a control signal of a control circuit.

[0027] A page buffer for sensing data stored in the memory cells can be disposed in a page buffer region PBR. Depending on an operation mode, the page buffer can temporarily store data to be stored in the memory cells or can sense data stored in the memory cells. The page buffer can function as a write driver circuit in a program operation mode and can function as a sense amplifier circuit in a read operation mode.

[0028] A column decoder connected to the bit lines of the memory cell array can be disposed in a column decoder region COL DCR. The column decoder can provide a data transfer path between the page buffer and an external device (e.g., a memory controller).

[0029] Figure 2 is a schematic block diagram illustrating a cell array of a 3D semiconductor memory device according to some embodiments of the inventive concepts.

[0030] Referring to Figure 2 The cell array region CAR can include a plurality of cell array blocks BLK1 to BLKn. Each of the cell array blocks BLK1 to BLKn can include an electrode structure including electrodes stacked in a third direction D3 on a plane defined by a first direction D1 and a second direction D2 crossing each other. The electrode structure can be joined to a plurality of vertical structures (e.g., semiconductor pillars) to constitute three-dimensionally arranged memory cells. Further, each of the cell array blocks BLK1 to BLKn can also include bit lines electrically connected to the memory cells.

[0031] Figure 3 is a schematic circuit diagram illustrating a 3D semiconductor memory device according to some embodiments of the inventive concepts.

[0032] Referring to Figure 3A cell array of a 3D semiconductor memory device according to some embodiments can include a common source line CSL, a plurality of bit lines BL0 to BL2, a plurality of string selection lines SSL11, SSL12, SSL13, SSL21, SSL22, and SSL23, and / or a plurality of cell strings CSTR disposed between the common source line CSL and the bit lines BL0 to BL2.

[0033] The bit lines BL0 to BL2 can be arranged two-dimensionally, and the plurality of cell strings CSTR can be connected in parallel to each of the bit lines BL0 to BL2. The cell strings CSTR can be commonly connected to the common source line CSL. In other words, the plurality of cell strings CSTR can be disposed between one common source line CSL and a plurality of bit lines BL0 to BL2. The common source line CSL can be disposed as a plurality, and the plurality of common source lines CSL can be arranged two-dimensionally. In some embodiments, the same voltage can be applied to the plurality of common source lines CSL. In certain embodiments, the common source lines CSL can be electrically controlled independently from each other.

[0034] In some embodiments, one cell string CSTR can include string selection transistors SST21 and SST11 connected in series to each other, memory cells MCT connected in series to each other, and a ground selection transistor GST. Each memory cell MCT can include a data storage element.

[0035] For example, the 2-1 string selection transistor SST21 can be connected to one of the bit lines BL0 to BL2, and the ground selection transistor GST can be connected to the common source line CSL. The memory cells MCT can be connected in series between the 1-1 string selection transistor SST11 and the ground selection transistor GST.

[0036] Further, one cell string CSTR can also include a dummy cell DMC connected between the 1-1 string selection transistor SST11 and the memory cells MCT. Although not shown in the drawings, an additional dummy cell can be connected between the ground selection transistor GST and the memory cells MCT adjacent to the ground selection transistor GST.

[0037] According to certain embodiments, in each cell string CSTR, the ground selection transistor GST can include a plurality of MOS transistors connected in series to each other, similar to the 1-1 string selection transistor SST11 and the 2-1 string selection transistor SST21. In certain embodiments, each cell string CSTR can include a single string selection transistor.

[0038] In some embodiments, the 1-1 string selection transistor SST11 can be controlled by a 1-1 string selection line SSL11, and the 2-1 string selection transistor SST21 can be controlled by a 2-1 string selection line SSL21. The memory cells MCT can be controlled by a plurality of word lines WL0 to WLn, and the dummy cell DMC can be controlled by a dummy word line DWL. The ground selection transistor GST can be controlled by a ground selection line GSL. The common source line CSL can be commonly connected to the source of the ground selection transistor GST.

[0039] One cell string CSTR can include a plurality of memory cells MCT disposed at different distances from the common source line CSL, respectively. The word lines WL0 to WLn and the DWL can be disposed between the common source line CSL and the bit lines BL0 to BL2.

[0040] The gate electrodes of the memory cells MCT (or dummy cells) disposed at the same level from the common source line CSL can be commonly connected to one of the word lines WL0 to WLn and the DWL, thereby being in an equipotential state. Alternatively, even if the gate electrodes of the memory cells MCT are disposed at substantially the same level from the common source line CSL, the gate electrodes disposed in one row (or one column) can be controlled independently of the gate electrodes disposed in another row (or another column).

[0041] Figure 4 is a plan view illustrating an electrode structure of a 3D semiconductor memory device according to some embodiments of the inventive concept. Figure 5 is a perspective view illustrating an electrode structure of a 3D semiconductor memory device according to some embodiments of the inventive concept.

[0042] Referring to Figure 4 and Figure 5 , a substrate 1 can be disposed. The substrate 1 can include a first connection region CNR1 and a second connection region CNR2 spaced apart from each other in a first direction X, and a cell array region CAR disposed between the first connection region CNR1 and the second connection region CNR2. First to fourth block structures BLS1, BLS2, BLS3, and BLS4 spaced apart from each other in a second direction Y crossing the first direction X can be disposed on the substrate 1. The second block structure BLS2 can have a structure in which the first block structure BLS1 is rotated by 180 degrees in a plan view, and the fourth block structure BLS4 can have a structure in which the third block structure BLS3 is rotated by 180 degrees in a plan view. The second block structure BLS2 and the fourth block structure BLS4 can be disposed to mesh with the first block structure BLS1 and the third block structure BLS3, respectively. The second block structure BLS2 can have a structure symmetrical to that of the third block structure BLS3.

[0043] The block separation regions SR1 can be respectively provided between the first block structure BLS1 to the fourth block structure BLS4. The block separation region SR1 located between the first block structure BLS1 and the second block structure BLS2 and the block separation region SR1 located between the third block structure BLS3 and the fourth block structure BLS4 can have a stepped shape when viewed in a plan view. The block separation region SR1 located between the second block structure BLS2 and the third block structure BLS3 can have a straight line shape when viewed in a plan view. Adjacent block separation regions SR1 can be spaced apart from each other without contacting each other from the first connection region CNR1 to the second connection region CNR2. This structure can easily control the depth of the recess in an etching process for forming the block separation region SR1.

[0044] As Figure 4 Unlike, if the planar shapes of adjacent block separation regions SR1 meet each other on the first connection region CNR1 or the second connection region CNR2 to form three points (where three lines meet each other) or four points (where four lines meet each other), it can be very difficult to control the depth of the recess in an etching process for forming the block separation region SR1. However, according to embodiments of the inventive concept, adjacent block separation regions SR1 can be spaced apart from each other as Figure 4 well, and thus these limitations can be addressed.

[0045] As Figure 4 shown in FIG. 1, the second block structure BLS2 can have a first width W1 parallel to the second direction Y on the cell array region CAR. The second block structure BLS2 can have a second width W2 parallel to the second direction Y on the first connection region CNR1. The second block structure BLS2 can have a third width W3 parallel to the second direction Y on the second connection region CNR2. The first width W1 can be smaller than the second width W2 and can be greater than the third width W3. The sum of the second width W2 and the third width W3 can correspond to about twice the first width W1. The relationship of the widths of the third block structure BLS3 can be the same as the relationship of the widths of the second block structure BLS2.

[0046] The first block structure BLS1 can have a first width W1 parallel to the second direction Y on the cell array region CAR. The first block structure BLS1 can have a third width W3 parallel to the second direction Y on the first connection region CNR1. The first block structure BLS1 can have a second width W2 parallel to the second direction Y on the second connection region CNR2. The relationship of the widths of the fourth block structure BLS4 can be the same as the relationship of the widths of the first block structure BLS1.

[0047] Each of the first to fourth block structures BLS1 to BLS4 can have a first length L1 parallel to the first direction X on the first connection region CNR1. Each of the first to fourth block structures BLS1 to BLS4 can have a second length L2 parallel to the first direction X on the second connection region CNR2. The first length L1 can be equal to the second length L2.

[0048] Referring to Figure 5 The first end side wall S1a of the first block structure BLS1 can be aligned with the first end side wall S2a of the second block structure BLS2 on the first connection region CNR1 when viewed in a plan view. Also, the second end side wall S1b of the first block structure BLS1 can be aligned with the second end side wall S2b of the second block structure BLS2 on the second connection region CNR2 when viewed in a plan view. The first to fourth block structures BLS1 to BLS4 can have a stepped structure on the first and second connection regions CNR1 and CNR2. These will be described in more detail.

[0049] Figure 6 is a perspective view showing a second block structure of the 3D semiconductor memory device of Figure 5 Figure 7 is a plan view showing a portion of the second block structure of the 3D semiconductor memory device of Figure 4 Figures 8A-8D is a plan view showing a structure of some electrodes on the cell array region CAR and the first connection region CNR1 except for the second connection region CNR2 of Figure 6 Figures 8A-8C

[0050] Referring to Figure 6 , Figure 7 and Figures 8A-8D , the second block structure BLS2 can include a lower stack structure 10, a first intermediate stack structure 20a, a second intermediate stack structure 20b, and an upper stack structure 30 sequentially stacked on the substrate 1.

[0051] ​​​​The lower stack structure 10 can include a plurality of lower electrodes 10e and 10eb vertically stacked. The lower electrodes 10e and 10eb can have a stepped structure inclined in both the first direction X and the second direction Y on the first connection region CNR1. The lower electrodes 10e and 10eb can have a first lower pad region LP1 to a fifth lower pad region LP5. The first lower pad region LP1 to the fifth lower pad region LP5 can constitute a stepped structure inclined downward in the first direction X and a direction opposite to the second direction Y. The areas of the first lower pad region LP1 to the fifth lower pad region LP5 can sequentially decrease as the vertical distance from the substrate 1 increases. In other words, the fifth lower pad region LP5 located at the lowest position can have the widest area, and the first lower pad region LP1 located at the highest position can have the narrowest area. The second lower pad region LP2 to the fifth lower pad region LP5 can have an L shape when viewed in a plan view. Although not shown in Figure 6 and Figure 7 , an insulating layer ILD (see Figure 9 ) can be disposed between the lower stack structure 10 and the substrate 1 and between the lower electrodes 10e and 10eb, so the substrate 1 and the lower electrodes 10e and 10eb can be vertically spaced apart from each other.

[0052] The first and second intermediate stack structures 20a and 20b can be offset from each other in the first direction X. Each of the first and second intermediate stack structures 20a and 20b can include a plurality of intermediate electrodes 20e and 20eb vertically stacked. The intermediate electrodes 20e and 20eb can have a stepped structure inclined in the second direction Y on the first connection region CNR1. The intermediate electrodes 20e and 20eb can have a first intermediate pad region MP1 to a fifth intermediate pad region MP5. The first intermediate pad region MP1 to the fifth intermediate pad region MP5 can constitute a stepped structure inclined downward in a direction opposite to the second direction Y. Although not shown in Figure 6 and Figure 7 , an insulating layer ILD (see Figure 9 ) can be disposed between the lower stack structure 10 and the first and second intermediate stack structures 20a and 20b and between the intermediate electrodes 20e and 20eb, so the intermediate electrodes 20e and 20eb can be vertically spaced apart from each other.

[0053] The upper stack structure 30 can include the second upper electrode 30e2 and the first upper electrode 30e1 vertically stacked. The first upper electrode 30e1 can have a linear shape spaced apart from each other in the second direction Y when viewed in a plan view. The end portions of the first upper electrode 30e1 can constitute a stepped shape inclined in the first direction X on the first connection region CNR1 and the second connection region CNR2. For example, the first upper electrode 30e1 can include a first upper pad region UP1 and a second upper pad region UP2 on the first connection region CNR1. The end portions of the second upper electrode 30e2 can constitute a stepped shape inclined in the first direction X on the first connection region CNR1 and the second connection region CNR2.

[0054] The second upper electrode 30e2 can include a third upper pad region UP3 to a fifth upper pad region UP5 on the first connection region CNR1. The first upper pad region UP1 to the fifth upper pad region UP5 can constitute a stepped structure inclined downward in the first direction X. The area of the fifth upper pad region UP5 located at the lowest position can be wider than the area of each of the first upper pad region UP1 to the fourth upper pad region UP4. Although not shown in Figure 6 and Figure 7 , an insulating layer ILD (see Figure 9 ) can be disposed between the second intermediate stack structure 20b and the upper stack structure 30 and between the first upper electrode 30e1 and the second upper electrode 30e2, so the upper electrodes 30e1 and 30e2 can be vertically spaced apart from each other.

[0055] The dummy stack structure 40 can be disposed on the fifth upper pad region UP5 on the first connection region CNR1. The dummy stack structure 40 can include dummy electrodes 40e vertically stacked. The dummy electrodes 40e can have a stepped structure inclined in the first direction X and the second direction Y. Although not shown in Figure 6 and Figure 7 , an insulating layer can be disposed between the fifth upper pad region UP5 and the dummy stack structure 40 and between the dummy electrodes 40e, so the fifth upper pad region UP5 and the dummy electrodes 40e can be vertically spaced apart from each other. A voltage is not applied to the dummy electrodes 40e, so the dummy electrodes 40e can be floating.

[0056] The dummy electrodes 40e constituting the dummy stack structure 40 can have first side walls SW1 exposed on the first connection region CNR1 in the first direction X and vertically aligned with each other. The intermediate electrodes 20e constituting the second intermediate stack structure 20b can have second side walls SW2 exposed on the first connection region CNR1 in the first direction X and vertically aligned with each other. The intermediate electrodes 20e constituting the first intermediate stack structure 20a can have third side walls SW3 exposed on the first connection region CNR1 in the first direction X and vertically aligned with each other. The first to third side walls SW1, SW2, and SW3 can be offset from each other.

[0057] The intermediate electrodes 20e in the second intermediate stack structure 20b except for the lowermost intermediate electrode 20eb and the lowermost one of the second upper electrodes 30e2 can have fourth side walls SW4 exposed on the second connection region CNR2 vertically aligned with each other. The intermediate electrodes 20e in the first intermediate stack structure 20a except for the lowermost intermediate electrode 20eb and the lowermost intermediate electrode 20eb of the second intermediate stack structure 20b can have fifth side walls SW5 exposed on the second connection region CNR2 vertically aligned with each other. The lower electrodes 10e in the lower stack structure 10 except for the lowermost lower electrode 10eb and the lowermost intermediate electrode 20eb of the first intermediate stack structure 20a can have sixth side walls SW6 exposed on the second connection region CNR2 vertically aligned with each other.

[0058] The cutout region CTR1 can penetrate the lower stack structure 10, the first intermediate stack structure 20a, the second intermediate stack structure 20b, and the upper stack structure 30, and can extend in the first direction X. The cutout region CTR1 can be present on the cell array region CAR, the first connection region CNR1, and the second connection region CNR2. The cutout region CTR1 can extend to the edge of the second block structure BLS2 on the first connection region CNR1 and the second connection region CNR2.

[0059] Each of the second upper electrodes 30e2, the intermediate electrodes 20e and 20eb, and the lower electrodes 10e and 10eb can include an electrode connection portion 5 on each of the first connection region CNR1 and the second connection region CNR2 to prevent each of the electrodes 30e2, 20e, 20eb, 10e, and 10eb from being divided into segments by the cutout region CTR1. Accordingly, segments of each of the second upper electrodes 30e2, the intermediate electrodes 20e and 20eb, and the lower electrodes 10e and 10eb disposed at the same height can be in the same potential state. The cutout region CTR1 can be spaced apart from the block separation region SR1.

[0060] Referring to Figure 6 and Figure 8DThe lowermost lower electrode 10eb and the lowermost intermediate electrode 20eb in the first intermediate stack structure 20a and the second intermediate stack structure 20b can be exposed on the second connection region CNR2. In other words, the lowermost lower electrode 10eb can also have an auxiliary fifth lower pad region LP5b. The lowermost intermediate electrode 20eb can also have an auxiliary fifth intermediate pad region MP5b.

[0061] The first contact plug CT1 can be disposed on the fifth lower pad region LP5, and the second contact plug CT2 can be disposed on the auxiliary fifth lower pad region LP5b. The lowermost lower electrode 10eb can correspond to the ground select line GSL. A voltage can be applied across the lowermost lower electrode 10eb through the first contact plug CT1 and the second contact plug CT2, so that a substantially uniform voltage can be applied to the entire ground select line GSL without voltage drop. As a result, the performance and reliability of the 3D semiconductor memory device can be improved. Although not shown in the drawings, other contact plugs for applying a voltage can be disposed on other pad regions than the fifth lower pad region LP5 and the auxiliary fifth lower pad region LP5b, respectively. Figure 3

[0062] In some embodiments, the number of the first upper electrodes 30e1 located in the uppermost layer of the second block structure BLS2 can be less than the number of the upper pad regions UP1 to UP5. The number of the first upper electrodes 30e1 located in the uppermost layer can be less than the number of the intermediate pad regions MP1 to MP5. The number of the first upper electrodes 30e1 located in the uppermost layer can be less than the number of the lower pad regions LP1 to LP5. In the present example, the number of the first upper electrodes 30e1 located in the uppermost layer is 4, and each of the number of the intermediate pad regions MP1 to MP5 and the number of the lower pad regions LP1 to LP5 is 5. The number of the first upper electrodes 30e1 located in the uppermost layer can correspond to the number of string select lines (hereinafter, referred to as SSL number) present in the uppermost layer. The number of the intermediate pad regions MP1 to MP5 in one intermediate stack structure 20a or 20b or the number of the lower pad regions LP1 to LP5 in the lower stack structure 10 can correspond to the number of step division patterns (hereinafter, referred to as SDP number). The SDP number can be greater than the SSL number and can be less than twice the SSL number. In other words, when the SSL number is n, the SDP number can be equal to or greater than n+1 and can be less than 2n. For example, in the present example, the SSL number is 4, and the SDP number is 5. However, embodiments of the inventive concept are not limited thereto. When the SSL number is 4, the SDP number can be in the range of 5 to 7. Figure 6

[0063] ​​In embodiments of the inventive concept, the width of the block structures BLS1 to BLS4 can be changed on the connection regions CNR1 and CNR2. In other words, the width of the ends of the block structures BLS1 to BLS4 on the connection regions CNR1 and CNR2 can be greater than the width of the block structures BLS1 to BLS4 on the cell array region CAR. Accordingly, a space for a staircase division pattern can be secured regardless of the number of SSLs. As a result, bridging between contact plugs can be prevented, and the degree of freedom of interconnection lines can be increased.

[0064] Further, although not shown in the drawings, a dummy vertical trench can be provided to penetrate the pad region, and thus collapse or tilting of the block structures BLS1 to BLS4 in a manufacturing process can be prevented. According to embodiments of the inventive concept, the area of the pad region can be increased by changing the width of the block structures on the connection regions, and thus the dummy vertical trench can be easily provided. As a result, the reliability of the 3D semiconductor memory device can be improved.

[0065] Further, the number of staircase division patterns can be increased to be greater than the number of string selection lines. Further, the block structures can be provided to be engaged or joined to each other. Accordingly, the total area of the 3D semiconductor memory device can be reduced, and thus the integration density of the 3D semiconductor memory device can be improved. The detailed structures of the first block structure BLS1, the third block structure BLS3, and the fourth block structure BLS4 of the 3D semiconductor memory device 1000 are described above with reference to Figure 6 Figure 7 and Figures 8A-8D The detailed structure of the second block structure BLS2 is described as an example. However, the detailed structures of the first block structure BLS1, the third block structure BLS3, and the fourth block structure BLS4 of the 3D semiconductor memory device 1000 can be the same / similar to the detailed structure of the second block structure BLS2. Figure 5 Each of the first block structure BLS1, the third block structure BLS3, and the fourth block structure BLS4 of the 3D semiconductor memory device 1000 can be symmetrical to the second block structure BLS2, or can have a structure in which the second block structure BLS2 is rotated by 180 degrees in a plan view. Figure 5

[0066] Figure 9 is a cross-sectional view taken along the line A-A' of the 3D semiconductor memory device 1000. Figure 7

[0067] Referring to Figure 6 Figure 7 and Figure 9 ​​​​The vertical channels VS and dummy vertical channels DVS can be provided on the base 1 of the cell array region CAR and can extend in the third direction Z. The vertical channels VS and dummy vertical channels DVS can penetrate the lower stack structure 10, the first intermediate stack structure 20a, the second intermediate stack structure 20b, and the upper stack structure 30 described above. When viewed in a plan view, the vertical channels VS constituting two rows adjacent to each other can be arranged in a zigzag form in the second direction Y. The dummy vertical channels DVS can be provided between two first upper electrodes 30e1 adjacent to each other. The isolation insulating pattern 50 can be provided between the two first upper electrodes 30e1 adjacent to each other and between the dummy vertical channels DVS.

[0068] The vertical channels VS and dummy vertical channels DVS can include substantially the same material and can have substantially the same structure. For example, the vertical channels VS and dummy vertical channels DVS can have a hollow pipe shape or a hollow penne shape. Alternatively, the vertical channels VS and dummy vertical channels DVS can have a cylindrical shape. The vertical channels VS can be electrically connected to the bit lines BL. The dummy vertical channels DVS can not be connected to the bit lines BL but can be electrically floating.

[0069] When viewed in a plan view, the common source region CSR can be provided in the base 1 between the electrode portions of the electrodes. The common source region CSR can be formed by doping a portion of the base 1 with a dopant of the second conductivity type. The common source plug CSP can be connected to the common source region CSR, and the sidewall insulating spacers SP can be provided between the common source plug CSP and the stack structures 10, 20a, 20b, and 30. The common source plug CSP can be provided in the block separation region SR1 of the memory cell array region CAR and in the cutout region CTR1 of the dummy memory cell array region DCA. Figure 5 The common source plug CSP can be provided in the block separation region SR1 of the memory cell array region CAR and in the cutout region CTR1 of the dummy memory cell array region DCA. Figure 7

[0070] The 3D semiconductor memory device of Figures 5-9 can be manufactured by the following processes.

[0071] Referring to Figures 5-9 , the insulating layers ILD and the sacrificial layers (not shown) can be alternately stacked on the base 1 to form the stack structures, and the trimming process and the etching process can be repeated to form the vertical channels VS and the dummy vertical channels DVS in the memory cell array region CAR and the dummy memory cell array region DCA, respectively. Figure 5 ​The staircase shape is formed on the first connection region CNR1 and the second connection region CNR2 as well. The vertical channel VS and the dummy vertical channel DVS can be formed to penetrate the stack structure on the cell array region CAR. The stack structure can be divided by an etching process to form the cut region CTR1 and the block separation region SR1. At this time, since the block separation regions SR1 are not connected to each other, the recess depth can be easily controlled in the etching process. A replacement process of replacing the sacrificial layer (not shown) with a conductive pattern can be performed through the cut region CTR1 and the block separation region SR1. The common source plug CSP and the sidewall insulating spacer SP can be formed in the cut region CTR1 and the block separation region SR1.

[0072] Figures 10A-10C is a plan view illustrating a 3D semiconductor memory device according to some embodiments of inventive concepts.

[0073] Referring to Figures 10A-10C , the first block structure BLS1 to the sixth block structure BLS6 can be spaced apart from each other in the second direction Y. The second block structure BLS2, the fourth block structure BLS4, and the sixth block structure BLS6 can respectively have structures in which the first block structure BLS1, the third block structure BLS3, and the fifth block structure BLS5 are rotated by 180 degrees in a plan view.

[0074] In Figure 10A , the block separation region SR1 can include first block separation regions SR11 and second block separation regions SR12 alternately arranged. Each first block separation region SR11 can have a staircase shape inclined upward in the first direction X when viewed in a plan view. Each second block separation region SR12 can have a straight line shape when viewed in a plan view.

[0075] Optionally, in Figure 10B , the block separation region SR1 can include first block separation regions SR11, second block separation regions SR12, and third block separation regions SR13 alternately arranged. Each first block separation region SR11 can have a staircase shape inclined upward in the first direction X when viewed in a plan view. Each second block separation region SR12 can have a straight line shape when viewed in a plan view. Each third block separation region SR13 can have a staircase shape inclined downward in the first direction X when viewed in a plan view.

[0076] Optionally, in Figure 10C , the block separation region SR1 can include first block separation regions SR11 and second block separation regions SR12 alternately arranged. Each first block separation region SR11 can have a staircase shape inclined upward in the first direction X when viewed in a plan view. Each second block separation region SR12 can have a staircase shape inclined downward in the first direction X when viewed in a plan view.

[0077] Other structures and / or components can be the same / similar to those described with reference to Figures 4-9

[0078] Figures 11A-11D is a plan view showing an end portion on a connection region CNR1 or CNR2 in a 3D semiconductor memory device according to some embodiments of the inventive concepts. Figures 11A-11C may correspond to a plan view showing an end portion on a connection region CNR1 or CNR2 in a block structure BLS1 to BLS6 in Figure 10A or Figure 10B

[0079] Referring to Figures 11A-11C When viewed in a plan view, the block separation region SR1 can have a step shape. The lowermost lower electrode 10eb of the j-th block structure BLSj can have a protrusion 10ebp protruding in the second direction Y on the connection region CNR1 or CNR2 in the plan view. The first upper electrode 30e1 of the j-th block structure BLSj can have a fourth width W4 parallel to the second direction Y, and the protrusion 10ebp can have a fifth width W5 parallel to the second direction Y. The fifth width W5 can be substantially equal to the fourth width W4, can correspond to about twice the fourth width W4, or can correspond to about three times the fourth width W4. In other words, the fifth width W5 can be in a range of one to three times the fourth width W4. When viewed in a plan view, the lowermost lower electrode 10eb of the k-th block structure BLSk adjacent to the j-th block structure BLSj can be recessed by a width of the protrusion 10ebp in the second direction Y. Figure 11A Figure 11B Figure 11C

[0080] In Figures 11A-11C , because the number of the first upper electrodes 30e1 (i.e., the SSL number) in the uppermost layer located in one block structure BLSj is 4, the fifth width W5 can be in a range of one to three times the fourth width W4. When the SSL number is n (a natural number) greater than 4, the fifth width W5 can be in a range of one to n-1 times the fourth width W4.

[0081] Optionally, referring to Figure 11D ​​​​​The lowermost lower electrode 10eb of the jth block structure BLSj can have a first protrusion 10ebp1 protruding in the second direction Y and a second protrusion 10ebp2 protruding in a direction opposite to the second direction Y on the connection region CNR1 or CNR2 when viewed in a plan view. Each of the first protrusion 10ebp1 and the second protrusion 10ebp2 can have a fifth width W5. The fifth width W5 can be substantially equal to the fourth width W4. Each of the lowermost lower electrodes 10eb of the ith block structure BLSi and the kth block structure BLSk adjacent to the jth block structure BLSj can be recessed in the second direction Y or in the direction opposite to the second direction Y when viewed in a plan view due to the first protrusion 10ebp1 and the second protrusion 10ebp2.

[0082] In Figures 11A-11D , the planar shape of the block structures BLSi, BLSj, and BLSk can be the same / similar to that of the lowermost lower electrode 10eb. In other words, the shapes of the protrusions 10ebp, 10ebp1, and 10ebp2 can be projected to the entire portions of the block structures BLSi, BLSj, and BLSk. Also, Figures 11A-11D the shape of the block separation region SR1 of Figures 4-9 may be projected to the entire portions of the block structures BLSi, BLSj, and BLSk. Other structures and / or components can be the same / similar to those described with reference to

[0083] Figure 12A and Figure 12B are plan views illustrating end portions in a 3D semiconductor memory device according to some embodiments of the inventive concept.

[0084] With reference to Figure 12A and Figure 12B , the lowermost lower electrode 10eb of the jth block structure BLSj can include a first electrode portion 10eb1, a second electrode portion 10eb2, and a third electrode portion 10eb3 arranged along the first direction X. The first electrode portion 10eb1 can be adjacent to the cell array region CAR and can have a first width W1. The third electrode portion 10eb3 can be spaced apart from the first electrode portion 10eb1 and can be adjacent to an end portion of the connection region CNR1 or CNR2. The third electrode portion 10eb3 can have a second width W2. The second electrode portion 10eb2 can be disposed between the first electrode portion 10eb1 and the third electrode portion 10eb3 to connect the first electrode portion 10eb1 and the third electrode portion 10eb3. The second electrode portion 10eb2 can have a sloped sidewall 10ebs as with Figure 12A , when viewed in a plan view. Alternatively, the second electrode portion 10eb2 can have a straight sidewall 10ebs as with Figure 12BThe sidewall 10ebs also has a stepped shape. Thus, the block separation region SR1 can have a diagonal shape or a stepped shape when viewed in a plan view.

[0085] In Figure 12A and Figure 12B , the planar shapes of the block structures BLSj and BLSk can be the same / similar to the planar shape of the lowermost lower electrode 10eb. In other words, the shape of the sidewall 10ebs of the second electrode portion 10eb2 can be projected to the entire portion of the block structure BLSj. Also, Figure 12A and Figure 12B , the shape of the block separation region SR1 can be projected to the entire portion of the block structures BLSj and BLSk. Other structures and / or components can be the same / similar to those described with reference to Figures 4-9 .

[0086] According to embodiments of the inventive concept, the block separation regions that separate the block structures can not be in contact with each other but can be spaced apart from each other, and thus the depth of recess can be easily controlled in an etching process for forming the block separation regions.

[0087] Also, the width of the block structure can be changed on the connection region. Thus, the area of the pad region can be increased, thereby preventing bridging between the contact plugs and increasing the degree of freedom of the interconnection lines. As a result, the reliability of the 3D semiconductor memory device can be improved.

[0088] Also, the number of the stepped division patterns can be increased to be more than the number of the string selection lines. Also, the block structures can be disposed to be engaged or joined with each other. Thus, the total area of the 3D semiconductor memory device can be reduced, thereby improving the integration density of the 3D semiconductor memory device.

[0089] Although the inventive concept has been described with reference to example embodiments, it will be apparent to those skilled in the art that various changes and modifications can be made thereto without departing from the spirit and scope of the inventive concept. It is therefore intended that such changes and modifications be included within the scope of the inventive concept, as defined by the appended claims and their equivalents. Thus, it is to be understood that the above embodiments are illustrative, but not restrictive, and the scope of the inventive concept should be given the broadest interpretation of the appended claims and their equivalents.

Claims

1. A three-dimensional semiconductor memory device, comprising: a substrate including a first connection region and a second connection region in a first direction and a cell array region between the first connection region and the second connection region; and a first block structure on the substrate, wherein the first block structure has a first width on the cell array region, wherein the first block structure has a third width on the first connection region, wherein the first block structure has a second width on the second connection region, wherein the first width, the second width, and the third width are parallel to a second direction that intersects the first direction, wherein the first width is smaller than the second width and larger than the third width, and wherein the first block structure includes a first contact plug at an end of the first block structure having the second width on the second connection region and a second contact plug at an end of the first block structure having the third width on the first connection region.

2. The three-dimensional semiconductor memory device of claim 1, further comprising: a second block structure and a third block structure spaced apart from the first block structure in the second direction; a first block partition separating the first block structure and the second block structure from each other; and a second block partition separating the second block structure and the third block structure from each other, wherein the first block partition is spaced apart from the second block partition.

3. The three-dimensional semiconductor memory device of claim 1, further comprising: a second block structure spaced apart from the first block structure in the second direction, wherein the second block structure is symmetrical to the first block structure or has a shape of the first block structure rotated 180 degrees in a plan view. an end side wall of the first block structure is aligned with an end side wall of the second block structure on the first connection region when viewed in a plan view, and wherein another end side wall of the first block structure is aligned with another end side wall of the second block structure on the second connection region when viewed in a plan view.

4. The three-dimensional semiconductor memory device of claim 3, wherein, 5. The three-dimensional semiconductor memory device of claim 1, further comprising: a second block structure spaced apart from the first block structure in the second direction, wherein the second block structure has the first width on the cell array region, wherein the second block structure has the second width on the first connection region, and wherein the second block structure has the third width on the second connection region. a sum of the second width and the third width corresponds to twice the first width. The first block structure includes:

6. The three-dimensional semiconductor memory device of claim 1, wherein, a lower stack structure including a plurality of lower electrodes vertically stacked on the substrate; and 7. The three-dimensional semiconductor memory device of claim 1, wherein, an intermediate stack structure including a plurality of intermediate electrodes vertically stacked on the lower stack structure, wherein the intermediate stack structure exposes the lower stack structure, wherein the intermediate stack structures are offset from each other in the first direction. The intermediate electrodes in each intermediate stack structure include side walls exposed in the first direction and vertically aligned with each other. The first block structure further includes: an upper stack structure on the plurality of intermediate stack structures, 8. The three-dimensional semiconductor memory device of claim 7, wherein, wherein the upper stack structure includes: n upper electrodes spaced apart from each other in the second direction and at a same height, 9. The three-dimensional semiconductor memory device of claim 7, wherein, wherein the n upper electrodes are electrically connected to the plurality of intermediate electrodes in the first block structure. ​ wherein end portions of the intermediate electrodes constituting one of the intermediate stack structures form a stepped structure in the second direction, and wherein the number of the intermediate electrodes forming the stepped structure is greater than n and less than 2n.

10. The three-dimensional semiconductor memory device of claim 7, wherein, the lower electrodes constituting the lower stack structure form a stepped shape on the second connection region, wherein the lowermost one of the lower electrodes is exposed on both the first connection region and the second connection region, and wherein the first contact plug and the second contact plug are in contact with the lowermost one of the lower electrodes on the second connection region and the first connection region, respectively.

11. The three-dimensional semiconductor memory device of claim 1, wherein, the first block structure includes a first lower electrode at a lowest position, wherein the first lower electrode on the second connection region includes a first electrode portion adjacent to the cell array region, a third electrode portion spaced apart from the first electrode portion, and a second electrode portion connecting the first electrode portion and the third electrode portion, and wherein the first electrode portion has a first width and the third electrode portion has a second width.

12. The three-dimensional semiconductor memory device of claim 11, wherein, a sidewall of the second electrode portion has a diagonal profile or a stepped profile when viewed in a plan view.

13. The three-dimensional semiconductor memory device of claim 7, further comprising: a dummy stack structure on the intermediate stack structure on the second connection region, wherein the dummy stack structure includes dummy electrodes stacked vertically, and wherein the dummy electrodes form a stepped structure.

14. The three-dimensional semiconductor memory device of claim 1, wherein, the first block structure has a first length parallel to the first direction on the first connection region, wherein the first block structure has a second length parallel to the first direction on the second connection region, and wherein the first length is equal to the second length.

15. A three-dimensional semiconductor memory device, comprising: a base including a first connection region and a second connection region arranged along a first direction intersecting a second direction, and a cell array region between the first connection region and the second connection region, a first block structure, a second block structure, and a third block structure on the base and spaced apart from each other in the second direction; a first block separation region separating the first block structure and the second block structure from each other; and a second block separation region separating the second block structure and the third block structure from each other, wherein the first block separation region is spaced apart from the second block separation region, wherein at least one of the first block separation region and the second block separation region has a stepped shape when viewed in a plan view, wherein the second block structure has a first width on the cell array region, a second width on the first connection region, and a third width on the second connection region, wherein the first width, the second width, and the third width are parallel to the second direction, the first width is smaller than the second width and greater than the third width, and wherein the second block structure includes a first contact plug at an end portion of the second block structure having the second width on the first connection region and a second contact plug at an end portion of the second block structure having the third width on the second connection region.

16. The three-dimensional semiconductor memory device of claim 15, wherein, the first block structure or the third block structure is symmetrical to the second block structure or has a shape of the second block structure rotated 180 degrees in a plan view.

17. A three-dimensional semiconductor memory device, comprising: a substrate including a first connection region and a second connection region in a first direction and a cell array region between the first connection region and the second connection region; and a first block structure provided on the substrate, wherein the first block structure includes: a first lower electrode located at a lowest position; and a first upper electrode located at a highest position, wherein the first upper electrode is spaced apart from each other in a second direction crossing the first direction and has a linear shape extending in the first direction, wherein each of the first upper electrode has a first width parallel to the second direction, wherein the first lower electrode includes a protrusion protruding laterally from a sidewall of an outermost one of the first upper electrode on one of the first connection region and the second connection region, wherein the protrusion has a second width parallel to the second direction, wherein the second width is in a range of one to three times the first width, wherein the first block structure has a third width on the cell array region, wherein the first block structure has a fourth width on the one of the first connection region and the second connection region, wherein the first block structure has a fifth width on the other of the first connection region and the second connection region, wherein the third width, the fourth width, and the fifth width are parallel to the second direction, wherein the third width is greater than the fifth width and smaller than the fourth width, and wherein the first block structure includes a first contact plug at an end portion of the first block structure having the fourth width on the one of the first connection region and the second connection region and a second contact plug at an end portion of the first block structure having the fifth width on the other of the first connection region and the second connection region.

18. The three-dimensional semiconductor memory device of claim 17, wherein, the first lower electrode is exposed on both of the first connection region and the second connection region, and wherein the first contact plug and the second contact plug are in contact with the first lower electrode on the second connection region and the first connection region, respectively.

19. The three-dimensional semiconductor memory device of claim 17, wherein, the first block structure includes: an upper stack structure; and a lower stack structure located below the upper stack structure, wherein the upper stack structure includes: the first upper electrode; and a second upper electrode located below the first upper electrode, wherein the lower stack structure includes: the first lower electrode; and a second lower electrode stacked on the first lower electrode, wherein end portions of the first lower electrode and the second lower electrode constitute a stepped shape in the first direction, and wherein a sum of the number of the first lower electrode and the second lower electrode is greater than the number of the first upper electrode and smaller than twice the number of the first upper electrode.

20. The three-dimensional semiconductor memory device of claim 17, further comprising: a second block structure spaced apart from the first block structure in the second direction, wherein the second block structure is symmetrical to the first block structure or has a shape of the first block structure rotated by 180 degrees in a plan view.

21. A three-dimensional semiconductor memory device, comprising: a substrate including a first connection region and a second connection region in a first direction and a cell array region between the first connection region and the second connection region; and a first block structure and a second block structure are located on the substrate and are spaced apart from each other by a block separation region in a second direction intersecting the first direction, wherein the block separation region has a step shape, a diagonal shape, or a stair shape on one of the first connection region and the second connection region when viewed in a plan view, wherein the first block structure has a first width on the cell array region, a second width on the first connection region, and a third width on the second connection region, wherein the first width, the second width, and the third width are parallel to the second direction, the first width is smaller than the second width and larger than the third width, and wherein the first block structure includes a first contact plug at an end portion of the first block structure having the second width on the first connection region and a second contact plug at an end portion of the first block structure having the third width on the second connection region.

22. The three-dimensional semiconductor memory device of claim 21, wherein, the first block structure includes first lower electrodes located at the lowest positions and first upper electrodes located at the highest positions, wherein the first upper electrodes are spaced apart from each other in the second direction and have a linear shape extending in the first direction, wherein each of the first upper electrodes has a fourth width parallel to the second direction, wherein the first lower electrodes include a protrusion protruding laterally from a sidewall of an outermost one of the first upper electrodes on the one of the first connection region and the second connection region, wherein the protrusion has a fifth width parallel to the second direction, and wherein the fifth width is in a range of one to three times the fourth width.

Images