Enhanced passivation and adhesion of metal linings by zinc doping

Abstract

A method includes: depositing a barrier layer on a dielectric layer to prevent oxidation of a metal layer to be deposited by electroplating due to the presence of oxides in the dielectric layer; and depositing a doped liner layer on the barrier layer to combine with the metal layer to be deposited on the liner layer by the electroplating. When the surface of the liner layer is exposed to air before the electroplating, the dopant forms a protective passivation layer on the surface and dissolves during the electroplating so that the metal layer deposited on the liner layer by the electroplating combines with the liner layer. The dopant reacts with the dielectric layer and forms a compound layer between the barrier layer and the dielectric layer. The compound layer prevents oxidation of the barrier layer and the liner layer due to the presence of oxides in the dielectric layer, and adheres the barrier layer to the dielectric layer.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to U.S. Patent Application No. 16 / 000,457, filed on June 5, 2018. The entire disclosure of the above-referenced application is incorporated herein by reference. Technical Field

[0003] The present disclosure relates generally to electroplated substrates, and more particularly to electroplated substrates equipped with metal liner passivation and adhesion enhancement provided by zinc doping. Background Art

[0004] The background description provided here is for the purpose of generally presenting the context of the present disclosure. The work of the presently designated inventors is neither explicitly nor implicitly admitted to be prior art against the present disclosure to the extent that it is described in this background section and in aspects of the specification that were not determined to be prior art at the time the application was filed.

[0005] Electrochemical deposition (ECD), also known as plating or electroplating, is used to deposit metal on a substrate. For example, ECD is used to deposit metal on interconnect structures in IC packaging. Examples of interconnect structures include bumps, pillars, through silicon vias (TSVs), and redistribution layers (RDLs). ECD is also used in multi-chip packaging and in an interconnect process commonly referred to as wafer-level packaging (WLP). Summary of the invention

[0006] A method includes depositing a barrier layer on a dielectric layer to prevent oxidation of a metal layer to be deposited by electroplating due to the presence of oxides in the dielectric layer. The method also includes depositing a liner layer on the barrier layer to combine with the metal layer to be deposited on the liner layer by the electroplating. The liner layer is doped with a dopant. When the surface of the liner layer is exposed to air before the electroplating, the dopant forms a passivation layer on the surface on which the metal layer will be deposited. When the liner layer is exposed to air before the electroplating, the passivation layer further prevents oxidation of the liner layer. The passivation layer dissolves during the electroplating so that the metal layer deposited on the liner layer by the electroplating combines with the liner layer. The dopant reacts with the dielectric layer and forms a compound layer between the barrier layer and the dielectric layer. The compound layer prevents oxidation of the barrier layer and the liner layer due to the oxides present in the dielectric layer. The compound layer adheres the barrier layer to the dielectric layer.

[0007] In other features, the method further comprises electroplating the metal layer on the liner layer and performing chemical mechanical planarization on the metal layer.

[0008] In other features, the method further comprises performing chemical mechanical planarization on the metal layer.

[0009] In other features, the dopant includes an element that is more electronegative than elements used to form the liner layer and the metal layer.

[0010] In other features, the method further includes co-depositing the liner layer and the dopant on the barrier layer.

[0011] In other features, the method further comprises depositing the dopant on the liner layer.

[0012] In other features, the dielectric layer includes a material having a low dielectric constant, the compound includes a substance formed from a combination of the material and the dopant, and the passivation layer includes an oxide of the dopant.

[0013] In other features, the dielectric layer includes SiO2, the compound includes a substance formed from a combination of SiO2 and the dopant, and the passivation layer includes an oxide of the dopant.

[0014] In other features, the method further comprises: forming the barrier layer using TaN; forming the liner layer using Ru, Co, or Mo; doping the liner layer using Zn, Mn, In, Sn, or Al; and forming the metal layer using Cu.

[0015] In other features, the method further comprises performing a thermal treatment on the liner layer, the barrier layer, and the dielectric layer prior to the electroplating.

[0016] In yet other features, a method includes: providing a dielectric layer; and depositing a liner layer on the dielectric layer to combine with a metal layer to be deposited on the liner layer by electroplating. The liner layer is doped with a dopant. When the liner layer is exposed to air before the electroplating, the dopant forms a passivation layer on the surface of the liner layer on which the metal layer will be deposited. The passivation layer further prevents oxidation of the liner layer due to exposure of the liner layer to air before the electroplating. The passivation layer dissolves during the electroplating so that the metal layer deposited on the liner layer by the electroplating combines with the liner layer. The dopant reacts with the dielectric layer and forms a compound layer between the liner layer and the dielectric layer. The compound layer prevents oxidation of the liner layer and the metal layer due to oxides present in the dielectric layer. The compound layer adheres the liner layer to the dielectric layer.

[0017] In other features, the method further comprises electroplating the metal layer on the liner layer and performing chemical mechanical planarization on the metal layer.

[0018] In other features, the method further comprises performing chemical mechanical planarization on the metal layer.

[0019] In other features, the dopant includes an element that is more electronegative than elements used to form the liner layer and the metal layer.

[0020] In other features, the method further includes co-depositing the liner layer and the dopant on the dielectric layer.

[0021] In other features, the method further comprises depositing the dopant on the liner layer.

[0022] In other features, the dielectric layer includes a material having a low dielectric constant, the compound includes a substance formed from a combination of the material and the dopant, and the passivation layer includes an oxide of the dopant.

[0023] In other features, the dielectric layer includes SiO2, the compound includes a substance formed from a combination of SiO2 and the dopant, and the passivation layer includes an oxide of the dopant.

[0024] In other features, the method further includes: forming the liner layer using Ru, Co, or Mo; doping the liner layer using Zn, Mn, In, Sn, or Al; and forming the metal layer using Cu.

[0025] In other features, the method further comprises performing a thermal treatment on the liner layer and the dielectric layer prior to the electroplating.

[0026] In still other features, the substrate processing system includes a chamber for processing a semiconductor substrate and a substrate support arranged in the chamber to support the semiconductor substrate during processing. The substrate processing system also includes a controller coupled to the chamber. The controller is configured to deposit a barrier layer on the semiconductor substrate to prevent oxidation of a metal layer to be deposited by electroplating due to the presence of oxides in the semiconductor substrate. The controller is configured to deposit a lining layer on the barrier layer to combine with the metal layer to be deposited on the lining layer by the electroplating. The lining layer is doped with a dopant. When the surface of the lining layer is exposed to air before the electroplating, the dopant forms a passivation layer on the surface on which the metal layer will be deposited. When the lining layer is exposed to air before the electroplating, the passivation layer further prevents oxidation of the lining layer. The passivation layer dissolves during the electroplating so that the metal layer deposited on the lining layer by the electroplating combines with the lining layer. The dopant reacts with the semiconductor substrate and forms a compound layer between the barrier layer and the semiconductor substrate. The compound layer prevents oxidation of the barrier layer and the liner layer due to the oxide present in the semiconductor substrate. The compound layer adheres the barrier layer to the semiconductor substrate.

[0027] In other features, the dopant includes an element that is more electronegative than elements used to form the liner layer and the metal layer.

[0028] In other features, the controller is configured to co-deposit the liner layer and the dopant on the barrier layer.

[0029] In other features, the controller is configured to deposit the dopant on the liner layer.

[0030] In other features, the semiconductor substrate includes a material having a low dielectric constant, the compound includes a substance formed from a combination of the material and the dopant, and the passivation layer includes an oxide of the dopant.

[0031] In other features, the semiconductor substrate includes SiO2, the compound includes a substance formed from a combination of SiO2 and the dopant, and the passivation layer includes an oxide of the dopant.

[0032] In other features, the liner layer comprises Ru, Co, or Mo; the dopant comprises Zn, Mn, In, Sn, or Al; the barrier layer comprises TaN; and the metal layer comprises Cu.

[0033] In yet other features, the substrate processing system includes a chamber for processing a semiconductor substrate and a substrate support disposed in the chamber to support the semiconductor substrate during processing. The substrate processing system also includes a controller coupled to the chamber. The controller is configured to deposit a lining layer on the semiconductor substrate to combine with a metal layer to be deposited on the lining layer by electroplating. The lining layer is doped with a dopant. When the lining layer is exposed to air before the electroplating, the dopant forms a passivation layer on the surface of the lining layer on which the metal layer will be deposited. The passivation layer further prevents oxidation of the lining layer due to exposure of the lining layer to air before the electroplating. The passivation layer dissolves during the electroplating so that the metal layer deposited on the lining layer by the electroplating combines with the lining layer. The dopant reacts with the semiconductor substrate and forms a compound layer between the lining layer and the semiconductor substrate. The compound layer prevents oxidation of the lining layer and the metal layer deposited on the lining layer due to oxides present in the semiconductor substrate. The compound layer adheres the lining layer to the semiconductor substrate.

[0034] In other features, the dopant includes an element that is more electronegative than elements used to form the liner layer and the metal layer.

[0035] In other features, the controller is configured to co-deposit the liner layer and the dopant on the semiconductor substrate.

[0036] In other features, the controller is configured to deposit the dopant on the liner layer.

[0037] In other features, the semiconductor substrate includes a material having a low dielectric constant, the compound includes a substance formed from a combination of the material and the dopant, and the passivation layer includes an oxide of the dopant.

[0038] In other features, the semiconductor substrate includes SiO2, the compound includes a substance formed from a combination of SiO2 and the dopant, and the passivation layer includes an oxide of the dopant.

[0039] In other features, the liner layer comprises Ru, Co, or Mo; the dopant comprises Zn, Mn, In, Sn, or Al; and the metal layer comprises Cu.

[0040] Further scope of applicability of the present disclosure will become apparent from the detailed description, claims and drawings.The detailed description and specific examples are intended for purposes of illustration only and are not intended to limit the scope of the disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] The present disclosure will be more fully understood from the detailed description and accompanying drawings, in which:

[0042] Figure 1A and Figure 1B An example of a component including an undoped liner layer and a barrier layer deposited on a substrate that may be electroplated with a metal layer is shown;

[0043] FIG. 2A to FIG. 2F An example of a component including a doped liner layer and a barrier layer deposited on a substrate that may be electroplated with a metal layer is shown;

[0044] FIG. 3A to FIG. 3F Examples of components including a doped liner layer deposited on a substrate that may be electroplated with a metal layer and without a barrier layer;

[0045] Figure 4A shows the method for forming Figures 2A-2F A flow chart of a method of a component including a doped liner layer and a barrier layer deposited on a substrate is shown;

[0046] Figure 4B shows the method for forming Figures 3A-3F A flow chart of a method for a component including a doped liner layer deposited on a substrate and without a barrier layer is shown;

[0047] Figure 5 An example of a substrate processing system including a plurality of processing modules is shown, wherein the processing modules can be used to deposit a substrate such as Figures 2A-3F the various lining and barrier layers shown;

[0048] Figure 6 Shows Figure 5 An example of a deposition chamber of a substrate processing system, which can be used to deposit a substrate such as Figures 2A-3F The various lining and barrier layers shown; and

[0049] Figure 7 An example of an electroplating system is shown, which can be used in Figures 2A-3F Metal layers are plated on the various components shown.

[0050] Among the drawings, reference numerals may be repeated to identify similar and / or identical elements. DETAILED DESCRIPTION

[0051] In the present disclosure, the following elements and symbols are used: copper (Cu), ruthenium (Ru), cobalt (Co), molybdenum (Mo), zinc (Zn), manganese (Mn), indium (In), tin (Stannum) or tin (Tin) (Sn), aluminum (Al), silicon (Si), tantalum (Ta), oxygen (O) and nitrogen (N).

[0052] The present disclosure relates to electrochemical techniques for doping liner materials (e.g., Ru, Co, or Mo) used in electroplating substrates, where the substrate may include a material with a low dielectric constant (a low-k material or dielectric; e.g., SiO2). The liner material is doped with an electronegative element X (e.g., Zn, Mn, In, Sn, or Al) that is more electronegative than the liner material and the metal (e.g., Cu) to be deposited on the liner material by electroplating. The doping element X has the following dual advantages.

[0053] First, the dopant element can be driven to the interface between the liner and the substrate (dielectric) using an appropriate thermal treatment process (e.g., annealing can be used, although some migration of the dopant element from the liner to the dielectric can be observed at room temperature). The dopant element reacts with the dielectric material to form a compound layer between the liner metal (e.g., Ru, Co, or Mo) layer and the substrate (i.e., the dielectric layer). The compound includes a substance formed by a combination of a dielectric material and a dopant. For example, if the dielectric material includes SiO2, the compound can be XSi y O Z The compound may be in the form of a silicate, silicide or oxide of the doped element X. If a low-k dielectric material other than SiO2 is used as the substrate, the compound may also include a nitride or a carbide. The compound layer formed between the liner metal (e.g., Ru, Co or Mo) layer and the dielectric layer provides adhesion. Secondly, when exposed to air, the doping element reacts with oxygen in the air and forms a sacrificial passivation layer on the liner material. The passivation layer protects the liner material (especially Co, which has a high affinity for oxygen) from queue time-dependent oxidation.

[0054] Furthermore, the technology enables a barrier-free metallization scheme, thereby providing superior adhesion and barrier properties for future technology nodes. Additionally, the technology prevents oxidation of the liner (and barrier) by forming a passivation layer. This is advantageous not only from an integration perspective, but also from a reliability perspective, as barrier oxidation through an extremely thin liner can degrade reliability. Thus, the technology eliminates the need to store substrates in an expensive vacuum environment, which is otherwise necessary to prevent oxidation of the liner (and barrier) while the substrate is waiting in line prior to electroplating.

[0055] Cu is widely used as an interconnect material in the manufacture of advanced semiconductor devices. Currently, the Cu metallization scheme involves depositing a Ru or Co liner on top of a TaN barrier layer stacked on a dielectric substrate. Cu is then deposited on the liner by electroplating. The TaN layer acts as a barrier to prevent Cu from diffusing through the liner into the dielectric layer, and the Ru or Co layer acts as a liner to enable Cu deposition by providing a lower resistance than TaN.

[0056] As process node dimensions continue to shrink, the barrier / liner layers need to be scaled to maximize the cross-sectional area of ​​copper. In future technology nodes, the thickness of the Co (or Ru) liner layer is about 1-2nm. At this thickness, barrier oxidation caused by oxygen diffusion through the liner can be problematic. For example, oxidation of a TaN barrier layer through an approximately 5nm Co liner (formed by PVD) can occur in an air interruption of about 4 hours (a typical queue time in a semiconductor manufacturing system). This barrier oxidation is detrimental to interconnect reliability.

[0057] The present disclosure solves the barrier layer oxidation problem by introducing doping elements into the liner layer. The method involves introducing Zn (or Mn, In, Sn or Al) dopants into the liner material (Co or Ru). When exposed to air, due to the high electronegativity of the dopant and the diffusivity of the dopant, Zn (or Mn, In, Sn or Al) diffuses to the air interface and forms a passivation oxide film on the liner material. The passivation oxide film prevents oxygen from diffusing through the liner material and protects the barrier layer from being oxidized.

[0058] Furthermore, this passivating oxide film preserves the metallic nature of the liner, which benefits in the subsequent electroplating step, where a pre-cleaning step is usually performed prior to plating to reduce the native metal oxide. It is worth noting that since Co has a high affinity for oxygen, the reduction of CoO is not trivial.

[0059] In addition, this doping technique can also realize a barrier-free metallization method. Specifically, in a barrier-free metallization method, a doped liner can be deposited directly on a dielectric substrate. The direct deposition of the doped liner on a dielectric substrate can play a dual role. First, the Zn (or Mn, In, Sn or Al) in the liner can chemically react with the dielectric material to form an adhesion layer. In the absence of a TaN barrier layer, the adhesion layer can additionally provide barrier properties and can be used during chemical mechanical planarization (CMP or simple polishing). Secondly, the Zn (or Mn, In, Sn or Al) can passivate the liner as described above.

[0060] Thus, the present invention involves doping electronegative elements directly onto liner materials (Ru, Co). Doping can be achieved by co-deposition using atomic layer deposition (ALD) during the liner deposition process, or by an electrochemical (wet) process after liner deposition. The doping element (i.e., dopant) provides protection from oxidation of the liner and barrier layers. In addition, the formation of an adhesion layer based on Zn (or Mn, In, Sn, or Al) can enable barrier-free metallization for future technology nodes. These and other features of the present disclosure are described in detail below.

[0061] The present disclosure is organized as follows. First, an overview of the present disclosure is presented. Thereafter, reference is made to Figure 1A-1B An example of a structure (component) including an undoped liner layer and a barrier layer is described. Figures 2A-2F An example of a structure including a doped liner layer and a barrier layer is described. Figures 3A-3F An example of a structure including a doped liner layer without a barrier layer is described. Figures 4A-4B Methods of forming structures having a doped liner layer and either with or without a barrier layer are described. Figure 5 An example of a substrate processing system including multiple processing modules that can be used to form various structures of the present disclosure is described. Figure 6 Examples of deposition chambers that can be used to deposit various liner layers and barrier layers of the present disclosure are described. Figure 7 Examples of electroplating systems that may be used to electroplate metal layers on various structures of the present disclosure are described.

[0062] In short, according to the present disclosure, a Co, Ru or Mo liner can be doped with Zn (or Mn, In, Sn or Al) using a wet or dry process. Zn prevents oxidation of the Co liner and makes the Co liner compatible with electroplating by retaining the electrical properties of the Co liner. Zn oxidizes, passivates the liner with a ZnO layer, and prevents further oxidation of the target metal (i.e., the liner). During electroplating, the ZnO passivation layer formed on the liner dissolves in the electrolyte used, and the electroplated metal (Cu) forms a strong, low-resistance metal-metal bond with the liner compared to the weak bond that Co would otherwise form if oxidized without the presence of Zn.

[0063] Zn also diffuses through the liner and reacts with the dielectric material in the substrate, forming a compound layer between the liner and the dielectric. The compound layer serves two purposes. First, the compound layer improves the adhesion between the liner and the dielectric layer; second, the compound layer prevents Cu ions (deposited by electroplating) from drifting into the dielectric layer. That is, the compound layer performs the function of a barrier layer and eliminates the need to deposit an explicit barrier layer such as TaN on the dielectric layer. Eliminating the explicit barrier layer by doping the liner and depositing the doped liner directly on the dielectric layer provides a barrier-free electroplating method, which is advantageous as process node dimensions continue to shrink.

[0064] The purpose of the barrier layer is to prevent the metal (e.g., Cu) deposited by electroplating on the dielectric layer from being oxidized. Typically, without a barrier layer, Cu oxidizes at the Cu-dielectric interface. When a bias is applied, the Cu ions drift into the dielectric layer, causing leakage current. To prevent this, a barrier layer (e.g., TaN) is usually added between the Cu and the dielectric layer to prevent Cu from oxidizing at the Cu-dielectric interface and causing leakage current when a bias is applied.

[0065] However, such a barrier layer is resistive and also takes up space, which is a problem as the size of process nodes continues to shrink as technology advances. In contrast, if the liner is doped with an electronegative element such as Zn (or Mn, In, Sn, or Al), the doping element can provide protection on both sides of the liner. On the liner-metal interface side, the doping element provides current protection to the liner (i.e., prevents the liner from oxidizing) by forming a sacrificial passivation layer on the liner. Additionally, on the liner-dielectric interface, the doping element leaks or migrates (diffuses) through the liner, reacts with the dielectric layer, and forms a compound layer, thereby providing adhesion between the liner and the dielectric layer and also eliminating the problem of leakage current.

[0066] In addition, if an explicit barrier layer is used between the liner and the dielectric layer, the doping elements in the liner can also protect the barrier layer from being oxidized. Specifically, due to the formation of a compound layer, the doping elements protect the barrier layer from being oxidized at the barrier layer-dielectric interface. In addition, the sacrificial passivation layer formed on the liner prevents oxygen from diffusing through the liner into the barrier layer and oxidizing the barrier layer.

[0067] Several doping techniques can be used to dope the liner. For example, a thin Zn (or Mn, In, Sn, or Al) layer can be deposited on a Ru (or Mo) liner. Alternatively, a single-layer doped liner can be formed by co-depositing a mixture of Ru (or Mo) and Zn (or Mn, In, Sn, or Al). Alternatively, a single-layer doped liner can be formed by co-depositing a mixture of Co and Zn (or Mn, In, Sn, or Al). Since Co has a higher affinity for oxygen than Ru (or Mo), Co may be more heavily doped with Zn (or Mn, In, Sn, or Al) than Ru (or Mo). By lightly doping the liner with a target metal (e.g., Co, Ru, or Mo), the metal can be electroplated on one side of the liner and adhere to the dielectric layer on the other side of the liner (otherwise, these metals will not adhere well to the dielectric layer regardless of whether a barrier layer is used). These and other features of the present disclosure can now be described in more detail below.

[0068] Figure 1A and 1B An example of a structure or component that is plated without using the doping scheme of the present disclosure is shown. Figure 1A In the embodiment, the component 100 to be plated includes a dielectric layer 102, a barrier layer 104 and a liner layer 106. The dielectric layer 102 includes a substrate having a low-k dielectric material (eg, a SiO2 substrate). The barrier layer 104 includes a TaN layer. The liner layer 106 includes a Ru or Co layer.

[0069] First, a barrier layer 104 is deposited on the dielectric layer 102 using a suitable deposition process. Subsequently, a liner layer 106 is deposited on the barrier layer 104 using a suitable deposition process. The stack of dielectric layer 102, barrier layer 104, and liner layer 106 is then subjected to a suitable heat treatment (e.g., annealing) to form component 100.

[0070] exist Figure 1B In the present invention, a metal layer (e.g., Cu) 108 is deposited on a liner layer 106 of a component 100 using electroplating. The barrier layer 104 prevents Cu from diffusing through the liner layer 106 into the dielectric layer 102. The liner layer 106 enables Cu deposition by providing a lower resistance than the barrier layer 104. However, since the liner layer 106 is not doped with Zn (or, Mn, In, Sn, or Al), as explained above, if the component 100 is exposed to air before electroplating, the liner layer 106 tends to oxidize. In addition, as the thickness of the liner layer 106 decreases, the barrier layer 104 becomes susceptible to oxidation, which is detrimental to interconnect reliability as described above. To prevent oxidation, the component 100 is stored in an expensive vacuum environment while it is waiting in line before electroplating.

[0071] Figures 2A-2F A first example of a structure or component plated using the doping scheme of the present disclosure is shown. In the first example, the component also includes a barrier layer.

[0072] exist Figure 2A In the embodiment, the component 200 to be plated includes a dielectric layer 102, a barrier layer 104 and a liner layer 202. The dielectric layer 102 includes a substrate (e.g., a SiO2 substrate) containing a low-k dielectric material. The barrier layer 104 includes a TaN layer. The liner layer 202 includes a Ru layer, a Co layer, or a Mo layer doped with Zn (or Mn, In, Sn, or Al).

[0073] First, a barrier layer 104 is deposited on the dielectric layer 102 using a suitable deposition process. Subsequently, a liner layer 202 is deposited on the barrier layer 104 using a suitable deposition process (e.g., ALD). The stack of the dielectric layer 102, the barrier layer 104, and the liner layer 202 is then subjected to a suitable heat treatment (e.g., annealing) to form the component 200.

[0074] exist Figure 2BIn the embodiment of the present invention, upon annealing or exposure to room temperature, a thin compound layer of Zn (or Mn, In, Sn, or Al) and a dielectric material (e.g., a silicate layer if SiO2 is used as the dielectric layer 102) is formed between the dielectric layer 102 and the barrier layer 104. The compound layer is shown at 204. The compound layer 204 prevents the barrier layer 104 from oxidizing at the interface of the barrier layer 104 and the dielectric layer 102. The compound layer 204 also provides adhesion between the barrier layer 104 and the liner layer 202 and the dielectric layer 102, which helps during the CMP or polishing process performed after electroplating.

[0075] exist Figure 2C In the embodiment of the present invention, when the component 200 is waiting for electroplating and is optionally exposed to air (vacuum environment is not required), a thin passivation layer (e.g., passivation layer or oxide layer 206) of Zn (or Mn, In, Sn or Al) oxide is formed on top of the liner layer 202. The oxide layer 206 protects the liner material from further oxidation due to exposure to air. The oxide layer 206 also prevents oxygen from diffusing through the liner layer 202 into the barrier layer 104 and protects the barrier layer 104 from being oxidized.

[0076] exist Figure 2D In the embodiment of the present invention, a metal layer (e.g., Cu) 108 is deposited on the liner layer 202 of the component 200 using electroplating. During the electroplating, the oxide layer 206 is dissolved in the electrolyte used. The metal layer 108 forms a strong metal-metal (Cu-Ru, Cu-Co or Cu-Mo) bond with the liner layer 202. The barrier layer 104 prevents the Cu ions from diffusing through the liner layer 202 into the dielectric layer 102.

[0077] Figure 2E and 2F Two different doping methods are shown, which can be used to deposit a liner layer 202 containing the dopant element Zn (or Mn, In, Sn or Al) on the barrier layer 104. Figure 2E In the embodiment, when Ru (or Mo) is used to form the liner layer 202, the undoped Ru (or Mo) liner layer 202 is first deposited on the barrier layer 104, and then a thin dopant element Zn (or Mn, In, Sn or Al) layer 208 is deposited on the undoped Ru (or Mo) liner layer 202.

[0078] exist Figure 2FAlternatively, when Co is used to form the liner layer 202, the liner layer 202 is formed by co-depositing Co and a dopant element Zn (or Mn, In, Sn, or Al) on the barrier layer 104. When Ru (or Mo) is used to form the liner layer 202, a co-deposition method may also be used. That is, when Ru (or Mo) is used to form the liner layer 202, the liner layer 202 may be formed by co-depositing Ru (or Mo) and a dopant element Zn (or Mn, In, Sn, or Al) on the barrier layer 104.

[0079] The term "co-deposition" means depositing two elements together or a mixture of two elements (e.g., Co and Zn). Due to co-deposition, the dopant concentration (i.e., doping level) throughout the liner layer 202 can be controlled (e.g., maintained). Since Co has a higher affinity for oxygen than Ru (and Mo), the concentration (i.e., doping level) of the dopant in the liner layer 202 can be greater when Co is used than when Ru or Mo is used to form the liner layer 202.

[0080] Figures 3A-3F A second example of a structure or component plated using the doping scheme of the present disclosure is shown. In the second example, the component does not include a barrier layer 104.

[0081] exist Figure 3A In the embodiment, the component 300 to be plated includes a dielectric layer 102 and a liner layer 302. The dielectric layer 102 includes a substrate (e.g., a SiO2 substrate) containing a low-k dielectric material. The liner layer 302 includes a Ru, Co, or Mo layer doped with Zn (or Mn, In, Sn, or Al).

[0082] The liner layer 302 is deposited on the dielectric layer 102 using a suitable deposition process (eg, ALD). The stack of the dielectric layer 102 and the liner layer 202 is then subjected to a suitable thermal treatment (eg, annealing) to form the component 300.

[0083] exist Figure 3B In the embodiment of the present invention, upon annealing or exposure to room temperature, a thin layer of a compound of Zn (or Mn, In, Sn, or Al) and a dielectric material (e.g., a silicate layer if SiO2 is used as the dielectric layer 102) is formed between the dielectric layer 102 and the liner layer 302. The compound layer is shown at 304. The compound layer 304 prevents the liner layer 302 from oxidizing at the interface of the liner layer 302 and the dielectric layer 102. The compound layer 304 also provides adhesion between the liner layer 302 and the dielectric layer 102, which helps during the CMP or polishing process performed after electroplating.

[0084] exist Figure 3CIn the embodiment of the present invention, when the component 300 is waiting to be electroplated and optionally exposed to air (vacuum environment is not required), a thin Zn (or Mn, In, Sn or Al) oxide passivation layer (e.g., passivation or oxide layer 306) is formed on top of the liner layer 302. The oxide layer 306 protects the liner layer material from further oxidation due to exposure to air.

[0085] exist Figure 3D In the embodiment of the present invention, a metal layer (e.g., Cu) 108 is deposited on a liner layer 302 of a component 300 using electroplating. During electroplating, an oxide layer 306 dissolves in the electrolyte used. The metal layer 108 forms a strong metal-metal (Cu-Ru, Cu-Co, or Cu-Mo) bond with the liner layer 302. The compound layer 304 prevents Cu ions from diffusing through the liner layer 302 into the dielectric layer 102.

[0086] Figure 3E and 3F Two different doping methods are shown, which can be used to deposit a liner layer 302 including a dopant element Zn (or Mn, In, Sn or Al) on the dielectric layer 102. Figure 3E In the embodiment, when Ru (or Mo) is used to form the liner layer 302, the undoped liner layer 302 is first deposited on the dielectric layer 102, and then a thin dopant element Zn (or Mn, In, Sn or Al) layer 308 is deposited on the undoped Ru (or Mo) liner layer 302.

[0087] exist Figure 3F Optionally, when Co is used to form the liner layer 302, the liner layer 302 is formed by co-depositing Co and a dopant element Zn (or Mn, In, Sn, or Al) on the dielectric layer 102. When Ru (or Mo) is used to form the liner layer 302, a co-deposition method may also be used. That is, when Ru (or Mo) is used to form the liner layer 302, the liner layer 302 may be formed by co-depositing Ru (or Mo) and a dopant element Zn (or Mn, In, Sn, or Al) on the dielectric layer 102.

[0088] Due to the co-deposition, the concentration of the dopant (i.e., the doping level) can be controlled (e.g., maintained) throughout the liner layer 302. Since Co has a higher affinity for oxygen than Ru (and Mo), the dopant concentration (i.e., the doping level) in the liner layer 302 can be greater when Co is used than when Ru or Mo is used to form the liner layer 302.

[0089] Figure 4A and Figure 4B Methods of forming and electroplating components according to the present disclosure are shown. Figure 4A Components for forming a liner layer including a doped layer and a barrier layer (eg, Figures 2A-2F A first method 400 of the component 200 shown in FIG. Figure 4B Components for forming a liner layer including a doping layer and no explicit barrier layer are shown (e.g., Figures 3A-3F 4. A second method 450 of the component 300 shown in FIG. Figure 5-7 The controllers shown and described below (eg, controllers 510 , 680 , and 730 ) include instructions stored in a memory and executed by a processor of the controller to perform each method.

[0090] exist Figure 4A In the method, at 402, the method deposits a barrier layer (e.g., barrier layer 104) on a dielectric layer (e.g., dielectric layer 102) using a suitable deposition method. At 404, the method deposits a doped liner layer (e.g., liner layer 202) on the barrier layer using a suitable deposition method. For example, as described above with reference to Figures 2A-2F As described, the method can form a doped liner layer by first depositing an undoped liner layer on the barrier layer and then depositing a thin layer of dopant on top of the undoped liner layer, or the method can form a doped liner layer by co-depositing the liner material and the dopant on the barrier layer (i.e., by depositing a mixture of the liner material and the dopant on the barrier layer).

[0091] At 406, the method subjects the stack of dielectric layer, barrier layer, and doped liner layer to a suitable heat treatment (e.g., annealing). At 408, the method deposits a metal layer on the doped liner layer by electroplating. At 410, the method performs CMP (polishing) of the metal layer.

[0092] exist Figure 4B In 402, the method deposits a doped liner layer (e.g., liner layer 302) on a dielectric layer (e.g., dielectric layer 102) using a suitable deposition method. For example, as described above with reference to Figures 3A-3F As described, the method can form a doped liner layer by first depositing an undoped liner layer on the dielectric layer and then depositing a thin layer of dopant on top of the undoped liner layer, or the method can form a doped liner layer by co-depositing a liner material and a dopant on the dielectric layer (i.e., by depositing a mixture of a liner material and a dopant on the dielectric layer).

[0093] At 454, the method subjects the stack of the dielectric layer and the doped liner layer to a suitable heat treatment (eg, annealing). At 456, the method deposits a metal layer on the doped liner layer by electroplating. At 458, the method performs CMP (polishing) of the metal layer.

[0094] Figure 5A top view of an example of a substrate processing system 500 including a plurality of processing modules that can be used to deposit various barrier and liner layers and to manufacture the above-referenced Figures 2A-4B The components 200 and 300 are described. Figure 6 Examples of processing modules or chambers used to deposit various barrier and liner layers in substrate processing system 500 are described. Figure 7 Examples of systems and apparatus for electroplating components 200 and 300 are described.

[0095] exist Figure 5 , the substrate processing system 500 includes a substrate processing tool 502 and a controller 510. The substrate processing tool (hereinafter referred to as the tool) 502 includes a plurality of processing modules 504. For example, each processing module 504 can be configured to perform one or more corresponding processes on a substrate (e.g., depositing a barrier layer and / or a liner layer on the dielectric layer 102). The substrate to be processed (e.g., the dielectric layer 102) is loaded into the substrate processing tool 502 via a port of a loading station of an equipment front end module (EFEM) 506. The robot 508 sequentially transfers the substrate to one or more processing modules 504, where the substrate will be processed by the processing module 504. The controller 510 is described above with reference to Figure 4A and 4B The controller 510 may include a server or any other suitable computing device that can perform the described functions.

[0096] Figure 6 An example system 600 of a processing module 504 is shown, which can be used in the above reference Figures 2A-4B Deposition of one or more barrier layers and liner layers on a substrate, such as dielectric layer 102, is described. Although the foregoing examples are described in the context of plasma enhanced chemical vapor deposition (PECVD), the teachings of the present disclosure may be applied to other substrate processing systems, such as atomic layer deposition (ALD), PEALD, CVD, or any other process.

[0097] The system 600 includes a process chamber 622 that surrounds the other components of the system 600 and contains the RF plasma (if used). The system 600 includes an upper electrode 624 and a substrate support component, such as an electrostatic chuck (ESC) 626 or other substrate support. During operation, a substrate 628 (e.g., dielectric layer 102) is placed on the ESC 626.

[0098] For example, the upper electrode 624 may include a gas distribution device 629, such as a showerhead that introduces and distributes process gases. The gas distribution device 629 may include a stem that includes one end connected to the top surface of the processing chamber. The base is generally cylindrical and extends radially outward from the opposite end of the stem at a position spaced apart from the top surface of the processing chamber. The surface or panel facing the substrate of the base of the showerhead includes a plurality of holes through which vaporized precursors, process gases, or purge gases flow. Alternatively, the upper electrode 624 may include a conductive plate and the process gas may be introduced in another manner.

[0099] The ESC 626 includes a substrate 630 that serves as a lower electrode. The substrate 630 supports a heating plate 632, which may correspond to a ceramic multi-zone heating plate. A thermal resistance layer 634 may be disposed between the heating plate 632 and the substrate 630. The substrate 630 may include one or more channels 636 for flowing a coolant through the substrate 630.

[0100] If plasma is used, the RF generation system 640 generates an RF voltage and outputs the RF voltage to one of the upper electrode 624 and the lower electrode (e.g., the substrate 630 of the ESC 626). The other of the upper electrode 624 and the substrate 630 can be DC grounded, AC grounded, or floating. By way of example only, the RF generation system 640 can include an RF generator 642 that generates RF power that is fed to the upper electrode 624 or the substrate 630 by a matching and distribution network 644. In other examples, the plasma can be generated inductively or remotely.

[0101] The gas delivery system 650 includes one or more gas sources 652-1, 652-2, ... and 652-N (collectively referred to as gas sources 652), where N is an integer greater than zero. The gas sources 652 are connected to the manifold 660 through valves 654-1, 654-2, ... and 654-N (collectively referred to as valves 654) and mass flow controllers 656-1, 656-2, ... and 656-N (collectively referred to as mass flow controllers 656). The vapor delivery system 661 supplies the vaporized precursor to the manifold 660 or another manifold (not shown) connected to the process chamber 622. The output of the manifold 660 is supplied to the process chamber 622.

[0102] The temperature controller 663 can be connected to a plurality of thermal control elements (TCE) 664 arranged in the heating plate 632. The temperature controller 663 can be used to control a plurality of TCEs 664 to control the temperature of the ESC 626 and the substrate 628. The temperature controller 663 can be communicated with a coolant assembly 666 to control the coolant flowing through the channel 636. For example, the coolant assembly 666 may include a coolant pump, a reservoir, and one or more temperature sensors. The temperature controller 663 operates the coolant assembly 66 so that the coolant selectively flows through the channel 636 to cool the ESC 626. The valve 670 and the pump 672 can be used to discharge the reactant from the processing chamber 622. The system controller 680 can be used to control the components of the system 600.

[0103] Figure 7 A schematic diagram showing a top view of an example of an electrodeposition apparatus 700 that can be used as described above with reference to Figures 2A-4B The metal layer (Cu) is deposited on the components 200 and 300 produced by the substrate processing system 500. The electrodeposition device 700 may include one or more electroplating modules (EPMs) 702, 704 and 706. The electrodeposition device 700 may also include one or more modules 712, 714 and 716 configured for various process operations. For example, in some embodiments, one or more modules 712, 714 and 716 may be spin rinse drying (SRD) modules. In other embodiments, one or more modules 712, 714 and 1016 may be post-electroporation modules (PEMs). Each of the modules 712, 714 and 716 may be configured to perform functions such as bevel removal, backside etching and acid cleaning of the substrate after the substrate is processed in one of the electroplating modules 702, 704 and 706.

[0104] The electrodeposition apparatus 700 includes a central electrodeposition chamber 724 that contains a chemical solution that is used as an electroplating solution in the electroplating modules 702, 704, and 706. The electrodeposition apparatus 700 also includes a dosing system 726 that can store and deliver additives for the electroplating solution. The chemical dilution module 722 can store and mix chemicals used as etchants. The filtration and exhaust system 728 can filter the electroplating solution used in the central electrodeposition chamber 724 and extract the filtered electroplating solution to the electroplating modules 702, 704, and 706. The system controller 730 provides various interfaces and control devices to operate the electrodeposition apparatus 700, and controls the operation of the electrodeposition apparatus 700 as described below.

[0105] Signals for monitoring the processes performed by the various modules of the electrodeposition apparatus 700 may be provided from various sensors (not shown) installed throughout the electrodeposition apparatus 700 through analog and / or digital inputs of the system controller 730. Signals for controlling these processes may be output on analog and digital outputs of the system controller 730. Non-limiting examples of sensors include mass flow sensors, pressure sensors (e.g., manometers), temperature sensors (e.g., thermocouples), optical position sensors, and the like.

[0106] The transfer tool 740 may select a substrate (e.g., component 200 or 300) from a substrate cassette such as cassette 742 or cassette 744. Cassettes 742 or 744 may be front opening unpacking units (FOUPs). A FOUP is a housing designed to securely hold a substrate (e.g., component 200 or 300 received from system 500) and enable the substrate to be removed for processing or measurement through a tool equipped with an appropriate load port and robotic handling system. The transfer tool 740 may use vacuum attachment or some other attachment mechanism to hold the substrate.

[0107] The transfer tool 740 can be docked with the wafer handling station 732, the cassettes 742 or 744, the transfer station 750, and / or the aligner 748. The transfer tool 746 can obtain a substrate (e.g., component 200 or 300) from the transfer station 750. The transfer station 750 can be a slot or location to which the transfer tools 740 and 746 can transfer the substrate without passing through the aligner 748. In some embodiments, to ensure that the substrate is properly aligned on the transfer tool 746 for accurate delivery to the electroplating module, the transfer tool 746 can align the substrate with the aligner 748. The transfer tool 746 can also deliver the substrate to one of the electroplating modules 702, 704, or 706, or to one of the other modules 712, 714, and 716 that are configured for various processing operations.

[0108] Examples of processing operations may be as follows: (1) copper or another material is electrodeposited on a substrate (eg, component 200 or 300 ) in electroplating module 1004 ; (2) the substrate is rinsed and dried in an SRD in module 1012 ; and (3) bevel removal is performed in module 1014 .

[0109] In this manner, systems 500 and 700 may be used to produce the Figures 2A-4B The components 200 and 300 are described above. Figures 2A-4B As described above, the doped liner protects components 200 and 300 and facilitates their electroplating by providing passivation and adhesion.

[0110] The foregoing description is merely illustrative in nature and is by no means intended to limit the present disclosure, its application or use. The broad teachings of the present disclosure can be implemented in various forms. Therefore, although the present disclosure includes specific examples, the true scope of the present disclosure should not be so limited, because when studying the drawings, the specification and the appended claims, other modifications will become apparent. It should be understood that one or more steps in the method can be performed in different orders (or simultaneously) without changing the principles of the present disclosure. In addition, although each embodiment is described above as having certain features, any one or more of those features described relative to any embodiment of the present disclosure can be implemented in the features of any other embodiment and / or combined with the features of any other embodiment, even if the combination is not explicitly described. In other words, the described embodiments are not mutually exclusive, and the replacement of one or more embodiments with each other remains within the scope of the present disclosure.

[0111] Various terms are used to describe the spatial and functional relationships between elements (e.g., between modules, between circuit elements, between semiconductor layers, etc.), including "connected," "engaged," "coupled," "adjacent," "next to," "on top of," "above," "below," and "disposed." Unless the relationship between a first and a second element is explicitly described as "direct," when such a relationship is described in the above disclosure, the relationship can be a direct relationship, in which there are no other intervening elements between the first and second elements, but can also be an indirect relationship, in which there are one or more intervening elements (spatially or functionally) between the first and second elements. As used herein, the phrase "at least one of A, B, and C" should be interpreted to mean a logical (A or B or C), using a non-exclusive logical OR, and should not be interpreted to mean "at least one of A, at least one of B, and at least one of C."

[0112] In some implementations, the controller is part of a system, which can be part of the above examples. Such a system can include a semiconductor processing device, which includes one or more processing tools, one or more chambers, one or more platforms for processing, and / or specific processing components (wafer pedestals, gas flow systems, etc.). These systems can be integrated with electronic devices for controlling their operations before, during, and after the processing of semiconductor wafers or substrates. The electronic device can be referred to as a "controller", which can control various components or subcomponents of one or more systems. Depending on the processing requirements and / or system type, the controller can be programmed to control any process disclosed herein, including the delivery of process gases, temperature settings (e.g., heating and / or cooling), pressure settings, vacuum settings, power settings, radio frequency (RF) generator settings, RF matching circuit settings, frequency settings, flow rate settings, fluid delivery settings, position and operation settings, wafer transfer in and out tools and other transfer tools and / or load locks connected to or connected to a specific system through an interface.

[0113] In general, a controller can be defined as an electronic device having various integrated circuits, logic, memory, and / or software that receive instructions, issue instructions, control operations, enable cleaning operations, enable endpoint measurements, etc. The integrated circuit can include a chip in the form of firmware that stores program instructions, a digital signal processor (DSP), a chip defined as an application specific integrated circuit (ASIC), and / or one or more microprocessors, or a microcontroller that executes program instructions (e.g., software). The program instructions can be instructions sent to the controller in the form of various individual settings (or program files) that define operating parameters for performing a specific process on or for a semiconductor wafer or system. In some embodiments, the operating parameters can be part of a recipe defined by a process engineer to complete one or more processing steps during the manufacture of one or more (kinds of) layers, materials, metals, oxides, silicon, silicon dioxide, surfaces, circuits, and / or dies of a wafer.

[0114] In some implementations, the controller may be part of or coupled to a computer that is integrated with the system, coupled to the system, otherwise networked to the system, or a combination thereof. For example, the controller may be in the "cloud" or all or part of a wafer fab host system that may allow remote access to wafer processing. The computer may enable remote access to the system to monitor the current progress of a manufacturing operation, check the history of past manufacturing operations, check trends or performance criteria for multiple manufacturing operations, change parameters of a current process, set processing steps to follow the current process, or start a new process. In some examples, a remote computer (e.g., a server) may provide a process recipe to the system via a network (which may include a local network or the Internet). The remote computer may include a user interface that enables input or programming of parameters and / or settings, which are then sent from the remote computer to the system. In some examples, the controller receives instructions in the form of data that specify parameters for each processing step to be performed during one or more operations. It should be understood that the parameters may be specific to the type of process to be performed and the type of tool that the controller is configured to interface with or control. Thus, as described above, the controller may be distributed, for example, by including one or more discrete controllers networked together and working toward a common purpose (e.g., the process and control described herein). An example of a distributed controller for such a purpose is one or more integrated circuits on a chamber communicating with one or more integrated circuits remotely (e.g., at a platform level or as part of a remote computer), which combine to control the process on the chamber.

[0115] Example systems may include, but are not limited to, plasma etch chambers or modules, deposition chambers or modules, spin rinse chambers or modules, metal plating chambers or modules, cleaning chambers or modules, chamfer edge etch chambers or modules, physical vapor deposition (PVD) chambers or modules, chemical vapor deposition (CVD) chambers or modules, atomic layer deposition (ALD) chambers or modules, atomic layer etch (ALE) chambers or modules, ion implantation chambers or modules, track chambers or modules, and any other semiconductor processing system that may be associated with or used in the manufacture and / or preparation of semiconductor wafers.

[0116] As described above, depending on one or more processing steps to be performed by the tool, the controller can communicate with one or more other tool circuits or modules, other tool components, cluster tools, other tool interfaces, adjacent tools, neighboring tools, tools located throughout the factory, a host computer, another controller, or tools used in material transport to transport wafer containers to and from tool locations and / or load ports in a semiconductor manufacturing facility.

Claims

1. A method for enhancing passivation and adhesion of a metal lining, comprising: depositing a barrier layer on the dielectric layer to prevent oxidation of a metal layer to be deposited by electroplating due to the presence of oxides in the dielectric layer; as well as depositing a liner layer on the barrier layer to combine with the metal layer to be deposited on the liner layer by the electroplating, wherein the liner layer is doped with a dopant, wherein, when the surface of the lining layer is exposed to air before the electroplating, the dopant forms a passivation layer on the surface, and the metal layer will be deposited on the surface, wherein the passivation layer further prevents oxidation of the lining layer when the lining layer is exposed to air before the electroplating, wherein the passivation layer is dissolved during the electroplating so that the metal layer deposited on the lining layer by the electroplating is combined with the lining layer, wherein the dopant reacts with the dielectric layer and forms a compound layer between the barrier layer and the dielectric layer, wherein the compound layer prevents oxidation of the barrier layer and the liner layer due to the oxide present in the dielectric layer, and wherein the compound layer adheres the barrier layer to the dielectric layer.

2. The method according to claim 1, further comprising: The metal layer is electroplated on the liner layer, and chemical mechanical planarization is performed on the metal layer. The method of claim 1 , further comprising performing chemical mechanical planarization on the metal layer.

4. The method according to claim 1, wherein: The dopant includes an element that is more electronegative than elements used to form the liner layer and the metal layer. The method of claim 1 , further comprising co-depositing the liner layer and the dopant on the barrier layer. The method of claim 1 , further comprising depositing the dopant on the liner layer.

7. The method according to claim 1, wherein: The dielectric layer includes a material having a low dielectric constant, the compound includes a substance formed of a combination of the material and the dopant, and the passivation layer includes an oxide of the dopant.

8. The method according to claim 1, wherein: The dielectric layer includes SiO 2 , the compound includes a substance formed of a combination of SiO 2 and the dopant, and the passivation layer includes an oxide of the dopant.

9. The method according to claim 1, further comprising: Using TaN to form the barrier layer; The lining layer is formed using one of Ru, Co and Mo; doping the liner layer with one of Zn, Mn, In, Sn and Al; and The metal layer is formed using Cu.

10. The method of claim 1, further comprising performing a heat treatment on the liner layer, the barrier layer, and the dielectric layer prior to the electroplating.

11. A method for enhancing passivation and adhesion of a metal lining, comprising: providing a dielectric layer; as well as depositing a liner layer on the dielectric layer to combine with a metal layer to be deposited on the liner layer by electroplating, wherein the liner layer is doped with a dopant, wherein, when the lining layer is exposed to air before the electroplating, the dopant forms a passivation layer on the surface of the lining layer, and the metal layer will be deposited on the surface, wherein the passivation layer further prevents oxidation of the lining layer caused by exposure of the lining layer to air before the electroplating, wherein the passivation layer is dissolved during the electroplating so that the metal layer deposited on the lining layer by the electroplating is combined with the lining layer, wherein the dopant reacts with the dielectric layer and forms a compound layer between the liner layer and the dielectric layer, wherein the compound layer prevents oxidation of the liner layer and the metal layer due to oxides present in the dielectric layer, and wherein the compound layer adheres the liner layer to the dielectric layer.

12. The method according to claim 11, further comprising: The metal layer is electroplated on the liner layer, and chemical mechanical planarization is performed on the metal layer.

13. The method of claim 11, further comprising performing chemical mechanical planarization on the metal layer.

14. The method according to claim 11, wherein: The dopant includes an element that is more electronegative than elements used to form the liner layer and the metal layer.

15. The method of claim 11, further comprising co-depositing the liner layer and the dopant on the dielectric layer.

16. The method of claim 11, further comprising depositing the dopant on the liner layer.

17. The method according to claim 11, wherein: The dielectric layer includes a material having a low dielectric constant, the compound includes a substance formed of a combination of the material and the dopant, and the passivation layer includes an oxide of the dopant.

18. The method according to claim 11, wherein: The dielectric layer includes SiO 2 , the compound includes a substance formed of a combination of SiO 2 and the dopant, and the passivation layer includes an oxide of the dopant.

19. The method according to claim 11, further comprising: The lining layer is formed using one of Ru, Co and Mo; doping the liner layer with one of Zn, Mn, In, Sn and Al; as well as The metal layer is formed using Cu.

20. The method of claim 11, further comprising performing a heat treatment on the liner layer and the dielectric layer prior to the electroplating.

21. The method of claim 11, wherein the compound layer prevents ions of the metal layer from drifting into the dielectric layer.

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