Vertical Hall element with small offset and method for manufacturing the same

Abstract

A vertical Hall element is disclosed, comprising: a substrate of a first conductivity type, having a first surface and a second surface; a well of a second conductivity type, disposed in and exposed on two surfaces of the substrate; and at least four terminals, preferably including highly doped regions of the second conductivity type in contact with the well. At least two terminals are disposed on the first surface, and at least two terminals are disposed on the second surface such that one terminal on the first surface and one terminal on the second surface have the same but opposite positions in a cross-section orthogonal to the substrate surface. Alternatively, an element includes a central pair of opposing surface terminals, while the other two terminals include laterally buried doped regions connected to the first surface.

Description

Technical Field

[0001] The present disclosure relates to a vertical Hall element with a small offset and a method of manufacturing the same. Background Art

[0002] Magnetic sensor ICs typically use silicon-based Hall elements, which are monolithically integrated with the circuits required for signal conditioning and amplification. Typical commercial products with monolithically integrated Hall elements are Hall switch ICs, Hall ICs for linear position measurement, angular position sensor Hall ICs, Hall ICs for current sensing, and 3D Hall sensor ICs. Depending on the product type, a Hall IC may include a horizontal Hall element, a vertical Hall element, or both. The vertical Hall element senses the magnetic field intensity in the plane direction of the silicon surface and is used for angular position sensor Hall ICs and, together with the horizontal Hall element, for 3D Hall sensor ICs.

[0003] A conventional vertical Hall element is formed as follows: a well with n-type conductivity is formed in a lightly doped p-type silicon substrate. The n-type well constitutes the Hall plate of the sensor, and the Hall plate is isolated from the substrate by a p-n junction. Three, four, five, or more Hall terminals are formed on the silicon surface within the region of the n-type well, and these Hall terminals are typically arranged in a row or in a circular pattern (R.S. Popoyic, “Hall Effect Deyices”, Institute of Physics Publishing, Bristoland Philadelphia 2004 (R.S. Popovic, “Hall Effect Devices”, published by the Institute of Physics, Bristol and Philadelphia (2004))).

[0004] In these conventional vertical Hall elements, the sensitivity is limited by the finite depth of the n-type well in which the Hall terminals are placed. Therefore, a high-voltage CMOS process with a deep well is typically used to manufacture a Hall IC with a vertical Hall element. Even with these processes, the well depth is typically only on the order of a few micrometers.

[0005] In addition to low sensitivity, conventional vertical Hall elements typically also have a high residual offset. The offset of a Hall element (i.e., the Hall voltage measured at zero magnetic field intensity) can be reduced by known techniques (e.g., current rotation, orthogonal coupling, or a combination thereof). Effective offset reduction depends on the commutation of the Hall terminals and the four-fold symmetry of the Hall device. The terminals of a single conventional vertical Hall element are all placed on the same silicon surface, which necessarily deviates from the ideal four-fold symmetry.

[0006] Another disadvantage of conventional vertical Hall elements is their non-linearity. When an n-type Hall plate is formed in a p-type substrate, during the operation of the Hall element, i.e., when a current is forced to flow through the Hall element, a depletion region is formed along the p-n junction. The width of the depletion region varies spatially and depends on the exact operating conditions. In any case, the formation of the depletion region changes the effective resistance of the Hall plate, resulting in non-linear behavior of the vertical Hall element. The non-linearity also makes it more difficult to cancel the offset of the Hall element.

[0007] There is a desire to provide a vertical Hall element with improved characteristic parameters (e.g., reduced effective offset, high sensitivity, and high linearity). Summary of the Invention

[0008] A first embodiment of a vertical Hall element providing improved characteristic parameters is specified in claim 1. Further embodiments are specified in claims 2 to 13.

[0009] According to a possible embodiment of the vertical Hall element, the vertical Hall element includes a substrate of a first conductivity type having a first surface and a second surface. The vertical Hall element further includes a well provided in the substrate, the well having a second conductivity type. The well is exposed on the second surface of the substrate. The vertical Hall element includes at least two terminals arranged on the first surface of the substrate and in contact with the well. The vertical Hall element further includes at least two terminals arranged on the second surface of the substrate and in contact with the well.

[0010] At least two terminals on the second surface of the substrate are arranged to be below at least two terminals on the first surface of the substrate in the orthogonal projection of the substrate.

[0011] According to a possible embodiment of the vertical Hall element, at least two terminals on the first surface of the substrate include a first terminal and a second terminal arranged adjacent to each other on the first surface of the substrate. At least two terminals on the second surface of the substrate include a third terminal and a fourth terminal arranged adjacent to each other on the second surface of the substrate. The fourth terminal is located directly below the first terminal such that the virtual straight line between the center of the first terminal and the center of the fourth terminal is perpendicular to the first surface and the second surface of the substrate. The third terminal is located directly below the second terminal such that the virtual straight line between the center of the second terminal and the center of the third terminal is perpendicular to the first surface and the second surface of the substrate.

[0012] According to a possible embodiment of the vertical Hall element, each of at least two terminals on the first surface of the substrate includes a shallow highly doped region extending from the first surface into the substrate, the highly doped region having a second conductivity type.

[0013] According to a possible embodiment of a vertical Hall element, the vertical Hall element includes a dielectric layer provided on a first surface of a substrate and wirings embedded in the dielectric layer. At least two terminals on the first surface of the substrate may be connected to a first metal layer of the wirings embedded in the dielectric layer.

[0014] According to a possible embodiment of a vertical Hall element, the vertical Hall element includes a carrier substrate bonded to a top surface of the dielectric layer. The top surface of the dielectric layer faces a surface of the dielectric layer provided on the first surface of the substrate.

[0015] According to a possible embodiment of a vertical Hall element, each of at least two terminals on a second surface of the substrate includes a shallow highly doped region extending from the second surface into the substrate, and the highly doped region has a second conductivity type.

[0016] According to a possible embodiment of a vertical Hall element, the vertical Hall element includes a second dielectric layer and a passivation layer. The second dielectric layer is provided on the second surface of the substrate, and the passivation layer is provided on the dielectric layer.

[0017] According to a possible embodiment of a vertical Hall element, the vertical Hall element includes a through-silicon via filled with a conductive filler, and the through-silicon via provides a vertical conduction path through the substrate for connecting one of a third terminal and a fourth terminal to the wirings in the dielectric layer. The conductive filler of the through-silicon via is isolated from the substrate by a dielectric lining provided on an inner surface of the through-silicon via.

[0018] According to a possible embodiment of a vertical Hall element, the vertical Hall element includes a deep trench isolation structure extending from a first surface of the substrate to a second surface of the substrate, such that a well is isolated from the substrate by the deep trench isolation structure.

[0019] According to another possible embodiment of a vertical Hall element, the vertical Hall element is configured as a circular vertical Hall element. The well is formed as an annular well. The vertical Hall element has: at least two terminals located on a first surface of the substrate in a first circle and in contact with the well; and at least two terminals located on a second surface of the substrate in a second circle and in contact with the well. A corresponding one of the at least two terminals on the second surface of the substrate is provided below a corresponding one of the at least two terminals on the first surface of the substrate in an orthogonal projection of the substrate.

[0020] According to a possible embodiment of a vertical Hall element, the vertical Hall element includes two annular isolation structures. The two annular isolation structures extend from a first surface of the substrate to a second surface of the substrate and are concentric with the annular well, such that the well is surrounded laterally by the two annular isolation structures and is isolated from the substrate.

[0021] According to a possible embodiment, a vertical Hall element has two terminals on a first surface of a thinned semiconductor substrate of a first conductivity type and two terminals on a second surface of the thinned semiconductor substrate. The four terminals are arranged such that one terminal on the first surface and one terminal on the second surface each have the same but opposite positions. The two terminals on the first surface are formed in a well of a second conductivity type. The well is exposed on the second surface such that the terminals on the second surface also contact the well. The geometry of the vertical Hall element is defined such that the four resistances between the four terminals are nearly equal. The terminals on the second surface are connected to the wiring on the first surface through vias in silicon.

[0022] According to another possible embodiment, a vertical Hall element has two terminals on a first surface of a thinned semiconductor substrate of a first conductivity type and two terminals on a second surface of the thinned semiconductor substrate. The four terminals are arranged such that one terminal on the first surface and one terminal on the second surface each have the same but opposite positions. The two terminals on the first surface are formed in a well of a second conductivity type. The well is exposed on the second surface such that the terminals on the second surface also contact the well. The well is surrounded by a deep trench isolation structure that extends from the first surface of the thinned semiconductor substrate to the second surface. The geometry of the vertical Hall element is defined such that the four resistances between the four terminals are nearly equal. The terminals on the second surface are connected to the wiring on the first surface through vias in silicon.

[0023] According to another possible embodiment, a vertical Hall element has two terminals on a first surface of a thinned semiconductor substrate of a first conductivity type and two terminals on a second surface of the thinned semiconductor substrate. The four terminals are arranged such that one terminal on the first surface and one terminal on the second surface each have the same but opposite positions. The four terminals are surrounded by a deep trench isolation structure that extends from the first surface of the thinned semiconductor substrate to the second surface. The geometry of the vertical Hall sensor is defined such that the four resistances between the four terminals are nearly equal. The terminals on the second surface are connected to the wiring on the first surface through vias in silicon.

[0024] According to another possible embodiment, a vertical Hall element has N terminals on a first surface of a thinned semiconductor substrate of a first conductivity type and N terminals on a second surface of the thinned semiconductor substrate. The N terminals on the first surface have the same size, are equally spaced apart, and are arranged in a circle. The N terminals on the second surface having the same size are placed such that for each terminal on the first surface, there is one terminal on the second surface having the same but opposite position. The N terminals on the first surface are formed in an annular well of a second conductivity type. The well is exposed on the second surface such that the N terminals on the second surface also contact the annular well. The geometry of the vertical Hall element is defined such that the four resistances between the four terminals of each temporary vertical Hall element that can be formed along the circle are nearly equal. The N terminals on the second surface are connected to the wiring on the first surface through N vias.

[0025] According to another possible embodiment, a vertical Hall element has N terminals on a first surface of a thinned semiconductor substrate of a first conductivity type and N terminals on a second surface of the thinned semiconductor substrate. The N terminals on the first surface have the same size, are equally spaced apart, and are arranged in a circle. The N terminals on the second surface having the same size are placed such that for each terminal on the first surface, there is one terminal on the second surface having the same but opposite position. The N terminals on the first surface are formed in an annular well of a second conductivity type. The well is exposed on the second surface such that the N terminals on the second surface also contact the annular well. The annular well is laterally isolated from the semiconductor substrate by two deep trench isolation rings. The two deep trench isolation rings extend from the first surface of the thinned semiconductor substrate to the second surface. The geometry of the vertical Hall element is defined such that the four resistances between the four terminals of each temporary vertical Hall element that can be formed along the circle are nearly equal. The N terminals on the second surface are connected to the wiring on the first surface through N vias.

[0026] Claims 13 to 20 define a second embodiment of a vertical Hall sensor element providing improved characteristic parameters.

[0027] According to a possible embodiment of a vertical Hall element, the Hall element includes: a substrate of a first conductivity type having a first surface and a second surface; and a well provided in the substrate. The well has a second conductivity type. The vertical Hall element includes a first terminal, a second terminal, a third terminal, and a fourth terminal. Each of the first terminal and the third terminal includes a connection region. The respective connection regions provide the connection of the first terminal and the second terminal to the first surface of the substrate. Each of the first terminal and the third terminal is accessed via a doped region extending from the first surface of the substrate into the doped region. The second terminal is arranged on the first surface of the substrate. The fourth terminal is arranged on the second surface of the substrate opposite the second terminal.

[0028] According to a possible embodiment of a vertical Hall element, the second terminal includes a conductive region extending from a first surface of the substrate into the substrate. The fourth terminal includes a conductive region extending from a second surface of the substrate into the substrate. The fourth terminal is located directly below the second terminal such that a virtual straight line between the center of the conductive region of the second terminal and the center of the conductive region of the fourth terminal is perpendicular to the first surface and the second surface of the substrate.

[0029] According to a possible embodiment of a vertical Hall element, the vertical Hall element includes a dielectric layer disposed on a first surface of the substrate. The vertical Hall element further includes a carrier attached to a top surface of the dielectric layer, wherein the top surface of the dielectric layer faces the surface of the dielectric layer disposed on the first surface of the substrate.

[0030] According to a possible embodiment of a vertical Hall element, each of the first terminal and the third terminal includes a conductive buried region buried in a well. A corresponding connection region provides a connection of the conductive buried region to the first surface of the substrate.

[0031] According to a possible embodiment of a vertical Hall element, the vertical Hall element includes a first doped well extending from a first surface of the substrate into the well and downward to the buried region of the first terminal. The vertical Hall element includes a second doped well extending from a first surface of the substrate into the well and downward to the buried region of the third terminal.

[0032] According to a possible embodiment of a vertical Hall element, the connection well of the first terminal is surrounded by a first dielectric structure. The connection well of the third terminal is surrounded by a second dielectric structure.

[0033] According to a possible embodiment of a vertical Hall element, the vertical Hall element includes a deep trench isolation structure extending from a first surface of the substrate to a second surface. The well is isolated from the substrate by the deep trench isolation structure.

[0034] A semiconductor device is specified in claim 21 that includes a vertical Hall element according to any one of the claims. The semiconductor device further includes a circuit for operating the vertical Hall element, wherein the circuit is configured to be an integrated circuit formed in the substrate.

[0035] According to a possible embodiment of the semiconductor device, the circuit includes a bonding pad formed on a second surface of the substrate. The circuit includes through-silicon vias to provide a connection between the bonding pad and the wiring in the dielectric layer disposed on the first surface of the substrate.

[0036] Additional features and advantages are set forth in the detailed description which follows, and in part will be obvious to those of ordinary skill in the art from the description or may be learned by practice of the embodiments as described in the written description and claims hereof and the appended drawings. It is to be understood that both the foregoing general description and the following detailed description are exemplary and intended to provide an overview or framework for understanding the nature and character of the claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] The present disclosure is further illustrated by the accompanying drawings, which are incorporated in and constitute a part of this specification. The drawings show one or more embodiments and, together with the detailed description, serve to explain the principles and operations of the various embodiments. Thus, the present disclosure will be more fully understood from the following detailed description when taken in conjunction with the accompanying drawings.

[0038] Figures 1 to 7 showing a first embodiment of a vertical Hall element;

[0039] Figures 8 to 14 showing a modified version of the first embodiment of the vertical Hall element;

[0040] Figure 15 showing a first embodiment of a semiconductor device including a vertical Hall element;

[0041] Figures 16 to 26 showing manufacturing steps of a manufacturing method of the first embodiment of a semiconductor device including a vertical Hall element;

[0042] Figure 27 showing a second embodiment of a semiconductor device including a vertical Hall sensor;

[0043] Figures 28 to 39 showing manufacturing steps of a manufacturing method of the second embodiment of a semiconductor device including a vertical Hall element;

[0044] Figures 40 to 42 showing another modified version of the first embodiment of the vertical Hall element;

[0045] Figures 43 to 49 showing a second embodiment of the vertical Hall element;

[0046] Figures 50 to 53 showing a modified version of the second embodiment of the vertical Hall element;

[0047] Figure 54 showing a third embodiment of a semiconductor device including a vertical Hall element;

[0048] Figures 55 to 65 showing manufacturing steps of a manufacturing method of the third embodiment of a semiconductor device including a vertical Hall element;

[0049] Figure 66 shows a fourth embodiment of a semiconductor device including a vertical Hall element; and

[0050] Figures 67 to 78 shows manufacturing steps of a manufacturing method of a fourth embodiment of a semiconductor device including a vertical Hall element. DETAILED DESCRIPTION

[0051] Reference will now be made in detail to various embodiments, examples of which are shown in part in the drawings. In all the drawings, wherever possible, the same or similar reference numerals and symbols are used to refer to the same or similar parts. The drawings are not necessarily to scale, and those skilled in the art will recognize that the drawings have been simplified to show key aspects of the present disclosure. The claims as set forth below are incorporated into this detailed description and form a part thereof.

[0052] Figure 1 、 Figure 2 and Figure 3 shows a vertical Hall element 100. In Figure 1 it shows the vertical Hall element as seen from above (looking at the first silicon surface). Two cutting lines are indicated, one cutting line parallel to the x direction from A to A′ and one cutting line parallel to the y direction from B to B′. Figure 2 shows a cross-section of the vertical Hall element 100 taken along the cutting line A-A′, Figure 3Shows a cross-section of a vertical Hall element 100 taken along the cut line B-B'. The vertical Hall element 100 is formed on a semiconductor substrate 101. The semiconductor substrate 101 can be a lightly doped silicon substrate of a first conductivity type. The first conductivity type is preferably p-type. The substrate has a first surface 101a and a second surface 101b. These two surfaces are opposite to each other and parallel to each other. The second surface 101b is obtained by thinning the substrate from the back side (i.e., from the side opposite to the first surface 101a). The vertical Hall element 100 is formed in a well 102 of a second conductivity type. The well 102 extends from the first surface 101a and is exposed at the second surface 101b. The well 102 forms a Hall plate or defines the Hall sensor region of the vertical Hall element 100. The vertical Hall element 100 has four terminals (indicated by the numbers 1, 2, 3, and 4). Terminal 1 and terminal 2 are arranged on the first silicon surface 101a, and terminal 3 and terminal 4 are arranged on the second silicon surface 101b. The terminals 1 and 2 formed at the first surface 101a are in contact with the well 102. Similarly, the terminals 3 and 4 formed at the second surface 101b are in contact with the well 102. The two terminals 1 and 2 on the first surface have the same width and the same length. Similarly, the two terminals 3 and 4 on the second surface have the same width and the same length. In terms of the virtual straight line between the center of terminal 1 and the center of terminal 4 being perpendicular to the silicon surface 101a, terminal 4 is located directly below terminal 1. Terminal 3 is located directly below terminal 2 in the same way. For each of the two terminals arranged on the first surface 101a, a shallow highly doped region 103 is formed extending from the first surface into the substrate. The highly doped region 103 has a second conductivity type, i.e., the conductivity type of the well 102. Some metal (e.g., cobalt) can be used to silicify the highly doped region 103. A metal contact 105 is formed in the dielectric layer 104, and the metal contact 105 connects the highly doped region 103 to the metal wiring of the first metal layer 106 embedded in the dielectric layer 104. The substrate 101 is bonded to a carrier substrate 201 through the top surface 104a of the dielectric layer 104. The carrier substrate 201 can also be a silicon substrate. At the second surface 101b, for each of the two terminals 3 and 4 extending from the second surface 101b into the substrate, a shallow highly doped region 303 is formed. The highly doped region 303 has a second conductivity type, i.e., the conductivity type of the well 102. A dielectric layer 304 is provided on the second surface 101b. The dielectric layer 304 is constructed in such a way as to form contact holes connecting the highly doped regions 303. Metal 305 is deposited in the contact holes. In addition, the metal 305 is constructed such that metal wiring is formed on the second surface of the substrate. A passivation layer 308 is provided on the dielectric layer 304 and the metal layer 305.

[0053] Figure 4 Is another representation of the vertical Hall element 100 along the cut line direction B-B'. To supplementFigure 3 , the through-silicon via (TSV) is depicted on the right side of Figure 4 . The through-silicon via provides a vertical conduction path through the substrate 101, which connects the terminal 3 disposed on the second surface 101b to the metal wiring formed on the first silicon surface. The through-silicon via associated with the terminal 3 is denoted as TSV(3). For each terminal disposed on the second surface 101b, there is one through-silicon via that connects the terminal to the wiring formed on the first surface. Since the vertical Hall element 100 has two terminals disposed on the second surface, there are also two through-silicon vias. The through-silicon via TSV(3) contacts a portion 106 of the first metal layer embedded in the dielectric layer 104. At the second surface 101b, the through-silicon via TSV(3) is connected to the terminal 3 through the metal wiring 305. In this way, the terminal 3 can be accessed at point C(3). As Figure 4 shown, the terminal 2 formed on the first surface 101a can be electrically accessed at point C(2). The through-silicon via is filled with a conductive material 305, and the conductive material 305 can be the same material as the material for metallization on the second surface. For example, this material can be aluminum. However, other metallization schemes can also be considered. In one scheme, the metal disposed in the through-silicon via is copper or tungsten, while the metal for wiring and for filling the contact holes connecting the highly doped regions 303 is aluminum. In another scheme, the metal disposed in the through-silicon via and the metal disposed in the contact holes connecting the highly doped regions 303 is tungsten, while the metal for the wiring on the second surface is aluminum. The conductive filler 305 of the through-silicon via is isolated from the silicon substrate 101 by a dielectric lining 306 disposed on the inner surface of the through-silicon via. The distance between the through-silicon via and the well 102 in which the Hall terminal is formed is L. The current I driven through the through-silicon via generates a magnetic field parallel to the silicon surface. The intensity of the induced magnetic field at the position of the vertical Hall element is B = μ0 / (2πL)·I. To minimize such interference effects, the distance L can be set large enough. For example, if the Hall current is 1 mA and the distance L is set to 100 μm, the induced magnetic field intensity is 2 μT, which is much lower than the measurement resolution of available vertical Hall elements.

[0054] A Hall element having four terminals can be formed by, for example, Figure 5The equivalent circuit representation shown. Four terminals 1, 2, 3, and 4 are connected via four resistors R1, R2, R3, and R4 (a Wheatstone bridge). If all four resistors are equal, the offset (i.e., the Hall voltage measured in the absence of a magnetic field) is zero. As is well known in the art, if one of the four resistors R1, R2, R3, and R4 is different while the other three are equal, the offset of the Hall element can be canceled by applying a current rotation technique. In US2016 / 0154066A1, it is shown that the offset can be canceled as long as two resistors R1 and R3 or two resistors R2 and R4 are equal.

[0055] In Figure 6 , the four resistors R1, R2, R3, and R4 of the vertical Hall element 100 are shown. In Figure 7 , the geometric dimensions of the vertical Hall element 100 are drawn. L represents the size of terminals 1 and 2 in the direction of the cut line A - A'. L' represents the size of terminals 3 and 4 in the direction of the cut line A - A'. The sizes of the terminals are respectively defined by the lateral dimensions of the highly doped regions 103 and 303. T represents the thickness of the thinned silicon substrate. P represents the distance between the centers of terminals 1 and 2 on the first surface 101a. Since terminal 4 has the same but opposite position as terminal 1 and terminal 3 has the same but opposite position as terminal 2, the distance between the centers of terminals 3 and 4 on the second surface is also P. D represents the distance between the edge of terminal 1 and the boundary of the well 102 along the direction of the cut line A - A'. On the Figure 7 right side, the distance between the edge of terminal 2 and the boundary of the well 102 is also D. The distance D can also be zero.

[0056] For the vertical Hall element 100 as shown in Figure 6 and Figure 7 , the resistors R2 and R4 are not necessarily equal. Possible reasons for the difference between R2 and R4 are, for example, the doping gradient of the well 102, the difference in contact resistance on the first and second surfaces, or the additional series resistance associated with the silicon via. However, in practice, the size L' of terminals 3 and 4 can be adjusted relative to the size L of terminals 1 and 2 such that the resistors R2 and R4 are approximately equal.

[0057] Similarly, for the vertical Hall element 100 as shown in Figure 6 and Figure 7 , the resistors R1 and R4 are not necessarily equal. However, in practice, for a given substrate thickness T and distance D to the boundary of the well 102, the distance P between terminals 1 and 2 can be adjusted such that the resistors R1 and R4 are approximately equal.

[0058] For geometric reasons, if the distances D from terminal 1 and terminal 2 to the boundary of the well are the same, then the resistances R1 and R3 are equal. If, due to imperfections in the manufacturing process, terminal 3 and terminal 4 are not aligned with respect to terminal 1 and terminal 2 in the x direction (along the cut line A - A′), or if the well 102 is not aligned with respect to terminal 1 and terminal 2 in the x direction, the equality of R1 and R3 no longer holds. However, if D is very large, even if terminal 3 and terminal 4 are not aligned in the x direction, R1 and R3 are approximately equal. Similarly, if D is very large, even if the well 102 is not aligned with respect to terminal 1 and terminal 2, R1 and R3 are approximately equal.

[0059] After optimizing the design parameters P, T, D, L, and L′, the vertical Hall element can be represented by a Wheatstone bridge, where the values of the four resistances R1, R2, R3, and R4 are almost all equal. In other words, the vertical Hall element has approximate fourfold symmetry.

[0060] In operation, terminal 1 of the vertical Hall element 100 can be connected to a current source, and terminal 3 can be connected to ground. In this way, a current is forced to flow through the Hall sensor region in an approximately diagonal direction. A Hall voltage can be obtained between terminal 2 and terminal 4. The Hall voltage represents the magnetic field perpendicular to the plane of terminals 1, 2, 3, and 4. Similarly, terminal 2 can be connected to the current source, and terminal 4 can be connected to ground. Then a Hall voltage can be obtained between terminal 1 and terminal 3. The Hall voltage again represents the magnetic field perpendicular to the plane of terminals 1, 2, 3, and 4. Along the same line, terminal 3 can be connected to the current source, and terminal 1 can be connected to ground. The Hall voltage obtained between terminal 4 and terminal 2 again represents the magnetic field perpendicular to the plane of terminals 1, 2, 3, and 4. Along the same line, terminal 4 can be connected to the current source, and terminal 2 can be connected to ground. The Hall voltage obtained between terminal 1 and terminal 3 again represents the magnetic field perpendicular to the plane of terminals 1, 2, 3, and 4. These are the four phases of the rotating current method considered for the vertical Hall element 100.

[0061] Due to the approximate fourfold symmetry of the vertical Hall element, the offset of each individual phase of the operation is already small. As a result, by averaging all four phases, a very small residual offset value can be obtained. As is known to those skilled in the art, the current rotation technique can be combined with the orthogonal coupling of two or four Hall elements to further reduce the residual offset.

[0062] Figure 40 and Figure 41 A vertical Hall element 600 is shown, which represents another embodiment of the present invention. In Figure 40 it, the vertical Hall element 600 is depicted as seen from above (looking at the first silicon surface). Figure 41 is shown along Figure 40The vertical Hall element 600 intercepted in the direction of the cutting line A-A' shown in the figure. Similar to the vertical Hall element 100, the vertical Hall element 600 is formed on a semiconductor substrate 101, and the semiconductor substrate 101 can be a low-doped silicon substrate with a first conductivity type. The Hall terminals 1 and 2 formed on the first surface 101a are in contact with the well 102, and the well 102 extends from the first surface 101a into the substrate and is exposed at the second surface 101b. Two Hall terminals 3 and 4 formed on the second surface are in contact with the well 102. The well 102 preferably has n-type conductivity, which can be the conductivity of the first type or the second type. The highly doped regions 103 and 303 have the same conductivity type as the well 102, that is, n-type. As Figure 40 shown, the Hall terminals 1 and 2 arranged in the well 102 are completely surrounded by the deep trench isolation structure 601. The well 102 extends to the inner surface 601c of the deep trench isolation structure 601 in the x direction and the y direction, so that there is no boundary between the well 102 and the substrate 101 inside the deep trench. Refer to Figure 41 , the deep trench isolation structure extends from the first surface 101a to the second surface 101b. The inner surface 601c surrounded by the deep trench isolation is in contact with the well 102 everywhere. The deep trench isolation structure is composed of a dielectric material.

[0063] As in the first embodiment, the design of the vertical Hall element 600 can be optimized to achieve approximate four-fold symmetry. As a result, the offset of the vertical Hall element 600 can also be effectively reduced. In addition, since the Hall sensor region 102 of the vertical Hall element 600 is bounded by dielectric isolation, no depletion region is formed along the boundary of the well 102 during the operation of the vertical Hall element 600.

[0064] Therefore, the vertical Hall element of the second embodiment also has the characteristic of high linearity.

[0065] Combined with Figure 42Another embodiment of the present invention is given. A vertical Hall element 700 is formed on a semiconductor substrate 1001 having a first conductivity type (p-type or n-type). Terminals 1 and 2 are provided on the first surface 1001a, where the highly doped region 103 has the first conductivity type, i.e., the same conductivity type as the substrate 1001. Terminals 3 and 4 are provided on the second surface 1001b, which is obtained by thinning the main substrate from the second side. The highly doped region 303 also has the first conductivity type. T700 represents the thickness of the substrate 1001. The thickness T700 of the substrate 1001 can be in the range of 5 micrometers to 100 micrometers, and more preferably in the range of 10 micrometers to 50 micrometers. The deep trench isolation structure 601 surrounds the terminals 1 and 2 on the first surface and the terminals 3 and 4 on the second surface in the x-direction and y-direction. The deep trench isolation structure 601 extends from the first surface 1001a to the second surface 1001b. The deep trench isolation structure is composed of a dielectric material.

[0066] In the embodiment of the vertical Hall element 700, the Hall sensor region is constituted by the portion of the semiconductor substrate 1001 surrounded and limited by the deep trench isolation structure 601. As in the first and second embodiments, the design of the vertical Hall element 700 can be optimized to achieve approximate four-fold symmetry with respect to the four terminals. Since the Hall sensor region is defined by the dielectric material of the deep trench isolation structure 601, no depletion region is formed during the operation of the vertical Hall element 700, thus ensuring high linearity. The sensitivity of the vertical Hall element 700 depends on the conductivity type of the substrate 1001, the doping level of the substrate 1001, the thickness T700, etc. The inventors have recognized that if the thickness T700 is within the preferred range of 10 micrometers to 50 micrometers, a relatively high sensitivity can be obtained for the vertical Hall element 700 by using a semiconductor substrate having n-type conductivity and an optimal doping concentration.

[0067] Figure 8 and Figure 9 shows a circular vertical Hall element according to another embodiment of the present invention. In Figure 8 is drawn a vertical Hall element 200 as seen from above (looking at the first surface 101a of the semiconductor substrate 101). Figure 9A cross-sectional view of a circularly cut vertical Hall element 200 taken along the path shown between C and C' is provided. The circular vertical Hall element 200 has N terminals disposed on a first surface 101a and N terminals disposed on a second surface 101b of a thinned semiconductor substrate 101. The N terminals on the first surface are arranged in a circle and are formed in an annular well 102. The annular well 102 constitutes the Hall plate or Hall sensor region of the circular vertical Hall element 200. The annular well 102 extends from the first surface 101a and is exposed at the second surface 101b, which is obtained by thinning the semiconductor substrate 100 from the second side. The N terminals on the first silicon surface have equal sizes and are equally spaced. The N terminals disposed on the second surface are also arranged in a circle such that the two circles are concentric and have the same radius. The N terminals disposed on the second silicon surface also have equal sizes, are equally spaced, and are in contact with the annular well 102 exposed on the second surface. Further, this arrangement is such that: for each terminal k on the first surface 101a, there is a terminal k' on the second surface 101b that is directly below the terminal k, i.e., the vertical line connecting the center of the terminal k and the center of the terminal k' is perpendicular to the silicon surface 101a. Further, N = 2M, where M is an integer greater than 2. In Figure 8 it, a possible direction of the magnetic field B is also shown.

[0068] Figure 10 is a simplified representation of the terminals on the first surface 101a and the second surface 101b taken along a circular cut line as Figure 8 shown. The first vertical Hall sub-element is formed by four terminals 1, 2, 2' and 1'. This vertical Hall sub-element is denoted by H(1). Moving one step to the right, a second vertical Hall sub-element can be formed by four terminals 2, 3, 3' and 2'. This vertical Hall sub-element can be denoted by H(2). The k-th vertical Hall sub-element is constituted by four terminals k, k + 1, (k + 1)' and k'. The k-th vertical Hall sub-element is denoted by H(k). By having N terminals on the first surface and N terminals on the second surface, N such vertical Hall sub-elements can be formed. However, by increasing the step size, a number less than N of vertical Hall sub-elements can also be formed in this way. Since usually not all N vertical Hall sub-elements are measured at the same time, they are referred to as temporary vertical Hall elements. During the operation of the k-th vertical Hall sub-element, all terminals that do not belong to the k-th vertical Hall sub-element are in an open state.

[0069] In a manner similar to the vertical Hall element 100, the design parameters of the circular vertical Hall element 200 can be optimized (in Figure 9(not shown in the figure) such that each temporary Hall element H(k) has approximate four-fold symmetry. As a result, a very low residual offset can be achieved for each temporary Hall element.

[0070] Figure 11a and Figure 11b and Figure 11c and Figure 11d show the application of the rotating current method to the first temporary vertical Hall element H(1). In Figure 11a , terminal 1 is connected to the current source and terminal 2′ is connected to ground. The Hall voltage is obtained between terminals 2 and 1′. All other terminals are not connected. The direction of the current flowing through well 102 is indicated by the arrow. This is the first phase of the current rotation. In the second phase, as shown in Figure 11b , terminal 2 is connected to the current source and terminal 1′ is connected to ground. The Hall voltage is obtained between terminals 2′ and 1. All other terminals are not connected. The direction of the current is shown again and is rotated with respect to the first phase. In Figure 11c and Figure 11d , the third phase and the fourth phase are shown respectively. By averaging the voltages obtained for all four phases, a stable Hall voltage of the first temporary vertical Hall element H(1) is obtained. In the same manner, the rotating current method is applied to the next temporary vertical Hall element H(2). In the same manner, the rotating current method is applied to the temporary vertical Hall element H(k).

[0071] By sequentially measuring N temporary Hall elements H(k) (k = 1...N), the direction of the magnetic field in the x-y plane can be evaluated. In addition, measuring a suitable subset of the N temporary Hall elements may be sufficient to determine the direction of the magnetic field. In addition, the following measurement scheme can be envisioned: If the interaction between two or more temporary Hall elements is small, two or more temporary Hall elements are measured at the same time. In any case, by reducing the offset of each temporary Hall element, the accuracy of determining the direction of the magnetic field in the x-y plane can be improved.

[0072] Figure 13 and Figure 14 show alternative embodiments of the present invention. In Figure 13 , a circular vertical Hall element 300 is shown as seen from above (looking at the first surface 101a). In Figure 14 , the circular vertical Hall element 300 is shown along the cutting line shown in the x direction from D to D′. The circular vertical Hall element 300 differs from the circular vertical Hall element 200 only in that there are two additional annular isolation structures 301a and 301b. From Figure 14It can be seen that the isolation structures 301a and 301b extend from the first surface 101a of the thinned silicon substrate to the second surface 101b. The two annular isolation structures 301a and 301b are concentric with the annular well 102. The region laterally surrounded by the two annular isolation structures is the well 102. In this way, the isolation structures 301a and 301b laterally isolate the well 102 from the substrate 101. There is no longer a p-n junction between the well 102 and the substrate 101. The isolation structures 301a and 301b are made of a dielectric material. The isolation structures can be realized by etching two annular trenches from the second surface 101b of the substrate towards the first surface 101a and filling the trenches with a dielectric material (e.g., silicon oxide).

[0073] As is known to those skilled in the art, if a voltage is applied between two terminals in an n-type Hall plate, a depletion region is formed along the p-n junction that defines the Hall plate. Since the depletion region reduces the effective size of the Hall plate, the resistance of the Hall plate increases. This effect introduces non-linearity, which hinders offset cancellation. This is known to those skilled in the art. In the embodiment 300 of the circular vertical Hall element, the Hall sensor region 102 is not defined by a p-n junction. The dielectric isolation of the Hall sensor region 102 thus further reduces the offset.

[0074] Figure 15 A semiconductor device 400 having one or more vertical Hall elements is shown. The semiconductor device 400 can be a Hall IC, such as a Hall IC for angular position measurement. On Figure 15 the left side, a vertical Hall element with a silicon via 310 is shown. This part of the figure is the same as Figure 4 . On Figure 15 the right side, two transistors 143 and 153 are shown, which should represent the circuitry required to operate the vertical Hall element. If the substrate is p-type, the transistor 143 is an NMOS, and the transistor 153 is a PMOS. On Figure 15 the far right, a second silicon via (represented by 311) is shown. The silicon via 311 is part of the I / O of the semiconductor device 400. 309 represents a bonding pad. The bonding pad 309 is formed with a metal layer 305. The silicon via 311 enables the connection between the wiring formed on the first surface of the substrate and the bonding pad 309 formed on the second surface of the thinned substrate 101. 106b represents the landing pad of the silicon via 311. The landing pad 106b is connected to the wiring (not shown) disposed in the dielectric layer 104. In Figure 15 , two metal layers are shown on the first surface. However, there can also be more than two metal layers.

[0075] Figures 16 to 26Shows the manufacturing steps for fabricating a semiconductor device 400. The basic manufacturing steps are described in patent EP2913847(A1), which is incorporated herein by reference in its entirety. Hereinafter, only the significant differences will be highlighted.

[0076] As Figure 16 shown, a well 102 is formed in a substrate 101 of a first conductivity type. The well 102 has a second conductivity type. The well 102 can be formed by a series of masked implantation steps with variable implantation energy. The series of implantation steps can include high-energy implantation with energy in the MeV range. After removing the mask, furnace annealing is applied at a temperature between 1000 °C and 1200 °C for several hours. The implantation and furnace annealing conditions are optimized to achieve a uniform dopant concentration in the vertical direction. In Figure 16 it, T1 represents the depth of the well 102 after furnace annealing. The depth T1 is greater than 4 μm, and preferably greater than 6 μm.

[0077] In the following series of drawings, the formation of isolation structures such as shallow trench isolation (STI) is not shown. However, it is assumed that shallow trench isolation is applied, and it can even be present in the area of the vertical Hall element.

[0078] As Figure 17 shown, transistor wells 112 and 113 are formed. 112 represents a p-type well in which an NMOS transistor is formed, and 113 represents an n-type well in which a PMOS transistor is formed. The respective depths T2 and T3 of the wells 112 and 113 are lower than the depth T1 of the well 102.

[0079] Turning to Figure 18 , transistor gates 115 and 116 for PMOS and NMOS, and highly doped regions 103 and 113 are formed. 103 represents a shallow highly doped region of the second conductivity type, and 113 represents a shallow highly doped region of the first conductivity type. Although the highly doped regions 103 and 113 respectively constitute the source and drain regions of the NMOS and PMOS transistors, 103 is also used to form the highly doped region of the Hall terminal on the first surface 101a. Alternatively, dedicated masks and processing steps can be used to define the doped region 103 in the Hall sensor region 102.

[0080] In Figure 19 , an interconnect layer is formed using a standard CMOS metallization scheme known in the art. Metal portions 106a and 106b are embedded in the dielectric stack 104 to serve as landing pads for forming vias in silicon. The top surface 104a of the dielectric stack 104 is planarized by chemical mechanical polishing.

[0081] In Figure 20In [the description], a carrier wafer 201 is provided. The carrier wafer 201 can be an inexpensive silicon substrate. The substrate 101 is flipped.

[0082] Go to Figure 21 , the substrate 101 is bonded to the carrier substrate 201, and then, the substrate 101 is thinned from the second side. 101c represents the initial second surface of the substrate before the thinning process, and 101b represents the second surface of the substrate after thinning. T represents the thickness of the thinned silicon substrate. T is less than the depth T1 of the well 102. Thus, after thinning, the well 102 is exposed at the second surface.

[0083] Go to Figure 22 , a highly doped region 303 is formed in the well 102 on the second surface 101b. The highly doped region 303 has a second conductivity type and is formed by shallow masking and high-dose implantation followed by laser thermal annealing.

[0084] Figure 27 A semiconductor device 500 having one or more vertical Hall elements 300 is shown. The semiconductor device 500 can be a Hall IC, such as a Hall IC for angular position measurement. Contrary to the semiconductor device 400, the semiconductor device 500 includes one or more vertical Hall elements 300 having a Hall sensor region 102 defined by an isolation structure 301.

[0085] Figures 28 to 39 Manufacturing steps for manufacturing the semiconductor device 500 are shown. The basic manufacturing steps are described in patent EP2913847(A1), which is incorporated herein by reference in its entirety.

[0086] Go to Figure 35 , a trench 325 is etched from the second surface 101b into the semiconductor substrate 101, which extends to the first surface 101a. A mask 324 for trench etching laterally confines the Hall sensor region 102 by the trench 325. Subsequently, the trench 325 is filled with a dielectric material such as silicon oxide.

[0087] Figure 43 , Figure 44 and Figure 45 A second embodiment of the vertical Hall element 100 is shown. In Figure 43 , a vertical Hall element is shown as seen from above (looking at the first silicon surface). Two cutting lines are shown, one cutting line parallel to the x direction from A to A′ and one cutting line parallel to the y direction from B to B′. Figure 44 A cross-section of the vertical Hall element 100 taken along the cutting line A - A′ is shown, Figure 45Shows a cross-section of a vertical Hall element 100 taken along the cutting line B - B'. The vertical Hall element 100 is formed on a semiconductor substrate 101. The semiconductor substrate 101 can be a lightly doped silicon substrate having a first conductivity type. The first conductivity type is preferably p-type. The substrate has a first surface 101a and a second surface 101b. These two surfaces are opposite to each other and parallel to each other. The second surface 101b is obtained by thinning the substrate from the back side (i.e., from the side opposite to the first surface 101a). A doped region 102 is formed, which extends from the first surface 101a to the second surface 101b. The doped region 102 has a second conductivity type, i.e., the region 102 has n-type conductivity. The region 102 can be doped with phosphorus, and the dopant concentration can be in the range of 1×10 14 / cm 3 to 1×10 17 / cm 3 . Preferably, the dopant concentration is uniform in the vertical direction. In the well 102, two doped regions represented by 152a and 152c are provided. The doped region 152a and the doped region 152c have a second conductivity type. They can be doped with phosphorus, and the dopant concentration can be in the range of 1×10 17 / cm 3 to 1×10 21 / cm 3 .

[0088] As Figure 44 shown, the doped region 152a and the doped region 152c are buried in the region 102. Preferably, the positions of the doped region 152a and the doped region 152c in the z direction are approximately at half the distance between the first surface 101a and the second surface 101b. In addition, there are wells 103a and 103c having a second conductivity. The well 103a extends from the first surface 101a into the doped region 102 and reaches the buried region 152a. In the same way, the well 103c extends from the first surface 101a into the doped region 102 such that the well 103c contacts the buried region 152c. At the first surface 101a, shallow highly doped regions 103a, 103b, and 103c are formed that extend from the first surface into the doped region 102. The highly doped regions 103a, 103b, and 103c have a second conductivity type. The dopant concentration can be in the range of 1×10 19 / cm 3 to 1×10 22 / cm 3 .

[0089] As Figure 43As shown, the highly doped regions 103a, 103b, and 103c are arranged in a row along the x direction. The doped region 103b is located between the doped region 103a and the doped region 103c in such a way that the distance between the doped region 103a and the doped region 103b is equal to the distance between the doped region 103b and the doped region 103c. In addition, the highly doped regions 103a, 103b, and 103c are provided inside the region 102. The highly doped region 103a is arranged inside the well 151a, and the highly doped region 103c is arranged inside the well 151c.

[0090] Turning back again to Figure 44 , a dielectric layer 104 is provided on the first surface 101a. The dielectric layer 104 may include several layers of silicon nitride, silicon oxide, or low-k dielectrics commonly used in CMOS manufacturing processes. The metal contacts 105a, 105b, and 105c are embedded in the dielectric layer 104. The metal contact 105a is placed on the highly doped region 103a, thereby achieving electrical connection with the highly doped region 103a, thus electrically connecting with the well 151a, and further electrically connecting with the buried region 152a. The metal contact 105b is placed on the highly doped region 103b, thereby achieving electrical connection with the highly doped region 103b. In addition, the metal contact 105c is placed on the highly doped region 103c, thereby achieving electrical connection with the highly doped region 103c, thus electrically connecting with the well 151c, and further electrically connecting with the buried region 152c.

[0091] As Figure 45 shown, a plurality of metal contacts may be placed on the highly doped region 103b, and similarly, also on the highly doped regions 103a and 103c. In a typical CMOS manufacturing process, metal silicide may be formed on the highly doped regions 103a, 103b, and 103c. The metal contacts 105a, 105b, and 105c may be made of tungsten or other suitable metals. In Figure 43 and Figure 44 , a first metal layer is shown to be embedded in the dielectric layer 104. Generally, CMOS metallization may include several metal layers and vertical interconnections. For simplicity, only one metal layer is shown in Figure 44 and Figure 45 . 106a, 106b, and 106c represent metal wirings formed by this first metal layer, respectively connecting to the metal contacts 105a, 105b, and 105c.

[0092] As Figure 45As shown, the metal wiring 106b is oriented along the y direction. Moreover, the metal wirings 106a and 106c are oriented along the y direction. The carrier 201 is attached to the top surface 104a of the dielectric layer 104. The carrier 201 can be a silicon wafer. On the second surface 101b of the substrate 101, a fourth shallow highly doped region is formed, which is denoted by 303d. The highly doped region 303d extends from the second surface 101b into the doped region 102. The doped region 303d has a second conductivity type, and the dopant concentration is in the range of 1×10 19 / cm 3 to 1×10 22 / cm 3 . The doped region 303d has the same but opposite position as the doped region 103b. More precisely, if a connection line is drawn from the center of the doped region 103b at the first surface 101a to the center of the doped region 303d at the second surface 101b, then this connection line is perpendicular to the surfaces 101a and 101b. The dielectric layer 304 is provided on the second surface 101b. The dielectric layer can be composed of silicon oxide. A metal contact 305d is formed in the dielectric layer 304 to establish an electrical connection with the highly doped region 303d.

[0093] The metal contact 305d can extend to the metal wiring formed on the dielectric layer 304, as shown in Figure 43 and Figure 44 . The metal wiring is oriented parallel to the y direction, as shown in Figure 44 . The metal contact and wiring 305b can be composed of aluminum. Alternatively, the contact hole formed in the dielectric layer 304 can be filled with tungsten. In this case, the wiring portion of 305d provided on the dielectric layer 304 can be composed of aluminum or copper. Other metallization schemes can also be conceived. A passivation layer 308 is provided on the metal wiring 305d and the dielectric layer 308.

[0094] The passivation layer 308 can be composed of silicon oxide, silicon nitride, silicon oxynitride, or a layered stack of these materials. In the embodiments shown in Figure 43 , Figure 44 and Figure 45 , there are additionally doped wells 153, which extend from the first surface 101a into the doped region 102. The two doped wells 153 are respectively located between the central highly doped region 103b and the two highly doped regions 103a and 103c on the left and right. As shown in Figure 41 and Figure 42 , the two doped wells 153 can respectively be adjacent to the wells 151a and 151c. The wells 153 can have a depth similar to that of the wells 151a and 151c, and can reach down to the buried doped regions 152a and 152c, as shown in Figure 43 . The doped wells 153 have a first conductivity type.

[0095] In the following, reference is made to Figure 45 , Figure 45 again shows a vertical Hall element 100 along the cutting line B-B'. The doped region 102 forms the Hall sensor region or Hall plate of the vertical Hall element 100. The doped region 102 is laterally (i.e., in the x-direction and y-direction) bounded by a p-n junction formed using a substrate 101 having a polarity opposite to that of the well 102. In the following, reference is made to Figure 46 , Figure 46 again shows a vertical Hall element 100 along the cutting line A-A'. The vertical Hall element 100 has four Hall terminals (denoted by the capital letters A, B, C, and D). The Hall terminal B is arranged on the first surface 101a. From an operational perspective, the terminal B of the vertical Hall element 100 is defined by the spatial dimensions of the highly conductive region 103b. The Hall terminal D is arranged opposite to the terminal B on the first surface 101b. Again, from an operational perspective, the terminal D of the vertical Hall element 100 is defined by the spatial dimensions of the highly conductive region 303d. The Hall terminal A includes a highly conductive buried region 152a, where the well 151a provides a connection to the first surface, and where the terminal A is accessed via the highly doped region 103a and a metal contact disposed thereon. In the same way, the terminal C includes a highly conductive buried region 152a, where the well 151c provides a connection to the first surface 101a, and where the terminal C is accessed via the highly doped region 103c and a metal contact disposed thereon. The well 153 having a polarity opposite to that of the doped regions 102, 151a, 152a, 151c, and 152c is used to electrostatically shield the active sensor region between the four Hall terminals from the wells 151a and 151c.

[0096] In Figure 46Four arrows are drawn in [the figure], which are represented by the numbers 1, 2, 3, and 4 respectively. Each arrow represents the direction of the operating current driven to flow through the Hall sensor region. Therefore, the four arrows represent four possible operating modes or phases of the vertical Hall element. Starting from operating mode 1, the current is forced to flow between terminal B and terminal D in the direction from terminal B to terminal D. In this mode, a Hall voltage is obtained between terminal C and terminal D, and this Hall voltage represents the magnetic field component pointing in the y direction. In operating mode 2, the current is forced to flow between terminal C and terminal A in the direction from terminal C to terminal A. A Hall voltage is obtained between terminal B and terminal C, and this Hall voltage again represents the magnetic field component pointing in the y direction. Operating mode 3 corresponds to operating mode 1, except that the current direction is opposite, and a Hall voltage is obtained between terminal D and terminal C. Similarly, operating mode 4 corresponds to operating mode 2, except that the current direction is opposite and terminals B and D are commutated with respect to operating mode 2. Since terminal D is located at the second surface 101b, the current can be forced to flow through the Hall element 100, and the current flows through the Hall sensor region 102 substantially vertically. Since the highly conductive regions 152a and 152c are buried in the doped region 102, the current can be forced to flow through the Hall sensor element, and the current flows substantially parallel to the first surface 101a at a certain depth, and this depth is determined by the depth of the highly conductive regions 152a and 152c.

[0097] Compared with a conventional vertical Hall element in which all terminals are arranged on the main surface of the substrate, the specific Hall terminal configuration of the vertical Hall element 100 (having two buried terminals (A and C), one terminal on the first surface 101a (B), and one terminal on the second surface 101b (D)) can in principle achieve a higher voltage-related sensitivity.

[0098] It will be apparent to those skilled in the art that the vertical Hall element 100 can be designed such that for each of the four operating modes, the offset (i.e., the Hall voltage measured at zero magnetic field) is low. Important design parameters are the thickness of the substrate 101 (the distance between the first surface 101a and the second surface 101b), the depth of the highly conductive regions 152a and 152b, the lateral spacing depth of the highly conductive regions 152a and 152b, and the spatial dimensions of the highly doped regions 103b and 303d. As already pointed out, the highly doped regions 103a, 103b, and 103c are arranged in a row along the x direction, and the highly doped region 103b is located in the middle between the highly doped regions 103a and 103c. The highly doped region 303d has the same but opposite position as the highly doped region 103b. Those skilled in the art will understand that there are more design parameters regarding the layout and doping conditions that can be optimized in the direction of achieving low offset values in the four operating modes. Optimization methods (e.g., TCAD simulation and design of experiments) are known in the art. As a result, an approximate fourfold symmetry is obtained with respect to the four terminals, thereby resulting in low offset values for the four operating modes. As is known in the art, the offset can be further reduced by averaging the four operating modes. Current rotation and orthogonal coupling of two or four Hall elements are known techniques that are often employed in the industry and can also be applied to the vertical Hall element 100.

[0099] In Figure 47 is shown a vertical Hall element 200, which represents another embodiment of the inventive concept. The Hall element 200 differs from the Hall element only in the absence of the shielding well 153.

[0100] In Figure 48 is shown another embodiment of the present invention, which shows a vertical Hall element 300 along a cut line in the x direction. The connection wells 151a and 151c are respectively surrounded by dielectric structures denoted by 154. The dielectric structure 154 may have a depth similar to that of the wells 151a and 151c. The well 151a may be surrounded laterally (i.e., in the xy plane) by the dielectric structure 154, and in the same manner, the well 151c may be surrounded laterally by a second dielectric structure 154. The dielectric structure may be composed of silicon oxide or another dielectric material. The dielectric structure 154 may also be a trench that has a lining made of a dielectric material (e.g., silicon oxide) and is further filled with polysilicon. The dielectric structure 154 enhances the shielding of the wells 151a and 151c, thereby enhancing the buried characteristics of the terminals A and C.

[0101] In Figure 49Another embodiment is shown. The vertical Hall element 400 differs from the vertical Hall element 300 in that there are no buried regions 152a and 152c. In this embodiment, the buried terminals A and C are defined by wells 151a and 151c, respectively. The wells 151a and 151c are surrounded by dielectric structures 154, respectively. Thus, the wells 151a and 151c are in electrical contact with the Hall sensor region 102 only at their bottom surfaces. Compared with the vertical Hall element 300, the depths of the wells 151a and 151c and the depths of the corresponding dielectric structures 154 are increased.

[0102] Combined with Figure 50 , Figure 51 and Figure 52 Another embodiment of the present invention is given. The vertical Hall element 500 differs from the vertical Hall element 100 in that the doped region 102 for establishing the Hall sensor region is separated from the substrate 101 by a deep trench isolation structure 301. As Figure 51 and Figure 52 shown, the deep trench isolation structure 301 extends in the z direction from the first surface 101a of the substrate 101 to the second surface 101b.

[0103] Referring to Figure 50 , the doped region 102 is surrounded by the deep trench isolation structure in the x and y directions. The surrounding causes the doped region 102 to extend to the deep trench isolation structure 301 everywhere in the x and y directions. Inside the deep trench isolation structure 301, there is no boundary between the well 102 and the substrate 101.

[0104] During the operation of the Hall element, when a driving current flows through the Hall sensor region, depletion regions are formed along all the p-n junctions defining the Hall sensor region. Since the Hall sensor region 102 of the vertical Hall element 500 no longer has a p-n junction boundary with the surrounding substrate 101, no depletion region is formed at this boundary. However, during the operation of the vertical Hall element 500, depletion regions are formed along the shielding well 153 having the first conductivity. In another embodiment (not shown in the figure), the shielding well 153 in the vertical Hall element 500 is removed and replaced by a dielectric isolation structure 154 as in the vertical Hall element 300. In this embodiment, the Hall sensor region 102 is not defined by a p-n junction in any case.

[0105] During the operation of the Hall element, the depletion regions formed at the boundary of the Hall plate change the resistance of the Hall plate, thereby affecting the sensitivity and offset. Since the width of the depletion region is a function of the operating current, the Hall element will exhibit non-linear behavior. This non-linearity increases the calibration workload and the associated cost.

[0106] Figure 53is another representation of the vertical Hall element 100 along the cutting line B-B'. To supplement Figure 45 , a through-silicon via (TSV) is shown on the right side of Figure 53 . The through-silicon via provides a vertical conduction path through the substrate 101, which connects the highly doped region 303d disposed on the second surface 101b and representing the terminal D to the metal wiring formed on the first silicon surface. The through-silicon via associated with the terminal D is denoted as TSV(D). The through-silicon via TSV(D) contacts a portion 106d of the first metal layer embedded in the dielectric layer 104. At the second surface 101b, the through-silicon via TSV(D) is connected to the terminal D through the metal wiring 305d. In this way, the terminal D can be accessed at the point C(D). The terminal B formed on the first surface 101a can be electrically accessed at the point C(B). The through-silicon via is filled with a conductive material 305d, which can be the same material as the material for metallization on the second surface. The conductive filler 305d of the through-silicon via is isolated from the silicon substrate 101 by a dielectric lining 306 disposed on the inner surface of the through-silicon via. The distance between the through-silicon via and the well 102 in which the Hall terminal is formed is L. The current I driven through the through-silicon via generates a magnetic field parallel to the silicon surface. The intensity of the induced magnetic field at the position of the vertical Hall element is B = μ0 / (2πL)·I. To minimize the influence of such interference, the distance L can be set large enough. For example, if the Hall current is 1 mA and the distance L is set to 100 μm, the induced magnetic field intensity is 2 μT, which is much lower than the measurement resolution of available vertical Hall elements.

[0107] Figure 54 Shows a third embodiment of a semiconductor device 600 including a vertical Hall element.

[0108] Figures 55 to 65 Shows the manufacturing steps of a manufacturing method of a third embodiment of a semiconductor device 600 including a vertical Hall element. The basic manufacturing steps are described in the patent EP2913847(A1), which is incorporated herein by reference in its entirety.

[0109] Figure 66 Shows a fourth embodiment of a semiconductor device 700 including a vertical Hall element.

[0110] Figures 67 to 78 Shows the manufacturing steps of a manufacturing method of a fourth embodiment of a semiconductor device 700 including a vertical Hall element. The basic manufacturing steps are described in the patent EP2913847(A1), which is incorporated herein by reference in its entirety.

Claims

1. A vertical Hall element, comprising: - A substrate of a first conductivity type, having a first surface and a second surface; - A well, disposed in the substrate, the well having a second conductivity type; Wherein the well is exposed on both the first surface and the second surface of the substrate, and the vertical Hall element includes at least two terminals disposed on the first surface of the substrate and in contact with the well, and at least two other terminals disposed on the second surface of the substrate and in contact with the well, wherein the at least two other terminals on the second surface of the substrate are arranged to be below the at least two terminals on the first surface of the substrate in the orthogonal projection of the substrate. The vertical Hall element further includes: A dielectric layer, disposed on the first surface of the substrate; Wiring, embedded in the dielectric layer; and A through-silicon via filled with a conductive filler, the through-silicon via providing a vertical conduction path through the substrate for connecting one of the at least two other terminals on the second surface of the substrate to the wiring in the dielectric layer.

2. The vertical Hall element according to claim 1, - Wherein the at least two terminals on the first surface of the substrate include a first terminal and a second terminal arranged adjacent to each other on the first surface of the substrate. - Wherein the at least two other terminals on the second surface of the substrate include a third terminal and a fourth terminal arranged adjacent to each other on the second surface of the substrate. - Wherein the fourth terminal is located directly below the first terminal, such that the virtual straight line between the center of the first terminal and the center of the fourth terminal is perpendicular to the first surface and the second surface of the substrate. - Wherein the third terminal is located directly below the second terminal, such that the virtual straight line between the center of the second terminal and the center of the third terminal is perpendicular to the first surface and the second surface of the substrate.

3. The vertical Hall element according to claim 1, Wherein each of the at least two terminals on the first surface of the substrate includes a shallow first highly doped region extending from the first surface into the substrate, the first highly doped region having the second conductivity type.

4. The vertical Hall element according to claim 1, Wherein the at least two terminals on the first surface of the substrate are connected to a first metal layer of the wiring embedded in the dielectric layer.

5. The vertical Hall element according to claim 1, comprising: A carrier substrate bonded to the top surface of the dielectric layer, wherein the top surface of the dielectric layer is opposite to the surface of the dielectric layer disposed on the first surface of the substrate.

6. The vertical Hall element according to claim 1, Wherein each of the at least two other terminals on the second surface of the substrate includes a shallow second highly doped region extending from the second surface into the substrate, the second highly doped region having the second conductivity type.

7. The vertical Hall element according to claim 6, comprising: - The second dielectric layer, - The passivation layer, - wherein the second dielectric layer is disposed on the second surface of the substrate, and the passivation layer is disposed on the second dielectric layer.

8. The vertical Hall element according to claim 1, wherein the conductive filling of the through-silicon via is isolated from the substrate by a dielectric lining disposed on the inner surface of the through-silicon via.

9. The vertical Hall element according to claim 1, comprising: A deep trench isolation structure extending from the first surface of the substrate to the second surface of the substrate such that the well is isolated from the substrate by the deep trench isolation structure.

10. The vertical Hall element according to claim 1, wherein the vertical Hall element is configured as a circular vertical Hall element, the well is formed as an annular well, and the vertical Hall element has: a plurality of at least two terminals located on the first surface of the substrate in a first circle and in contact with the well; and a plurality of at least another two terminals located on the second surface of the substrate in a second circle and in contact with the well, wherein a corresponding one of the plurality of at least another two terminals on the second surface of the substrate is disposed below a corresponding one of the plurality of at least two terminals on the first surface of the substrate in the orthogonal projection of the substrate.

11. The vertical Hall element according to claim 10, comprising: Two annular isolation structures extending from the first surface of the substrate to the second surface of the substrate and concentric with the annular well such that the well is surrounded laterally by the two annular isolation structures and isolated from the substrate.

12. A vertical Hall element, comprising: - A substrate of a first conductivity type having a first surface and a second surface; - A well disposed in the substrate, the well having a second conductivity type; wherein the well is exposed on both the first surface and the second surface of the substrate, the vertical Hall element includes a first terminal, a second terminal, a third terminal, and a fourth terminal, the first terminal, the second terminal, the third terminal, and the fourth terminal are in contact with the well, each of the first terminal and the third terminal includes a connection region, the corresponding connection region provides the connection of the first terminal and the third terminal to the first surface of the substrate, and each of the first terminal and the third terminal is accessed via a doped region extending from the first surface of the substrate into the interior of the connection region, the second terminal is disposed on the first surface of the substrate between the first terminal and the third terminal, and the fourth terminal is disposed on the second surface of the substrate opposite to the second terminal, wherein each of the first terminal and the third terminal includes a conductive buried region buried in the well, and the corresponding connection region provides the connection of the conductive buried region to the first surface of the substrate.

13. The vertical Hall element according to claim 12, - wherein the second terminal includes a first conductive region that extends from the first surface of the substrate into the substrate, - wherein the fourth terminal includes a second conductive region that extends from the second surface of the substrate into the substrate, - wherein the fourth terminal is located directly below the second terminal such that a virtual straight line between the center of the first conductive region of the second terminal and the center of the second conductive region of the fourth terminal is perpendicular to the first surface and the second surface of the substrate.

14. The vertical Hall element according to claim 12, comprising: - a dielectric layer disposed on the first surface of the substrate, - a carrier attached to the top surface of the dielectric layer, wherein the top surface of the dielectric layer is opposite to the surface of the dielectric layer disposed on the first surface of the substrate.

15. The vertical Hall element according to claim 12, comprising: - a first doped well that extends from the first surface of the substrate into the well and extends downward to the first conductive buried region of the first terminal, - a second doped well that extends from the first surface of the substrate into the well and extends downward to the second conductive buried region of the third terminal.

16. The vertical Hall element according to claim 12, - wherein the first connection region of the first terminal is surrounded by a first dielectric structure, - wherein the second connection region of the third terminal is surrounded by a second dielectric structure.

17. The vertical Hall element according to claim 12, comprising: - a deep trench isolation structure that extends from the first surface of the substrate to the second surface, - wherein the well is isolated from the substrate by the deep trench isolation structure.

18. A semiconductor device, comprising: - the vertical Hall element according to claim 1, - a circuit for operating the vertical Hall element, wherein the circuit is configured to be an integrated circuit formed in the substrate.

19. The semiconductor device according to claim 18, - wherein the circuit includes: - a bonding pad formed on the second surface of the substrate, - a silicon via to provide a connection between the bonding pad and the wiring in the dielectric layer disposed on the first surface of the substrate.

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