Enhanced local routing and improved clocking; configurable logic block internal routing architecture

Abstract

This disclosure relates to a configurable logic block internal routing architecture with enhanced local routing and clock improvements. A system includes a pair of configurable logic blocks (CLBs) placed adjacent to each other, wherein each CLB includes a plurality of configurable logic elements. Multiple sets of inodes are configured to receive signals to and / or from the CLBs, wherein a first set of inodes is located on the left side of the adjacent CLB, and a second set of inodes is located on the right side of the adjacent CLB. A plurality of bnodes are embedded in the middle of the adjacent CLBs, wherein each bnode is configured to establish a first connection between the bnode and an inode in the first set of inodes on the left side of the CLB, and a second connection between the bnode and an inode in the second set of inodes on the right side of the CLB. Both the first and second routing connections are located within the pair of adjacent CLBs.

Description

Technical Field

[0001] This disclosure generally relates to internal routing for configurable logic blocks (CLBs) and a routing architecture for implementing the proposed CLB internal routing architecture. Background Technology

[0002] Recent advancements in Field-Programmable Gate Array (FPGA) architecture have reduced the size of wiring multiplexers (or multiplexers) due to NMOS / CMOS scaling, and also decreased the number of horizontal tracks required to maintain reasonable wire size and layer count. These changes reduce the connectivity between general interconnect routing and configurable logic block (CLB) input pins. Current approaches to address connectivity issues utilize interconnect nodes, or inode structures, to add connectivity to a single CLB chip. Here, inode structures are nodes used for interconnection, and these nodes can also serve as interfaces for conventional wiring.

[0003] As the size of transistors in a CLB continues to shrink, the interconnects have not shrunk accordingly, resulting in a reduction in the area available for general wiring of the interconnects. Meanwhile, the size of the CLB in some FPGA architectures has increased several times over. Therefore, using a large number of interconnects between individual chips in the CLB becomes impractical. Summary of the Invention

[0004] A system includes a pair of configurable logic blocks (CLBs) placed adjacent to each other, wherein each adjacent CLB includes a plurality of configurable logic elements. Multiple sets of inodes are configured to receive signals to and / or from the pair of adjacent CLBs, wherein a first set of inodes is located on the left side of the pair of adjacent CLBs, and a second set of inodes is located on the right side of the pair of adjacent CLBs. A plurality of bnodes are embedded in the middle of the adjacent CLBs, wherein each bnode is configured to establish a first connection between the bnode and an inode in the first set of inodes on the left side of the pair of adjacent CLBs, and a second connection between the bnode and an inode in the second set of inodes on the right side of the pair of adjacent CLBs. Both the first and second wiring connections are located within the pair of adjacent CLBs.

[0005] It is understood that each of the plurality of bnodes and inodes includes one or more multiplexers, wherein at least one group of bnodes among the plurality of bnodes shares multiple inputs of its one or more multiplexers. The plurality of bnodes are configured to route inputs from one inode in a first group of inodes to one of the plurality of bnodes, and to route inputs from a bnode to all inodes in a second group of inodes to which the inputs are intended, without requiring any direct point-to-point connection between one inode in the first group of inodes and one inode in the second group of inodes. In some embodiments, one or more dedicated point-to-point connections are made between one inode in the first group of inodes on the left side of the CLB and one inode in the second group of inodes on the right side of the CLB, without utilizing the plurality of bnodes in the middle of adjacent CLBs for fast connections between inodes on either side of adjacent CLBs. In some embodiments, the plurality of bnodes are arranged into multiple groups, each group having four bnodes, wherein two bnodes in each group are configured to connect to the first group of inodes on the left side of the adjacent CLB, and two bnodes in that group are configured to connect to the second group of inodes on the right side of the adjacent CLB. In some embodiments, a plurality of bnodes are configured to serve as cross switches between the inputs and / or outputs of a first set of inodes and a second set of inodes on different sides of an adjacent CLB.

[0006] In some embodiments, the system includes: a configurable logic block (CLB) comprising a plurality of configurable logic elements; and a clock backbone of interconnects configured to provide one or more clock signals to the plurality of configurable logic elements via a plurality of control nodes (cnodes). The plurality of cnodes are connected to the plurality of configurable logic elements and are configured to drive control pins of the configurable logic elements using clock signals from the clock backbone. The clock backbone and the plurality of cnodes are embedded in the middle of the CLB, wherein the plurality of configurable logic elements in the CLB are located to the left and right of the clock backbone and the plurality of cnodes, and are all connected to the plurality of cnodes in the middle of the CLB.

[0007] These and other aspects can be understood by referring to the following detailed description. Attached Figure Description

[0008] To gain a more detailed understanding of the features described above, a more specific description of the brief overview can be obtained by referring to the example implementations, some of which are shown in the accompanying drawings. However, it should be noted that the drawings only show typical example implementations and should not be considered as limiting their scope.

[0009] Figure 1Examples of enhanced local routing CLB internal routing architectures for configurable logic blocks (CLBs) in FPGA architectures are depicted, based on some examples.

[0010] Figure 2 An example of an internal routing architecture for a CLB is described, where an input from one of the input multiplexers / inodes is first routed to one of the internal bnodes, which then route the input to all other input multiplexers / inodes.

[0011] Figure 3 An example of internal wiring within a CLB is depicted, where the faster path provides a dedicated point-to-point connection between one of the input multiplexers on the left side of the CLB and one of the input multiplexers on the right side of the CLB, without utilizing the internal bnode in the middle of the CLB.

[0012] Figure 4 Examples of CLB internal wiring / connection patterns are depicted, based on some examples, from the inode on the left side of the CLB to the inode on the right side of the CLB through a set of bnodes in the middle of the CLB.

[0013] Figure 5 An example of a bnode, comprising four 8×1 multiplexers shared in a 7:1 ratio across its inputs, is depicted, based on some examples.

[0014] Figure 6 An example of the internal wiring architecture of a CLB is depicted, based on some examples, in which the clock backbone and a set of cnodes are moved and embedded in the middle of the CLB;

[0015] Figure 7 It is a block diagram depicting a programmable integrated circuit (IC) according to some examples; and

[0016] Figure 8 It is implemented using a Field Programmable Gate Array (FPGA) based on some example programmable ICs.

[0017] For ease of understanding, the same reference numerals are used where possible to denote common elements in the figures. It is conceivable that elements of one example can be beneficially incorporated into other examples. Detailed Implementation

[0018] The examples described herein relate to enhanced internal local wiring and clock improvements for CLBs. Various features are described below with reference to the accompanying drawings. It should be noted that the drawings may be drawn to scale or not, and elements of similar structure or function are indicated by similar reference numerals throughout the drawings. It should be noted that the drawings are intended only to facilitate the description of features. They are not intended as an exhaustive description of the claimed invention or a limitation on the scope of the claimed invention. For example, various methods according to some examples may include more or fewer operations, and the order of operations in the various methods according to the examples may differ from that described herein. Furthermore, the examples shown need not possess all aspects or advantages shown. Aspects or advantages described in connection with a particular example are not limited to that example and may be practiced in any other example, even if not so shown or explicitly described.

[0019] A bounce is a connection between a pin of one multiplexer and a pin of another multiplexer (in this case, an inode). If the pin is unused or driven by the same network as the pin connected via the bounce line, the bounce line can be used as a bounce routing resource to route to another inode and another pin. Bounces are used for the versatility of inputs, allowing routing to hit a specific input without having to perform general routing. For CLBs, bounces exist on bypass pins. If a routing path can quickly utilize a bounce resource due to connectivity, the bounce resource provides an alternative path that reduces the use of conventional routing. A quick connection is the same type of wire connection but specific to output pins on the same module. Quick connections allow block output pins to be driven directly back to block output pins via a point-to-point connection through the inode structure. The purpose of quick connections is to achieve fast point-to-point paths and reduce the use of general routing from local block outputs to input pins.

[0020] There is a need for enhanced internal local routing and clock improvements for the CLB. A novel approach is proposed, in which a multiplexer layer is added in the middle of the CLB to create a large interconnect pattern within the CLB. This large interconnect pattern within the CLB can be used to route most drivers to load connections / pins within the CLB, and to improve the ability to route any inodes to the sides of the CLB. In some embodiments, the clock pins and / or multiplexed structures used to drive the flip-flop control pins are also moved to the middle of the CLB to reduce the horizontal tracks used for interconnects and to reduce the distance between the clock trunk and the flip-flop control pins, thereby reducing clock skew and clock power consumption.

[0021] The proposed method internalizes as many connections as possible to localize routing within the CLB, thereby reducing general-purpose routing requirements, as general-purpose routing resources have been decreasing in the latest generation of FPGA architectures. Under the proposed method, fast connections and bounce become scalable to large CLBs, and connectivity with the CLB's input / / inodes is significantly improved. In the worst case, the proposed method can also make paths through the CLB faster.

[0022] Figure 1 An example of a CLB internal routing architecture 100 with enhanced local routing for configurable logic blocks (CLBs) in an FPGA architecture is depicted. Figure 1 In the example shown, a set (e.g., 64) of bounce nodes (or bnodes) 104s are multiplexers embedded in the middle / between of two adjacent CLBs 102_1 and 102_2 for wiring versatility within the CLB at additional / lower layer wiring depths. The bnodes 104s are configured to connect to at least two sets of interconnects / input elements / multiplexers / nodes or inodes 106_1 and 106_2, respectively, located on the left and right sides of CLBs 102_1 and 102_2, for example, from input to output within the same CLB 102, to avoid long conventional interconnect wiring across CLB 102 by offloading congestion to local and inexpensive metal lines within the same CLB 102s. Specifically, each bnode 104 is configured to establish a first wiring connection 108_1 between bnode 104 and one of the inodes 106_1 to the left of CLB 102s, and a second wiring connection 108_2 between bnode 104 and one of the inodes 106_2 to the right of CLB 102s, wherein both the first and second wiring connections are located within adjacent CLBs 102s. Thus, instead of using relatively few fixed paths across CLBs 102 for fast connections from output to input, the CLB internal wiring architecture 100 achieves reliable, shorter-distance local wiring between any outputs and inputs of adjacent CLBs 104s without using or competing for limited global wiring resources.

[0023] In some embodiments, bnode 104s are driven by one or more of the following: local outputs of CLB 102s, horizontal routing resources, bypass pins, and inodes. Because both horizontal routing resources and bypass pins can drive bnode 104s, more inode inputs can be used for these connections when alternative routing paths become available. In some embodiments, bnode 104s are configured such that the inputs of the internal bnode 104s can reach all input multiplexers of inode 106s. Figure 2An example of an internal routing architecture 100 for a CLB is depicted, in which an input from one of inodes 106_1 is first routed to one of internal bnodes 104, where bnode 104 is then configured to route the input to all multiplexers / inodes 106_2 to which the input is intended. Thus, the internal routing architecture 100 for the CLB allows one of the input multiplexers 106_1 to the left of the CLB 102s to reach all inodes 106_2 to the right of the CLB 102s without requiring or consuming significant point-to-point global routing resources between the input multiplexers / inodes 106s.

[0024] In some embodiments, the CLB internal wiring architecture 100 is configured to include and enable a faster connection between the input multiplexers 106s on the left and right sides of the CLB 102 that bypass the bnodes 104s, and a slower connection that utilizes the bnodes 104s to reach the input multiplexer 106 on one side of the CLB 102, wherein the input multiplexer 106 may otherwise be unreachable. Figure 3 An example of the internal wiring architecture 100 of the CLB is depicted, wherein a dedicated point-to-point connection between one of the input multiplexers 106_1 on the left side of the CLB 102s and one of the input multiplexers 106_1 on the left side of the CLB 102s or the input multiplexer 106_2 on the right side of the CLB 102s provides a faster path 109_1 between the input multiplexers without using the intermediate internal bnode 104s of the CLB 102s. Figure 3 The internal cabling architecture 100 of the CLB also provides a slower path 109_2 for cabling from the input multiplexer 106_1 on the left side of the CLB 102s to one of the input multiplexers 106_2 on the right side of the CLB 102s via a "bounce-through" bnode 104s on an additional multiplexer layer. Thus, the cabling passes through the bnode 104s in the middle of the CLB 102s. Figure 3 The internal cabling architecture 100 of the CLB enables a limited number of fast point-to-point connections between the input multiplexers 106_1 and 106_2 on both sides of the CLB 102s, as well as the reachability of all input multiplexers 106_2 on the right side of the CLB 102s.

[0025] Figure 4 An example of the internal wiring / connection pattern of the CLB is depicted, from inode 106_1s on the left side of the CLB through a set of bnodes 104s in the middle of the CLB to inode 106_2s on the right side of the CLB. (See example...) Figure 4As shown in the example, there are 64 bnodes in the middle of the CLB, with two slices, 102_1 and 102_2, on the left and right sides of the CLB, respectively. These 64 bnodes can be arranged into 16 groups of four bnodes each, with two bnodes in each group connected to inode 106_1 on the left side of the CLB 102s, and two bnodes in the same group connected to inode 106_2 on the right side of the CLB 102s. The two groups of four bnodes are configured to connect to all quadrants of the CLB. Figure 5 An example of a bnode104 is depicted, comprising four 8×1 multiplexers sharing a 7:1 ratio among their inputs. As a non-limiting example, the inputs of a multiplexer may include four bypasses, three outputs, and one single shared pin.

[0026] In some embodiments, the group of bnodes 104s is configured to act as cross switches between the inputs and / or outputs of nodes 106_1s and 106_2s on different sides of the CLB by routing signals between nodes 106_1s and 106_2s, without requiring a direct point-to-point connection between inodes 106_1s and 106_2s (which could further increase the complexity of the cross switches as the number of inodes increases). In some embodiments, the group of bnodes 104s is configured such that signals from inodes 106s on the left and / or right sides of the CLB can first go to the bnodes 104s in the middle of the CLB and then from the group of bnodes 104s in the middle of the CLB to the inodes 106s on the left or right sides of the CLB. This connection mode increases the possibility of establishing local connections within the lower-level CLB without entering the conventional interconnect wiring of higher levels. Furthermore, the connection pattern allows signals from the general interconnect to find a path to the opposite pin / second inode via bnode 104s using a first inode hit, without having to backtrack to the general interconnect routing. As the new flow leads to a reduction in general interconnects in the architecture, it becomes more valuable to perform as many internal CLB connections as possible internally. Additionally, since FPGA-style interconnects are not designed for fast routing and backtracking, tight connections performed locally avoid routing interconnects in a loop and looping back (which typically results in higher latency and routing costs).

[0027] In some embodiments, the internal wiring architecture 100 of the CLB is configured to move and embed a clock backbone 110 and a set of control multiplexers / inodes 112s of the interconnects. The clock backbone 110 and the control multiplexers / inodes 112s are configured to provide clock signals to multiple flip-flops of a plurality of configurable logic elements 114s in the CLB 102 from one side / edge to the middle of the CLB 102, such as... Figure 6 As shown in the example, the configurable logic elements 114s in CLB 102 are located to the left and right of the clock backbone 110 and cnode 112s, and are all connected to multiple cnode 112s in the middle of the CLB. The main function of the clock backbone 110 is to provide clock signals to the control multiplexers / inodes 112s, which are connected to the configurable logic elements 114s on the left and right sides, and to drive the control pins of the flip-flops of the configurable logic elements 114s via the clock signals from the clock backbone 110. Moving the clock backbone 110 and cnode 112s to the middle of CLB 102 reduces the distance / line length from the clock backbone 110 and cnode 112s to the logic elements 114s in CLB 102, thereby reducing the horizontal rails used in the interconnects required to provide clock signals to the logic elements 114s. Because the configurable logic elements 114s in the CLB 102, located to the left and right of the clock backbone 110 and cnode 112s, are closer and have a shorter distance from the clock backbone 110, which is placed in the middle of the CLB 102, to the logic elements 114s to the left and right of the clock backbone 110, is narrower compared to the case where the clock backbone 110 is placed on one side of the CLB 102. As a result, the clock skew between the clock signals of the logic elements 114s is reduced. In addition, due to the tighter connection from the clock backbone 110 to control the logic elements 114s, clock power consumption is also reduced.

[0028] In some embodiments, one or more cnodes 112s embedded in the middle of CLB 102 are also configured to serve as additional bounce nodes to offload localized internal wiring within CLB 102, as discussed above, when cnodes 112s are not used to drive clock signals to logic elements 114s. Specifically, each of the one or more cnodes 112s is configured to establish a first wiring connection between cnode 112 and one of the configurable logic elements 114_1 to the left of cnode 112, and a second wiring connection between cnode 112 and one of the configurable logic elements 114_2 to the right of cnode 112, wherein both the first and second wiring connections are located within CLB 102. In some embodiments, the cnodes 112s embedded in the middle of CLB 102 are configured to serve as cross switches for inbound signals entering CLB 102 and internal feedback signals within CLB 102. In some embodiments, cnode 112s are used as an optional routing path to the input pins of CLB 102 without causing an increase in delay to the input pins, since the routing path is optional.

[0029] Figure 7 This is a block diagram depicting a programmable integrated circuit (IC) 900 according to an example. The programmable IC 900 can be implemented in whole or in part. Figures 1-6 The system is an integrated circuit (IC) chip. The programmable IC 900 includes a processing system 902, programmable logic 904, configuration logic 906, and configuration memory 908. The programmable IC 900 can be coupled to external circuitry, such as non-volatile memory 910, RAM 912, and other circuitry 914.

[0030] Processing system 902 may include a microprocessor, memory, support circuitry, I / O circuitry, etc. Programmable logic 904 includes logic units 916, support circuitry 918, and programmable interconnects 920. Logic units 916 include circuitry that can be configured to implement general-purpose logic functions with multiple inputs. Support circuitry 918 includes dedicated circuitry such as transceivers, input / output blocks, digital signal processors, memory, etc. Logic units and support circuitry 918 can be interconnected using programmable interconnects 920. Information for programming logic units 916, setting parameters for support circuitry 918, and programming programmable interconnects 920 is stored in configuration memory 908 via configuration logic 906. Configuration logic 906 can obtain configuration data from non-volatile memory 910 or any other source (e.g., RAM 912 or from other circuitry 914).

[0031] Figure 8An FPGA implementation of a programmable IC 900 is shown, comprising a large number of different programmable blocks, including configurable logic blocks (“CLBs”) 930, random access memory blocks (“BRAMs”) 932, signal processing blocks (“DSPs”) 934, input / output blocks (“IOBs”) 936, configuration and clock logic (“CONFIG / CLOCKS”) 938, digital transceivers 940, dedicated input / output blocks (“I / O”) 942 (e.g., configuration ports and clock ports), and other programmable logic 944, such as a digital clock manager, system monitoring logic, etc. The FPGA may also include a PCIe interface 946, an analog-to-digital converter (ADC) 948, etc.

[0032] In some FPGAs, each programmable block may include at least one programmable interconnect element (“INT”) 950, which has connections to input and output terminals 952 of programmable logic elements within the same block, such as... Figure 8 The example included is shown. Each programmable interconnect element 950 may also include a connection to an interconnect segment 954 of an adjacent programmable interconnect element in the same block or another block. Each programmable interconnect element 950 may also include a connection to an interconnect segment 956 of a general-purpose wiring resource between logic blocks (not shown). The general-purpose wiring resource may include wiring paths between logic blocks (not shown), which include interconnect segments (e.g., interconnect segment 956) and tracks for connecting switch blocks (not shown) to the interconnect segments. The interconnect segment of the general-purpose wiring resource (e.g., interconnect segment 956) may span one or more logic blocks. The programmable interconnect element 950, together with the general-purpose wiring resource, implements a programmable interconnect structure (“programmable interconnect”) for the FPGA shown.

[0033] In the example implementation, CLB 930 may include configurable logic elements (“CLE”) 960 that can be programmed to implement user logic and a single programmable interconnect element (“INT”) 950. In addition to one or more programmable interconnect elements, BRAM 932 may also include BRAM logic elements (“BRL”) 962. Typically, the number of interconnect elements included in a block depends on the block height. In the illustrated example, the BRAM block has the same height as five CLBs, but other numbers (e.g., four) may also be used. In addition to an appropriate number of programmable interconnect elements, signal processing block 934 may also include DSP logic elements (“DSPL”) 964. In addition to one instance of programmable interconnect element 950, IOB 936 may also include two instances, for example, input / output logic elements (“IOL”) 966. Those skilled in the art will appreciate that the actual I / O pads connected to, for example, the input / output logic elements 966 are typically not limited to the area of ​​the input / output logic elements 966.

[0034] In the illustrated example, the horizontal region near the center of the die is used for configuration, clock, and other control logic. The vertical column 968 extending from this horizontal region or column is used to distribute clock and configuration signals across the entire width of the FPGA.

[0035] use Figure 8 Some FPGAs in the architecture shown include additional logic blocks that disrupt the regular columnar structure that makes up a large part of the FPGA. These additional logic blocks can be programmable blocks and / or dedicated logic.

[0036] Notice, Figure 8 This is intended only to illustrate exemplary FPGA architectures. For example, Figure 8 The information at the top, including the number of logic blocks in a row, the relative width of the rows, the number and order of the rows, the types of logic blocks included in the rows, the relative sizes of the logic blocks, and the interconnect / logic implementation, is purely illustrative. For example, in a real FPGA, wherever a CLB appears, there is usually more than one adjacent CLB row to facilitate efficient implementation of user logic, but the number of adjacent CLB rows varies with the overall size of the FPGA.

[0037] Although the foregoing relates to specific examples, other and additional examples may be devised without departing from its essential scope, the scope of which is determined by the appended claims.

Claims

1. A circuit system comprising: a pair of configurable logic blocks (CLBs) placed next to each other, each CLB comprising a plurality of configurable logic elements; a first set of interconnect nodes (inodes) and a second set of inodes configured to accept input and / or output signals to and / or from the pair of CLBs, wherein the first set of inodes is located left of the pair of adjacent CLBs and the second set of inodes is located right of the pair of adjacent CLBs; and a plurality of bounce nodes (bnodes) embedded in the middle of the pair of adjacent CLBs, wherein each bnode of the plurality of bnodes is configured to establish a first routing connection between the bnode and one inode of the first set of inodes left of the pair of adjacent CLBs, and establish a second routing connection between the bnode and one inode of the second set of inodes right of the pair of adjacent CLBs, wherein the first routing connection and the second routing connection are both located in the pair of adjacent CLBs.

2. The system of claim 1, wherein each bnode of the plurality of bnodes and each inode of the first and second sets of inodes comprises one or more multiplexers.

3. The system of claim 2, wherein at least one set of bnodes of the plurality of bnodes shares a plurality of inputs of one or more multiplexers of the at least one set of bnodes.

4. The system of claim 1, wherein the plurality of bnodes are driven by one or more of a local output of the CLB, a horizontal routing resource, a bypass pin, and an inode.

5. The system of claim 1, wherein the plurality of bnodes are configured to: route an input from one inode of the first set of inodes of a plurality of sets of inodes to one bnode of the plurality of bnodes, and route an input from the one bnode of the plurality of bnodes to all inodes of the second set of inodes of the plurality of sets of inodes where the input is intended to reach without requiring any direct point-to-point connection between an inode of the first set of inodes and an inode of the second set of inodes.

6. The system of claim 1, further comprising: one or more dedicated point-to-point connections between one inode of the first set of inodes left of the CLB and another inode of the first set of inodes left of the CLB or another inode of the second set of inodes right of the CLB without utilizing the plurality of bnodes in the middle of the adjacent CLBs for fast connection between one inode and another inode on both sides of the adjacent CLBs.

7. The system of claim 1, wherein the plurality of bnodes are arranged into a plurality of groups, wherein each group comprises four bnodes, wherein two bnodes in each group are configured to connect to the first group of inodes left side of an adjacent CLB, and two bnodes in the group are configured to connect to the second group of inodes right side of the adjacent CLB.

8. The system of claim 1, wherein the plurality of bnodes are configured to function as crossbars between inputs and / or outputs of the first and second groups of inodes on different sides of an adjacent CLB, respectively.

9. The system of claim 8, wherein the plurality of bnodes are configured to: wire a signal from one inode in the first group of inodes left side of an adjacent CLB to one bnode in the plurality of bnodes in the middle of the CLB, and wire a signal from one bnode in the middle of the CLB to one or more inodes in the first group of inodes left side of the CLB or the second group of inodes right side of the CLB.

10. A circuit system comprising: a configurable logic block (CLB) comprising a plurality of configurable logic elements; a clock backbone of interconnect wires configured to provide one or more clock signals to the plurality of configurable logic elements via a plurality of control nodes (cnode); and the plurality of cnode connected to the plurality of configurable logic elements and configured to drive control pins of the configurable logic elements with the one or more clock signals from the clock backbone, wherein the clock backbone and the plurality of cnode are embedded in the middle of the CLB, wherein the plurality of configurable logic elements in the CLB are located left and right of the clock backbone and are all connected to the plurality of cnode in the middle of the CLB.

11. The system of claim 10, wherein each cnode in the plurality of cnode comprises one or more multiplexers.

12. The system of claim 10, wherein one or more cnode in the plurality of cnode embedded in the middle of the CLB are configured to function as a bounce node (bnode) to offload local internal wiring in the CLB when the one or more cnode are not used to drive the one or more clock signals to the plurality of configurable logic elements of the CLB.

13. The system of claim 12, wherein each cnode of the one or more cnode is configured to: establish a first wiring connection between the cnode and one configurable logic element in the plurality of configurable logic elements left side of the cnode, establish a second wiring connection between the cnode and one configurable logic element in the plurality of configurable logic elements right side of the cnode, wherein the first and second wiring connections are both located in the CLB.

14. The system of claim 10, wherein the plurality of cnodes embedded in the middle of the CLB are configured as crossbars for inbound signals into the CLB and internal feedback signals in the CLB.

15. The system of claim 10, wherein the plurality of cnodes wire signals from input pins of the CLB without causing an increase in delay to the input pins.

16. A wiring method, comprising: placing a pair of configurable logic blocks (CLBs) adjacent to each other, each CLB comprising a plurality of configurable logic elements; placing a first set of interconnect nodes (inode) to the left of a pair of adjacent CLBs and a second set of inode to the right of the pair of adjacent CLBs, wherein the first and second sets of inode are configured to accept input and / or output signals to and / or from the plurality of CLBs; embedding a plurality of bounce nodes (bnode) in the middle of the pair of adjacent CLBs, wherein each bnode of the plurality of bnode is configured to establish a first wiring connection between the bnode and one inode of the first set of inode to the left of the pair of adjacent CLBs; establish a second wiring connection between the bnode and one inode of the second set of inode to the right of the pair of adjacent CLBs, wherein the first and second wiring connections are both located in the CLB.

17. The wiring method of claim 16, further comprising: wiring input from one inode of the first set of inode to one bnode of the plurality of bnode; and wiring input from the bnode to all inode of the second set of inode where the input is intended to reach, without any direct point-to-point connection between one inode of the first set of inode and one inode of the second set of inode.

18. The wiring method of claim 16, further comprising: establishing one or more dedicated point-to-point connections between one inode of the first set of inode to the left of the CLB and another inode of the first set of inode to the left of the CLB or an inode of the second set of inode to the right of the CLB, without utilizing the plurality of bnode in the middle of the adjacent CLBs to make fast connections between inode on both sides of the adjacent CLBs.

19. The wiring method of claim 16, further comprising: ​ arranging the plurality of bnodes into a plurality of groups, each group having four bnodes, wherein two bnodes in each group are configured to connect to the first group of inodes adjacent left of the CLB and two bnodes in the group are configured to connect to the second group of inodes adjacent right of the CLB.

20. The routing method of claim 16, further comprising: routing a signal from one inode of the first group of inodes adjacent left of the CLB to one bnode of the plurality of bnodes in the middle of the CLB; and routing a signal from one bnode in the middle of the CLB to one or more inodes of the first group of inodes left of the CLB or the second group of inodes right of the CLB.

21. A routing method, comprising: embedding a clock backbone of interconnect wires in the middle of a configurable logic block (CLB) comprising a plurality of configurable logic elements, wherein the clock backbone is configured to provide one or more clock signals to the plurality of configurable logic elements via a plurality of control nodes (cnode); embedding the plurality of cnode in the middle of the CLB, wherein the plurality of cnode are connected to the plurality of configurable logic elements and are configured to drive control pins of the plurality of configurable logic elements with the clock signals from the clock backbone; positioning the plurality of configurable logic elements in CLBs left and right of the clock backbone and in the plurality of cnode; and connecting the plurality of configurable logic elements to the plurality of cnode in the middle of the CLB. ​ ​

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