Methods and apparatus for photonic circuit simulation

Abstract

In one embodiment, a non-transient medium stores code representing instructions to be executed by the processor. The instructions include code that causes the processor to automatically and without requiring user input to identify multiple computational regions for a photonic integrated circuit (PIC). Each computational region from the multiple computational regions is associated with a portion of the PIC that is different from the remaining computational regions from the multiple computational regions. The multiple computational regions include adjacent regions of computational regions. The instructions cause the processor to perform electromagnetic simulations on each computational region from the multiple computational regions, resulting in multiple electromagnetic simulation results. The instructions include code that causes the processor to assemble the multiple electromagnetic simulation results based on the multiple adjacent computational regions, and determine a simulated response for the PIC.

Description

Technical Field

[0001] One or more embodiments relate to methods and apparatus for photonic circuit simulation.

Background Art

[0002] It may be desirable to operate a simulation for a circuit, including a circuit in the optical domain. However, known simulation techniques can be overly burdensome for a computer and for a user. For example, a computer using known techniques can be slow and / or may not even be able to simulate relatively simple circuits.

Summary of the Invention

Means for Solving the Problems

[0003] In one embodiment, a non-transitory medium stores code representing instructions to be executed by one or more processors. The instructions comprise code that causes one or more processors to automatically identify, without requiring user input, a plurality of computational regions for a photonic integrated circuit (PIC). Each computational region from the plurality of computational regions is associated with a part of the PIC that is different from the remaining computational regions from the plurality of computational regions. The plurality of computational regions includes adjacent regions of the computational regions. The instructions comprise code that causes one or more processors to perform an electromagnetic simulation on each computational region from the plurality of computational regions, resulting in a plurality of electromagnetic simulation results. The instructions comprise code that causes one or more processors to assemble the plurality of electromagnetic simulation results based on the plurality of adjacent computational regions to determine a simulated response for the PIC.

[0004] In one embodiment, the method includes, via a processor, inducing a display of a photonic integrated circuit (PIC) represented in a graphical user interface (GUI). The method further includes, via a processor, receiving indications of multiple computational domains for the PIC based on user input. Each computational domain from the multiple computational domains is associated with a portion of the PIC that is different from the remaining computational domains from the multiple computational domains. The multiple computational domains include adjacent regions of the computational domains. The method further includes, via a processor, performing electromagnetic simulations on each computational domain from the multiple computational domains and generating multiple electromagnetic simulation results. The method further includes, via a processor, assembling the multiple electromagnetic simulation results based on adjacent regions of the computational domains and determining a simulated response for the PIC. The method further includes, via a processor, transmitting information representing the PIC and associated with the control of a lithography mask writer, and processing the PIC based on the information.

[0005] In one embodiment, the device includes memory and a processor operably coupled to the memory. The processor is configured to display, in response to user input, a representation of a first computational domain for a photonic integrated circuit (PIC) and a second computational domain for a PIC distinct from the first computational domain. The first computational domain is adjacent to the second computational domain, at least partially, via an adjacent boundary. The processor is further configured to (1) perform a simulation on the first computational domain to produce a first simulation result, and (2) perform a simulation on the second computational domain to produce a second simulation result. The processor is further configured to determine a simulated response for the PIC based on the first simulation result, the second simulation result, and the adjacent boundary. The processor is further configured to transmit information representing the PIC and associated with the control of a lithography mask writer, and to process the PIC based on the information. [Brief explanation of the drawing]

[0006] [Figure 1] Figure 1 shows a block diagram of an electromagnetic simulation calculation device according to an embodiment.

[0007] [Figure 2A] Figure 2A shows an example of how a photonic integrated circuit (PIC) is represented in a graphical user interface (GUI) according to an embodiment.

[0008] [Figure 2B] Figure 2B shows an embodiment of the computational domain for representing the PIC shown in Figure 2A, according to the embodiment.

[0009] [Figure 3] Figure 3 shows examples of various paths and waveguide shapes according to the embodiment.

[0010] [Figure 4] Figure 4 shows a flowchart of a method for generating a simulated response for a PIC according to an embodiment.

[0011] [Figure 5] Figure 5 shows a flowchart of a method for generating a simulated response for a PIC according to an embodiment.

[0012] [Figure 6] Figure 6 shows a flowchart of a method for generating a simulated response for a PIC according to an embodiment. [Modes for carrying out the invention]

[0013] Detailed explanation Electromagnetic simulators can be run to simulate circuits. However, some circuits, including very simple ones, may be too large and / or complex to simulate using a single electromagnetic simulator. Therefore, the simulation may fail, time out, be slow, inaccurate, incomplete, and / or similar.

[0014] In some known techniques, the circuit in simulation is divided into fundamental elements, each of which is simulated separately. The results of each simulation are then exported to a circuit simulator, which symbolically represents each fundamental element and generally does not recognize the geometric shape of each fundamental element. When the results of the circuit simulator are satisfactory, the circuit description is exported to a layout editor. The layout editor obtains geometric information about each fundamental element from another source and then generates a complete layout of the circuit. The layout may now need to be adjusted, taking into account layout rules such as minimum spacing. This may involve changes to the PIC's representation, and therefore the circuit simulator is run again. Several iterations between the circuit simulator and the layout editor may occur before the design is approved. Finally, the layout editor generates a mask file, which is used to generate a lithography mask set for manufacturing. However, the aforementioned known techniques may be slow, computationally inefficient, and / or similar. Therefore, some implementations herein relate to PIC simulation environments that are faster, more computationally efficient, and / or similar to known techniques.

[0015] In some implementations, the representation of the PIC (or its functional blocks) is fully laid out within the simulation environment of the electromagnetic simulator. A human and / or software model then identifies and / or adds computational domains for the PIC within the representation of the PIC. Each computational domain can be associated with a unique region of the representation of the PIC. Any light flowing into the region of the representation of the PIC that is not covered by a computational domain is assumed to be lost during the simulation, and therefore the computational domains can be adjacent to the region of the representation of the PIC into which light would flow. The electromagnetic simulation is then performed on each computational domain. These individual simulations can then be assembled together automatically (e.g., without requiring human intervention) to produce a simulated response for the PIC. The simulation is produced by referring to the edges where pairs of computational domains are adjacent. If the simulated response of the PIC is unsatisfactory (e.g., as determined by a human, as determined by a software model, etc.), the layout can be modified, and the computational domains can be adjusted to adapt to the modified layout (e.g., automatically).

[0016] Figure 1 shows a block diagram of an electromagnetic simulation computing device 100 according to an embodiment. The electromagnetic simulation computing device 100 can be any type of computing device, such as a server, desktop, laptop, tablet, telephone, Internet of Things (IoT) device, and / or equivalent. The electromagnetic simulation computing device 100 may include a processor 102, memory 104, and display 118, each operably coupled to one another (for example, via a system bus).

[0017] The display 118 can be any type of display, such as a CRT (cathode ray tube) display, an LCD (liquid crystal display) display, an LED (light-emitting diode) display, an OLED (organic light-emitting diode) display, and / or equivalents. The display can be used, for example, to display the PIC representation, the computational domain of the PIC representation, simulation results, and / or equivalents.

[0018] The processor 102 can be, for example, a hardware-based integrated circuit (IC) or any other suitable processing device configured to actuate and / or execute a set of instructions or code. For example, the processor 102 can be a general-purpose processor, a central processing unit (CPU), an accelerated processing unit (APU), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), a programmable logic array (PLA), a complex-programmable logic device (CPLD), a programmable logic controller (PLC), and / or equivalents. In some implementations, the processor 102 can be configured to actuate any of the methods and / or parts of the methods discussed herein.

[0019] Memory 104 can be, for example, a random access memory (RAM), a memory buffer, a hard drive, a read-only memory (ROM), an erasable programmable read-only memory (EPROM), and / or the like. Memory 104 can be configured to store data used by processor 102 to implement the techniques discussed herein. In some instances, memory 104 can store one or more software programs and / or code that can include instructions, for example, to cause processor 102 to implement one or more processes, functions, and / or the like. In some implementations, memory 104 can include an expandable memory unit that can be added and used incrementally. In some implementations, memory 104 can be a portable memory (e.g., a flash drive, a portable hard disk, and / or the like) that can be operably coupled to processor 102. In some instances, memory 104 can be operably coupled remotely to a computing device.

[0020] Memory 104 can include (e.g., store) a representation of PIC 106. PIC 106 can be a software representation of a PIC within a computer environment. PIC 106 can be any type of circuit such as, for example, a quadrature phase shift keying optical receiver, an array of optical ring resonators, and / or the like. PIC 106 can include a representation of optical and optoelectronic components such as, for example, directional couplers, phase shifters, photodetectors, laser diodes, light emitting diodes, optical amplifiers, and associated electrical components used for control or power. In some implementations, PIC 106 is displayed within a graphical user interface (GUI) via display 118. In some implementations, PIC 106 is not displayed within a graphical user interface (GUI) via display 118.

[0021] Memory 104 may contain (for example, store) a representation of the compute region 108. In some implementations, compute region 108 contains multiple compute regions. Each compute region within compute region 108 may be associated with a part of the PIC106 that is different from the rest of the compute regions from compute region 108 (for example, overlapping with it, covering it, etc.). Each compute region within compute region 108 is bounded by straight and / or curved sections, and these sections may include region joint boundaries, region side boundaries, or a combination of region joint boundaries and region side boundaries. A section is a region joint boundary if it is permitted to be adjacent to a section of another compute region. A section is a region side boundary if it is not permitted to be adjacent to a section of another compute region. In other words, compute regions may be adjacent to other compute regions at region joint boundaries, but not at region side boundaries. The computational domain 108 can include computational domains having any shape, such as a ring, square, circle, rectangle, triangle, and / or equivalent. In some implementations, the computational domain 108 can be displayed as partially transparent and / or containing transparent portions, and can be displayed within the GUI as a superimposed on the PIC106 via the display 118. The shape and / or location of the computational domain 108 can be provided by the user alone, by software alone (e.g., based on the layout of the PIC106), or a combination thereof. In some implementations, the computational domain 108 is automatically determined based on the waveguide shape 110. In such implementations, an initial analysis of the waveguide shape 110 can provide an estimate of the range of likely electromagnetic fields, and the computational domain 108 is then sized to enclose all areas where the electromagnetic field is significant (e.g., above a predetermined threshold). This initial analysis may use the optical modes of the cross-sections of individual waveguide shapes from waveguide shape 110 and estimates of the electromagnetic coupling between adjacent waveguide shapes from waveguide shape 110. The computational domain 108 may also be updated based on previous electromagnetic simulation results 114, for example, by monitoring the magnitude of the electromagnetic field at the boundary of the computational domain.In some implementations, this update may automatically merge two computational domains from computational domain 108 into one larger computational domain and include it within computational domain 108. In some implementations, if the residual electromagnetic field at the domain boundary of a first computational domain from computational domain 108 is expected to propagate within the manufactured device into a domain defined by an adjacent second computational domain from computational domain 108, as predicted by the analysis of the waveguide geometry included by the computational domain, or as calculated by previous electromagnetic simulation results from electromagnetic simulation results 114, then the first and second computational domains may then automatically merge into one larger computational domain and include it within computational domain 108. In some implementations, this analysis of waveguide geometry may include a study of the behavior of optical modes induced by any waveguide included within the computational domain. This study may include observation of the amplitude of the optical modes at the domain boundary, and also the extent to which the modes leak in the direction of the domain boundary. In some implementations, the waveguide shape refers to a two-dimensional shape that can define an electromagnetic waveguide or a part thereof.

[0022] In some implementations, any representation of light flowing into the region of PIC106 that is not covered by computational region 108 within the simulation environment may be expected to be lost during the simulation. Therefore, computational regions are typically adjacent where light is flowing in. In some implementations, adjacent regions may refer to computational regions that only overlap, only touch (abut), or a combination of these.

[0023] Memory 104 can also include (e.g., store) a representation of the electromagnetic simulation results 114. The electromagnetic simulation results 114 can represent the electromagnetic simulation results of the computational region 108. In other words, the electromagnetic simulation can be executed on each computational region from the computational region 108 and generate simulation results for that computational region. Each electromagnetic simulation result from the electromagnetic simulation results 114 can represent the electromagnetic simulation results of the computational region from the computational region 108 that are different from the remaining electromagnetic simulation results from the electromagnetic simulation results 114. The electromagnetic simulation can be executed by referring to adjacent computational regions from the computational region 108. Therefore, the results can more accurately resemble the real-world behavior of the PIC106 because in the real world (i.e., not in a computing environment), the behavior within one region of the circuit can affect the behavior of another region of the circuit.

[0024] Memory 104 can also include (e.g., store) a representation of the simulated response 116. The simulated response 116 can represent the simulated response of the PIC106. The simulated response 116 can be generated based on the electromagnetic simulation results 114. In some implementations, the simulation response of each computational region from the computational region 108 is represented by a scattering matrix that relates an input vector to an output vector. The input vector defines the electromagnetic field that flows into one or more regions that abut the boundary of that computational region. The output vector defines the electromagnetic field that flows out of one or more regions that abut the boundary of that computational region. When a pair of computational regions from the computational region 108 that share the region junction boundary entirely or partially is given, the scattering matrix representing the combined simulation response of the pair of computational regions is calculated from the two scattering matrices of the individual computational regions. This operation can be repeated until the scattering matrix representing the simulation response of the entire PIC106 is obtained.

[0025] In some implementations, memory 104 may also contain (e.g., store) representations of waveguide shapes 110 and / or paths 112. In some implementations, waveguide shapes 110 and paths 112 may be used to define the computational domain 108 (e.g., by the user, electromagnetic simulation computing device 100, and / or equivalent). For example, waveguide shape may refer to a two-dimensional shape (e.g., defining an electromagnetic waveguide or a portion thereof, which will be exported to a lithography mask file). In some cases, waveguide shape is the shape that defines the waveguide during subsequent manufacturing (e.g., of the PIC). In some cases, waveguide shape may define an electromagnetic waveguide (or a portion thereof) and / or an electrical path. In some implementations, a path refers to a finite-length path through a top view and / or perspective view of the PIC 106. Waveguide shapes 110 and / or paths 112 may be displayed within a graphical user interface (GUI) via a display 118. However, in some implementations, waveguide shapes 110 and / or paths 112 are not used. In some implementations, path 112 includes either the main path only or a combination of the main path and subpaths.

[0026] In some implementations, the PIC106, computational domain 108, waveguide geometry 110, path 112, electromagnetic simulation results 114, and / or simulated response 116 are defined, generated, processed, used, and / or equivalent via the simulation engine (e.g., within a single simulation application / program). In some implementations, the simulation engine can be stored in memory 104. In some implementations, the simulation engine can model optical structures as ring resonators, optical gratings, photonic crystals, nanophotonics, and / or equivalents. In some implementations, the simulation engine can model plasmonics and / or metamaterials. In some implementations, the simulation engine can model electromagnetic fields within photon structures. In some implementations, the simulation engine can model the propagation of light incident on 1D or 2D periodic structures (e.g., diffraction gratings, periodic metamaterials, diffractive optical elements, etc.).

[0027] In some implementations, the path 112 is used to guide the placement of the computing region 108 (e.g., by a human, by an electromagnetic simulation computing device 100). For example, a computing region placed near the path will automatically extend to cover the length of the path and laterally on each side of the path by a certain predetermined or calculated width. In some implementations, the computing region 108 is tied to the path 112 so that it moves with the path when the path is moved, extends in length when the path is extended, or follows any other change in the shape of the path.

[0028] In some cases, a representation of the simulated response 116 can be displayed on the display 118. In some cases, corrective actions may occur and / or be triggered in response to the simulated response 116 failing to meet a predetermined set of criteria. For example, a warning message may be displayed on the display 118 (e.g., that the simulation failed, that PIC 106 should be corrected, that the computational domain 108 should be corrected, that the waveguide shape 110 should be corrected, that the path 112 should be corrected, that human intervention is required or recommended, and / or equivalent). In another embodiment, PIC 106, computational domain 108, waveguide shape 110, and / or path 112 can be corrected automatically (e.g., by a software model and / or without human intervention). An example of the predetermined criteria is the value of light (e.g., phase, amplitude, etc.) propagating within PIC 106.

[0029] In some cases, in response to the simulated response 116 not meeting a predetermined set of criteria, the PIC 106, waveguide shape 110, and / or path 112 are modified (e.g., by the user, software model, a combination thereof, and / or equivalent). In response to the modification, the computational domain 108 can be automatically updated. For example, if an optical component within the PIC 106 is moved to a different location in the GUI, the computational domain associated with that optical component (e.g., covering it) can also be moved to the new location in the GUI.

[0030] In some cases, the representation of PIC106 can be processed (e.g., in response to a simulated response 116 satisfying a predetermined set of criteria). For example, an electronic signal containing the representation of PIC106 can be sent to a computing device, causing the computing device to process the PIC106. For example, the computing device could be a lithography mask writer that can process the PIC106 in response to the reception of an electronic signal. In some implementations, the computing domain 108 indicates / defines the portion of the PIC106 presentation where the simulation calculation will be performed separately. In some implementations, the computing domain 108 can be defined / established without any use of the path 112. In some implementations, the path 112 and / or the computing domain 108 can be defined manually only, autonomously via software only, or a combination thereof (e.g., first defined by software and then manually verified and / or edited). In other words, in some implementations, (1) path 112 is used and manually defined (e.g., installed) by the user, (2) waveguide shape 110 is manually defined (e.g., guided by the location of path 112), and (3) computational domain 108 is manually defined (e.g., guided by the location of waveguide shape 110 and / or path 112). In other implementations, (1) path 112 is used and manually defined (e.g., installed) by the user, (2) waveguide shape 110 is manually defined (e.g., guided by the location of path 112), and (3) computational domain 108 is automatically defined (e.g., guided by the location of waveguide shape 110 and / or path 112). In yet another implementation, (1) path 112 is not used, (2) waveguide shape 110 is manually defined, and (3) computational domain 108 is manually defined (e.g., guided by the location of waveguide shape 110). In an alternative implementation, (1) path 112 is not used, (2) waveguide shape 110 is manually defined, and (3) computational domain 108 is automatically defined (e.g., induced by the location of waveguide shape 110).In an alternative implementation, (1) path 112 is not used, (2) waveguide shape 110 is automatically defined from the imported design of PIC106, and (3) calculation domain 108 is manually defined (e.g., induced by the location of waveguide shape 110). In an alternative implementation, (1) path 112 is not used, (2) waveguide shape 110 is automatically defined from the imported design of PIC, and (3) calculation domain 108 is automatically defined (e.g., induced by the location of waveguide shape 110). In some cases, the user may have the ability to correct the automatic placement of calculation domain 108 after the automatic placement has occurred and the results have been displayed.

[0031] In some implementations, the computation domain 108 starts and ends at the end of path 112 (for example, by default). For example, the computation domain 108 can be laterally centered on path 112 (for example, by default). In some implementations, the waveguide shape 110 starts and ends at the end of path 112 and / or is laterally centered by path 112 (for example, by default). In some implementations, path 112 can contain subpaths so that multiple different waveguide shapes from waveguide shape 112 can be linked to a single path from path 112. In some implementations, waveguide shape 110 can define a lateral offset from path 112, with an offset that varies along path 112, allowing the computation domain and multiple waveguide shapes to be linked to a single path.

[0032] In some implementations, an offset exists between the waveguide shape and the path contained within it. For example, the path may not be at the center of the waveguide shape, but rather closer to one side.

[0033] In some implementations, the computational domain 108 can be identified based on predictions of (1) which waveguide shapes from waveguide shape 110 are capable of inducing electromagnetic radiation (e.g., based on location, width, length, component type, and / or equivalents), and / or (2) which pairs of waveguide shapes from waveguide shape 110 are electromagnetically coupled to each other (e.g., based on the distance between waveguide shapes). The predictions can be, for example, made by a human and provided to the electromagnetic simulation computing device 100, performed by a software model (e.g., a neural network) without human intervention, or a combination thereof (e.g., a software model makes the first prediction and the user double-checks it).

[0034] In some implementations, the waveguide shape 110 is identified prior to the identification of the computational domain 108. For example, path 112 can be identified prior to the waveguide shape 110, and the waveguide shape 110 can be identified prior to the computational domain 108. In another embodiment, the waveguide shape 110 can be identified prior to the computational domain 108 (while path 112 is not identified).

[0035] In some implementations, a third-party tool (e.g., one not shown in Figure 1, operating on a computing device) can generate a circuit layout (e.g., PIC106) and send a representation of the circuit layout to an electromagnetic simulation computing device 100. A computing domain 108 is added, and the simulation is performed. Based on feedback from these simulations (e.g., sent from the electromagnetic simulation computing device 100 to the computing device operating the third-party tool), the user can adjust the layout within the third-party tool and re-export the updated layout to the electromagnetic simulation computing device 100. Feedback can continue to be sent / received by the user until the user provides an indication to the third-party tool via those computing devices to generate a lithography mask file. Thus, in some implementations, the electromagnetic simulation computing device 100 does not generate a mask layout file (rather, it only guides the design of the layout). However, in some implementations, the electromagnetic simulation computing device 100 can generate a mask layout file and / or send a signal to another computing device to generate a mask layout file on that computing device.

[0036] Figure 2A shows an example of the representation of the PIC in the GUI according to an embodiment. The PIC shown in Figure 2A is an optical ring resonator. The PIC shown in Figure 2A includes waveguide shapes 202, 204, and 206 (solid lines) and paths 208, 210, and 212 (dashed lines within the solid lines). As can be seen from the figure, paths 208, 210, and 212 are located within waveguide shapes 202, 204, and 206, respectively. Figure 2B shows an example of the computational domain for the representation of the PIC shown in Figure 2A according to an embodiment. Figure 2B includes computational domains 214, 216, 218, 220, 222, and 224 (similar to, for example, computational domain 108), domain-side boundaries 225, 226, and 227, and domain-joint boundaries 228, 229, and 230. In some implementations, electromagnetic simulations are run separately on each of the computational domains 214, 216, 218, 220, 222, and 224, allowing for the generation of six different electromagnetic simulation results (since there are six computational domains), which are then used to generate a single simulation result for the PIC.

[0037] Figure 3 shows examples of various paths and waveguide shapes according to the embodiment. Figure 3 shows various sets of waveguide shapes 350-363. Figure 3 also shows various paths 370-387. Path 371 is linked to the root path 370. Subpaths 372 and 373 are linked to path 371. Paths 374 and 375 are linked to subpaths 372 and 373. Waveguide shapes 350-354 are linked to paths 370-375. Waveguide shapes 355-358 are linked to paths 376-379. Waveguide shapes 359-360 are linked to paths 380-381. Waveguide shapes 361-363 are linked to paths 382-387. In some cases, moving a root path automatically moves all paths associated with that root path. In other cases, subpaths provide a convenient way to guide multiple waveguide shapes associated with a single computational domain in different directions.

[0038] Figure 4 shows a flowchart of method 400 for generating a simulated response for a PIC according to an embodiment. In some implementations, method 400 is carried out by a processor (e.g., processor 102).

[0039] In 402, multiple compute regions (e.g., compute region 108) for a PIC (e.g., PIC106) are automatically identified without requiring user input. Each compute region from the multiple compute regions is associated with a portion of the PIC that is different from the remaining compute regions from the multiple compute regions. The multiple compute regions include adjacent regions of the compute regions.

[0040] In step 404, electromagnetic simulations are performed on each of the multiple computational domains, resulting in multiple electromagnetic simulation results (e.g., electromagnetic simulation result 114). In some implementations, step 404 is performed automatically (e.g., without human intervention) in response to the completion of step 402.

[0041] In step 406, multiple electromagnetic simulation results are assembled based on multiple adjacent computational domains to determine a simulated response for the PIC (e.g., simulated response 116). In some implementations, step 406 is performed automatically (e.g., without human intervention) in response to the completion of step 404.

[0042] In some implementations of Method 400, the PIC is represented within a graphical user interface (GUI). Method 400 may further include receiving indications to modify the layout of the PIC based on user input, resulting in a modified PIC represented within the GUI. Method 400 may further include automatically modifying multiple computational regions for the modified PIC without additional user input.

[0043] In some implementations, a path (e.g., path 112) can be used in step 402 to help identify multiple computing regions (e.g., by the processor). In some implementations, as paths are defined and / or identified, they can be automatically aligned with each other (e.g., by the processor). For example, if a new path is located near an existing path, the closer ends of both paths can be automatically aligned via the processor.

[0044] Some implementations of Method 400 further include receiving an indication of a set of waveguide shapes (e.g., waveguide shape 110) that define at least a portion of the representation of the PIC, based on user input. Multiple computational domains can be identified based on the set of waveguide shapes. In some implementations, the multiple computational domains completely cover the set of waveguide shapes. In some implementations, the multiple computational domains do not completely cover the set of waveguide shapes, and the portion of the set of waveguide shapes not covered by the multiple computational domains is not considered during the execution of the electromagnetic simulation and the assembly of the results of the multiple electromagnetic simulations.

[0045] In some implementations of Method 400, identifying multiple computational domains, performing electromagnetic simulations, and assembling multiple electromagnetic simulation results are all done within a single electromagnetic simulator application.

[0046] In some implementations of Method 400, the PIC includes a set of waveguide shapes (e.g., waveguide shape 110). Some implementations of Method 400 further include generating predictions of (1) which waveguide shapes from the set of waveguide shapes are capable of inducing electromagnetic radiation, and (2) which pairs of waveguide shapes from the set of waveguide shapes are electromagnetically coupled to each other, with multiple computational domains identified based on the predictions.

[0047] Figure 5 shows a flowchart of method 500 for generating a simulated response for a PIC according to an embodiment. In some implementations, method 500 is carried out by a processor (e.g., processor 102).

[0048] In 502, the PIC (for example, PIC106) is displayed within the GUI (for example, on display 118).

[0049] In 504, indications for multiple compute regions (e.g., compute region 108) for the PIC are received based on user input. Each compute region from the multiple compute regions is associated with a portion of the PIC that is different from the rest of the compute regions from the multiple compute regions. The multiple compute regions include adjacent regions of the compute regions.

[0050] In step 506, electromagnetic simulations are performed on each of the multiple computational domains, resulting in multiple electromagnetic simulation results (e.g., electromagnetic simulation result 114). In some implementations, step 506 is performed automatically (e.g., without human intervention) in response to the completion of step 504.

[0051] In step 508, multiple electromagnetic simulation results are assembled based on adjacent regions of the computational domain to determine a simulated response for the PIC (e.g., simulated response 116). In some implementations, step 508 is performed automatically (e.g., without human intervention) in response to completing step 506.

[0052] In 510, information representing the PIC and associated with the control of the lithography mask writer is transmitted to process the PIC based on the information. In some implementations, 510 is performed automatically (e.g., without human intervention) in response to the completion of 508.

[0053] In some implementations of Method 500, the information is contained within a file associated with the input to the lithography mask writer. The lithography mask writer can be configured to process the PIC based on the information.

[0054] In some implementations of Method 500, the input is a first input. Some implementations of Method 500 further include receiving indications of a set of paths (e.g., path 112) and a set of waveguide shapes (e.g., waveguide shape 110) before displaying the PIC, based on a second input from the user. The set of paths and the set of waveguide shapes can represent at least a portion of the PIC.

[0055] In some implementations of Method 500, the input is a first input. Some implementations of Method 500 further include receiving an indication of a set of paths (e.g., path 112) based on a second input from the user. At least one path from the set of paths may be in and / or traverse at least one computational domain from multiple computational domains, such that at least one path from the set of paths traverses through each computational domain from multiple computational domains. In some cases, at least one path from the set of paths extends from one edge of a computational domain from multiple computational domains to another edge of a computational domain. In some implementations, the end of one path may easily be contiguous with the start of another path in an adjacent computational domain.

[0056] Some implementations of Method 500 further include receiving an indication from a second input from the user to associate at least one waveguide shape (e.g., waveguide shape) from a set of waveguide shapes with a path (e.g., path 112). Each waveguide shape from the set of waveguide shapes may extend along the entire length or only a portion of the path (e.g., based on a second and / or third input from the user). In some implementations, the waveguide shape may be offset from its associated path (e.g., in response to an indication from the user to offset). The offset may be constant along the length of the path, vary along the length of the path, and / or a combination thereof.

[0057] In some implementations of Method 500, multiple computational domains fully cover all parts of the PIC that have electromagnetic radiation magnitudes expected to exceed a predetermined threshold. In some implementations of Method 500, multiple computational domains do not fully cover the PIC, and the parts of the PIC not covered by the multiple computational domains are not considered during the execution of the electromagnetic simulation and the assembly of multiple electromagnetic simulation results to determine the simulated response for the PIC.

[0058] In some implementations of Method 500, triggering a PIC representation, receiving indications of multiple computational domains for the PIC, performing electromagnetic simulations, and assembling multiple electromagnetic simulation results are performed within a single electromagnetic simulator application. In some implementations, the PIC is the first PIC, the inputs are the first inputs, the multiple computational domains are the first multiple computational domains, and the multiple electromagnetic simulation results are the first multiple electromagnetic simulation results. Some implementations further include receiving a representation of a second PIC, different from the first PIC, from the application, which differs from the single electromagnetic simulator application. Some implementations further include receiving indications of a second multiple computational domain for the second PIC based on a second input from the user. Each computational domain from the second multiple computational domains can be associated with a part of the second PIC, different from the rest of the computational domains from the second multiple computational domains. The second multiple computational domains can include adjacent regions of computational domains. Some implementations further include performing electromagnetic simulations on each computational domain from the second multiple computational domains to produce the second multiple electromagnetic simulation results. Some implementations further include assembling a second set of electromagnetic simulation results based on adjacent regions of the computation domains, which are contained within the second set of computation domains, to determine a simulated response for the second PIC. Some implementations further include causing the simulated response for the second PIC to be displayed or shared with an application, or at least one of the latter. Some implementations further include receiving the first PIC after assembling the second set of electromagnetic simulation results but before causing a display of the first PIC.

[0059] In some implementations of Method 500, the input is a first input, and Method 500 further includes receiving an indication of a set of paths based on a second input from the user. The first path from the set of paths extends from a first edge of the first computational domain to a second edge of the first computational domain from multiple computational domains. The second path from the set of paths extends from a first edge of the second computational domain to a second edge of the second computational domain from multiple computational domains. The first computational domain is adjacent to the second computational domain, and the first path is contiguous with the second path.

[0060] In some implementations of Method 500, the input is a first input, and Method 500 further includes receiving an indication from the user, based on a second input from the user, for associating a set of waveguide shapes with a set of paths. Each waveguide shape from the set of waveguide shapes extends along at least one of either the entire length of a path or only a portion of a path from the set of paths. Method 500 further includes receiving an indication from the user, based on a third input from the user, of the offset in that waveguide shape from the path. The offset is either constant along the length of the path or varies along the length of the path. In some implementations, the offset is the lateral distance from the center of the waveguide shape to the path for that waveguide shape. In some implementations, subpaths are offset from their main path, and there is no offset from the subpath to the waveguide shape for that subpath.

[0061] Figure 6 shows a flowchart of method 600 for generating a simulated response for a PIC according to an embodiment. In some implementations, method 600 is carried out by a processor (e.g., processor 102).

[0062] In 602, representations of a first computational domain for a photonic integrated circuit (PIC) and a second computational domain for a PIC different from the first computational domain are shown on the display in response to user input. The first computational domain is adjacent to the second computational domain, at least partially, via adjacent boundaries.

[0063] In step 604, (1) a simulation is performed on the first computational domain to produce a first simulation result, and (2) a simulation is performed on the second computational domain to produce a second simulation result. In some implementations, step 604 is performed automatically (e.g., without human intervention) in response to the completion of step 602.

[0064] In 606, the simulated response for PIC is determined based on the first simulation result, the second simulation result, and adjacent boundaries. In some implementations, 606 is performed automatically (e.g., without human intervention) in response to completing 604.

[0065] In 608, information representing the PIC and associated with the control of the lithography mask writer is transmitted to process the PIC based on that information. In some implementations, 608 is performed automatically (e.g., without human intervention) in response to the completion of 606.

[0066] In some implementations of Method 600, the information is contained within a file associated with the input to the lithography mask writer. The lithography mask writer can be configured to process the PIC based on the information.

[0067] In some implementations of Method 600, the input is a first input. Method 600 may further include identifying a set of routes (e.g., route 112) associated with the PIC (e.g., manually and / or automatically, and without requiring user input). Some implementations may further include receiving confirmation that the set of routes is acceptable via a second input from the user.

[0068] In some implementations of Method 600, adjacent boundaries are first adjacent boundaries. Some implementations further include, on a display, showing a representation of a third computational domain for the PIC that is different from the first and second computational domains, based on user input. The third computational domain is adjacent to at least one of the first or second computational domains via a second adjacent boundary that is at least partially different from the first adjacent boundaries. Some implementations further include performing a simulation on the third computational domain to produce a third simulation result. Determining the simulated response for the PIC can further be based on the third simulation result and the second adjacent boundary.

[0069] In some implementations of Method 600, adjacent boundaries are the first adjacent boundaries. Some implementations further include, on the display, representing a third calculation domain for the PIC that is different from the first and second calculation domains, and a fourth calculation domain for the PIC that is different from the first, second, and third calculation domains, based on user input. The third calculation domain may be adjacent to the fourth calculation domain via a second adjacent boundary that is at least partially different from the first adjacent boundaries. Some implementations further include performing a simulation on the third calculation domain to produce a third simulation result, and performing a simulation on the fourth calculation domain to produce a fourth simulation result. Determining the simulated response for the PIC may further be based on the third simulation result, the fourth simulation result, and the second adjacent boundary.

[0070] In some implementations of Method 600, the representation of the first and second computational domains, the execution of the simulation, and the determination of the simulated response are all performed within a single simulator application.

[0071] Some implementations of Method 600 further include automatically and without requiring user input identifying a first potential compute region for the PIC. Some implementations further include automatically and without requiring user input identifying a second potential compute region for the PIC. Some implementations further include receiving, as input, confirmation that the first and second compute regions are acceptable. The first potential compute region may become the first compute region in response to the receipt of the confirmation, and the second potential compute region may become the second compute region in response to the receipt of the confirmation.

[0072] Any combination of the aforementioned and additional concepts discussed herein (provided that such concepts are not contradictory) shall be considered part of the subject matter disclosed herein. Technical terms explicitly adopted herein, which may also appear in any disclosure incorporated by reference, should be given meanings that best correspond to the specific concepts disclosed herein.

[0073] The drawings are primarily for illustrative purposes and are not intended to limit the scope of the subject matter described herein. The drawings are not necessarily to exact scale, and in some cases, various aspects of the subject matter disclosed herein are exaggerated or enlarged in the drawings to facilitate understanding of different features. In the drawings, similar reference letters generally refer to similar features (e.g., functionally similar and / or structurally similar elements).

[0074] The entire application (including the cover page, title, headings, background, summary, brief description of drawings, detailed description, embodiments, abstract, figures, appendices, and others) illustrates various embodiments in which the embodiments may be put into practice. The advantages and features of the application are merely representative samples of embodiments and are not exhaustive and / or exclusive. Rather, they are presented to aid understanding and to teach embodiments, and are not representative of all embodiments. Accordingly, certain aspects of the disclosure are not discussed herein. The fact that alternative embodiments may not be presented for a particular part of the innovation, or that alternative embodiments not further described may be available for a part, should not be considered to exclude such alternative embodiments from the scope of the disclosure. It should be understood that many of those undescribed embodiments incorporate the same principles of the innovation, and others are equivalents. Accordingly, it should be understood that other embodiments may be utilized, and functional, logical, operational, organizational, structural, and / or topological modifications may be made without departing from the scope and / or spirit of the disclosure. Therefore, all examples and / or embodiments described herein are considered non-limiting throughout this disclosure.

[0075] Furthermore, embodiments not discussed herein are provided solely for the purpose of reducing space and repetition, and no inferences should be made in comparison to those embodiments discussed herein. For example, the logical and / or topological structures of any program component (component set), other components, and / or any combination of any presented feature set, as described in the figures and / or throughout, are not limited to a fixed operating order and / or arrangement; rather, any disclosed order is illustrative, and all equivalents are considered by this disclosure regardless of the order.

[0076] Unless otherwise stated, the term “automatically” is used herein to describe actions that occur without direct input or prompting from an external source, such as a user. Automatically occurring actions may occur periodically, spontaneously, in response to detected events (e.g., user login), or according to a predetermined schedule.

[0077] The term "to decide" encompasses a wide variety of actions, and therefore "to decide" can include performing calculations, computations, processing, derivation, investigation, lookups (e.g., looking up in a table, database, or another data structure), verification, and equivalents. It can also include receiving (e.g., receiving information), accessing (e.g., accessing data in memory), and equivalents. Furthermore, it can include resolving, selecting, choosing, establishing, and equivalents.

[0078] The phrase "based on" does not mean "based solely on" unless explicitly stated otherwise. In other words, the phrase "based on" describes both "based solely on" and "at least, based on."

[0079] Unless otherwise discussed, the term “processor” can be interpreted broadly to include general-purpose processors, central processing units (CPUs), microprocessors, digital signal processors (DSPs), graphics processing units (GPUs), controllers, microcontrollers, state machines, and / or equivalents. In some circumstances, “processor” can refer to application-specific integrated circuits (ASICs), programmable logic devices (PLDs), field-programmable gate arrays (FPGAs), and so on. The term “processor” can refer to a combination of processing devices, e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors combined with a DSP core, or any other such configuration.

[0080] The term "memory" should be interpreted broadly to encompass any electronic component capable of storing electronic information. The term "memory" can refer to various types of processor-readable media, such as random access memory (RAM), read-only memory (ROM), non-volatile random access memory (NVRAM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable PROM (EEPROM), flash memory, magnetic or optical data storage devices, and registers. Memory is said to communicate electronically with the processor if the processor can read information from and / or write information to it. If integrated with the processor, memory communicates electronically with the processor.

[0081] The terms “instruction” and “code” should be interpreted broadly to include any type of computer-readable statement. For example, the terms “instruction” and “code” may refer to one or more programs, routines, subroutines, functions, procedures, etc. “Instructions” and “code” may consist of a single computer-readable description or many computer-readable descriptions.

[0082] Some embodiments described herein relate to computer storage devices that include a non-transient computer-readable medium (which has instructions or computer code for performing various computer implementation operations on the non-transient computer-readable medium) (which may also be referred to as a non-transient processor-readable medium). The computer-readable medium (or processor-readable medium) is non-transient in the sense that it does not itself contain transient propagating signals (for example, propagating electromagnetic waves that carry information on a transmission medium such as space or a cable). The medium and the computer code (which may also be referred to as the code) may be designed and constructed for a specific purpose or for multiple purposes. Examples of non-transient computer-readable media include, but are not limited to, magnetic storage media such as hard disks, floppy disks, and magnetic tapes; optical storage media such as compact discs / digital video discs (CD / DVDs), compact disc-read-only memory (CD-ROMs), and holographic devices; magneto-optical storage media such as optical discs; carrier signal processing modules and application-specific integrated circuits (ASICs); programmable logic devices (PLDs); read-only memory (ROMs), and random access memory (RAM) devices; and hardware devices specifically configured to store and execute program code. Other embodiments described herein relate to computer program products, which may include instructions and / or computer code discussed herein.

[0083] Some embodiments and / or methods described herein can be implemented by software (running on hardware), hardware, or a combination thereof. Hardware modules may include, for example, general-purpose processors, field-programmable gate arrays (FPGAs), and / or application-specific integrated circuits (ASICs). Software modules (running on hardware) may be C, C++, Java®, Ruby, Visual Basic TM, and / or other object-oriented, procedural, or other programming languages ​​and development tools can be represented in a variety of software languages ​​(e.g., computer code). Embodiments of computer code include, but are not limited to, microcode or microinstructions, machine instructions such as those produced by a compiler, code used to produce web services, and files containing high-level instructions executed by a computer using an interpreter. For example, embodiments may be implemented using imperative programming languages ​​(e.g., C, Fortran, etc.), functional programming languages ​​(e.g., Haskell, Erlang, etc.), logic programming languages ​​(e.g., Prolog), object-oriented programming languages ​​(e.g., Java®, C++, etc.), or other preferred programming languages ​​and / or development tools. Additional embodiments of computer code include, but are not limited to, control signals, encrypted code, and compressed code.

[0084] Various concepts may be embodied in one or more ways, and embodiments thereof are provided. The actions performed as part of the method may be ordered in any preferred manner. Thus, even when an illustrative embodiment is shown as a sequential actions, embodiments may be constructed in which the actions are performed in a different order than those illustrated therein, which may include performing several actions simultaneously. In other words, it should be understood that such features are not necessarily limited to a particular order of execution, but rather may be performed sequentially, asynchronously, concurrently, in parallel, simultaneously, synchronously, and / or equivalently by any number of threads, processes, services, servers, and / or equivalents in a manner consistent with the Disclosure. Accordingly, some of these features may be mutually contradictory in that they cannot coexist simultaneously within a single embodiment. Similarly, some features may be applicable to one aspect of the innovation but not to others.

[0085] In addition, this disclosure may include other innovations not described herein. The applicant reserves all rights in such innovations, including the right to file embodiments of such innovations, supplementary applications, continuation applications, continuation-part applications, divisional applications, and / or equivalents thereof. Accordingly, it should be understood that the merits, embodiments, examples, functional, characteristic, logical, operational, organizational, structural, topological, and / or other aspects of this disclosure should not be considered limitations relating to this disclosure or equivalents of embodiments as defined by the embodiments. Depending on the specific desires and / or characteristics of individual and / or corporate users, database configurations and / or relational models, data types, data transmission and / or network frameworks, syntactic structures, and / or equivalents, various embodiments of the technology disclosed herein may be implemented in a manner that enables high flexibility and customization, as described herein.

[0086] It should be understood that all definitions defined and used herein take precedence over dictionary definitions, definitions in literature incorporated by reference, and / or the ordinary meanings of the defined terms.

[0087] As used herein, in certain embodiments, the terms “about” or “approximately” when preceding a number indicate a value within a range of ±10%. Where a range of values ​​is provided, it should be understood that, unless the context explicitly indicates otherwise, each intermediary value up to one-tenth of the lower limit between any other stated or intermediary values ​​within that range is also included in this disclosure. The fact that these smaller ranges may independently fall within smaller ranges is also included in this disclosure, unless subject to any specifically excluded limitations within the described range. Where a described range includes one or both of those limitations, a range that excludes either or both of those included limitations is also included in this disclosure.

[0088] The indefinite articles "a" and "an," as used in the specification and embodiments herein, should be understood to mean "at least one" unless explicitly indicated in contrast.

[0089] The phrase "and / or" as used in the specification and embodiments herein should be understood to mean "either one or both" of the elements thus combined, that is, elements that exist jointly in some cases and disjunctly in others. Multiple elements listed using "and / or" should be interpreted in the same manner, that is, "one or more" of the elements thus combined. In addition to the elements specifically identified by the "and / or" clause, other elements may optionally exist, whether related to or unrelated to those specifically identified elements. Thus, in non-restrictive embodiments, a reference to "A and / or B," when used in conjunction with non-restrictive terms such as "comprising," may refer in one embodiment to A only (optionally including elements other than B), in another embodiment to B only (optionally including elements other than A), in yet another embodiment to both A and B (optionally including other elements), and so on.

[0090] As used in the specification and embodiments herein, “or” should be understood to have the same meaning as “and / or” as defined above. For example, when separating items in a list, “or” or “and / or” should be interpreted as inclusive, i.e., including at least one, but also optionally including more than one of several elements or a list of elements, additional unlisted items. Only terms that are clearly indicated in contrast, such as “one of” or “exactly one of,” or “consisting of” as used in embodiments, would refer to the inclusion of exactly one element of several elements or a list of elements. In general, the term “or” as used herein should be interpreted only as indicating exclusive substitution (i.e., “one or the other, but not both”) when preceded by terms of exclusivity such as “either one,” “one of,” “one of,” or “exactly one of.” “Essentially consisting of” shall, when used in embodiments, have its usual meaning as used in the field of patent law.

[0091] As used in the specification and embodiments herein, the phrase “at least one” refers to a list of one or more elements, meaning at least one element selected from any one or more of the elements in the list of elements, but not necessarily including at least one of all elements specifically enumerated in the list of elements, and not excluding any combination of elements in the list of elements. This definition also allows for the optional presence of elements other than those specifically identified in the list of elements, which the phrase “at least one” refers to, whether related to or unrelated to those specifically identified elements. Therefore, in non-limiting embodiments, “at least one of A and B” (or equivalently “at least one of A or B” or equivalently “at least one of A and / or B”) may refer to, in one embodiment, at least one A (and optionally including elements other than B) which may be absent and optionally include one or more; in another embodiment, at least one B (and optionally including elements other than A) which may be absent and optionally include one or more; and in yet another embodiment, at least one A which may optionally include one or more, and at least one B (and optionally including other elements), and so on.

[0092] In embodiments and in the above specification, all transitional phrases such as “comprising,” “including,” “carrying,” “having,” “containing,” “involving,” “holding,” “composed of,” and their equivalents shall be understood to be open-ended, meaning they include but are not limited to them. Only the transitional phrases “consisting of” and “consisting essentially of” are considered restrictive or semi-restrictive transitional phrases, respectively, as described in Section 2111.03 of the U.S. Patent and Trademark Office’s U.S. Patent Examination Procedure Manual.

Claims

1. A non-transient medium for storing code representing instructions to be executed by one or more processors, wherein the instructions are to be executed by the one or more processors. To automatically and without requiring user input identify multiple computing regions for a photonic integrated circuit (PIC), wherein each computing region from the multiple computing regions is associated with a portion of the PIC that is different from the remaining computing regions from the multiple computing regions, and the multiple computing regions include adjacent regions of the computing regions. The electromagnetic simulation is performed on each of the aforementioned multiple computational domains, and multiple electromagnetic simulation results are generated. Based on the aforementioned multiple adjacent computational domains, the multiple electromagnetic simulation results are assembled to determine the simulated response for the PIC. A non-transient medium equipped with code to perform the following action.

2. The PIC is represented within a graphical user interface (GUI), and the code is further transmitted to the one or more processors. Based on the input from the user, the system receives an indication to modify the layout of the PIC and produce the modified PIC represented in the GUI. To automatically modify the multiple computing domains for the modified PIC without any additional input from the user. A non-transient processor-readable medium according to claim 1, comprising code to perform the following action.

3. The code further provides the one or more processors: Based on the user input, an indication of a set of waveguide shapes defining at least a portion of the PIC is received, wherein the plurality of computational domains are identified based on the set of waveguide shapes. A non-transient processor-readable medium according to claim 1, comprising code to perform the following action.

4. The non-transient processor-readable medium according to claim 3, wherein the plurality of computing domains completely cover the set of waveguide shapes.

5. The non-transient processor-readable medium according to claim 3, wherein the plurality of computational domains do not completely cover the set of waveguide shapes, and any portion of the set of waveguide shapes not covered by the plurality of computational domains is not considered during the execution of the electromagnetic simulation and the assembly of the results of the plurality of electromagnetic simulations.

6. The non-transient processor-readable medium according to claim 1, wherein identifying the plurality of computational domains, performing the electromagnetic simulation, and assembling the plurality of electromagnetic simulation results are performed within a single electromagnetic simulator application.

7. The PIC includes a set of waveguide shapes, and the code further provides the one or more processors. (1) to generate predictions of which waveguide shapes from the set of waveguide shapes are capable of inducing electromagnetic radiation, and (2) to generate predictions of which pairs of waveguide shapes from the set of waveguide shapes are electromagnetically coupled to each other, wherein the plurality of computational domains are identified based on the predictions. A non-transient processor-readable medium according to claim 1, comprising code to perform the following action.

8. It is a method, The processor triggers the display of a photonic integrated circuit (PIC) within a graphical user interface (GUI), The process involves receiving indications of multiple computing regions for the PIC via the processor, based on user input, wherein each computing region from the multiple computing regions is associated with a portion of the PIC that is different from the remaining computing regions from the multiple computing regions, and the multiple computing regions include adjacent regions of the computing regions. The process involves performing electromagnetic simulations on each of the multiple computational domains via the aforementioned processor, thereby generating multiple electromagnetic simulation results. The processor assembles the plurality of electromagnetic simulation results based on adjacent regions of the computation domain and determines the simulated response for the PIC. The processor transmits information representing the PIC and associated with the control of the lithography mask writer, and processes the PIC based on the information. Methods that include...

9. The method according to claim 8, wherein the information is contained in a file associated with the input to the lithography mask writer, and the lithography mask writer is configured to cause the PIC to be fabricated based on the information.

10. The input is a first input, and the method further includes, via the processor, receiving an indication of a set of waveguide shapes before the display of the PIC, based on a second input from the user. The method according to claim 8, wherein the set of waveguide shapes represents at least a portion of the PIC.

11. The input is a first input, and the method further includes receiving an indication of a set of routes based on a second input from the user via the processor. The first path from the set of paths extends from the first edge of the first computational domain to the second edge of the first computational domain from the plurality of computational domains, The method according to claim 8, wherein a second path from the set of paths extends from a first edge of the second calculation region from the plurality of calculation regions to a second edge of the second calculation region, the first calculation region is adjacent to the second calculation region, and the first path is continuous with the second path.

12. The input is a first input, and the method further, The processor receives, based on a second input from the user, an indication from the user for associating a set of waveguide shapes with a set of paths, wherein each waveguide shape from the set of waveguide shapes extends along at least one of the entire length of the paths from the set of paths or only a portion of the paths. The processor receives an indication from the user of an offset from the path in the waveguide shape based on a third input from the user, wherein the offset is either constant along the length of the path or varies along the length of the path. The method according to claim 8, including the method described in claim 8.

13. The method according to claim 8, wherein the plurality of computational domains completely cover all portions of the PIC having an electromagnetic radiation magnitude that is predicted to exceed a predetermined threshold.

14. The method according to claim 8, wherein the plurality of computational domains do not completely cover the PIC, and any portion of the PIC not covered by the plurality of computational domains is not considered during the execution of the electromagnetic simulation and the assembly of the plurality of electromagnetic simulation results for determining the simulated response for the PIC.

15. (1) The functions of triggering the display of the PIC, receiving the indications of the plurality of computational domains for the PIC, performing the electromagnetic simulation, and assembling the plurality of electromagnetic simulation results are performed within a single electromagnetic simulator application; (2) the PIC is the first PIC; (3) the input is the first input; (4) the plurality of computational domains are the first plurality of computational domains; (5) the plurality of electromagnetic simulation results are the first plurality of electromagnetic simulation results; (6) the method further, The processor receives a representation of a second PIC, which is different from the first PIC, from an application different from the single electromagnetic simulator application. The process involves receiving indications of a second plurality of computing regions for the second PIC via the processor, based on a second input from the user, wherein each computing region from the second plurality of computing regions is associated with a portion of the second PIC that is different from the remaining computing regions from the second plurality of computing regions, and the second plurality of computing regions include adjacent regions of computing regions. The electromagnetic simulation is performed on each of the second plurality of computational domains via the aforementioned processor, and the second plurality of electromagnetic simulation results are generated. The processor assembles the second plurality of electromagnetic simulation results based on adjacent regions of the computational domains contained within the second plurality of computational domains, and determines the simulated response for the second PIC. The processor causes at least one of the following to occur: the simulated response for the second PIC is displayed or shared with the application. After assembling the second set of electromagnetic simulation results via the processor, and before causing the display of the first PIC, the first PIC is received. The method according to claim 8, including the method described in claim 8.

16. It is a device, Memory and A processor operably coupled to the memory, wherein the processor is In a display, in response to user input, a representation of a first computing region for a photonic integrated circuit (PIC) and a second computing region for the PIC distinct from the first computing region are shown, wherein the first computing region is at least partially adjacent to the second computing region via adjacent boundaries. (1) Perform a simulation on the first computational domain to produce a first simulation result, and (2) Perform a simulation on the second computational domain to produce a second simulation result, Based on the first simulation result, the second simulation result, and the adjacent boundary, the simulated response for the PIC is determined. The system transmits information representing the PIC and associated with the control of the lithography mask writer, and processes the PIC based on the information. A processor and A device equipped with the following features.

17. The apparatus according to claim 16, wherein the information is contained in a file associated with the input to the lithography mask writer, and the lithography mask writer is configured to cause the PIC to be fabricated based on the information.

18. The aforementioned input is a first input, and the processor further, Identifying the set of paths associated with the aforementioned PIC, Confirmation that the set of routes is acceptable is received via a second input from the user. The apparatus according to claim 16, configured to perform the following:

19. The adjacent boundary is the first adjacent boundary, and the processor further, The display, based on the input from the user, shows a representation of a third calculation area for the PIC, which is different from the first and second calculation areas, wherein the third calculation area is at least partially adjacent to at least one of the first or second calculation areas via a second adjacent boundary that is different from the first adjacent boundary. The simulation is performed on the third computational domain to produce the third simulation result. It is configured to do the following: The apparatus according to claim 16, wherein the processor is configured to determine the simulated response for the PIC based on the third simulation result and the second adjacent boundary.

20. The adjacent boundary is the first adjacent boundary, and the processor further, The display, based on the input from the user, shows a representation of a third calculation area for the PIC, which is different from the first and second calculation areas, and a fourth calculation area for the PIC, which is different from the first, second, and third calculation areas, wherein the third calculation area is at least partially adjacent to the fourth calculation area via a second adjacent boundary that is different from the first adjacent boundary. Performing a simulation in the third computational domain to produce a third simulation result, and performing a simulation in the fourth computational domain to produce a fourth simulation result. It is configured to do the following: The processor is configured to determine the simulated response for the PIC based on the third simulation result, the fourth simulation result, and the second adjacent boundary. The apparatus according to claim 16.

21. The apparatus according to claim 16, wherein the representation of the first and second computational domains, the performance of the simulation, and the determination of the simulated response are performed within a single simulator application.

22. The aforementioned processor further, To automatically identify a first potential computing area for the PIC without requiring user input, To automatically identify a second potential computing area for the PIC without requiring user input, The input is to receive confirmation that the first computational domain and the second computational domain are acceptable, wherein the first potential computational domain becomes the first computational domain in response to the receipt of the confirmation, and the second potential computational domain becomes the second computational domain in response to the receipt of the confirmation. The apparatus according to claim 16, configured to perform the following:

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