Method and apparatus for fabricating thin semiconductor chips using sacrificial sidewall layers

Abstract

Embodiments of this disclosure relate to methods and apparatus for fabricating thin semiconductor chips using sacrificial sidewall layers. This disclosure provides apparatus and methods in which the semiconductor chip has reduced size and thickness. The apparatus is fabricated using a sacrificial or sacrificial silicon wafer. A recess is formed in the sacrificial silicon wafer, in which the semiconductor chip is mounted. The space between the sacrificial silicon wafer and the chip is filled using an underfill material. Using any suitable etching process, the back sides of the sacrificial silicon wafer and the chip are etched until the sacrificial silicon wafer is removed and the thickness of the chip is reduced. Using this process, in some embodiments, the overall size of the semiconductor chip can be thinned to less than 50 μm. This ultrathin semiconductor chip can be incorporated into the fabrication of flexible / rollable display panels, foldable mobile devices, wearable displays, or any other electrical or electronic equipment.

Description

Technical Field

[0001] This disclosure relates to a method and apparatus for manufacturing integrated circuit (IC) chips with reduced thickness, suitable for use in wearable electronics and flexible devices. Background Technology

[0002] With growing interest in flexible devices and wearable electronics, the semiconductor manufacturing industry is struggling to find a way to make semiconductor devices, or IC chips, thinner to ultra-thin levels. Current semiconductor manufacturing processes typically produce IC chips with a thickness greater than approximately 100 μm, or even thicker. However, further thinning of IC chips is not feasible due to inherent limitations of existing manufacturing processes.

[0003] With limitations on the ability to thin IC chips, the semiconductor industry is unable to expand the application of its IC chips into various technological fields, such as rollable displays, foldable mobile devices, wearable displays, and flexible film displays, which are beyond the conventional application areas.

[0004] Due to the limitations of conventional IC chips, the size and thickness of the chips cannot meet the growing industry demand for IC chips with the smallest possible size. Summary of the Invention

[0005] This disclosure relates to the manufacture of semiconductor chips with reduced size and thickness. Accordingly, semiconductor chips and methods for manufacturing such semiconductor chips with an overall ultra-thin size are provided. By providing semiconductor chips with reduced thickness (less than 50 μm in some embodiments), the industry can find breakthroughs in realizing the aforementioned rollable displays, foldable mobile devices (e.g., mobile handsets, laptops, tablets, etc.), wearable displays, and flexible film displays.

[0006] In various embodiments, electronic devices incorporating one or more semiconductor chips of this disclosure will have reduced dimensions (such as reduced thickness).

[0007] In various embodiments, this disclosure provides a method for manufacturing a semiconductor chip with reduced thickness by employing a sacrificial (or surrogate) wafer as a sidewall. The sacrificial wafer may be a silicon wafer, and it serves as a sacrificial sidewall when an underfill material is filled between the semiconductor chip and the sacrificial wafer. The sacrificial wafer is then further co-ground with the passive surface (i.e., the surface without active circuitry components) of the semiconductor chip to be thinned to a preferred thickness. This process using a sacrificial silicon wafer helps to significantly reduce the size of the semiconductor chip.

[0008] In at least one embodiment, this disclosure provides a semiconductor device including a circuit board, a chip, a plurality of solder balls, and an underfill material. The chip is positioned on the surface of the circuit board and has a first side and a second side opposite to the first side. The plurality of solder balls are electrically coupled to the circuit board and the first side of the chip, and the solder balls are spaced apart from each other. The underfill material contacts the circuit board, the chip, and the solder balls, and the underfill material has a first surface opposite to the surface of the circuit board and sidewalls transverse to the first surface.

[0009] In some embodiments, the second side of the chip and the first surface of the underlying filler material are substantially coplanar.

[0010] In some embodiments, the first surfaces of the sidewalls and the bottom fill material are perpendicular to each other.

[0011] In some embodiments, the sidewalls of the underfill material are substantially perpendicular to the surface of the circuit board, and the first surface of the underfill material is substantially parallel to the circuit board.

[0012] In some embodiments, the underfill material extends between the spaced solder balls and laterally surrounds the solder balls.

[0013] In some embodiments, the semiconductor device further includes a first contact pad on the surface of the circuit board. At least one of the plurality of solder balls is mounted on the first contact pad.

[0014] In some embodiments, the semiconductor device further includes a second contact pad on a first side of the chip. At least one of the plurality of solder balls is connected to the second contact pad and the chip.

[0015] In some embodiments, the circuit board is a flexible printed circuit board.

[0016] In some embodiments, the thickness of the chip between the first side and the second side is less than 50 μm.

[0017] In one or more embodiments, this disclosure provides a method comprising: attaching a silicon wafer to the surface of a circuit board having conductive pads; forming a recess that exposes a first portion of the conductive pads and the surface of the circuit board by removing a portion of the silicon wafer; positioning a chip at least partially in the recess, the chip having a first surface facing the circuit board; distributing an underfill material in the recess, the underfill material substantially filling the space between the silicon wafer and the chip, and filling the space between the chip in the recess and the surface of the circuit board; forming a second surface of the chip coplanar with the silicon wafer by removing a portion of the chip opposite to the first surface; and exposing a second portion of the surface of the circuit board by removing the silicon wafer. Attached Figure Description

[0018] To better understand the embodiments, reference will now be made to the accompanying drawings by way of example only. In the drawings, the same reference numerals identify similar elements or actions. The dimensions and relative positions of elements in the drawings need not be drawn to scale. For example, the shapes and angles of individual elements need not be drawn to scale, and some of these elements may be enlarged and positioned to improve the readability of the drawings. Furthermore, the particular shapes of elements shown are not necessarily intended to convey any information about the actual shape of that particular element, and these shapes may be chosen solely for simple identification in the drawings.

[0019] Figure 1 This is a cross-sectional view of an example embodiment of a semiconductor device according to the present disclosure.

[0020] Figure 2 This is a cross-sectional view of a structure including a circuit board provided on a carrier, according to an embodiment of the present disclosure.

[0021] Figure 3 This is a cross-sectional view of a structure including a sacrificial layer provided on a circuit board, according to an embodiment of the present disclosure.

[0022] Figure 4A According to one embodiment of this disclosure, along Figure 4B A cross-sectional view of the structure with cut lines 4A-4A, showing the mask on the sacrificial layer.

[0023] Figure 4B This is a top view of a structure having a mask on a sacrificial layer according to an embodiment of the present disclosure.

[0024] Figure 5 This is a cross-sectional view of a structure formed by etching a sacrificial layer according to an embodiment of the present disclosure.

[0025] Figure 6 This is a cross-sectional view of a structure including a semiconductor chip mounted on a circuit board, according to an embodiment of the present disclosure.

[0026] Figure 7A According to one embodiment of this disclosure, along Figure 7B A cross-sectional view of the structure with cut lines 7A-7A shows the underlying filler material being filled between the semiconductor chip and the sacrificial layer.

[0027] Figure 7B This is a top view of a structure having an underfill material filled between a semiconductor chip and a sacrificial layer, according to an embodiment of the present disclosure.

[0028] Figure 8 This is a cross-sectional view of a structure in which etching is performed on a sacrificial layer and a portion of a semiconductor chip according to an embodiment of the present disclosure. Detailed Implementation

[0029] In the following description, certain specific details are set forth in order to provide a thorough understanding of the various embodiments disclosed. However, those skilled in the art will recognize that the embodiments may be practiced without one or more of these specific details, or using other methods, components, materials, etc. In other instances, well-known structures associated with semiconductor chips or semiconductor chip packages have not been shown or described in detail to avoid unnecessarily obscuring the description of the embodiments.

[0030] Unless otherwise required herein, the word “comprising” and its variations, such as “comprises” and “comprising”, throughout the following specification and claims are to be interpreted in an open, inclusive sense, meaning “including, but not limited to”. Furthermore, unless expressly indicated otherwise herein, the terms “first,” “second,” and similar sequences are to be interpreted as interchangeable.

[0031] The reference to "an embodiment" or "an embodiment" throughout this specification means that a particular feature, structure, or characteristic described relating to an embodiment is included in at least one embodiment. Therefore, the appearance of the phrase "an embodiment" or "an embodiment" throughout this specification does not necessarily refer to the same embodiment in all instances. Furthermore, the particular feature, structure, or characteristic may be combined in any suitable manner in one or more embodiments.

[0032] As used in this specification and the appended claims, the singular forms “a,” “an,” and “the” include the plural objects referred to, unless otherwise expressly indicated in the text. It should also be noted that the term “or” is generally used in its broadest sense, meaning “and / or,” unless otherwise expressly specified in the text.

[0033] Figure 1 This is a cross-sectional view of an example embodiment of a semiconductor device 10 according to the present disclosure. The semiconductor device 10 includes: a circuit board 110, and a semiconductor structure 100 having a semiconductor chip 130 and an underfill material 150.

[0034] In this embodiment, the semiconductor structure 100 is mounted on a circuit board 110. The semiconductor structure 100 includes a semiconductor chip 130, which, among other things, has various active and passive circuits (such as transistors, resistors, capacitors, and logic circuits) on or near a first surface 138 of the semiconductor chip 130. However, other embodiments may include fewer or more semiconductor structure elements according to specific design requirements. The term "semiconductor chip" may also be used to refer to a semiconductor package in one or more embodiments.

[0035] The first contact pad 160 is located on the first surface 138 of the semiconductor chip 130. In one embodiment, the outer surface of the first contact pad 160 is coplanar with the first surface 138 of the semiconductor chip 130. However, in other embodiments, the first contact pad 160 may not be coplanar with the first surface 138 of the semiconductor chip 130 (e.g., where the first contact pad 160 extends outward beyond the first surface 138). In one or more embodiments, the first contact pad 160 is coplanar with the first surface 138 to reduce the height or thickness H1 of the semiconductor chip 130 and the thickness H2 of the semiconductor structure 100.

[0036] Solder balls 140 are positioned between semiconductor chip 130 and circuit board 110 to provide electrical contact. For example, solder balls 140 can be melted to create an electrical connection for attaching semiconductor chip 130 to circuit board 110. For example, chip 130 can be inverted such that solder balls 140 are positioned between a first contact pad 160 on chip 130 and a second contact pad 120 on the underlying electronics or circuit board 110, and the solder balls are melted using, for example, ultrasonic thermal soldering, reflow soldering, or any other known method. The space between the chip's circuitry and circuit board 110 is filled with an underfill material 150. For example, the underfill material may extend between circuit board 110 and a first surface 138 of semiconductor chip 130.

[0037] In one or more embodiments, solder balls 140 are attached to circuit board 110 via second contact pads 120 located on circuit board 110. The second contact pads 120 may be coplanar with a surface of circuit board 110 (e.g., the upper surface as shown). In other embodiments, the second contact pads 120 may be arranged in a non-coplanar manner, for example, where the second contact pads 120 extend outward beyond the surface of circuit board 110. Solder balls 140 form electrical paths that transmit electrical signals radially to and from the first contact pads 160 of semiconductor chip 130 and the second contact pads 120 of circuit board 110. Solder balls 140 may be any suitable conductive structure capable of transmitting electrical signals and may be (but are not limited to) solder blocks or solder joints, etc.

[0038] Underfill material 150 is located adjacent to semiconductor chip 130 and solder ball 140. Underfill material 150 can be used to improve the structural integrity of the joint (e.g., solder ball 140) and provide a stronger mechanical connection. Furthermore, underfill material 150 can be used to make semiconductor structure 100 reliably resistant to vibration, shock, cracks, or temperature changes, enabling semiconductor structure 100 to withstand the product's lifespan. For example, underfill material 150 disperses thermal expansion mismatch between semiconductor chip 130 and circuit board 110, preventing stress concentration in solder ball 140. Underfill material 150 also provides thermal bridging and reduces or eliminates stress in solder ball 140 caused by the chip and remainder (not shown) of the differential heating system, to which semiconductor structure 100 can be connected or, conversely, included as part of the remainder (not shown).

[0039] In one embodiment, the underfill material 150 laterally surrounds the periphery of the semiconductor chip 130 and substantially fills the space between the solder balls 140. In one or more embodiments, the underfill material 150 may have a surface 170 (e.g., the upper surface shown) and sidewalls 180, and the surface 170 and sidewalls 180 may be laterally adjacent to each other. In one embodiment, the sidewalls 180 of the underfill material 150 are substantially perpendicular or orthogonal to the surface of the circuit board 110. For example, the sidewalls 180 may have a precisely vertical surface relative to the circuit board 110 due to the use of a sacrificial sidewall layer, which will be described in detail in the following figures. The first surface 138 and the second surface 136 of the semiconductor chip 130 are opposite each other and may be parallel to each other. In one embodiment, the second surface 136 of the semiconductor chip 130 is coplanar with the surface 170 of the underfill material 150. For example, the second surface 136 of the semiconductor chip 130 and the surface 170 of the underfill material 150 may be coplanar due to the simultaneous application of an etching process to both surfaces. The underfill material 150 may be any suitable electrically insulating material. For example, electrical insulating materials can be epoxy resin molding compounds, etc.

[0040] The first contact pad 160 is located on the first plane 138 of the semiconductor chip 130. As explained above, in one embodiment, the first contact pad 160 may cover (or extend outward from) a region of the semiconductor chip 130, and the first contact pad 160 does not necessarily need to have a surface coplanar with the first plane 138 of the semiconductor chip 130. However, in some embodiments, the first contact pad 160 may be embedded or recessed into the semiconductor chip 130, and the first contact pad 160 may have a top surface coplanar with the semiconductor chip 130. Embedding the first contact pad 160 into the semiconductor chip 130 may involve etching the chip 130 and distributing the pad 160 onto the etched portion of the chip 130. This contact may be part of a processing step for forming active and passive circuitry in the chip 130. Therefore, in some embodiments, the first contact pad 160 may be disposed on the semiconductor chip 130 at a location lower than the first surface 138 of the semiconductor chip 130, which allows the overall thickness H2 of the semiconductor structure 100 to be further reduced. In one embodiment, the first contact pad 160 may be a metal pad and may be made of a conductive material, including (but not limited to) metals such as copper (Cu), aluminum (Al), nickel (Ni), chromium (Cr), titanium (Ti), or any combination thereof. Similarly, the second contact pad 120 may be made of the same or similar conductive material as the first contact pad 160 and formed in substantially the same or similar manner as the first contact pad 160.

[0041] Circuit board 110 is electrically and physically connected to second contact pad 120. Furthermore, although not shown, circuit board 110 may be electrically and physically connected to other electronic components or other circuits (not shown). In one embodiment, circuit board 110 includes a flexible printed circuit board (PCB). A flexible PCB mounts electronic devices on a flexible plastic substrate, such as polyimide, polyetheretherketone (PEEK), or a transparent conductive polyether film. However, the type of flexible plastic substrate can vary accordingly based on other design requirements and manufacturing processes, and is not limited to the examples described above. Examples of flexible PCBs include single-sided circuits, double-sided circuits, multilayer circuits, rigid-flex circuits, etc.

[0042] Semiconductor chip 130 refers to any suitable semiconductor device manufactured using semiconductor materials such as silicon (Si). The term semiconductor chip 130 can be used interchangeably with integrated circuit (IC) chip or microchip, both of which broadly refer to a collection of electronic circuits having electronic components. In one embodiment, semiconductor chip 130 may be electrically connected to circuit board 110 using flip-chip processing or any suitable process for interconnecting semiconductor devices (such as interconnecting IC chips to external circuitry using solder balls 140). In one embodiment, solder balls 140 are applied to chip 130, and in order to mount chip 130 to an external circuit device (e.g., a circuit board or another chip or wafer), the chip is flipped so that its top side faces down, and the chip is aligned so that its contact pads 160 align with matching contact pads 120 on the external circuitry, and then solder is reflowed to complete the interconnection.

[0043] In one or more embodiments, the second surface 136 of the semiconductor chip 130 is a passivated surface of the semiconductor chip. For example, the semiconductor chip 130 may be located at or near the second surface 136 without any active circuit components. This surface can be formed by etching the semiconductor chip 130 to give the semiconductor chip 130 a thickness of less than 50 μm. On the other hand, the first surface 138 is the active surface of the semiconductor chip, where electronic circuit components are formed.

[0044] By utilizing the manufacturing process according to this disclosure, the thickness H1 of the semiconductor chip 130 can be less than 100 μm, and in some embodiments, the thickness H1 can be less than 50 μm. For example, using a sacrificial silicon wafer wall, the thickness H1 of the semiconductor chip 130 can be thinned to approximately 30 μm or less. The solder ball 140 can have a height between 15 μm and 200 μm. Accordingly, the thickness H2 of the semiconductor structure 100 can be in the range of approximately 45 μm to 250 μm. In one example, the semiconductor structure 100 can have a thickness as small as approximately 45 μm. The manufacturing process according to this disclosure for obtaining an ultrathin semiconductor chip (less than 50 μm) will be... Figures 2 to 8 The explanation is provided below.

[0045] Figures 2 to 8 This is a cross-sectional view illustrating an example method for fabricating an ultrathin semiconductor chip according to an exemplary embodiment of the present disclosure.

[0046] Figure 2 This is a cross-sectional view of a structure 200 including a circuit board 110 provided on a carrier 205, according to the present disclosure.

[0047] The carrier 205 provides support for further processing of the circuit board 110. In one embodiment, the carrier 205 may be made of materials including, but not limited to, silicon (Si), gallium arsenide (GaAs), glass, or ceramic. In other embodiments, any suitable structure for providing support for the processing of the flexible printed circuit board may be used.

[0048] A circuit board 110 is provided on a surface 114 of a carrier 205. The surface 114 of the carrier 205 physically contacts the surface of the circuit board 110. The surfaces 114 of the carrier 205 and 112 of the circuit board 110 are opposite to each other and may be parallel to each other. A plurality of second contact pads 120 are formed on the surface 112 of the circuit board 110 and are formed to be coplanar with the circuit board 110. For example, the second contact pads 120 may be embedded or recessed into the circuit board 110 and may have a top surface coplanar with the circuit board 110. Embedding the second contact pads 120 in the circuit board 110 may involve etching the board 110 and arranging the contact pads 120 on the etched portions of the board 110. In another embodiment, the second contact pads 120 may be overlapped on a region of the circuit board 110 and do not necessarily have a surface coplanar with the surface 112 of the circuit board 110. In other embodiments, the second contact pad 120 may be assigned on the board 110, positioned below the surface 112 of the board 110, which allows the semiconductor structure 100 ( Figure 1The overall thickness H2 is further reduced. The second contact pad 120 (similar to the first contact pad 160) can be made of a conductive material (including, but not limited to, metals such as Cu, Al, etc.).

[0049] In one embodiment, the circuit board 110 may be a flexible printed circuit board formed on the surface of the carrier 205, and the thickness of the flexible printed circuit board may range from approximately 70 μm to 150 μm. Other circuit boards 110 with different thickness ranges may also be used. In addition, various methods known in the art can be used to attach or mount the circuit board 110 to the carrier 205.

[0050] Figure 3 This is a cross-sectional view of a structure 300 including a sacrificial layer 310 provided on a circuit board 110, according to an embodiment of the present disclosure.

[0051] A sacrificial layer 310 is provided on the surface 112 of the circuit board 110. In one embodiment, the sacrificial layer 310 comprises a silicon wafer. However, other suitable sacrificial layers besides silicon wafers may also be used to achieve an ultra-thin semiconductor chip. The sacrificial layer 310 may be attached or bonded to the circuit board 110 using any suitable method (such as any suitable method for silicon wafer bonding). However, other bonding methods known in the art may also be used.

[0052] Once the sacrificial layer 310 is bonded to the circuit board 110, the top surface of the sacrificial layer 310 is ground. For example, the grinding or thinning of the wafer is performed by mechanical grinding. For example, silicon can be removed by a first coarse grinding followed by a fine grinding. Grinding tools containing diamond particles of a specific size can be used. Coarse grinding significantly reduces the thickness of the sacrificial layer 310 (e.g., the silicon wafer), which can cause microcracks and damage to the silicon lattice. Fine grinding then completes the grinding process and removes any potentially damaged portions of silicon. However, other suitable grinding or thinning methods known in the art can also be used.

[0053] In one embodiment, the sacrificial layer 310 is ground to a thickness of 45 μm to 250 μm, that is, the top of the sacrificial layer 310 is ground such that the thickness between the surface 112 of the circuit board 110 and the surface 312 of the sacrificial layer 310 has the thickness described above. The surface 312 of the sacrificial layer 310 is opposite to the surface 112 of the circuit board 110, and they can be parallel to each other. In some embodiments, the degree to which the sacrificial layer is ground to a certain thickness can be used to determine the overall thickness that the semiconductor chip 130 will ultimately have. This will be combined with Figure 8 It is explained in more detail in the description.

[0054] Figure 4A According to one embodiment of this disclosure, along Figure 4B A cross-sectional view of structure 400 with cut lines 4A-4A shows mask 410 on sacrificial layer 310. Figure 4B This is a top view of a structure 400 having a mask 410 on a sacrificial layer 310 according to an embodiment of the present disclosure.

[0055] Figure 4A The diagram illustrates a mask 410 superimposed on the sacrificial layer 310. The mask 410 is applied to the surface of the sacrificial layer 310 such that only the unmasked areas of the sacrificial layer 310 are exposed. These unmasked areas can be referred to as openings 415. Based on... Figure 1 The size and dimensions of the semiconductor chip 130 shown herein allow the size of the opening 415 to be determined. More specifically, the opening 415 can be selected to have a sufficiently large size so that the semiconductor chip 130 can be fitted into the recess subsequently formed through the opening 415. A masked area of ​​mask 410 is used. The sacrificial layer 310 can be protected from etching by the wet etching method used (e.g., plasma cutting or water jet etching). Any suitable mask known in the art for protecting the sacrificial layer 310 from etching can be used.

[0056] exist Figure 4B As can be seen, mask 410 forms an additional opening 420 that protrudes from opening 415. In some embodiments, opening 415 may be generally rectangular in shape, while the additional opening 420 may be semi-circular or other shapes, protruding outward from the edge of opening 415. It will be readily appreciated that opening 415 and additional opening 420 may be part of the same opening or aperture formed by mask 410. The additional opening 420 provides, as in... Figure 1 The space filled with the underlying filler material is shown in the diagram (e.g., through an injection process). The injection process of the underlying filler material will be combined with... Figure 7A and 7B This is explained in detail. As shown, the additional opening 420 is illustrated as a semi-circular shape. However, in other embodiments, the additional opening 420 can have a variety of different shapes and sizes. For example, the additional opening 420 can have a triangular shape, a rectangular shape, or any other shape. In various embodiments, the additional opening 420 can have any suitable size and shape for the injection processing apparatus to inject the underfill material 15 into the additional opening 420. In one embodiment, the additional opening 420 has a semi-circular shape with a diameter ranging from 150 μm to 400 μm.

[0057] The additional opening 420 is located adjacent to (and protrudes from) the opening 415 of the mask 410. (As from...) Figure 4BAs can be seen, the depicted location is shown at the upper left corner of opening 415; however, additional opening 420 can be positioned in various suitable locations for filling the underfill material 150 between the sacrificial layer 310 and the semiconductor chip 130. In other embodiments, if the underfill material 150 can be injected between the sacrificial layer 310 and the semiconductor chip 130, the additional opening 420 can be spaced from opening 415 of mask 410.

[0058] Figure 5 This is a cross-sectional view of a structure 500 formed by etching the sacrificial layer 310 according to an embodiment of the present disclosure.

[0059] Etching process 510 is employed to etch the exposed or unmasked areas of the sacrificial layer 310. The unmasked areas of the sacrificial layer 310 correspond to... Figure 4A The opening 415 shown in the figure and Figure 4B The opening 420 is shown in the diagram. An etching process 510 is applied until the surface 112 of the circuit board 110 and the second link pad 120 are exposed. In various embodiments, the etching process 510 may include dry etching, wet etching, or plasma cutting. In the etching process, liquid (“wet”) or plasma (“dry”) chemicals remove the uppermost layer of the substrate (e.g., sacrificial layer 310) in areas not protected by the mask 410 or photoresist. This etching process removes the unmasked sacrificial layer 310 while forming sidewalls 520 using the sacrificial layer 310 that was not etched during the etching process 510. In one or more embodiments, the etching process 510 shapes the sidewalls 520 of the sacrificial layer 310, which are flat and perpendicular to the surface 112 of the circuit board 110. For example, because the sacrificial layer 310 (a silicon wafer in one embodiment) is etched by plasma cutting the sidewalls 520, the sacrificial layer 310 can have sharp, orthogonal, vertical sidewalls 520 that are close to or approximately 90 degrees to the surface 112 of the circuit board 110. In some embodiments, the sidewalls 520 may be somewhat tapered as a result of etching.

[0060] Before subsequent processing, the remaining mask 410 is removed. That is, the mask 410 or photoresist is removed from the sacrificial layer 310 after it is no longer needed. In one embodiment, a resist stripper can be used to remove the mask 410. The resist stripper chemically alters the resist so that it no longer adheres to the sacrificial layer 310. Other known alternative methods can be used to remove the mask 410. For example, the mask 410 can be removed by using oxygen-containing plasma or other suitable methods.

[0061] Figure 6This is a cross-sectional view of a structure 600 including a semiconductor chip 130 mounted on a circuit board 110, according to an embodiment of the present disclosure.

[0062] exist Figure 6 In this configuration, the semiconductor chip 130 is mounted on the recessed portion 610 of the sacrificial layer 310. For example, in... Figure 5 As shown and described herein, the recessed portion 610 of the sacrificial layer 310 may, for example, be a portion of the dummy layer 310 removed by etching. The semiconductor chip 130 shown here is related to... Figure 1 The difference in chip 130 shown is its thickness. Figure 6 The thickness of semiconductor chip 130, designated H3, is greater than the thickness of H1. The thickness H3 of semiconductor chip 130 will be reduced to a thickness greater than H1. Figure 1 The thickness H1 in the middle. The thickness H4 of the sacrificial layer 310 is less than the thickness H3 of the semiconductor chip 130 in some embodiments.

[0063] In one embodiment, a flip-chip process is used to attach a semiconductor chip 130 to a circuit board 110. Specifically, this process may include creating an integrated circuit on the wafer. In this process, first contact pads 160 are metallized on a first surface 138 of the semiconductor chip 130. Solder balls 140 are then distributed onto each of the first contact pads 160. Individual chips are cut, and the semiconductor chip 130 is flipped and positioned so that the solder balls 140 face second contact pads 120 of external circuitry, such as the circuit board 110. Subsequently, these solder balls 140 are melted using a high-temperature reflow soldering process or the like to complete the interconnection.

[0064] Figure 7A According to one embodiment of this disclosure, along Figure 7B A cross-sectional view of structure 700 with cut lines 7A-7A shows the underfill material filled between the semiconductor chip and the sacrificial layer. Figure 7B This is a top view of an embodiment of the present disclosure showing the underfill material between the semiconductor chip and the sacrificial layer.

[0065] exist Figure 7A In the cross-sectional view, the underfill material 150 is shown filling the space between the solder balls 140 and the space between the semiconductor chip 130 and the sacrificial layer 310.

[0066] In one or more embodiments, the thickness H4 of the sacrificial layer 310 and the thickness of the semiconductor chip 130 from the top surface 312 of the sacrificial layer 310 are the same. Then, portions of the sacrificial layer 310 and the semiconductor chip 130 are etched using a dry etching or wet etching method. This process will combine... Figure 8It was explained in detail.

[0067] Figure 7B An underfill injection apparatus 720 for injecting underfill material 150 at the locations mentioned above is shown. The underfill injection apparatus 720 uses an opening 420 to inject the underfill material 150. As shown, the opening 420 is illustrated as a semi-circular shape with a diameter D. In various embodiments, the opening 420 can have various different shapes and sizes, provided that the dimensions of the opening 420 provide a suitable injection aperture for injecting the underfill material 150. For example, the diameter D of the semi-circular opening 420 can range from approximately 150 μm to 400 μm. However, smaller or larger diameters D can be used depending on the type of underfill injection apparatus used and the size of the semiconductor chip 130.

[0068] In addition to the opening 420 for the underfill implantation apparatus 720, another space exists between the semiconductor chip 130 and the sacrificial layer 310 (e.g., the sidewall of the sacrificial layer 310), which will be filled by the underfill material 150. The space between the sacrificial layer 310 and the semiconductor 130 has a first width W1 and a second width W2. This portion of the underfill material 150 will subsequently form the sidewall of the semiconductor chip 130. In one embodiment, the first width W1 and the second width W2 may be approximately 50 μm. That is, the first width W1 and the second width W2 may have the same width. In other embodiments, the first width W1 and the second width W2 may have widths greater than or less than approximately 50 μm. The width and space formed between the sacrificial layer 310 and the semiconductor chip 130 can vary based on different designs and different dimensions.

[0069] In some embodiments, the first width W1 and the second width W2 may be different from each other. For example, the second width W2 may be smaller than W1 because the slightly larger first width W1 provides more space for the underfill injection apparatus 720 to inject the underfill material 150. However, in other embodiments, the second width W2 may have a width greater than the first width W1.

[0070] Figure 8 This is a cross-sectional view of a structure 800 in which etching is performed on a sacrificial layer and a portion of a semiconductor chip 130 according to an embodiment of the present disclosure.

[0071] Etching process 810 is performed to etch away the sacrificial layer 310 adjacent to the semiconductor chip 130 and a portion of the semiconductor chip 130. In some embodiments, a portion of the underfill material 150 may be etched together with the sacrificial layer 310 and a portion of the semiconductor chip 130, and in other embodiments, the underfill material 150 may be resistant to the etchant so that the underfill material 150 has substantially the same geometry after the etching process is completed as before the etching process. The etching process 810 used herein can be combined with... Figure 5 The etching processes used are similar or substantially the same as those shown. In various embodiments, etching process 810 may include dry etching or wet etching. One example of dry etching that can be used is plasma cutting. This etching process removes the sacrificial layer 310 and exposes the surface 112 of the circuit board 110 and portions of the semiconductor chip 130. For example, a plasma cutting process may etch the sacrificial layer 310 and the semiconductor chip 130 at substantially the same or similar rate (e.g., each of the sacrificial layer and the semiconductor chip may be formed of silicon). As a result, when the plasma cutting process is applied, the thickness H4 of the sacrificial layer 310 can be completely removed by etching, thereby exposing the surface 112 of the circuit board 110, and the same thickness H4 can be removed from the semiconductor chip 130 by etching. This process results in the semiconductor chip 130 having a thickness H1 (which is the thickness of the semiconductor chip 130 after etching). Figure 6 As explained, the original thickness of semiconductor chip 130 is H3. However, by using etching process 810 to etch silicon (e.g., silicon sacrificial layer 310 and silicon chip 130) at the same rate, the original thickness H3 of semiconductor chip 130 is reduced to H1 (e.g., H3-H4=H1) by etching away a thickness equal to H4. Accordingly, in some embodiments, the thickness of semiconductor chip 130 is based on the sacrificial layer 310.

[0072] In one or more embodiments, plasma cutting leaves a smooth, vertical edge with a trace on the edge or sidewall surface 180 of the underfill material 150. This creates a lateral relationship between the sidewall 180 and the surface 112 of the circuit board 110. For example, because the sacrificial layer 310 (in one embodiment, a silicon wafer) is plasma-cut, the sidewall 180 may have a sharp, orthogonal sidewall that is close to or approximately 90 degrees to the surface 112 of the circuit board 110.

[0073] Following an etching process 810 that causes the removal of a portion of the sacrificial layer 310 and the semiconductor chip 130, separation of the semiconductor chip 130, including the circuit board 110, is performed. Although not shown, those skilled in the art will readily recognize that multiple semiconductor chips in an array can be mounted on the carrier 205. After each semiconductor chip is separated, each semiconductor chip 130 is removed from the carrier 205 by means of... Figures 2 to 8 The final product processed in Figure 1 It is shown in the middle.

[0074] Based on this disclosure, it is possible to manufacture semiconductor chips with compact dimensions of less than 50 μm. These ultrathin semiconductor chips can save space and thus provide more space for integrating chips by stacking them vertically or horizontally.

[0075] The various embodiments described above can be combined to provide additional embodiments, and these and other modifications can be made to the embodiments based on the detailed description above. Generally, the terminology used in the following claims should not be construed as limiting the claims to the specific embodiments disclosed in this specification and claims, but should be construed as including all possible embodiments and the full scope of equivalents entitled to be enjoyed in these claims. Accordingly, the claims are not limited by this disclosure.

Claims

1. A semiconductor device, comprising: A circuit board having a first surface; A chip, on the first surface of the circuit board, the chip having a first side and a second side opposite to the first side; Multiple solder balls are electrically coupled to the first side of the circuit board and the chip, and the multiple solder balls are spaced apart from each other; as well as An underfill material contacts the circuit board, the chip, and the solder balls. The underfill material has a second surface opposite to the first surface of the circuit board and sidewalls transverse to the second surface. The outer edge of the bottom filling material; as well as The side edge of the circuit board, the outer edge of the underfill material is positioned inside relative to the side edge of the circuit board, and the first surface of the circuit board is exposed between the sidewall of the underfill material and the side edge of the circuit board; The second side of the chip and the second surface of the underlying filler material are coplanar. The sidewalls of the underlying filler material and the second surface of the underlying filler material are perpendicular to each other.

2. The semiconductor device of claim 1, wherein the sidewall of the underlying filler material is perpendicular to the first surface of the circuit board, and the second surface of the underlying filler material is parallel to the circuit board.

3. The semiconductor device of claim 1, wherein the underlying filler material extends between the spaced solder balls and laterally surrounds the solder balls.

4. The semiconductor device according to claim 1, further comprising: On the first contact pad of the circuit board, at least one of the plurality of solder balls is mounted on the first contact pad.

5. The semiconductor device according to claim 4, further comprising: On the first side of the chip, at least one of the plurality of solder balls is connected to the second contact pad and the chip.

6. The semiconductor device according to claim 1, wherein the circuit board is a flexible printed circuit board.

7. The semiconductor device of claim 1, wherein the thickness of the chip between the first side and the second side is less than 50 μm.

8. A method for manufacturing a semiconductor device, comprising: Attach the silicon wafer to the first surface of a circuit board with conductive pads; By removing a portion of the silicon wafer, a recess is formed that exposes the conductive pads and a first portion of the first surface of the circuit board; The chip is positioned at least partially in the recess, the chip having a second surface facing the circuit board; An underfill material is distributed in the recess, the underfill material filling the space between the silicon wafer and the chip, and filling the space between the chip and the first surface of the circuit board in the recess; A third surface of the chip is formed by removing the portion of the chip that is opposite to the second surface; as well as By removing the silicon wafer, a second portion of the first surface of the circuit board is exposed; The process of simultaneously etching the chip and the silicon wafer to form the third surface of the chip and the second portion of the first surface of the circuit board is performed simultaneously.

9. The method of claim 8, further comprising electrically connecting the chip to the conductive pads of the circuit board.

10. The method of claim 8, wherein the etching comprises plasma cutting.

11. The method of claim 8, wherein the selected thickness of the chip is less than 50 μm.

12. The method of claim 8, wherein the second surface of the chip is the active surface of the chip.

13. The method of claim 8, wherein the space between the silicon wafer and the chip is less than 50 μm.

14. The method of claim 8, wherein forming the recess comprises: A mask is disposed on the silicon wafer; A first opening is formed in the mask, the first opening corresponding to the area of ​​the circuit board to be exposed. A second opening is formed in the mask for injecting the underlying filler material, and the second opening is adjacent to the first opening. as well as The portion of the silicon wafer is removed by etching the portion of the silicon wafer exposed by the first opening and the second opening.

15. The method of claim 14, wherein the second opening has a semi-circular shape and the diameter of the semi-circle is less than 400 μm.

16. A method for manufacturing a semiconductor device, comprising: A sacrificial layer having a first thickness is provided on a circuit board having multiple conductive pads; By removing a portion of the sacrificial layer, a recess is formed that exposes the plurality of conductive pads; A chip is positioned in the recess, the chip having a second thickness greater than the first thickness; as well as By simultaneously etching the chip and the sacrificial layer, a portion of the chip and the sacrificial layer are removed, and after the etching, the chip has a third thickness that is less than the second thickness.

17. The method of claim 16, wherein after the etching, the chip has a thickness of less than 50 μm.

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