Method for manufacturing semiconductor device and semiconductor device

Abstract

The semiconductor device includes a fin structure protruding from a first isolation insulating layer disposed above a substrate, a gate dielectric layer disposed above a channel region of the fin structure, a gate electrode layer disposed above the gate dielectric layer, a base semiconductor epitaxial layer disposed above a source / drain region of the fin structure, and a cap semiconductor epitaxial layer disposed above the base semiconductor epitaxial layer. The cap semiconductor epitaxial layer has a lattice constant different from that of the base semiconductor epitaxial layer, and the surface roughness of the cap semiconductor epitaxial layer along the source to drain direction is greater than zero and less than the surface roughness of the base semiconductor epitaxial layer along the source to drain direction. An embodiment of the present invention also relates to a method for manufacturing a semiconductor device.

Description

Technical Field

[0001] Embodiments of the present invention relate to a method of manufacturing a semiconductor device and a semiconductor device. Background Art

[0002] As the semiconductor industry moves into nanotechnology process nodes in pursuit of higher device density, higher performance, and lower cost, challenges from manufacturing and design issues have led to the development of three-dimensional designs such as multi-gate field effect transistors (FETs), including fin FETs (FinFETs) and gate-all-around (GAA) FETs. In FinFETs, the gate electrode layer is adjacent to three sides of the channel region, with a gate dielectric layer between the gate electrode layer and the channel region. Because the gate structure surrounds (wraps) the fins on three surfaces, the transistor essentially has three gates, thereby controlling the current through the fin or channel region. The current drive capability of a FinFET is typically determined by the number of fins at the channel region, the fin width, and the fin height. Summary of the invention

[0003] Some embodiments of the present invention provide a method for manufacturing a semiconductor device, the method comprising: forming a fin structure protruding from a first isolation insulating layer disposed above a substrate; forming a dummy gate structure above an upper portion of the fin structure; forming a second isolation insulating layer above the first isolation insulating layer; forming a groove by etching a source / drain region of the fin structure; forming a base semiconductor epitaxial layer in the groove; and forming a cap semiconductor epitaxial layer on the base semiconductor epitaxial layer, the lattice constant of the cap semiconductor epitaxial layer being different from the lattice constant of the base semiconductor epitaxial layer; wherein a surface of the cap semiconductor epitaxial layer is smoother than a surface of the base semiconductor epitaxial layer.

[0004] Some other embodiments of the present invention provide a method for manufacturing a semiconductor device, the method comprising: forming a fin structure protruding from a first isolation insulating layer disposed above a substrate; forming a dummy gate structure above an upper portion of the fin structure; forming a second isolation insulating layer above the first isolation insulating layer; forming a groove by etching a source / drain region of the fin structure; forming a base semiconductor epitaxial layer in the groove; and forming a cap semiconductor epitaxial layer on the base semiconductor epitaxial layer, the cap semiconductor epitaxial layer having a lattice constant different from that of the base semiconductor epitaxial layer, wherein: the base semiconductor epitaxial layer is a merged epitaxial layer coupled to the fin structure, the lattice constant of the cap semiconductor epitaxial layer is greater than the lattice constant of the base semiconductor epitaxial layer, and the surface roughness of the cap semiconductor epitaxial layer along the source to drain direction is less than the surface roughness of the base semiconductor epitaxial layer along the source to drain direction.

[0005] Other embodiments of the present invention provide a semiconductor device, comprising: a fin structure protruding from a first isolation insulating layer disposed above a substrate; a gate dielectric layer disposed above a channel region of the fin structure; a gate electrode layer disposed above the gate dielectric layer; a base semiconductor epitaxial layer disposed above a source / drain region of the fin structure; and a cap semiconductor epitaxial layer disposed above the base semiconductor epitaxial layer, wherein: the cap semiconductor epitaxial layer has a lattice constant different from that of the base semiconductor epitaxial layer, and the surface roughness of the cap semiconductor epitaxial layer along the source to drain direction is greater than zero and less than the surface roughness of the base semiconductor epitaxial layer along the source to drain direction. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The present invention can be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be emphasized that, in accordance with standard practice in the industry, the various components are not drawn to scale and are only used for illustration purposes. In fact, the size of the various components may be arbitrarily increased or reduced for clarity of discussion.

[0007] Figure 1A and Figure 1B One of the various stages of a sequential process for manufacturing a semiconductor device having FinFETs according to an embodiment of the present invention is shown.

[0008] Figure 2A and Figure 2B One of the various stages of a sequential process for manufacturing a semiconductor device having FinFETs according to an embodiment of the present invention is shown.

[0009] Figure 3A and Figure 3B One of the various stages of a sequential process for manufacturing a semiconductor device having FinFETs according to an embodiment of the present invention is shown.

[0010] Figure 4A and Figure 4B One of the various stages of a sequential process for manufacturing a semiconductor device having FinFETs according to an embodiment of the present invention is shown.

[0011] Figure 5A and Figure 5B One of the various stages of a sequential process for manufacturing a semiconductor device having FinFETs according to an embodiment of the present invention is shown.

[0012] Fig. 6A and Figure 6B One of the various stages of a sequential process for manufacturing a semiconductor device having FinFETs according to an embodiment of the present invention is shown.

[0013] Fig. 7A , Figure 7B and Figure 7C One of the various stages of a sequential process for manufacturing a semiconductor device having FinFETs according to an embodiment of the present invention is shown.

[0014] Fig. 8A , Figure 8B , Figure 8C , Fig.8D and Fig. 8E One of the various stages of a sequential process for manufacturing a semiconductor device having FinFETs according to an embodiment of the present invention is shown.

[0015] Fig. 9A , Fig. 9B , Fig. 9C and Fig.9D One of the various stages of a sequential process for manufacturing a semiconductor device having FinFETs according to an embodiment of the present invention is shown.

[0016] Fig. 10A , Fig. 10B , Fig. 10C and Fig. 10D One of the various stages of a sequential process for manufacturing a semiconductor device having FinFETs according to another embodiment of the present invention is shown.

[0017] Fig.11A , Fig. 11B and Fig. 11C One of the various stages of a sequential process for manufacturing a semiconductor device having FinFETs according to another embodiment of the present invention is shown.

[0018] Fig. 12A , Fig. 12B and Fig. 12C One of the various stages of a sequential process for manufacturing a semiconductor device having FinFETs according to another embodiment of the present invention is shown.

[0019] Fig.13 A semiconductor device having FinFET according to another embodiment of the present invention is shown.

[0020] Fig.14 A semiconductor device having FinFET according to another embodiment of the present invention is shown. DETAILED DESCRIPTION

[0021] It should be understood that the following disclosure provides many different embodiments or examples for realizing different features of the present invention. Specific embodiments or examples of components and arrangements are described below to simplify the present invention. Of course, these are merely examples and are not intended to limit the present invention. For example, the size of the element is not limited to the disclosed range or value, but may depend on the process conditions and / or the desired characteristics of the device. In addition, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly contacted, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. For simplicity and clarity, each component may be arbitrarily drawn in different proportions.

[0022] Moreover, for ease of description, spatially relative terms such as "under...", "below...", "lower", "above...", "upper", etc. may be used herein to describe the relationship between an element or component as shown in the figure and another (or other) originals or components. In addition to the orientation shown in the figure, spatially relative terms are intended to include different orientations of the device in use or operation. The device can be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially relative descriptors used herein can be interpreted accordingly. In addition, the term "made of..." can mean "including" or "consisting of...". In addition, in the subsequent manufacturing process, there may be one or more additional operations in / between the described operations, and the order of operations may change. In the present invention, the phrase "one of A, B and C" means "A, B and / or C" (A, B, C, A and B, A and C, B and C or A, B and C), unless otherwise specified, it does not mean one element from A, one element from B and one element from C. Unless otherwise stated, the material, process, size, and / or configuration of one embodiment may be adopted in other embodiments, and a detailed description thereof may be omitted.

[0023] In the present invention, the source / drain structure of FinFET includes a base epitaxial layer and a cap epitaxial layer that introduces appropriate stress to the base epitaxial layer. For p-type FET, the lattice constant of the cap epitaxial layer is smaller than that of the base epitaxial layer to introduce compressive stress in the base epitaxial layer. For n-type FET, the lattice constant of the cap epitaxial layer is greater than that of the base epitaxial layer to introduce tensile stress in the base epitaxial layer. In addition, the cap epitaxial layer has a smoother surface than the base epitaxial layer, and therefore the source / drain structure of the present invention can improve the interface characteristics (e.g., contact resistance) with the metal contact.

[0024] Figures 1A to 9B FIG. 1 shows a sequential process for manufacturing a semiconductor device having a FinFET according to an embodiment of the present invention. It should be understood that Figures 1A to 9B Additional operations are provided before, during, and after the processes shown, and some of the operations described below may be replaced or eliminated for other embodiments of the method. The order of operations / processes may be interchanged. Figures 1A to 9B In the “A” figure ( Figure 1A , Figure 2A , ...) shows a plan view (seen from above), while the "B" view ( Figure 1B , Figure 2B , ...) show a cross-sectional view.

[0025] Figure 1A and Figure 1B One of the various stages of a sequential process for manufacturing a semiconductor device having FinFETs according to an embodiment of the present invention is shown. Figure 1B is with Figure 1A The cross-sectional view corresponding to the line Y1-Y1.

[0026] like Figure 1A and Figure 1B As shown, a fin structure 20 is formed over a substrate 100. In one embodiment, the substrate 100 includes a single crystal semiconductor layer at least on a surface portion thereof. The substrate 100 may include a single crystal semiconductor material such as, but not limited to, Si, Ge, SiGe, GaAs, InSb, GaP, GaSb, InAlAs, InGaAs, GaSbP, GaAsSb, and InP. In this embodiment, the substrate 100 is made of Si.

[0027] In some embodiments, the fin structure 20 includes a fin bottom 100A that is a protruding portion of the substrate 100 , a buffer semiconductor layer 101 formed on the fin bottom 100A, a channel semiconductor layer 102 formed on the buffer semiconductor layer 101 , and a hard mask layer 103 formed on the channel semiconductor layer 102 .

[0028] In some embodiments, the buffer semiconductor layer 101 includes one or more semiconductor layers having different compositions and can be used to gradually or stepwise change the lattice constant from the lattice constant of the substrate 100 to the lattice constant of the channel semiconductor layer 102. The buffer semiconductor layer 101 can be formed of an epitaxially grown single crystalline semiconductor material such as, but not limited to, Si, Ge, GeSn, SiGe, SiGeSn, GaAs, InSb, GaP, GaSb, InAlAs, InGaAs, GaSbP, GaAsSb, GaN, GaP, and InP. In some embodiments, the buffer layer 101 includes Si 1-x Ge x , where 0<x<1.0. In other embodiments, the buffer layer 101 includes Si 1-x Ge x , where 0.2<x<0.5.

[0029] In some embodiments, the channel semiconductor layer 102 includes one or more semiconductor layers and may be formed of epitaxially grown single crystal semiconductor materials such as, but not limited to, Si, Ge, GeSn, SiGe, SiGeSn, GaAs, InSb, GaP, GaSb, InAlAs, InGaAs, GaSbP, GaAsSb, GaN, GaP, and InP. In some embodiments, the channel layer 102 includes Si 1-y Ge y , where 0<y≤1.0. In other embodiments, the channel semiconductor layer 102 includes Si 1-y Ge y , where 0.3<y≤1.0. In some embodiments, x<y. When the substrate, the buffer semiconductor layer, and the channel semiconductor layer include Si and Ge and / or Sn, the amount of Ge and / or Sn in the upper layer is greater than the amount of Ge and / or Sn in the lower layer. The substrate 100 may include various regions that have been appropriately doped with impurities (e.g., p-type or n-type conductivity).

[0030] In some embodiments, the thickness of the buffer semiconductor layer 101 is in a range from about 10 nm to about 200 nm, and in other embodiments, in a range from about 20 nm to about 100 nm. In some embodiments, the thickness of the channel semiconductor layer 102 is in a range from about 20 nm to about 200 nm, and in other embodiments, in a range from about 50 nm to about 100 nm.

[0031] The hard mask layer 103 is used to pattern the fin structure 20 and includes one or more dielectric material layers.

[0032] The fin structure 20 may be patterned by any suitable method. For example, the fin structure may be patterned using one or more photolithography processes including a double patterning process or a multiple patterning process. Typically, the double patterning or multiple patterning process combines photolithography and self-alignment processes, thereby allowing the creation of patterns having, for example, a pitch that is smaller than that obtainable using a single direct photolithography process. For example, in one embodiment, a dummy layer is formed over the substrate and patterned using a photolithography process. Spacers are formed next to the patterned dummy layer using a self-alignment process. The dummy layer is then removed, and the remaining spacers may then be used to pattern the fins.

[0033] In other embodiments, the fin structure can be patterned by using the hard mask layer (pattern) 103 as an etching mask. In some embodiments, the hard mask layer 103 includes a first mask layer and a second mask layer disposed on the first mask layer. The first mask layer is a pad oxide layer made of silicon oxide, which can be formed by thermal oxidation. The second mask layer is made of silicon nitride (SiN) formed by chemical vapor deposition (CVD), including low pressure CVD (LPCVD) and plasma enhanced CVD (PECVD), physical vapor deposition (PVD), atomic layer deposition (ALD) or other suitable processes. The deposited hard mask layer is patterned into a hard mask pattern by using a patterning operation including photolithography and etching. Then, the channel semiconductor layer 102, the buffer semiconductor layer 101 and the substrate 100 are patterned into a fin structure 20 extending in the X direction by using the hard mask pattern. In Figure 1A and Figure 1B In the embodiment, four fin structures 20 are arranged in the Y direction. However, the number of fin structures is not limited to four, and may be as small as one or two, or three or more. In some embodiments, the number of fin structures is as high as 20. In some embodiments, one or more dummy fin structures are formed on both sides of the fin structure to improve pattern fidelity in the patterning operation.

[0034] In some embodiments, the width of the upper portion of the fin structure 20 along the Y direction ranges from about 5 nm to about 40 nm, and in other embodiments ranges from about 10 nm to about 20 nm.

[0035] In addition, if Figure 1A and Figure 1B As shown, a first isolation insulating layer 104 is formed, such as a shallow trench isolation (STI). After the fin structure 20 is formed, a first insulating material layer including one or more insulating material layers is formed above the substrate 100, so that the fin structure 20 is completely embedded in the first insulating material layer. The insulating material used for the first insulating material layer may include silicon oxide, silicon nitride, silicon oxynitride (SiON), SiCN, fluorine-doped silicate glass (FSG) or low-K dielectric material formed by LPCVD (low pressure chemical vapor deposition), plasma CVD or flowable CVD or any other suitable film formation method. In some embodiments, the first insulating material layer is made of silicon oxide. An annealing operation may be performed after the first insulating material layer is formed. Then, a planarization operation such as a chemical mechanical polishing (CMP) method and / or an etch-back method is performed to expose the hard mask layer 103.

[0036] Then, if Figure 1BAs shown, the first insulating material layer is recessed by etching to form a first isolation insulating layer 104, thereby exposing the upper portion of the fin structure 20, such as the buffer semiconductor layer 101 and the channel semiconductor layer 102. In some embodiments, part or all of the buffer semiconductor layer 101 is embedded in the isolation insulating layer 104. In some embodiments, the bottom portion of the channel semiconductor layer 102 is embedded in the isolation insulating layer 104. In some embodiments, the upper portion of the fin bottom structure 100A protrudes from the isolation insulating layer 104.

[0037] In some embodiments, before forming the first insulating material layer, one or more fin liner layers (not shown) are formed over the fin structure. The fin liner layers may be made of SiN or a silicon nitride-based material (eg, SiON or SiCN).

[0038] Figure 2A and Figure 2B One of the various stages of a sequential process for manufacturing a semiconductor device having FinFETs according to an embodiment of the present invention is shown. Figure 2B is with Figure 2A The cross-sectional view corresponding to the line X1-X1.

[0039] After forming the first isolation insulating layer 104, Figure 2A and Figure 2B As shown, a dummy gate structure 105 is formed. The dummy gate structure 105 includes a dummy gate dielectric layer and a dummy gate electrode layer. The dummy gate dielectric layer includes one or more insulating material layers, such as a silicon oxide-based material. In one embodiment, silicon oxide formed by CVD is used. In some embodiments, the thickness of the dummy gate dielectric layer is in the range from about 1 nm to about 5 nm. In other embodiments, a dummy gate dielectric layer is not formed, and in this case, the hard mask layer 103 can be used as a dummy gate dielectric layer.

[0040] The pseudo gate structure 105 is formed by first blanket depositing a pseudo gate dielectric layer (if used) over the upper surface of the exposed fin structure 20 and the first isolation insulating layer 104. Then a pseudo gate electrode layer is blanket deposited on the pseudo gate dielectric layer so that the fin structure is completely embedded in the pseudo gate electrode layer. The pseudo gate electrode layer includes silicon such as polysilicon or amorphous silicon. In some embodiments, the pseudo gate electrode layer is made of polysilicon. In some embodiments, the thickness of the pseudo gate electrode layer is in the range of from about 100nm to about 200nm. In some embodiments, the pseudo gate electrode layer is subjected to a planarization operation. The pseudo gate dielectric layer and the pseudo gate electrode layer are deposited using CVD, PVD, ALD or other suitable processes including LPCVD and PECVD. Subsequently, a mask layer is formed above the pseudo gate electrode layer. The mask layer can be a photoresist pattern or a hard mask pattern.

[0041] Next, the mask layer is patterned, and the dummy gate electrode layer is patterned into a dummy gate structure 105, such as Figure 2A and Figure 2B By patterning the dummy gate structure, the upper portion of the fin structure 20 that will become the source / drain region on the opposite side of the dummy gate structure 105 is partially exposed, as shown in FIG. Figure 2B As shown. In the present invention, the source and drain can be used interchangeably, and their structures are basically the same. Figure 2A and Figure 2B In the embodiment, two dummy gate structures 105 are formed on four fin structures 20. However, the layout is not limited to Figure 2A and Figure 2B , and for the same fin structure, the number of the dummy gate structures may be one or more than two.

[0042] In some embodiments, the width of the dummy gate structure 105 in the X direction ranges from about 5 nm to about 30 nm, and in other embodiments ranges from about 7 nm to about 15 nm.

[0043] Figure 3A and Figure 3B One of the various stages of a sequential process for manufacturing a semiconductor device having FinFETs according to an embodiment of the present invention is shown. Figure 3B is with Figure 3A The cross-sectional view corresponding to the line X1-X1.

[0044] In addition, a second isolation insulating layer 106 including one or more insulating material layers is formed over the first isolation insulating layer 104, so that the fin structure 20 and the dummy gate structure 105 are completely embedded in the second insulating material layer. The second isolation insulating layer 106 covers the end surface of the fin structure 20 and defines the source / drain spacing in which the source / drain epitaxial layer is formed. The insulating material used for the second isolation insulating layer 106 is different from the insulating material of the first isolation insulating layer 104, and includes silicon oxide, silicon nitride, silicon oxynitride (SiON), SiOCN, SiOC, SiCN, fluorine-doped silicate glass (FSG) or low-k dielectric material formed by LPCVD (low pressure chemical vapor deposition), plasma CVD, atomic layer deposition (ALD) or flowable CVD or any other suitable film formation method. In some embodiments, the second isolation insulating layer 106 includes SiOC or SiOCN. An annealing operation may be performed after the second isolation insulating layer is formed. Then, a planarization operation is performed, such as a chemical mechanical polishing (CMP) method and / or an etch-back method, so that the upper surface of the dummy gate structure 105 is exposed from the second isolation insulating layer 106, as shown in FIG. Figure 3A and Figure 3B shown.

[0045] Figure 4A and Figure 4B One of the various stages of a sequential process for manufacturing a semiconductor device having FinFETs according to an embodiment of the present invention is shown. Figure 4B is with Figure 4A The cross-sectional view corresponding to the line X1-X1.

[0046] Then, if Figure 4A and Figure 4B As shown, the second isolation insulating layer 106 is recessed by etching to expose the hard mask layer 103. In some embodiments, the upper surface of the second isolation insulating layer 106 is at the same level as the upper surface of the hard mask layer 103. In other embodiments, the upper surface of the second isolation insulating layer 106 is lower than the upper surface of the hard mask layer 103 and higher than the upper surface of the channel semiconductor layer 102. In other embodiments, the second isolation insulating layer 106 is further recessed to completely expose the side of the channel semiconductor layer 102. In some embodiments, the second isolation insulating layer 106 is further recessed to expose a portion of the side of the buffer semiconductor layer 101.

[0047] Figure 5A and Figure 5B One of the various stages of a sequential process for manufacturing a semiconductor device having FinFETs according to an embodiment of the present invention is shown. Figure 5B is with Figure 5A The cross-sectional view corresponding to the line X1-X1.

[0048] After the second isolation insulating layer 106 is recessed, the hard mask layer 103 is patterned by etching using the dummy gate structure 105 as an etching mask, thereby exposing the channel semiconductor layer 102, as shown in FIG. Figure 5A and Figure 5B As shown. A portion of the second isolation insulating layer 106 is also etched. In some embodiments, the second isolation insulating layer 106 is etched to be equal to or lower than the upper surface of the channel semiconductor layer 102 .

[0049] Fig. 6A and Figure 6B One of the various stages of a sequential process for manufacturing a semiconductor device having FinFETs according to an embodiment of the present invention is shown. Figure 6B is with Fig. 6A The cross-sectional view corresponding to the line X1-X1.

[0050] After patterning the hard mask layer 103, a blanket layer of insulating material for the sidewall spacer 107 is conformally formed by using CVD or other suitable methods. The blanket layer is deposited in a conformal manner so that it has substantially equal thickness on vertical surfaces, horizontal surfaces, and the top of the dummy gate structure, such as the sidewalls. In some embodiments, the blanket layer is deposited to a thickness ranging from about 2 nm to about 20 nm. In some embodiments, the insulating material of the blanket layer is different from the material of the second isolation insulating layer 106 and is made of one or more of silicon oxide, silicon nitride, SiON, SiOC, SiOCN or SiCN and any other suitable dielectric material. Porous materials or organic materials can be used for the sidewall spacer 107. In some embodiments, two or more layers (for example, 3 or 4 layers) of dielectric material are formed. In some embodiments, the blanket layer (sidewall spacer 107) is made of non-porous or porous SiOC. The sidewall spacer 107 is formed on the opposite sidewalls of the dummy gate structure 105 and the hard mask layer 103 by anisotropic etching, such as Fig. 6A and Figure 6B shown.

[0051] 7A to 7C One of the various stages of a sequential process for manufacturing a semiconductor device having FinFETs according to an embodiment of the present invention is shown. Figure 7B is with Fig. 7A The cross-sectional view corresponding to the line X1-X1, and Figure 7C is with Fig. 7A The cross-sectional view corresponding to the line Y1-Y1.

[0052] After forming the sidewall spacer 107, the source / drain region of the fin structure not covered by the dummy gate structure 105 and the sidewall spacer 107 is recessed downward to the fin bottom structure 100A to form a trench 90 defined by the second isolation insulating layer 106, the channel semiconductor layer 102, the buffer semiconductor layer 101, and the fin bottom structure 100A. In some embodiments, a portion of the source / drain region of the buffer semiconductor layer 101 remains, and the fin bottom structure 100A is not exposed. In certain embodiments, only the channel semiconductor layer 102 is etched, and the buffer semiconductor layer 101 is not etched.

[0053] FIG. 8A to FIG. 8E One of the various stages of a sequential process for manufacturing a semiconductor device having FinFETs according to an embodiment of the present invention is shown. Figure 8B is with Fig. 8A The cross-sectional view corresponding to the line X1-X1, Figure 8C is with Fig. 8A The cross-sectional view corresponding to the line Y1-Y1, and Fig.8D and Fig. 8E yes Figure 8B Magnified view of the area SD.

[0054] Then, a base source / drain epitaxial layer 108 is formed in the trench. The base source / drain epitaxial layer 108 includes one or more epitaxially formed semiconductor layers. In some embodiments, the base semiconductor epitaxial layer 108 is in contact with the buffer semiconductor layer 101 and the channel semiconductor layer 102. In some embodiments, the second isolation insulating layer 106 is in contact with the base semiconductor epitaxial layer 108. In some embodiments, the first isolation insulating layer 104 is not in contact with the base semiconductor epitaxial layer 108.

[0055] For n-type FET, one or more of Si, SiP, SiC and SiCP are used as base source / drain epitaxial layer 108. When two or more SiP layers are used, the concentrations of P are different from each other. In some embodiments, the concentration of P in the later formed layer is higher than that in the earlier formed layer.

[0056] For p-type FET, one or more of SiGe, Ge, Sn, GeSn, and SiGeSn are used as the base source / drain epitaxial layer 108. In some embodiments, boron (B) is doped in the base source / drain epitaxial layer 108. When two or more SiGe layers are used, the concentrations of Ge are different from each other. In some embodiments, the concentration of Ge in the later formed layer is higher than that in the earlier formed layer.

[0057] like Figure 8B and Figure 8C As shown, the upper surface of the base source / drain epitaxial layer 108 is rough or uneven. In some embodiments, the surface roughness Ra measured along the X direction (source to drain direction) at the central region is in a range from about 2 nm to about 10 nm. Fig. 8E The bottom of the buffer semiconductor layer 101 is shown to remain in the etched trench. In some embodiments, the average height of the base source / drain epitaxial layer 108 is higher than the level of the upper surface of the channel semiconductor layer 102. In other embodiments, the average height of the base source / drain epitaxial layer 108 is equal to or lower than the level of the upper surface of the channel semiconductor layer 102.

[0058] The base source / drain epitaxial layer 108 is selectively formed in the trench 90 by epitaxial growth methods using CVD, ALD, molecular beam epitaxy (MBE), or other suitable methods. Figure 8B and Figure 8C As shown, a base source / drain epitaxial layer 108 is defined in the trench 90 .

[0059] Fig. 9A , Fig. 9B and Fig. 9COne of the various stages of a sequential process for manufacturing a semiconductor device having FinFETs according to an embodiment of the present invention is shown. Fig. 9B is with Fig. 9A The cross-sectional view corresponding to the line X1-X1, and Fig. 9C and Fig.9D yes Fig. 9B Magnified view of the area SD. Fig. 9C is a cross-sectional view along the X direction, and Fig.9D It is a cross-sectional view along the Y direction.

[0060] After forming the base source / drain epitaxial layer 108, a cap source / drain epitaxial layer 109 is formed on the base source / drain epitaxial layer 108, such as 9A to 9D shown.

[0061] For n-type FET, the lattice constant of the cap source / drain epitaxial layer 109 is greater than the lattice constant of the base source / drain epitaxial layer 108 to introduce tensile stress in the base source / drain epitaxial layer 108. In some embodiments, when the base source / drain epitaxial layer 108 is SiP, SiC and / or SiCP, the cap source / drain epitaxial layer 109 includes one or more of Si, SiGe, Ge, Sn and GeSn. In some embodiments, SiGe is used as the cap source / drain epitaxial layer 109 of the n-type FET.

[0062] For a p-type FET, the lattice constant of the cap source / drain epitaxial layer 109 is smaller than the lattice constant of the base source / drain epitaxial layer 108 to introduce compressive stress in the base source / drain epitaxial layer 108. In some embodiments, when the base source / drain epitaxial layer 108 is SiGe, the cap source / drain epitaxial layer 109 includes one or more of Si, SiC, and SiGe having a lower Ge content than the base source / drain epitaxial layer 108. In some embodiments, when the base source / drain epitaxial layer 108 is Ge, the cap source / drain epitaxial layer 109 includes one or more of Si and SiGe. In some embodiments, when the base source / drain epitaxial layer 108 is GeSn, the cap source / drain epitaxial layer 109 includes one or more of Si, SiGe, Ge, and GeSn having a lower Sn content than the base source / drain epitaxial layer 108.

[0063] In addition, the cap source / drain epitaxial layer 109 has a smoother surface than the base source / drain epitaxial layer 108. In some embodiments, the cap source / drain epitaxial layer 109 is formed in a temperature range from about 600°C to about 800°C. In this temperature range, the lateral growth of atomic diffusion (atoms on the growth surface) is enhanced to make the surface of the cap source / drain epitaxial layer smoother without affecting the rest of the structure. In particular, when the gas pressure is high, the surface diffusion of the adsorbed atoms is suppressed, and the adsorbed atoms gather in the concave portion of the base source / drain epitaxial layer 108, which makes the surface of the cap source / drain epitaxial layer smoother (flattened). When the temperature is below 600°C, the lateral diffusion is insufficient, and when the temperature is above 800°C, the fin structure may be damaged. In some embodiments, the surface roughness Ra measured in the center area of ​​the cap source / drain epitaxial layer 109 along the X direction (source to drain direction) is greater than zero (i.e., not flat) and is less than the surface roughness of the base source / drain epitaxial layer before the cap source / drain epitaxial layer is formed. In some embodiments, the surface roughness Ra of the cap source / drain epitaxial layer 109 is in a range from about 0.2 nm to about 5 nm. In other embodiments, the surface roughness Ra of the cap source / drain epitaxial layer 109 is in a range from about 0.5 nm to about 2 nm. In some embodiments, the surface roughness Ra of the cap source / drain epitaxial layer 109 is about 1 / 20 to about 1 / 5 of the surface roughness of the base source / drain epitaxial layer 108 before the cap source / drain epitaxial layer is formed.

[0064] In some embodiments, the thickness of the cap source / drain epitaxial layer 109 is in a range from about 5 nm to about 25 nm, and in other embodiments in a range from about 10 nm to about 20 nm. In some embodiments, the thickness of the cap source / drain epitaxial layer 109 is about 1 / 10 to 1 / 5 of the thickness of the base source / drain epitaxial layer 108. The thickness of the cap and base source / drain epitaxial layers is an average thickness measured from the upper surface of the fin bottom structure 100A. In some embodiments, the cap source / drain epitaxial layer 109 is in contact with the channel semiconductor layer 102, and in other embodiments, the cap source / drain epitaxial layer 109 is not in contact with the channel semiconductor layer 102. In some embodiments, the cap source / drain epitaxial layer 109 is in contact with the sidewall spacer 107. In some embodiments, the cap source / drain epitaxial layer 109 is in contact with the second isolation insulating layer 106, while in other embodiments, the cap source / drain epitaxial layer 109 is not in contact with the second isolation insulating layer 106. In some embodiments, the bottommost portion of the cap source / drain epitaxial layer 109 is lower than the bottom of the sidewall spacer 107 or the top of the channel semiconductor layer 102, while in other embodiments, the bottommost portion of the cap source / drain epitaxial layer 109 is higher than the bottom of the sidewall spacer 107 or the top of the channel semiconductor layer 102. In some embodiments, the topmost portion of the cap source / drain epitaxial layer 109 is lower than the bottom of the sidewall spacer 107 or the top of the channel semiconductor layer 102, while in other embodiments, the topmost portion of the cap source / drain epitaxial layer 109 is higher than the bottom of the sidewall spacer 107 or the top of the channel semiconductor layer 102.

[0065] Fig. 10A and Fig. 10B One of the various stages of a sequential process for manufacturing a semiconductor device having FinFETs according to an embodiment of the present invention is shown. Fig. 10B is with Fig. 10A The cross-sectional view corresponding to the line X1-X1. Fig. 10C and Fig. 10D yes Fig. 10B 1. An enlarged view of the region SD of the gate electrode 105. After forming the cap source / drain epitaxial layer 109, an interlayer dielectric (ILD) layer 190 is formed over the second isolation insulating layer and the source / drain structure. Materials for the ILD layer 190 include compounds containing Si, O, C and / or H, such as silicon oxide, SiCOH and SiOC. Organic materials such as polymers can be used for the ILD layer 190. After forming the ILD layer 190, a planarization operation such as CMP is performed so that the top of the dummy gate electrode layer 105 is exposed.

[0066] Next, remove the dummy gate electrode layer 105 and the hard mask layer 103 (also used as a dummy gate dielectric layer) thereunder, thereby forming a gate spacer, wherein the side of the channel semiconductor layer 102 and the buffer semiconductor layer 101 are exposed. The sidewall spacer 107 is not removed. The ILD layer 190 protects the source / drain structure during the removal of the dummy gate structure. The dummy gate structure can be removed using plasma dry etching and / or wet etching. When the dummy gate electrode layer is polysilicon and the ILD layer 190 is silicon oxide, a wet etchant such as a TMAH solution can be used to selectively remove the dummy gate electrode layer. Thereafter, use plasma dry etching and / or wet etching to remove the hard mask layer and / or the dummy gate dielectric layer.

[0067] After forming the gate spacer, a gate dielectric layer 202 is formed over the exposed fin structure (channel and buffer semiconductor layer). In some embodiments, the gate dielectric layer 202 includes one or more dielectric material layers, such as silicon oxide, silicon nitride or high-k dielectric materials, other suitable dielectric materials and / or combinations thereof. Examples of high-k dielectric materials include HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, zirconium oxide, aluminum oxide, titanium oxide, hafnium dioxide-aluminum oxide (HfO2-Al2O3) alloys, other suitable high-k dielectric materials and / or combinations thereof. In some embodiments, the gate dielectric layer 202 includes an interface layer formed between the channel layer and the dielectric material.

[0068] The gate dielectric layer 202 may be formed by CVD, ALD, or any suitable method. In one embodiment, the gate dielectric layer 202 is formed using a highly conformal deposition process such as ALD to ensure that a gate dielectric layer having a uniform thickness is formed around each channel layer. In one embodiment, the thickness of the gate dielectric layer 202 is in a range from about 1 nm to about 6 nm.

[0069] Subsequently, a gate electrode layer 204 is formed on the gate dielectric layer 202. The gate electrode layer 204 includes one or more conductive material layers, such as polysilicon, aluminum, copper, titanium, tantalum, tungsten, cobalt, molybdenum, tantalum nitride, nickel silicide, cobalt silicide, TiN, WN, TiAl, TiAlN, TaCN, TaC, TaSiN, metal alloys, other suitable materials and / or combinations thereof.

[0070] The gate electrode layer 204 may be formed by CVD, ALD, electroplating or other suitable methods. The gate dielectric layer and the electrode layer are also deposited over the upper surface of the ILD layer 190. The gate dielectric layer and the gate electrode layer formed over the ILD layer 190 are then planarized by using, for example, CMP until the top surface of the ILD layer 190 is exposed. Fig. 10B shown.

[0071] In some embodiments of the present invention, one or more work function adjustment layers (not shown) are inserted between the gate dielectric layer 202 and the gate electrode layer 204. The work function adjustment layer is made of a conductive material, such as a single layer of TiN, TaN, TaAlC, TiC, TaC, Co, Al, TiAl, HfTi, TiSi, TaSi or TiAlC, or a multilayer of two or more of these materials. For n-channel FETs, one or more of TaN, TaAlC, TiN, TiC, Co, TiAl, HfTi, TiSi and TaSi are used as the work function adjustment layer, while for p-channel FETs, one or more of TiAlC, Al, TiAl, TaN, TaAlC, TiN, TiC and Co are used as the work function adjustment layer. The work function adjustment layer can be formed by ALD, PVD, CVD, electron beam evaporation or other suitable processes. In addition, the work function adjustment layer can be formed separately for n-channel FETs and p-channel FETs, which can use different metal layers.

[0072] After forming the metal gate structure, the ILD layer 190 is partially etched (patterned) by using photolithography and etching operations to form contact openings in which the source / drain regions are exposed. Then, in the contact openings, a conductive material is formed. A conductive material is formed in and over the contact openings, and then a planarization operation such as a CMP operation is performed to form the contact 210. The conductive material includes one or more layers of Co, Ni, W, Ti, Ta, Cu, Al, TiN, and TaN, or any other suitable material. In some embodiments, before forming the conductive material, a silicide layer 205 is formed over the cap source / drain epitaxial layer 108, such as Fig. 10D The silicide layer includes one or more of WSi, CoSi, NiSi, TiSi, MoSi and TaSi.

[0073] It should be understood that the FinFET undergoes further CMOS processing to form various components, such as interconnect metal layers, dielectric layers, passivation layers, and the like.

[0074] FIG. 11A to FIG. 12C FIG. 2 shows a sequential process for manufacturing a semiconductor device having FinFET according to another embodiment of the present invention. It should be understood that FIG. 11A to FIG. 12C Additional operations are provided before, during, and after the processes shown, and some of the operations described below may be replaced or eliminated for other embodiments of the method. The order of operations / processes may be interchanged.

[0075] As about Fig. 7A and Figure 7BAs explained, the trench 90 is formed by etching the source / drain regions of the channel semiconductor layer 102 and the buffer semiconductor layer 101. Then, the base source / drain epitaxial layer 108' is formed, as shown in FIG. Fig.11A (Floor plan), Fig. 11B (and Fig.11A The cross-sectional view corresponding to Y1-Y1) and Fig. 11C (and Fig.11A In some embodiments, adjacent base epitaxial layers have a rhombus shape and are merged to form a merged base epitaxial layer 108'. In some embodiments, a gap 112 is formed between the merged epitaxial layer 108' and the isolation insulating layer 104. The material, configuration and / or structure of the base epitaxial layer 108' are the same as those of the base epitaxial layer 108.

[0076] like Fig. 11B and Fig. 11C As shown, the upper surface of the base source / drain epitaxial layer 108' is rough or uneven. In some embodiments, the surface roughness Ra measured along the X direction (source to drain direction) at the central region above the fin bottom structure 100A is in a range from about 2 nm to about 10 nm.

[0077] Then, similar to 9A to 9D , a cap source / drain epitaxial layer 109' is formed on the merged base epitaxial layer 108', as shown in FIG. FIG. 12A to FIG. 12C shown. Fig. 12A It is a floor plan. Fig. 12B is with Fig. 12A The Y1-Y1 corresponds to the cross-sectional view, and Fig. 12C is with Fig. 12A The material, configuration and / or structure of the cap source / drain epitaxial layer 109 ′ are the same as those of the cap source / drain epitaxial layer 109 . In some embodiments, the cap source / drain epitaxial layer 109 ′ is not formed in the gap 112 .

[0078] In the fin bottom structure 100A (see Fig. 12A and Fig. 12C) measured along the X direction (source to drain direction) of the central area of ​​the cap source / drain epitaxial layer 109' above the base source / drain epitaxial layer 108' is greater than zero and is less than the surface roughness of the combined base source / drain epitaxial layer 108' before (and after) the cap source / drain epitaxial layer is formed. In some embodiments, the surface roughness Ra is in the range from about 0.2nm to about 5nm. In other embodiments, the surface roughness Ra of the cap source / drain epitaxial layer 109' is in the range from about 0.5nm to about 2nm. In some embodiments, the surface roughness Ra of the cap source / drain epitaxial layer 109' is about 1 / 20 to about 1 / 5 of the surface roughness of the base source / drain epitaxial layer 108' before the cap source / drain epitaxial layer is formed.

[0079] In some embodiments, the thickness of the cap source / drain epitaxial layer 109' measured from the upper surface of the fin bottom structure 100A is in a range from about 5 nm to about 25 nm, and in other embodiments, in a range from about 10 nm to about 20 nm. In some embodiments, the thickness of the cap source / drain epitaxial layer 109' is about 1 / 10 to 1 / 5 of the thickness of the base source / drain epitaxial layer 108'. The thickness of the cap and base source / drain epitaxial layers is the average thickness over the fin bottom structure 100A.

[0080] Fig.13 A semiconductor device having FinFET according to another embodiment of the present invention is shown.

[0081] In this embodiment, an additional cap source / drain epitaxial layer 110 is formed on the cap source / drain epitaxial layer 109'. The additional cap source / drain epitaxial layer 110 further increases the stress to be applied to the source / drain epitaxial layer in the channel region.

[0082] For n-type FETs, the lattice constant of the additional cap source / drain epitaxial layer 110 is greater than the lattice constant of the cap source / drain epitaxial layer 109'. In some embodiments, when the cap source / drain epitaxial layer 109 is Si, the additional cap source / drain epitaxial layer 110 includes one or more of SiGe, Ge, Sn, and GeSn. In some embodiments, when the cap source / drain epitaxial layer 109' is SiGe, the additional cap source / drain epitaxial layer 110 includes one or more of SiGe, Ge, and GeSn having a higher Ge content than the cap source / drain epitaxial layer 109. In some embodiments, when the cap source / drain epitaxial layer 109 is Ge, the additional cap source / drain epitaxial layer 110 includes GeSn.

[0083] For a p-type FET, the additional cap source / drain epitaxial layer 110 has a lattice constant that is less than the lattice constant of the cap source / drain epitaxial layer 109'. In some embodiments, when the cap source / drain epitaxial layer 109' is SiGe, the additional cap source / drain epitaxial layer 110 includes one or more of Si and SiGe having a lower Ge content than the cap source / drain epitaxial layer 109'. In some embodiments, when the cap source / drain epitaxial layer 109' is Ge, the additional cap source / drain epitaxial layer 110 includes one or more of Si and SiGe. In some embodiments, when the cap source / drain epitaxial layer 109' is GeSn, the additional cap source / drain epitaxial layer 110 includes one or more of Si, SiGe, Ge, Sn, and GeSn having a lower Sn content than the cap source / drain epitaxial layer 109'.

[0084] In addition, before (and after) forming the additional cap source / drain epitaxial layer 110, the additional cap source / drain epitaxial layer 110 has a smoother surface than the cap source / drain epitaxial layer 109'. The surface roughness Ra measured along the X direction in the central area of ​​the additional cap source / drain epitaxial layer 110 is less than the surface roughness of the cap source / drain epitaxial layer 109', and in some embodiments, is in the range from about 0.1nm to about 4nm. In other embodiments, the surface roughness Ra of the additional cap source / drain epitaxial layer 110 is in the range from about 0.2nm to about 1.5nm. The surface roughness Ra of the additional cap source / drain epitaxial layer 110 is about 1 / 2 to about 1 / 5 of the surface roughness of the cap source / drain epitaxial layer 109'.

[0085] In some embodiments, the thickness of the additional cap source / drain epitaxial layer 110 ranges from about 5 nm to about 25 nm, and in other embodiments ranges from about 10 nm to about 20 nm. The thickness of the additional cap source / drain epitaxial layer 110 is an average thickness over the fin bottom structure 100A.

[0086] Fig.14 A semiconductor device having FinFET according to another embodiment of the present invention is shown.

[0087] In this embodiment, the recess (groove) formed at the source / drain region of the channel semiconductor layer 102 and the buffer semiconductor 101 does not reach the fin bottom structure 100A. In some embodiments, the upper surface of the cap source / drain epitaxial layer 109 is located above the upper surface of the channel semiconductor layer 102. In some embodiments, the sidewall spacer 107 includes three layers 107A, 107B, and 107C made of different materials from each other. In some embodiments, a gate cap insulating layer 206 is formed over the gate electrode layer 204.

[0088] In the case of an n-type FET, the cap source / drain epitaxial layer 109 introduces tensile stress to the base source / drain epitaxial layer 108, which in turn introduces compressive stress to the channel semiconductor layer 102. The cap source / drain epitaxial layer 109 has compressive stress.

[0089] In the case of a p-type FET, the cap source / drain epitaxial layer 109 introduces compressive stress to the base source / drain epitaxial layer 108, which in turn introduces tensile stress to the channel semiconductor layer 102. The cap source / drain epitaxial layer 109 has tensile stress.

[0090] The above embodiments may be applied to source / drain structures having epitaxial layers of any type of FET, such as planar FET, gate-all-around FET.

[0091] The various embodiments or examples described herein provide several advantages over the prior art. For example, in the present invention, by using one or more cap source / drain epitaxial layers on the base source / drain epitaxial layers, appropriate stress can be applied to the base source / drain epitaxial layers and the channel of the FET. In addition, the cap source / drain epitaxial layers can flatten the rough surface of the base source / drain epitaxial layers, and thus the interface characteristics of the metal contact to the source / drain structure can be improved.

[0092] It should be understood that not all advantages are necessarily discussed herein, that no particular advantage is required for all embodiments or examples, and that other embodiments or examples may provide different advantages.

[0093] According to one aspect of the present invention, in a method for manufacturing a semiconductor device, a fin structure protruding from a first isolation insulating layer disposed above a substrate is formed, a pseudo gate structure is formed above an upper portion of the fin structure, a second isolation insulating layer is formed above the first isolation insulating layer, a groove is formed by etching the source / drain region of the fin structure, a base semiconductor epitaxial layer is formed in the groove, and a cap semiconductor epitaxial layer is formed on the base semiconductor epitaxial layer. The cap semiconductor epitaxial layer has a lattice constant different from that of the base semiconductor epitaxial layer, and the surface of the cap semiconductor epitaxial layer is smoother than that of the base semiconductor epitaxial layer. In one or more embodiments above or below, the semiconductor device is a p-type field effect transistor (FET), and the lattice constant of the cap semiconductor epitaxial layer is less than that of the base semiconductor epitaxial layer. In one or more embodiments above or below, the semiconductor device is an n-type field effect transistor (FET), and the lattice constant of the cap semiconductor epitaxial layer is greater than that of the base semiconductor epitaxial layer. In one or more embodiments above or below, the second isolation insulating layer is made of a material different from that of the first isolation insulating layer. In one or more embodiments above or below, the second isolation insulating layer is made of at least one of SiOC and SiOCN. In one or more embodiments above or below, a fin structure is formed by the following operations. A buffer semiconductor layer is formed above a substrate, a channel semiconductor layer is formed on the buffer semiconductor layer, a hard mask pattern is formed above the channel semiconductor layer, and the channel semiconductor layer and the buffer semiconductor layer are patterned by etching using the hard mask pattern as an etching mask. The fin structure includes a patterned buffer semiconductor layer, a patterned channel semiconductor layer, and a hard mask pattern. In one or more embodiments above or below, when patterning to form a fin structure, a portion of the substrate is also patterned, and the fin structure also includes a fin bottom structure, which is a patterned portion of the substrate on which a patterned buffer semiconductor layer is formed. In one or more embodiments above or below, a dummy gate structure is formed above the hard mask pattern, and the method also includes patterning the hard mask pattern by etching using the dummy gate structure as an etching mask. In one or more embodiments above or below, when etching the hard mask pattern, the second isolation insulating layer is also etched so that the upper surface of the second isolation insulating layer is located at a level equal to or lower than the upper surface of the channel semiconductor layer. In one or more embodiments above or below, after forming the trench, the fin bottom structure is exposed at the bottom of the trench, and a base semiconductor epitaxial layer is formed on the exposed fin bottom structure. In one or more embodiments above or below, after forming the trench, a portion of the buffer semiconductor layer is retained, and a base semiconductor epitaxial layer is formed on the remaining portion of the buffer semiconductor layer. In one or more embodiments above or below, an additional cap semiconductor epitaxial layer is formed on the cap semiconductor epitaxial layer.The additional cap semiconductor epitaxial layer has a different lattice constant than the cap semiconductor epitaxial layer and the base semiconductor epitaxial layer. In one or more embodiments above or below, the semiconductor device is a p-type field effect transistor (FET), the lattice constant of the cap semiconductor epitaxial layer is less than the lattice constant of the base semiconductor epitaxial layer, and the lattice constant of the additional cap semiconductor epitaxial layer is less than the lattice constant of the cap semiconductor epitaxial layer. In one or more embodiments above or below, the semiconductor device is an n-type field effect transistor (FET), the lattice constant of the cap semiconductor epitaxial layer is greater than the lattice constant of the base semiconductor epitaxial layer, and the lattice constant of the additional cap semiconductor epitaxial layer is greater than the lattice constant of the cap semiconductor epitaxial layer.

[0094] According to another aspect of the present invention, in a method for manufacturing a semiconductor device, a fin structure protruding from a first isolation insulating layer disposed above a substrate is formed, a pseudo gate structure is formed above an upper portion of the fin structure, a second isolation insulating layer is formed above the first isolation insulating layer, a groove is formed by etching the source / drain region of the fin structure, a base semiconductor epitaxial layer is formed in the groove, and a cap semiconductor epitaxial layer is formed on the base semiconductor epitaxial layer. The cap semiconductor epitaxial layer has a lattice constant different from that of the base semiconductor epitaxial layer. The base semiconductor epitaxial layer is a merged epitaxial layer coupled to the fin structure. The lattice constant of the cap semiconductor epitaxial layer is greater than the lattice constant of the base semiconductor epitaxial layer, and the surface roughness of the cap semiconductor epitaxial layer along the source to drain direction is less than the surface roughness of the base semiconductor epitaxial layer along the source to drain direction. In one or more embodiments above or below, the base semiconductor epitaxial layer is made of one or more layers of SiP, SiC, and SiCP, and the cap semiconductor epitaxial layer is made of one of SiGe, Ge, and GeSn. In one or more embodiments above or below, an additional cap semiconductor epitaxial layer having a larger lattice constant than the cap semiconductor epitaxial layer is formed on the cap semiconductor epitaxial layer, and the additional cap semiconductor epitaxial layer is made of one of SiGe, Ge and GeSn.

[0095] According to another aspect of the present invention, in a method for manufacturing a semiconductor device, a fin structure protruding from a first isolation insulating layer disposed above a substrate is formed, a pseudo gate structure is formed above an upper portion of the fin structure, a second isolation insulating layer is formed above the first isolation insulating layer, a groove is formed by etching the source / drain region of the fin structure, a base semiconductor epitaxial layer is formed in the groove, and a cap semiconductor epitaxial layer is formed on the base semiconductor epitaxial layer. The cap semiconductor epitaxial layer has a lattice constant different from that of the base semiconductor epitaxial layer. The base semiconductor epitaxial layer is a merged epitaxial layer coupled to the fin structure. The lattice constant of the cap semiconductor epitaxial layer is smaller than the lattice constant of the base semiconductor epitaxial layer. The surface roughness of the cap semiconductor epitaxial layer along the source to drain direction is smaller than the surface roughness of the base semiconductor epitaxial layer along the source to drain direction. In one or more embodiments above or below, the base semiconductor epitaxial layer is made of one or more layers of SiGe, Ge, and GeSn, and the cap semiconductor epitaxial layer is made of one of SiGe and Ge. In one or more embodiments above or below, an additional cap semiconductor epitaxial layer having a lattice constant smaller than that of the cap semiconductor epitaxial layer is formed on the cap semiconductor epitaxial layer, and the additional cap semiconductor epitaxial layer is made of one of Si and SiGe.

[0096] According to one aspect of the present invention, a semiconductor device includes a fin structure protruding from a first isolation insulating layer disposed above a substrate, a gate dielectric layer disposed above a channel region of the fin structure, a gate electrode layer disposed above the gate dielectric layer, a base semiconductor epitaxial layer disposed above a source / drain region of the fin structure, and a cap semiconductor epitaxial layer disposed above the base semiconductor epitaxial layer. The cap semiconductor epitaxial layer has a lattice constant different from that of the base semiconductor epitaxial layer. The surface roughness of the cap semiconductor epitaxial layer along the source to drain direction is greater than zero and less than the surface roughness of the base semiconductor epitaxial layer along the source to drain direction. In one or more embodiments above or below, the semiconductor device is an n-type field effect transistor (FET), and the lattice constant of the cap semiconductor epitaxial layer is greater than the lattice constant of the base semiconductor epitaxial layer. In one or more embodiments above or below, the base semiconductor epitaxial layer is made of one or more layers of SiP, SiC, and SiCP, and the cap semiconductor epitaxial layer is made of one of SiGe, Ge, and GeSn. In one or more embodiments above or below, the semiconductor device further comprises an additional cap semiconductor epitaxial layer disposed on the cap semiconductor epitaxial layer, which has a larger lattice constant than the cap semiconductor epitaxial layer. The additional cap semiconductor epitaxial layer is made of one of SiGe, Ge and GeSn. In one or more embodiments above or below, the semiconductor device is a p-type field effect transistor (FET), and the lattice constant of the cap semiconductor epitaxial layer is smaller than the lattice constant of the base semiconductor epitaxial layer. In one or more embodiments above or below, the base semiconductor epitaxial layer is made of one or more layers of SiGe, Ge and GeSn, and the cap semiconductor epitaxial layer is made of one of SiGe and Ge. In one or more embodiments above or below, the semiconductor device further comprises an additional cap semiconductor epitaxial layer disposed on the cap semiconductor epitaxial layer, which has a smaller lattice constant than the cap semiconductor epitaxial layer. The additional cap semiconductor epitaxial layer is made of one of Si and SiGe. In one or more embodiments above or below, the fin structure includes a fin bottom protruding from a substrate, a buffer semiconductor layer disposed above the fin bottom, and a channel semiconductor layer disposed on the buffer semiconductor layer and having a lattice constant different from that of the buffer semiconductor layer. The base semiconductor epitaxial layer is in contact with the buffer semiconductor layer and the channel semiconductor layer. In one or more embodiments above or below, the substrate is made of silicon, and the buffer semiconductor layer includes Si 1-x Ge x , and the channel semiconductor layer includes Si 1-y Ge y, where 0 < x < y ≤ 1.0. In one or more of the above or below embodiments, the semiconductor device further includes a second isolation insulating layer made of an insulating material different from that of the first isolation insulating layer and disposed on the first isolation insulating layer. The second isolation insulating layer is in contact with the base semiconductor epitaxial layer. In one or more of the above or below embodiments, the first isolation insulating layer is not in contact with the base semiconductor epitaxial layer. In one or more of the above or below embodiments, the second isolation insulating layer includes porous SiOC.

[0097] According to another aspect of the present invention, a semiconductor device includes a fin structure protruding from a first isolation insulating layer disposed above a substrate, a gate dielectric layer disposed above the channel region of each fin structure, a gate electrode layer disposed above the gate dielectric layer, a combined base semiconductor epitaxial layer disposed above the source / drain region of the fin structure, and a cap semiconductor epitaxial layer disposed above the base semiconductor epitaxial layer. The cap semiconductor epitaxial layer has a lattice constant different from that of the combined base semiconductor epitaxial layer. The surface of the cap semiconductor epitaxial layer along the source-to-drain direction above one fin structure is uneven, but smoother than the surface of the combined base semiconductor epitaxial layer. In one or more of the above or below embodiments, the semiconductor device is an n-type field effect transistor (FET), and the lattice constant of the cap semiconductor epitaxial layer is greater than that of the base semiconductor epitaxial layer. In one or more of the above or below embodiments, the semiconductor device further includes an additional cap semiconductor epitaxial layer disposed on the cap semiconductor epitaxial layer, which has a lattice constant greater than that of the cap semiconductor epitaxial layer. In one or more of the above or below embodiments, the base semiconductor epitaxial layer is made of one or more layers of SiP, SiC, and SiCP, the cap semiconductor epitaxial layer is made of one of SiGe, Ge, and GeSn, and the additional cap semiconductor epitaxial layer is made of one of SiGe, Ge, and GeSn. In one or more of the above or below embodiments, the semiconductor device is a p-type field effect transistor (FET), and the lattice constant of the cap semiconductor epitaxial layer is less than that of the base semiconductor epitaxial layer. In one or more of the above or below embodiments, the semiconductor device further includes an additional cap semiconductor epitaxial layer disposed on the cap semiconductor epitaxial layer, which has a lattice constant smaller than that of the cap semiconductor epitaxial layer. In one or more of the above or below embodiments, the base semiconductor epitaxial layer is made of one or more layers of SiGe, Ge, and GeSn, the cap semiconductor epitaxial layer is made of one of SiGe and Ge, and the additional cap semiconductor epitaxial layer is made of one of Si and SiGe.

[0098] According to another aspect of the present invention, a semiconductor device includes a fin structure protruding from a first isolation insulating layer disposed above a substrate. Each fin structure includes a fin bottom protruding from the substrate, a buffer semiconductor layer disposed above the fin bottom, and a channel semiconductor layer disposed on the buffer semiconductor layer and having a lattice constant different from that of the buffer semiconductor layer. The semiconductor device also includes a second isolation insulating layer disposed above the first isolation insulating layer and made of an insulating material different from that of the first isolation insulating layer, a gate dielectric layer disposed above the channel region of each fin structure, a gate electrode layer disposed above the gate dielectric layer, a merged base semiconductor epitaxial layer disposed above the source / drain region of the fin structure and in contact with the second isolation insulating layer, and a cap semiconductor epitaxial layer disposed above the base semiconductor epitaxial layer. The cap semiconductor epitaxial layer has a lattice constant different from that of the merged base semiconductor epitaxial layer. The surface roughness of the cap semiconductor epitaxial layer along the source to drain direction is greater than zero and less than the surface roughness of the merged base semiconductor epitaxial layer along the source to drain direction.

[0099] According to one aspect of the present invention, a semiconductor device includes a p-type FET and an n-type FET. Each p-type FET and n-type FET includes a fin structure, which protrudes from a first isolation insulating layer disposed above a substrate and has a fin bottom protruding from the substrate, a buffer semiconductor layer disposed above the fin bottom, and a channel semiconductor layer disposed on the buffer semiconductor layer and having a lattice constant different from that of the buffer semiconductor layer. Each p-type FET and n-type FET also includes a second isolation insulating layer disposed above the first isolation insulating layer and made of an insulating material different from that of the first isolation insulating layer, a gate dielectric layer disposed above the channel region of the fin structure, a gate electrode layer disposed above the gate dielectric layer, a base semiconductor epitaxial layer disposed above the source / drain region of the fin structure and in contact with the second isolation insulating layer, and a cap semiconductor epitaxial layer disposed above the base semiconductor epitaxial layer. The surface roughness of the cap semiconductor epitaxial layer along the source to drain direction is greater than zero and less than the surface roughness of the base semiconductor epitaxial layer along the source to drain direction. In a p-type FET, the lattice constant of the cap semiconductor epitaxial layer is smaller than the lattice constant of the base semiconductor epitaxial layer, while in an n-type FET, the lattice constant of the cap semiconductor epitaxial layer is larger than the lattice constant of the base semiconductor epitaxial layer. Features of several embodiments or examples are summarized above so that those skilled in the art can better understand aspects of the present invention. Those skilled in the art should understand that they can easily use the present invention as a basis to design or modify other processes and structures for implementing the same purposes and / or achieving the same advantages as the embodiments described herein. Those skilled in the art should also appreciate that such equivalent constructions do not depart from the spirit and scope of the present invention, and that they may make various changes, substitutions, and modifications herein without departing from the spirit and scope of the present invention.

Claims

1. A method for manufacturing a semiconductor device, the method comprising: forming a fin structure protruding from a first isolation insulating layer disposed above the substrate; forming a dummy gate structure over an upper portion of the fin structure; After forming the dummy gate structure, forming a second isolation insulating layer above the first isolation insulating layer; After forming the second isolation insulating layer, forming a gate sidewall spacer on the opposite side of the dummy gate structure, the gate sidewall spacer being made of an insulating material different from that of the second isolation insulating layer; After forming the gate sidewall spacer, forming a trench by etching the source / drain region of the fin structure; forming a base semiconductor epitaxial layer in the trench; and forming a cap semiconductor epitaxial layer on the base semiconductor epitaxial layer, wherein the lattice constant of the cap semiconductor epitaxial layer is different from that of the base semiconductor epitaxial layer; Wherein, the surface of the cap semiconductor epitaxial layer is smoother than the surface of the base semiconductor epitaxial layer.

2. The method according to claim 1, wherein: The semiconductor device is a p-type field effect transistor (FET), and The lattice constant of the cap semiconductor epitaxial layer is smaller than the lattice constant of the base semiconductor epitaxial layer.

3. The method according to claim 1, wherein: The semiconductor device is an n-type field effect transistor (FET), and The lattice constant of the cap semiconductor epitaxial layer is greater than the lattice constant of the base semiconductor epitaxial layer.

4. The method according to claim 1, wherein: The second isolating insulating layer is made of a material different from that of the first isolating insulating layer.

5. The method according to claim 4, wherein: The second isolation insulating layer is made of at least one of SiOC and SiOCN.

6. The method according to claim 1, wherein: The fin structure is formed by: forming a buffer semiconductor layer above the substrate; forming a channel semiconductor layer on the buffer semiconductor layer; forming a hard mask pattern over the channel semiconductor layer; as well as patterning the channel semiconductor layer and the buffer semiconductor layer by etching using the hard mask pattern as an etching mask, The fin structure includes a patterned buffer semiconductor layer, a patterned channel semiconductor layer and the hard mask pattern.

7. The method according to claim 6, wherein: When patterning to form the fin structure, a portion of the substrate is also patterned, and The fin structure further includes a fin bottom structure, which is a patterned portion of the substrate, and the patterned buffer semiconductor layer is formed on the fin bottom structure.

8. The method according to claim 6, wherein: forming the dummy gate structure over the hard mask pattern, and The method further includes patterning the hard mask pattern by etching using the dummy gate structure as an etch mask.

9. The method according to claim 8, wherein: When the hard mask pattern is etched, the second isolation insulating layer is also etched so that an upper surface of the second isolation insulating layer is located at a level equal to or lower than an upper surface of the channel semiconductor layer.

10. The method according to claim 7, wherein: After the trench is formed, the fin bottom structure is exposed at the bottom of the trench, and the base semiconductor epitaxial layer is formed on the exposed fin bottom structure.

11. The method according to claim 7, wherein: After forming the trench, a portion of the buffer semiconductor layer remains, and the base semiconductor epitaxial layer is formed on the remaining portion of the buffer semiconductor layer.

12. The method according to claim 1, further comprising: forming an additional cap semiconductor epitaxial layer on the cap semiconductor epitaxial layer, The additional cap semiconductor epitaxial layer has a lattice constant different from that of the cap semiconductor epitaxial layer and the base semiconductor epitaxial layer.

13. The method according to claim 12, wherein: The semiconductor device is a p-type field effect transistor (FET), The lattice constant of the cap semiconductor epitaxial layer is smaller than the lattice constant of the base semiconductor epitaxial layer. The additional cap semiconductor epitaxial layer has a lattice constant that is smaller than the lattice constant of the cap semiconductor epitaxial layer.

14. The method of claim 12, wherein: The semiconductor device is an n-type field effect transistor (FET), The lattice constant of the cap semiconductor epitaxial layer is greater than the lattice constant of the base semiconductor epitaxial layer, and The additional cap semiconductor epitaxial layer has a lattice constant greater than the lattice constant of the cap semiconductor epitaxial layer.

15. A method for manufacturing a semiconductor device, the method comprising: forming a fin structure protruding from a first isolation insulating layer disposed above the substrate; forming a dummy gate structure over an upper portion of the fin structure; After forming the dummy gate structure, forming a second isolation insulating layer above the first isolation insulating layer; After forming the second isolation insulating layer, forming gate sidewall spacers on opposite sides of the dummy gate structure; After forming the gate sidewall spacer, forming a trench by etching the source / drain region of the fin structure; forming a base semiconductor epitaxial layer in the trench; and A cap semiconductor epitaxial layer is formed on the base semiconductor epitaxial layer, wherein the cap semiconductor epitaxial layer has a lattice constant different from that of the base semiconductor epitaxial layer, wherein: The base semiconductor epitaxial layer is a merged epitaxial layer coupled to the fin structure, The lattice constant of the cap semiconductor epitaxial layer is greater than the lattice constant of the base semiconductor epitaxial layer, and The surface roughness of the cap semiconductor epitaxial layer along the direction from the source to the drain is smaller than the surface roughness of the base semiconductor epitaxial layer along the direction from the source to the drain.

16. The method of claim 15, wherein: The base semiconductor epitaxial layer is made of one or more layers of SiP, SiC and SiCP, and The cap semiconductor epitaxial layer is made of one of SiGe, Ge and GeSn.

17. The method according to claim 16, further comprising: forming an additional cap semiconductor epitaxial layer on the cap semiconductor epitaxial layer, the additional cap semiconductor epitaxial layer having a larger lattice constant than the cap semiconductor epitaxial layer, Wherein, the additional cap semiconductor epitaxial layer is made of one of SiGe, Ge and GeSn.

18. A semiconductor device comprising: a fin structure protruding from a first isolation insulating layer disposed above the substrate; a gate dielectric layer disposed above the channel region of the fin structure; A gate electrode layer, disposed above the gate dielectric layer; a sidewall spacer disposed over opposing sidewalls of the gate dielectric layer and the gate electrode layer in a cross-sectional view; A base semiconductor epitaxial layer, disposed above the source / drain region of the fin structure; as well as The cap semiconductor epitaxial layer is arranged above the base semiconductor epitaxial layer, wherein: The cap semiconductor epitaxial layer has a lattice constant different from that of the base semiconductor epitaxial layer, and The surface roughness of the cap semiconductor epitaxial layer along the direction from the source to the drain is greater than zero and less than the surface roughness of the base semiconductor epitaxial layer along the direction from the source to the drain. The interface between the cap semiconductor epitaxial layer and the base semiconductor epitaxial layer is located below the interface between the gate dielectric layer and the channel region, and the top of the cap semiconductor epitaxial layer is located above the interface between the gate dielectric layer and the channel region, and Interfaces between the cap semiconductor epitaxial layer and the base semiconductor epitaxial layer and the sidewall spacers and outer surfaces of the channel region are smooth curves in a cross-sectional view.

19. The semiconductor device according to claim 18, wherein: The semiconductor device is an n-type field effect transistor (FET), and The lattice constant of the cap semiconductor epitaxial layer is greater than the lattice constant of the base semiconductor epitaxial layer.

20. The semiconductor device according to claim 18, wherein: The semiconductor device is a p-type field effect transistor (FET), and The lattice constant of the cap semiconductor epitaxial layer is smaller than the lattice constant of the base semiconductor epitaxial layer.

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