Level shifting circuit and integrated circuit

Abstract

The present invention provides a level shifting circuit and an integrated circuit. The level shifting circuit includes: a load unit for receiving a power supply voltage signal and a first control signal to generate a gate control signal; an input unit for receiving an input signal to ground the gate control signal; and a plurality of bias units disposed between the load unit and the input unit. The plurality of bias units are for receiving a bias voltage signal to transmit the gate control signal to the input unit, and the plurality of bias units are connected in series with each other and coupled to the load unit. Wherein, the level shifting circuit is used to convert a first signal into a second signal, and the voltage of the second signal is greater than the voltage of the first signal. The present invention can improve the robustness of the level shifting circuit.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuits, and particularly to a level shifter circuit and an integrated circuit. Background Art

[0002] A level shifter circuit converts a low-voltage logic control signal into a high-voltage logic control signal to realize the control of a high-voltage logic output stage by a low-voltage logic input stage, and has wide applications in display driving, flash memory, etc. In applications such as source driver chips, power management chips, and timing control chips of liquid crystal displays, the level shifter circuit requires a lower voltage input on the one hand, and on the other hand, it requires to work normally under a large power supply noise.

[0003] As Figure 1 shown, the prior art provides a conventional low-voltage input type level shifter circuit for a scan driver of an LCD module, which converts a low-voltage digital signal into a high-voltage digital signal. The level shifter circuit includes two LV (low-voltage) MOS transistors M1-M2 and four HV (high-voltage) MOS transistors M3-M6. The sources and substrates of the two LV NMOS transistors M1 and M2 are connected to the ground voltage VSSA, and the drains are respectively connected to the sources of the two HV NMOS transistors M5 and M6. The substrates of M5 and M6 are connected to the ground voltage VSSA, and the gates are connected to the control signal VB. VB has a suitable voltage to ensure that M5 and M6 are turned on simultaneously and protect the LV NMOS M1 and M2 from damage from the high power supply voltage VDDA. The drains are respectively connected to the drains of the two HV PMOS transistors M3 and M4. The sources and substrates of M3 and M4 are connected to the power supply voltage VDDA (such as 9 volts or 18 volts). However, when multiple buffers driving large loads flip simultaneously, the high-voltage power supply is likely to generate a large noise. Under the influence of the high power supply noise, the level shifter circuit provided by the prior art will have some problems. For example: First, the time for the output signal state to switch will increase. Second, a DC current path may be generated when all six transistors M1-M6 are turned on, thus consuming a large current. Third, the switching states fail due to DC current latch. Furthermore, the level shifter circuit provided by the prior art is prone to abnormal operation under low-voltage input and large power supply noise. Summary of the Invention

[0004] The present invention provides a level shifter circuit and an integrated circuit to solve the problem that the level shifter circuit is prone to abnormal operation under low-voltage input and large power supply noise.

[0005] According to a first aspect of the present invention, the present invention provides a level shift circuit, comprising: a load unit for receiving a power supply voltage signal and a first control signal to generate a gate control signal; an input unit for receiving an input signal to ground the gate control signal; and a plurality of bias units disposed between the load unit and the input unit, the plurality of bias units for receiving a bias voltage signal to transmit the gate control signal to the input unit, the plurality of bias units being connected in series with each other and coupled to the load unit, the plurality of bias units including a first bias unit, a second bias unit, and a third bias unit, the first bias unit for limiting the drain potential of the input unit, the second bias unit for limiting the drain potential of the first bias unit, and the third bias unit for providing a gate control power supply for the load unit; wherein the level shift circuit is configured to convert a first signal into a second signal, and the voltage of the second signal is greater than the voltage of the first signal.

[0006] In some embodiments, the input unit includes: a first switching transistor and a second switching transistor. The substrates and sources of the first switching transistor and the second switching transistor are both connected to a ground voltage signal. The gates of the first switching transistor and the second switching transistor are respectively connected to an input signal and an inverted input signal. The plurality of bias units include: a third switching transistor and a fourth switching transistor. The substrates of the third switching transistor and the fourth switching transistor are both connected to a ground voltage signal. The sources of the third switching transistor and the fourth switching transistor are respectively connected to the drains of the first switching transistor and the second switching transistor. The gates of the third switching transistor and the fourth switching transistor are both connected to a first bias voltage signal. A fifth switching transistor and a sixth switching transistor. The substrates of the fifth switching transistor and the sixth switching transistor are both connected to a ground voltage signal. The sources of the fifth switching transistor and the sixth switching transistor are respectively connected to the drains of the third switching transistor and the fourth switching transistor. The gates of the fifth switching transistor and the sixth switching transistor are both connected to a second bias voltage signal. A seventh switching transistor and an eighth switching transistor. The substrates of the seventh switching transistor and the eighth switching transistor are both connected to a power supply voltage signal. The drains of the seventh switching transistor and the eighth switching transistor are respectively connected to the drains of the fifth switching transistor and the sixth switching transistor. The gates of the seventh switching transistor and the eighth switching transistor are both connected to a third bias voltage signal. The load unit includes: a ninth switching transistor and a tenth switching transistor. The substrates and sources of the ninth switching transistor and the tenth switching transistor are both connected to a power supply voltage signal. The drains of the ninth switching transistor and the tenth switching transistor are connected to the sources of the seventh switching transistor and the eighth switching transistor. The gate of the ninth switching transistor is respectively coupled to the drains of the sixth switching transistor and the eighth switching transistor. The gate of the tenth switching transistor is respectively coupled to the drains of the fifth switching transistor and the seventh switching transistor. Wherein, the drains of the fifth switching transistor and the seventh switching transistor are the first output terminals of the level shift circuit, and the drains of the sixth switching transistor and the eighth switching transistor are the second output terminals of the level shift circuit.

[0007] In some embodiments, the first switching transistor and the second switching transistor are one of a first N-type transistor or a first P-type transistor.

[0008] In some embodiments, the third switching transistor and the fourth switching transistor are one of a second N-type transistor or a second P-type transistor.

[0009] In some embodiments, the fifth switching transistor and the sixth switching transistor are one of a second N-type transistor or a second P-type transistor.

[0010] In some embodiments, the seventh switching transistor and the eighth switching transistor are one of a second N-type transistor or a second P-type transistor.

[0011] In some embodiments, the ninth switching transistor and the tenth switching transistor are one of a second N-type transistor or a second P-type transistor.

[0012] According to a second aspect of the present invention, the present invention provides an integrated circuit, including the level shifter circuit as described above.

[0013] In some embodiments, the integrated circuit further includes: a bias voltage generator, configured to provide a plurality of bias voltage signals for the level shifter circuit, where the plurality of bias voltage signals include: a power supply voltage signal, a ground voltage signal, a first control voltage signal, a second control voltage signal, and a third control voltage signal.

[0014] Compared with the prior art, the beneficial effects of the present invention are as follows: Without increasing too much layout area, it ensures the fast transition of low-voltage input, and at the same time effectively reduces the influence of power supply noise on the level shifter circuit, thereby increasing the robustness of the level shifter circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 FIG. is a schematic structural diagram of a level shifter circuit provided by the prior art

[0016] Figure 2 FIG. is a schematic structural diagram of a level shifter circuit provided by an embodiment of the present invention.

[0017] Figures 3a - 3c For Figure 2 the circuit simulation diagram of the level shifter circuit shown.

[0018] Figure 4 FIG. is a schematic structural diagram of an integrated circuit provided by an embodiment of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0019] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative efforts belong to the scope of protection of the present invention.

[0020] As Figure 2 shown, an embodiment of the present invention provides a level shifter circuit, which is configured to convert a first signal into a second signal, where the voltage of the second signal is greater than the voltage of the first signal. The level shifter circuit includes an input unit 21, a plurality of bias units 22, and a load unit 23. Among them, the plurality of bias units 22 include a first bias unit 221, a second bias unit 222, and a third bias unit 223.

[0021] The load unit 23 is used to receive a power supply voltage signal (VDDA) and a first control signal (VDDA) to generate gate control signals (VOUT, VOUTB).

[0022] A plurality of bias units 22 are disposed between the load unit 23 and the input unit 21. The plurality of bias units 22 are used to receive bias voltage signals (VB1, VB2, VB3) to transmit the gate control signals (VOUT, VOUTB) to the input unit 21. The plurality of bias units 22 are connected in series with each other and coupled to the load unit 23.

[0023] The input unit 21 is used to receive input signals (VIN, VINB) to ground the gate control signals (VOUT, VOUTB).

[0024] Specifically, the input unit 21 includes: a first switching transistor M1 and a second switching transistor M2. The substrates and sources of the first switching transistor M1 and the second switching transistor M2 are both connected to a ground voltage signal (VSSA). The gates of the first switching transistor M1 and the second switching transistor M2 are respectively connected to the input signal (VIN) and the inverted input signal (VINB).

[0025] The first bias unit 221 includes: a third switching transistor M3 and a fourth switching transistor M4. The substrates of the third switching transistor M3 and the fourth switching transistor M4 are both connected to the ground voltage signal (VSSA). The sources of the third switching transistor M3 and the fourth switching transistor M4 are respectively connected to the drains of the first switching transistor M1 and the second switching transistor M2. The gates of the third switching transistor M3 and the fourth switching transistor M4 are both connected to the first bias voltage signal (VB1). The first bias unit 221 is used to limit the drain potential of the first switching transistor M1 and the second switching transistor M2 in the input unit 21, limit the switching spike current of the level shift circuit itself, reduce the power supply noise, thereby accelerating the switching time of the output signal state.

[0026] The second bias unit 222 includes: a fifth switching transistor M5 and a sixth switching transistor M6. The substrates of the fifth switching transistor M5 and the sixth switching transistor M6 are both connected to the ground voltage signal (VSSA). The sources of the fifth switching transistor M5 and the sixth switching transistor M6 are respectively connected to the drains of the third switching transistor M3 and the fourth switching transistor M4. The gates of the fifth switching transistor M5 and the sixth switching transistor M6 are both connected to the second bias voltage signal (VB2). The second bias unit 222 is used to further improve the power supply noise immunity of the circuit, and thus improve the robustness of the level shift circuit.

[0027] The third bias unit 223 includes: a seventh switching transistor M7 and an eighth switching transistor M8. The substrates of the seventh switching transistor M7 and the eighth switching transistor M8 are both connected to a power supply voltage signal (VDDA). The drains of the seventh switching transistor M7 and the eighth switching transistor M8 are respectively connected to the drains of the fifth switching transistor M5 and the sixth switching transistor M6. The gates of the seventh switching transistor M7 and the eighth switching transistor M8 are both connected to a third bias voltage signal (VB3). The third bias unit 223 is used to limit the current of the ninth switching transistor M9 and the tenth switching transistor M10 in the load unit 23, and at the same time provides a gate control current source to improve the circuit driving ability.

[0028] Providing multiple bias units 22, that is, providing multiple switching transistors and applying corresponding bias voltages thereto, can reduce the impact of power supply noise on the level shift circuit, thereby avoiding the generation of a DC current path.

[0029] The load unit 23 includes: a ninth switching transistor M9 and a tenth switching transistor M10. The substrates and sources of the ninth switching transistor M9 and the tenth switching transistor M10 are both connected to a power supply voltage signal (VDDA). The drains of the ninth switching transistor M9 and the tenth switching transistor M10 are connected to the sources of the seventh switching transistor M7 and the eighth switching transistor M8. The gate of the ninth switching transistor M9 is respectively coupled to the drains of the sixth switching transistor M6 and the eighth switching transistor M8. The gate of the tenth switching transistor M10 is respectively coupled to the drains of the fifth switching transistor M5 and the seventh switching transistor M7.

[0030] The drains of the fifth switching transistor M5 and the seventh switching transistor M7 are the first output terminals of the level shift circuit. The drains of the sixth switching transistor M6 and the eighth switching transistor M8 are the second output terminals of the level shift circuit.

[0031] Among them, the first switching transistor M1 and the second switching transistor M2 are one of a first N-type transistor (low-voltage N-type transistor) or a first P-type transistor (low-voltage P-type transistor).

[0032] The third switching transistor M3 and the fourth switching transistor M4 are one of a second N-type transistor (high-voltage N-type transistor) or a second P-type transistor (high-voltage P-type transistor).

[0033] The fifth switching transistor M5 and the sixth switching transistor M6 are one of a second N-type transistor (high-voltage N-type transistor) or a second P-type transistor (high-voltage P-type transistor).

[0034] The seventh switching transistor M7 and the eighth switching transistor M8 are one of a second N-type transistor (high-voltage N-type transistor) or a second P-type transistor (high-voltage P-type transistor).

[0035] The ninth switching transistor M9 and the tenth switching transistor M10 are one of a second N-type transistor (high-voltage N-type transistor) or a second P-type transistor (high-voltage P-type transistor).

[0036] In an embodiment of the present invention, the first switching transistor M1 and the second switching transistor M2 are low-voltage N-type transistors, the third switching transistor M3 to the sixth switching transistor M6 are high-voltage N-type transistors, and the seventh switching transistor M7 to the tenth switching transistor M10 are high-voltage P-type transistors. The operation principle of the level-shifting circuit according to the embodiment of the present invention is described as follows.

[0037] Bias voltage signals VB1, VB2, and VB3 are provided to turn on the third switching transistor M3 to the eighth switching transistor M8. When an input signal VIN having a low-voltage high logic state (e.g., 1.4 volts) is applied to the first switching transistor M1 and an inverted input signal VINB having a low-voltage low logic state (e.g., 0 volts) is applied to the second switching transistor M2, the first switching transistor M1 is turned on, and the gate of the tenth switching transistor M10 is connected to ground through the fifth switching transistor M5, the third switching transistor M3, and the first switching transistor M1, and thus the tenth switching transistor M10 is turned on. The second switching transistor M2 is turned off due to the inverted signal VINB having a low-voltage low logic state (i.e., 0 volts) applied to its gate. Therefore, the output signal VOUT shows the high-voltage high logic state of the power supply voltage VDDA, and the output signal VOUTB is connected to ground to show the high-voltage low logic state of the ground voltage VSSA. That is, the input signal VIN having a low-voltage high logic state (e.g., 1.4 volts) is converted into an output signal VOUT having a high-voltage high logic state (e.g., 9 volts or 18 volts) through the level-shifting circuit. When the input signal VIN switches to the low-voltage low logic state (0 volts) and the inverted signal VINB switches to the low-voltage high logic state (1.4 volts), the first switching transistor M1 is turned off and the second switching transistor M2 is turned on. The gate of the ninth switching transistor M9 is connected to ground through the turned-on sixth switching transistor M6, the fourth switching transistor M4, and the second switching transistor M2, and thus the ninth switching transistor M9 is turned on. The gate of the tenth switching transistor M10 is connected to the power supply voltage VDDA through the turned-on ninth switching transistor M9, and thus the tenth switching transistor M10 is turned off. Therefore, the output signal VOUT shows the high-voltage low logic state (0 volts). That is, the low-voltage low logic state (0 volts) is converted into the high-voltage low logic state (0 volts) through the level-shifting circuit.

[0038] Refer to Figures 3a - 3c , which is the circuit simulation diagram of the level-shifting circuit as Figure 2 . Curve A is the curve of the power supply voltage VDDA changing with time; Curve B is the curve of the ground voltage VSSA changing with time; Curve C is the curve of the input signal changing with time; Curves D and E are the comparison of the output voltages, where Curve D is the curve of the output voltage of the level-shifting circuit in the prior art changing with time, and Curve E is the curve of the output voltage of the level-shifting circuit in this embodiment changing with time. From Figures 3a - 3cIt can be seen that when the input signal rises from 0 volts to 1.4 volts, the output voltage rises from 0 volts to about 13 volts. While the input signal rises from 0 volts to 1.4 volts, a noise of 1.5V is applied to the power supply voltage VDDA and the ground voltage VSSA simultaneously. The state transition of the level shift circuit in the prior art has problems and cannot flip normally, while the level shift circuit in this embodiment works normally. Therefore, the level shift circuit in the embodiment of the present invention has the functions of low input voltage and anti-power supply noise at the same time.

[0039] As Figure 4 shown, an integrated circuit 40 is provided in an embodiment of the present invention, including the level shift circuit 41 and the bias voltage generator 42 described above.

[0040] The bias voltage generator 42 is used to provide a plurality of bias voltage signals for the level shift circuit 41. The plurality of bias voltage signals include: a power supply voltage signal, a ground voltage signal, a first control voltage signal, a second control voltage signal, and a third control voltage signal.

[0041] The beneficial effects of the present invention are as follows: Without increasing too much layout area, it ensures the fast transition of low-voltage input, and at the same time effectively reduces the influence of power supply noise on the level shift circuit, thereby increasing the robustness of the level shift circuit.

[0042] In the above embodiments, the descriptions of the respective embodiments have their own emphases. For parts not detailed in a certain embodiment, reference may be made to the relevant descriptions of other embodiments.

[0043] The embodiments of the present invention have been described above in conjunction with the accompanying drawings. However, the present invention is not limited to the above specific embodiments. The above specific embodiments are merely illustrative and not restrictive. Under the inspiration of the present invention, those of ordinary skill in the art can also make many forms without departing from the spirit and scope protected by the present invention and the claims, and all of them belong to the protection scope of the present invention.

Claims

1. A level shift circuit, characterized in that Comprising: A load unit for receiving a power supply voltage signal and a first control signal to generate a gate control signal; An input unit for receiving an input signal to ground the gate control signal; And A plurality of bias units disposed between the load unit and the input unit, the plurality of bias units for receiving a bias voltage signal to transmit the gate control signal to the input unit, the plurality of bias units being connected in series with each other and coupled to the load unit, the plurality of bias units including a first bias unit, a second bias unit, and a third bias unit, the first bias unit for limiting the drain potential of the input unit, the second bias unit for improving the power supply noise resistance of the level shift circuit by limiting the drain potential of the first bias unit, and the third bias unit for limiting the current of the load unit and providing the gate control power supply for the load unit; Wherein, the level shift circuit is used to convert a first signal into a second signal, and the voltage of the second signal is greater than the voltage of the first signal; Wherein, the switching transistors in the first bias unit and the second bias unit are high-voltage N-type transistors, and the switching transistor in the third bias unit is a high-voltage P-type transistor.

2. The level shift circuit according to claim 1, wherein The input unit includes: A first switching transistor and a second switching transistor, the substrates and sources of the first switching transistor and the second switching transistor are both connected to a ground voltage signal, and the gates of the first switching transistor and the second switching transistor are respectively connected to an input signal and an inverted input signal; The first bias unit includes: A third switching transistor and a fourth switching transistor, the substrates of the third switching transistor and the fourth switching transistor are both connected to a ground voltage signal, the sources of the third switching transistor and the fourth switching transistor are respectively connected to the drains of the first switching transistor and the second switching transistor, and the gates of the third switching transistor and the fourth switching transistor are both connected to a first bias voltage signal; The second bias unit includes: A fifth switching transistor and a sixth switching transistor, the substrates of the fifth switching transistor and the sixth switching transistor are both connected to a ground voltage signal, the sources of the fifth switching transistor and the sixth switching transistor are respectively connected to the drains of the third switching transistor and the fourth switching transistor, and the gates of the fifth switching transistor and the sixth switching transistor are both connected to a second bias voltage signal; The third bias unit includes: A seventh switching transistor and an eighth switching transistor, the substrates of the seventh switching transistor and the eighth switching transistor are both connected to a power supply voltage signal, the drains of the seventh switching transistor and the eighth switching transistor are respectively connected to the drains of the fifth switching transistor and the sixth switching transistor, and the gates of the seventh switching transistor and the eighth switching transistor are both connected to a third bias voltage signal; The load unit includes: A ninth switching transistor and a tenth switching transistor, wherein the substrates and sources of the ninth switching transistor and the tenth switching transistor are both connected to a power supply voltage signal, the drains of the ninth switching transistor and the tenth switching transistor are connected to the sources of the seventh switching transistor and the eighth switching transistor, the gate of the ninth switching transistor is respectively coupled to the drains of the sixth switching transistor and the eighth switching transistor, and the gate of the tenth switching transistor is respectively coupled to the drains of the fifth switching transistor and the seventh switching transistor; Wherein, the drains of the fifth switching transistor and the seventh switching transistor are the first output terminals of the level shifting circuit, and the drains of the sixth switching transistor and the eighth switching transistor are the second output terminals of the level shifting circuit.

3. The level shift circuit according to claim 2, wherein, The first switching transistor and the second switching transistor are one of a first N-type transistor or a first P-type transistor.

4. The level shift circuit according to claim 2, wherein, The ninth switching transistor and the tenth switching transistor are one of a second N-type transistor or a second P-type transistor.

5. An integrated circuit, characterized in that, Comprising the level shifting circuit according to any one of claims 1-4.

6. The integrated circuit according to claim 5, wherein The integrated circuit further comprises: A bias voltage generator for providing a plurality of bias voltage signals to the level shifting circuit, the plurality of bias voltage signals including: a power supply voltage signal, a ground voltage signal, a first control voltage signal, a second control voltage signal, and a third control voltage signal.

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