Heterogeneous system simulator framework and its generation, access and main loop operation method

Abstract

The present invention provides a method for generating a heterogeneous system simulator framework, a method for accessing the heterogeneous system simulator framework, a main loop operation method for the heterogeneous system simulator framework, and a heterogeneous system simulator framework. The simulator framework of the heterogeneous system is centered on a bus that connects various modules. Through a standardized bus interface, various computing units and peripheral devices are conveniently and quickly connected together to achieve heterogeneous system simulation with bus clock accuracy. The interfaces connecting the modules to the bus are divided into two types: a master interface and a slave interface. The same module can choose to include both interfaces or only one of them. The master interface can actively initiate bus access, and the slave interface defines the response when the device is accessed. Through the framework, the user can ignore the structural differences between the modules and easily complete the construction of the heterogeneous system simulator.

Description

Technical Field

[0001] The present invention relates to the field of computer technology, and specifically to a heterogeneous system simulator framework and a method for generating, accessing and running a main loop thereof. Background Art

[0002] After more than half a century of exponential growth in the semiconductor industry, the number of transistors that can be integrated into a single chip has far exceeded 1 billion, which is enough to easily place an entire system on a small chip. As Moore's Law gradually reaches its limit, people have to turn their attention from simply improving the process to exploring the processor architecture. Symmetric multi-processor architecture, big and small core architecture, heterogeneous system, various processor platforms are emerging in an endless stream. The layout of symmetric multi-processors and big and small core architectures is regular and orderly, while in heterogeneous systems, in addition to traditional general-purpose processors, it also includes a variety of dedicated computing modules, such as graphics processing units (GPUs), digital signal processors (DSPs), field programmable gate arrays (FPGAs) and neural network accelerators, etc., which greatly increases the complexity.

[0003] There is no mature and reliable simulator framework for heterogeneous systems so far. It can only be rebuilt from scratch according to development requirements. Not only does it require a huge workload, but because there is no unified interface, the modules cannot be well integrated together, the simulation accuracy at the clock level cannot be achieved, and even the correctness of the simulation is affected. Therefore, a heterogeneous simulator framework is needed that can integrate the modules together with only a small amount of code. Summary of the invention

[0004] The purpose of the present invention is to provide a method for generating a heterogeneous system simulator framework, a method for accessing a heterogeneous system simulator framework, a main loop running method for a heterogeneous system simulator framework, and a heterogeneous system simulator framework.

[0005] The simulator framework of the heterogeneous system in the present invention is centered on a bus that connects various modules. Through standardized bus interfaces, various computing units and peripheral devices are conveniently and quickly connected together to achieve heterogeneous system simulation with bus clock accuracy. The interfaces connecting the modules to the bus are divided into two types: master interface and slave interface. The same module can choose to include both interfaces or only one of them. The master interface can actively initiate bus access, and the slave interface defines the response when the device is accessed. Through the framework, users can ignore the structural differences between modules and easily complete the construction of a heterogeneous system simulator.

[0006] The first aspect of the present invention provides a method for generating a heterogeneous system simulator framework, wherein the simulator can call a parameter parser, in which a parameter list supported by the simulator and a corresponding parameter processing function are registered, and the heterogeneous system simulator framework can configure multiple submodules on a bus.

[0007] Multiple submodules, each of which includes a slave interface class. The multiple slave interface classes define corresponding response information of the submodule after receiving the bus access.

[0008] The simulator framework generation method for heterogeneous systems includes:

[0009] Step S101: The parameter parser parses the initialization parameters of the simulator according to the command line.

[0010] Step S102: The simulator calls the initialization function of the submodule according to the initialization parameters.

[0011] Step S103: The submodule initialization function obtains the submodule initialization configuration parameters, configures the simulator system resources according to the simulator initialization configuration parameters, and configures the submodule system resources according to the submodule initialization configuration parameters.

[0012] Step S104, a bus is generated. The bus has a registration function. Multiple slave interface classes are added to the device list of the bus by the registration function.

[0013] Step S105: Generate a bus master interface. The bus master interface is a bus handle.

[0014] In one embodiment of the method for generating a heterogeneous system simulator framework of the present invention, before step S101, the method further includes: step S100, obtaining a startup command line, wherein the startup command line includes a simulator name and simulator parameters.

[0015] In another implementation of the method for generating a heterogeneous system simulator framework of the present invention, the submodule registration parameters include: a starting address of the submodule, a length of the submodule, and slave interface class information.

[0016] A second aspect of the present invention provides a method for accessing a simulator framework of a heterogeneous system, including a simulator framework generated by the simulator framework generation method of the heterogeneous system. The method for accessing a simulator framework of a heterogeneous system includes:

[0017] Step S201, when an access device accesses a bus through a bus master interface.

[0018] Step S202, the bus searches the bus registration list for the current submodule corresponding to the access address according to the starting address and length of each submodule, and if a submodule that meets the conditions is found, the access address is subtracted from the base address of the module, and the access request is passed to the submodule. If not, a bus access warning message is issued.

[0019] In one implementation of the method for accessing a heterogeneous system simulator framework of the present invention, step S202 includes:

[0020] Step S2021, calling a corresponding access request function through the bus handle. The access request function includes: passing a target address parameter of the access, a type parameter of the access, a length parameter of the access, and a pointer parameter of the data.

[0021] Step S2022, determine whether the corresponding submodule can be obtained through the submodule registration parameters according to the access request function called by the bus handle and the current access address in the bus registration table. If yes, request to access the submodule. If not, issue a bus access warning message.

[0022] The third aspect of the present invention provides a main loop running method of a heterogeneous system simulator framework, including a simulator framework generated by the simulator framework generation method of a heterogeneous system in the present invention. The response information includes a loop processing function. The main loop method of the heterogeneous system simulator framework includes:

[0023] Step S301, obtaining the registration order of the current submodule according to the bus registration table.

[0024] Step S302: Obtain an access count threshold, which is the number of submodule interfaces that can be accessed simultaneously within the main loop period.

[0025] Step S303, within a main loop period, cyclically calling the processing functions of the sub-modules according to the registration order of the sub-modules.

[0026] Step S304: Determine whether the bus access times of the current main loop are less than the access times threshold, if yes, generate access success information, if no, generate access failure information.

[0027] In another implementation of the main loop operation method of the heterogeneous system simulator framework of the present invention, step S303 also includes:

[0028] Step S3031: If a debug interrupt instruction is obtained, the operation of the main loop is interrupted.

[0029] A fourth aspect of the present invention provides a heterogeneous system simulator framework, wherein the simulator can call a parameter parser, in which a parameter list supported by the simulator and corresponding parameter processing functions are registered, and the heterogeneous system simulator framework can configure multiple submodules on a bus.

[0030] Multiple submodules, each of which includes a slave interface class. The multiple slave interface classes define corresponding response information of the submodule after receiving the bus access.

[0031] The simulator framework for heterogeneous systems includes:

[0032] An initialization module is configured as a parameter parser to parse the initialization parameters of the simulator according to the command line.

[0033] A submodule initialization function acquisition module is configured so that the simulator calls the initialization function of the submodule according to the initialization parameters.

[0034] A system resource configuration module is configured as a submodule initialization function to obtain submodule initialization configuration parameters, configure the simulator's system resources according to the simulator initialization configuration parameters, and configure the submodule's system resources according to the submodule initialization configuration parameters.

[0035] A bus has a registration function. Multiple slave interface classes are added to the bus device list by the registration function. The bus master interface is a bus handle.

[0036] In one implementation of the heterogeneous system simulator framework of the present invention, the multiple sub-modules include a riscv open source core sub-module, a RAM memory sub-module and a DEBUG log printing sub-module.

[0037] The following will further explain the generation method of the heterogeneous system simulator framework, the access method of the heterogeneous system simulator framework, the main loop operation method of the heterogeneous system simulator framework, and the characteristics, technical features, advantages and implementation methods of the heterogeneous system simulator framework in a clear and easy-to-understand manner, combined with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] Figure 1 It is a flowchart for illustrating a method for generating a heterogeneous system simulator framework in one embodiment of the present invention.

[0039] Figure 2 It is a flowchart for illustrating a method for generating a heterogeneous system simulator framework in another embodiment of the present invention.

[0040] Figure 3 It is a flowchart for illustrating a method for accessing a heterogeneous system simulator framework in one embodiment of the present invention.

[0041] Figure 4 It is a flowchart for illustrating a main loop operation method of a heterogeneous system simulator framework in one embodiment of the present invention.

[0042] Figure 5 It is a schematic diagram for illustrating the composition of a heterogeneous system simulator framework in one embodiment of the present invention.

[0043] Figure 6 It is a system schematic diagram for illustrating a simulator in one embodiment of the present invention.

[0044] Figure 7 It is a schematic diagram for explaining the operation flow of the simulator in another embodiment of the present invention. DETAILED DESCRIPTION

[0045] In order to have a clearer understanding of the technical features, purposes and effects of the invention, the specific embodiments of the present invention are now described with reference to the accompanying drawings. The same reference numerals in the drawings represent components with the same structure or similar structures but the same functions.

[0046] In this article, "schematic" means "serving as an example, instance or illustration", and any diagram or implementation described as "schematic" in this article should not be interpreted as a more preferred or more advantageous technical solution. In order to make the drawings concise, each figure only schematically shows the parts related to the exemplary embodiment, and they do not represent the actual structure and true proportion of the product.

[0047] The first aspect of the present invention provides a method for generating a heterogeneous system simulator framework, wherein the simulator can call a parameter parser, in which a parameter list supported by the simulator and a corresponding parameter processing function are registered, and the heterogeneous system simulator framework can configure multiple submodules on a bus.

[0048] Multiple submodules generate a slave interface class, which defines the corresponding response information of the submodule after receiving the bus access.

[0049] like Figure 1 As shown, the simulator framework generation method for heterogeneous systems includes:

[0050] Step S101, parsing initialization parameters.

[0051] In this step, the parameter parser parses the initialization parameters of the simulator according to the command line.

[0052] Step S102, obtaining the initialization function of the submodule.

[0053] In this step, the simulator calls the initialization function of the submodule according to the initialization parameters.

[0054] Step S103: configure system resources.

[0055] In this step, the submodule initialization function obtains the submodule initialization configuration parameters, configures the simulator's system resources according to the simulator initialization configuration parameters, and configures the submodule's system resources according to the submodule initialization configuration parameters.

[0056] Step S104, configuring the bus.

[0057] In this step, a bus is generated. The bus has a registration function. Multiple slave interface classes are added to the bus device list by the registration function.

[0058] Step S105: Generate a bus master interface.

[0059] In this step, a bus master interface is generated. The bus master interface is a bus handle.

[0060] like Figure 2 As shown, in one embodiment of the method for generating a heterogeneous system simulator framework of the present invention, before step S101, the following steps are further included:

[0061] Step S100, obtaining a startup command line.

[0062] In this step, a startup command line is obtained, which includes a simulator name and simulator parameters.

[0063] In another implementation of the method for generating a heterogeneous system simulator framework of the present invention, the submodule registration parameters include: a starting address of the submodule, a length of the submodule, and slave interface class information.

[0064] like Figure 3 As shown, the second aspect of the present invention provides a method for accessing a simulator framework of a heterogeneous system, including a simulator framework generated by the simulator framework generation method of the heterogeneous system. The method for accessing a simulator framework of a heterogeneous system includes:

[0065] Step S201, obtaining a bus registration table.

[0066] In this step, the access device accesses the bus through the bus master interface.

[0067] Step S202, determining the corresponding current submodule.

[0068] In this step, the bus searches the bus registration list for the current submodule corresponding to the access address according to the starting address and length of each submodule. If a submodule that meets the conditions is found, the access address is subtracted from the base address of the module and the access request is passed to the submodule. If not, a bus access warning message is issued.

[0069] like Figure 3 As shown, in one implementation of the method for accessing the heterogeneous system simulator framework of the present invention, step S202 includes:

[0070] Step S2021, calling the corresponding access request function through the bus handle.

[0071] In this step, the corresponding access request function is called through the bus handle. The access request function includes: passing the access target address parameter, the access type parameter, the access length parameter and the data pointer parameter.

[0072] Step S2022, determining the corresponding current submodule according to the bus handle.

[0073] In this step, it is determined whether the corresponding submodule can be obtained through the submodule registration parameters according to the access request function called by the bus handle and the current access address in the bus registration table. If so, the submodule is requested to be accessed. If not, a bus access warning message is issued.

[0074] like Figure 4 As shown, the third aspect of the present invention provides a main loop running method of a heterogeneous system simulator framework, including a simulator framework generated by the heterogeneous system simulator framework generation method of the present invention. The response information includes a loop processing function.

[0075] The main loop method of the heterogeneous system simulator framework includes:

[0076] Step S301, obtaining the registration order of the current submodule according to the bus registration table.

[0077] Step S302, obtaining a threshold of the number of visits.

[0078] In this step, an access count threshold is obtained, which is the number of submodule interfaces that can be accessed simultaneously within the main loop period.

[0079] Step S303, obtaining the access count of the current main loop.

[0080] In this step, within a main loop period, the processing functions of the sub-modules are cyclically called according to the registration order of the sub-modules.

[0081] Step S304: Determine the access count threshold.

[0082] In this step, it is determined whether the bus access times of the current main loop are less than the access times threshold, and if so, access success information is generated, and if not, access failure information is generated.

[0083] like Figure 4As shown, in another implementation of the main loop running method of the heterogeneous system simulator framework of the present invention, step S303 also includes:

[0084] Step S3031, interrupt the operation of the main loop.

[0085] In this step, if a debug interrupt instruction is obtained, the operation of the main loop is interrupted.

[0086] A fourth aspect of the present invention is as follows Figure 5 As shown, a heterogeneous system simulator framework is provided, and the simulator can call a parameter parser. The parameter parser registers the parameter list supported by the simulator and the corresponding parameter processing function. The heterogeneous system simulator framework can configure multiple sub-modules on a bus.

[0087] Multiple submodules generate a slave interface class, which defines the corresponding response information of the submodule after receiving the bus access.

[0088] The simulator framework of the heterogeneous system includes: a bus 10 , an initialization module 20 , a sub-module initialization function acquisition module 30 , a system resource configuration module 40 and a generation module 50 .

[0089] An initialization module 20 is configured as a parameter parser to parse the initialization parameters of the simulator according to the command line.

[0090] A submodule initialization function acquisition module 30 is configured so that the simulator calls the initialization function of the submodule according to the initialization parameters.

[0091] A system resource configuration module 40 is configured as a submodule initialization function to obtain submodule initialization configuration parameters, configure the simulator's system resources according to the simulator initialization configuration parameters, and configure the submodule's system resources according to the submodule initialization configuration parameters.

[0092] Bus 10 has a registration function. Multiple slave interface classes are added to the bus device list by the registration function. The bus master interface is a bus handle.

[0093] In one implementation of the heterogeneous system simulator framework of the present invention, the multiple sub-modules include a riscv open source core sub-module, a RAM memory sub-module and a DEBUG log printing sub-module.

[0094] In another embodiment of the present invention, a simulator framework for heterogeneous systems is provided, which is based on a bus that can connect all modules as the core, and the submodules can be integrated into the bus by replacing the memory access operation with the bus master interface, encapsulating the slave interface module for responding to the bus access, registering the slave module to the bus, etc. Various computing cores and peripheral devices of different architectures can be integrated together simply and quickly through this approach, which greatly simplifies the development of heterogeneous system simulators.

[0095] The entire simulator framework consists of the following parts:

[0096] a) Parameter parsing and module initialization

[0097] b) Simulator bus

[0098] c) Simulator loop control

[0099] d) Debug module of simulator

[0100] e) Simulator operation information control module

[0101] 1. Contents of Part A:

[0102] The simulator generated by this simulator framework will be started in command line mode, and the startup command is: simulator name + [simulator parameters]. The simulator parameters are optional. The framework first registers the parameter list supported by the simulator and the corresponding parameter processing function into the parameter parser. The supported parameter formats are -x (x is the name of the parameter) and -x=y (x is the parameter name, y is the value of the parameter). Then, the command line input is obtained from the system, and then the input parameters are parsed by the parser to obtain the configuration parameters required for the simulator initialization (such as the size of the simulator RAM, the instruction subset supported by riscv, etc.), and the initialization function of each sub-module is called to initialize the module (such as allocating RAM memory, initializing riscv core, etc.), and finally each module is registered on the bus.

[0103] 2. Contents of Part B:

[0104] like Figure 6 As shown, each submodule (riscv open source core, RAM, DEBUG log printing module, etc.) is connected together through a bus.

[0105] When the simulator is initialized, it is necessary to configure the length of data that can be obtained by a single bus access, the number of interfaces that can be accessed simultaneously in the same cycle, etc.

[0106] Before accessing the bus, the submodule needs to create a slave interface class. In the slave interface class, the submodule's response when receiving a bus access is defined, mainly including the operations that need to be triggered for bus reading and bus writing (such as reading RAM will return the content at the corresponding address of RAM, and writing UART will output characters to the console). A successful access will pass data through a pointer and return 0; a failed access will return a non-zero error code.

[0107] After creating the slave interface class, you can use the bus registration function to connect the submodule to the bus. The registration (i.e., connection) of the submodule requires the input of three parameters: the starting address of the submodule, the length of the submodule, and the call pointer of the slave interface class. The master interface of the bus is a unique bus handle. The module that wants to connect to the bus master interface must save the bus handle during initialization, and can initiate bus access through the handle when entering the main loop.

[0108] When a device accesses the bus through the main interface, the bus first searches the device's registration list for the module corresponding to the access address based on the starting address and length of each module. If a module that meets the conditions is found, the access address is subtracted from the base address of the module and the access request is passed to the submodule; if the corresponding module cannot be found, a bus access warning is issued and a corresponding non-zero error code is returned. The accessed submodule cannot access the bus in reverse from the slave interface class, and the bus access must be executed in the main loop.

[0109] A bus access requires calling the corresponding access request function through the bus handle, and passing four parameters: the access target address, access type, access length, and data pointer through the function.

[0110] 3. Contents of Part C:

[0111] The framework has a main loop. After completing the initialization operation of each module of the simulator, the simulator will enter the main loop, in which the loop processing function of each submodule will be called cyclically according to the registration order of the submodule. Each iteration of the main loop is equivalent to running a clock cycle in the hardware, which ensures the simulation accuracy of the simulator. The read and write interface of the bus can be called in the main loop. If the number of bus accesses in the current clock cycle does not exceed the allowed number of times (that is, the number of interfaces that can be accessed simultaneously in the same bus cycle), a zero value will be returned, indicating a successful access. Otherwise, it means that the access failed and needs to be tried again in the next iteration.

[0112] IV. Contents of Part D:

[0113] The framework has a simple debugging module. You can enter the debugging mode by pressing ctrl+C in the console. At this time, the debugging module will interrupt the operation of the main loop. In the debugging mode, you can enter debugging instructions in the console to read the data on the bus or modify the value of a certain address. You can also configure the debugger to detect the value of a certain address on the bus during the loop and interrupt the operation of the main loop according to the change of the value. These functions can basically meet the requirements of most applications.

[0114] V. Contents of Part E:

[0115] The framework comes with a running information control module, through which the command line can be used to configure the start and stop of running information. The control rules of running information can be specified using regular expressions. Each rule contains two parts, one is the name of the module, and the other is the type of information. The two parts of the rule are separated by ':'. Through the combination of multiple control rules, useful information can be filtered out from a large amount of running information and output to the console.

[0116] Advantages of the present invention:

[0117] 1) Strong interface versatility: Various modules such as CPU, GPU and other computing cores and UART, SDRAM and other peripheral devices can be connected to the bus.

[0118] 2) Simple interface: Generally, it only takes more than 100 lines of code to add a module to the simulator.

[0119] 3) High efficiency: The entire framework only needs to perform a small amount of processing when accessing the bus, which does not take up too much computing time.

[0120] 4) Approximate clock-level simulation accuracy: The entire simulator can achieve approximate clock-level simulation accuracy (the specific accuracy depends on the implementation of the sub-module), which is suitable for most research tasks.

[0121] 5) Fully functional: With parameter parsing module, debugging module and operation information control module, it is suitable for most simulator applications.

[0122] It should be understood that although this specification is described according to various implementation methods, not every implementation method contains only one independent technical solution. This narrative method of the specification is only for the sake of clarity. Those skilled in the art should regard the specification as a whole. The technical solutions in each embodiment can also be appropriately combined to form other implementation methods that can be understood by those skilled in the art.

[0123] The series of detailed descriptions listed above are only specific descriptions of feasible implementation methods of the present invention. They are not intended to limit the scope of protection of the present invention. Any equivalent implementation methods or changes that do not deviate from the technical spirit of the present invention should be included in the scope of protection of the present invention.

Claims

1. A method for generating a heterogeneous system simulator framework, characterized in that: The simulator can call a parameter parser; the parameter parser registers a parameter list supported by the simulator and a corresponding parameter processing function; the heterogeneous system simulator framework can configure multiple submodules on a bus; The plurality of submodules each include a slave interface class; The plurality of submodules defined in the slave interface class receive corresponding response information after receiving the bus access; The submodule registration parameters include: the starting address of the submodule, the length of the submodule and the slave interface class information; The simulator framework generation method of the heterogeneous system includes: Step S101, the parameter parser parses the initialization parameters of the simulator according to the command line; Step S102, the simulator calls the initialization function of the submodule according to the initialization parameters; Step S103, the submodule initialization function obtains submodule initialization configuration parameters; configures the system resources of the simulator according to the simulator initialization configuration parameters; configures the system resources of the submodule according to the submodule initialization configuration parameters; Step S104, generating a bus; the bus has a registration function; the multiple slave interface classes are added to the device list of the bus by the registration function; Step S105, generating a bus master interface; the bus master interface is a bus handle.

2. The generation method according to claim 1, characterized in that: Before step S101, the following steps are also included: Step S100, obtaining a startup command line; the startup command line includes a simulator name and simulator parameters.

3. The access method of the heterogeneous system simulator framework is characterized by: A simulator framework comprising the method for generating a heterogeneous system simulator framework according to any one of claims 1 to 2; The access method of the heterogeneous system simulator framework includes: Step S201, an access device accesses the bus through the bus master interface; In step S202, the bus searches the bus registration list for the current submodule corresponding to the access address according to the starting address and length of each submodule. If a submodule that meets the conditions is found, the base address of the module is subtracted from the access address, and the access request is passed to the submodule; if not, a bus access warning message is issued.

4. The access method according to claim 3, characterized in that: The step S202 includes: Step S2021, calling a corresponding access request function through the bus handle; the access request function includes: passing a target address parameter for access, a type parameter for access, a length parameter for access, and a pointer parameter for data; Step S2022, determine whether the corresponding sub-module can be obtained through the sub-module registration parameters according to the access request function called by the bus handle and the current access address in the bus registration table; if so, request to access the sub-module; if not, issue a bus access warning message.

5. The main loop operation method of the heterogeneous system simulator framework is characterized by: A simulator framework comprising the method for generating a heterogeneous system simulator framework according to any one of claims 1 to 2; The response information includes a loop processing function; The main loop method of the heterogeneous system simulator framework includes: Step S301, obtaining the registration order of the current submodule according to the bus registration table; Step S302, obtaining an access count threshold; the access count threshold is the number of submodule interfaces that can be accessed simultaneously within the period of the main loop; Step S303, within a main loop period, cyclically calling the processing function of the submodule according to the registration order of the submodule; Step S304: Determine whether the bus access times of the current main loop are less than the access times threshold, if so, generate access success information; if not, generate access failure information.

6. The main cycle operation method according to claim 5, characterized in that: The step S303 also includes: Step S3031: If a debug interrupt instruction is obtained, the execution of the main loop is interrupted.

7. Heterogeneous system simulator framework, characterized by: The simulator can call a parameter parser; the parameter parser registers a parameter list supported by the simulator and a corresponding parameter processing function; the heterogeneous system simulator framework can configure multiple submodules on a bus; The plurality of submodules each include a slave interface class; The plurality of submodules defined in the slave interface class receive corresponding response information after receiving the bus access; The submodule registration parameters include: the starting address of the submodule, the length of the submodule and the slave interface class information; The simulator framework of the heterogeneous system includes: An initialization module, configured so that the parameter parser parses the initialization parameters of the simulator according to the command line; a submodule initialization function acquisition module, configured so that the simulator calls the initialization function of the submodule according to the initialization parameters; A system resource configuration module, configured to obtain submodule initialization configuration parameters by the submodule initialization function; configure the system resources of the simulator according to the simulator initialization configuration parameters; configure the system resources of the submodule according to the submodule initialization configuration parameters; A bus having a registration function; the multiple slave interface classes will be added to the device list of the bus by the registration function; the bus master interface is a bus handle.

8. The heterogeneous system simulator framework according to claim 7, characterized in that: The multiple sub-modules include a riscv open source core sub-module, a RAM memory sub-module and a DEBUG log printing sub-module.

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