A fully controlled thyristor chip and design method thereof

Abstract

The present invention relates to a fully controlled thyristor chip and a design method thereof, characterized in that it comprises: a gate electrode and a plurality of cathode electrodes, wherein the gate electrode and the cathode electrode are isolated from each other, and each of the cathode electrode units is connected through an external conductive sheet, and the gate electrodes are directly connected through the same aluminum layer; the cathode electrode is arranged in a honeycomb shape, comprising a plurality of hexagonal structures that are arranged around the center of the chip at equal intervals and extend outward in a circular manner, and each of the hexagonal structures comprises a plurality of regular hexagonal cathode electrode units, and each of the cathode electrode units is evenly arranged on each side of the hexagonal structure, so that the center line of each cathode electrode unit forms a regular hexagonal structure. The present invention can be widely used in the field of device design.

Description

Technical Field

[0001] The invention relates to the field of electronic device design, and in particular to a fully-controlled thyristor chip and a design method thereof. Background Art

[0002] With the rapid development of UHV DC transmission technology in recent years, a closely connected AC / DC grid structure has been formed. IGCT has the advantages of low conduction loss, high single-tube power capacity, reliable short-circuit failure mode, easy series connection and heat dissipation, making it one of the preferred devices for grid applications. In order to meet better application needs, IGCT devices will further improve their current capacity by optimizing the cathode graphic design of the device.

[0003] Cathode graphic design is a basic link in the design of various electronic devices, and is particularly important for fully controlled thyristors. The cathode graphic of a fully controlled thyristor complements the gate graphic and directly affects the dynamic parameters of the device, so the graphic design of a fully controlled thyristor must be cautious. Generally, a rough graphic is designed after balancing the various parameters of the device, and the final graphic is determined by combining the designer's aesthetic style and the graphic characteristics of the company. The designed graphic is then transferred to the chip surface through a photolithography process using a mask as a carrier, and the corresponding gate and cathode are divided.

[0004] For fully controlled power semiconductors such as IGCT and GTO, the cathode is usually formed by many small patterns and surrounded by an integrally connected gate region. This is a typical structural design that fully meets the static and dynamic performance requirements of the device. There are many different gate electrode designs and specific arrangements of cathode patterns.

[0005] 1. There are three types according to the gate electrode lead position:

[0006] ① Center gate type: An area is designed at the center of the chip cathode pattern to lead out the gate electrode.

[0007] ② Ring gate type: A circular ring area is designed in the middle of the cathode pattern of the chip to lead out the gate electrode.

[0008] ③ Edge gate type: A circular ring area is designed at the edge of the chip cathode pattern to lead out the gate electrode.

[0009] The characteristics of the three types of cathode patterns classified by gate electrode position are compared as shown in Table 1 below.

[0010] Table 1 Cathode pattern characteristics classified by gate electrode position

[0011]

[0012]

[0013] 2. Existing designs are divided into three categories according to the cathode pattern arrangement:

[0014] ①Uniform arrangement: including uniform rectangular arrangement and uniform circular arrangement

[0015] Uniform rectangular arrangement: the slivers are of the same size, in the same direction, and arranged neatly in rows (such as Figure 1a As shown in Figure 1.1, the circular chip surface is divided into several rectangles. The graphic structure is simple and the chip area utilization rate is high. However, the intersection with the circular curve cannot be fully utilized, especially the ring gate structure is not suitable. Therefore, it is only used for low-end current capacity devices in the early stage of the development of fully controlled thyristors.

[0016] Uniform circumferential arrangement: the slivers are of the same size, radially oriented, and arranged in concentric circles (such as Figure 1b As shown in the figure, the overall pattern is uniform, the structure is simple, and the distribution is regular, so it is widely used. However, the slivers are distributed radially, and the circumferences of the concentric circles are not equal. The slivers cannot correspond one to one, and as the radius of the circle increases, the radial angle margin continues to increase. The gap between the slivers is approximately trapezoidal, and the shape and area of ​​the gap between the slivers in each circle are different, so the chip area utilization rate is not high.

[0017] ②Compound layout by partition:

[0018] The cathode of the chip is divided into 16 sectors with the center of the circle as the axis. The comb bars in the sectors are arranged in a rectangular shape, and the comb bars between the sectors are still arranged in a circular shape (such as Figure 2 As shown in the figure, the overall pattern is relatively regular, and the gates around the comb strips in the partitions are uniform. However, each partition has an irregular area at the junction of the rectangle and the arc, which reduces the utilization rate of the chip area. The waste is greater as the pattern radius increases, and it is not suitable for large-diameter fully controlled devices.

[0019] ③ Sector arc arrangement: Divide the circle into equal sectors. The comb strips inside the sectors are in the same direction and parallel to the center line of the sectors. The comb strips of the same circle are arranged along the arc. A single radial comb strip is inserted between the sectors according to the size of the area (such as Figure 3 As shown in the figure). In this way, the chip area utilization rate is high, the comb strips are arranged neatly, the gate shapes between the comb strips in the sector are completely consistent, and a gate current fast channel is formed between the sectors, but some adjacent comb strips in the sector area are close to each other. Summary of the invention

[0020] In view of the above problems, the purpose of the present invention is to provide a fully-controlled thyristor chip and a design method thereof, which adopts a cathode-type regular hexagonal pattern honeycomb arrangement and is suitable for fully-controlled power semiconductor devices such as IGCT or GTO of various specifications and types.

[0021] To achieve the above object, the present invention adopts the following technical solutions:

[0022] The first aspect of the present invention is to provide a fully controlled thyristor chip, which includes: a gate electrode and a plurality of cathode electrodes, the gate electrode and the cathode electrode are isolated from each other, and each of the cathode electrode units is connected by an external conductive sheet, and the gate electrodes are directly connected through the same aluminum layer; the cathode electrodes are arranged in a honeycomb shape, which includes a plurality of hexagonal structures that are arranged around the center of the chip at equal intervals and extend outward in a cycle, and each of the hexagonal structures includes a plurality of regular hexagonal cathode electrode units, and each of the cathode electrode units is evenly arranged on each side of the hexagonal structure, so that the center line of each cathode electrode unit forms a regular hexagonal structure.

[0023] Furthermore, the side length of each cathode electrode unit is in the range of 0.2 to 3 mm.

[0024] Furthermore, the side length of the cathode electrode unit within the range of 3 to 8 circles close to the gate lead-out electrode region is in the range of 0.5 to 3 mm; the side length of the other cathode electrode units far from the gate region is in the range of 0.2 to 2.7 mm.

[0025] Furthermore, the side length spacing between two adjacent cathode electrode units ranges from 0.2 to 0.4 mm.

[0026] A second aspect of the present invention is to provide a design method for a fully controlled thyristor, which comprises the following steps:

[0027] 1) The chip cathode of the fully controlled thyristor is designed so that the chip cathode is arranged in a honeycomb shape, including a plurality of quasi-hexagonal structures that are arranged around the center of the chip at equal intervals and extend outward in a circular manner, and each of the quasi-hexagonal structures includes a plurality of cathode electrode units in the form of regular hexagons, and the cathode electrode units are evenly arranged on each side of the quasi-hexagonal structure, so that the center line of each cathode electrode unit forms a regular hexagonal structure;

[0028] 2) Design the gate electrode arrangement of the fully controlled thyristor;

[0029] 3) Based on the cathode and gate electrode arrangements of the fully-controlled thyristor determined in step 1) and step 2), a honeycomb-arranged photolithography mask is designed, and the designed cathode pattern is transferred to the chip surface through photolithography processing, and other processing processes are matched to complete the production of the entire fully-controlled thyristor chip.

[0030] Furthermore, in the step 2), the gate electrode arrangement adopts a central gate, a ring gate or an edge gate.

[0031] Furthermore, in the step 2), when the diameter of the fully-controlled thyristor chip is ≤3 inches, the gate electrode adopts a central gate arrangement; when the diameter of the fully-controlled thyristor chip is >3 inches, the gate electrode adopts an intermediate ring gate or a central gate.

[0032] Since the present invention adopts the above technical scheme, it has the following advantages: 1. The cathode regular hexagonal pattern honeycomb arrangement method proposed in the present invention has a larger area than other polygonal cathode arrangement methods, which is conducive to large-area arrangement and forms a regular honeycomb structure. 2. The cathode graphic arrangement method proposed in the present invention is honeycomb-shaped because the six sides are arranged in six regular hexagons at equal intervals. The overall cathode graphic is regular and the gate graphic remains consistent, which improves the uniformity of each cathode opening / closing. 3. In the present invention, the cathode graphic is arranged to expand outward in a circle from the center, so it is sparse away from the gate area, which can effectively balance the cathode opening / closing difference caused by the distance from the gate electrode. 4. The cathode graphic arrangement method proposed in the present invention has a large cathode area ratio, which improves the device's on-state current capacity. Therefore, the present invention can be widely used in the field of electronic device design. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Figure 1a It is a schematic diagram of the existing uniform rectangular arrangement;

[0034] Figure 1b It is a schematic diagram of the existing uniform circular arrangement;

[0035] Figure 2 It is a schematic diagram of the existing partition composite arrangement;

[0036] Figure 3 It is a schematic diagram of the existing sector arc arrangement;

[0037] Figure 4 This is a schematic diagram of the honeycomb arrangement of a regular hexagonal pattern of the present invention;

[0038] Figure 5 It is a schematic diagram of the honeycomb arrangement of the present invention;

[0039] Figure 6 This is an application example of the center gate of the present invention;

[0040] Figure 7 This is an application example of the edge gate of the present invention. DETAILED DESCRIPTION

[0041] The present invention is described in detail below with reference to the accompanying drawings and embodiments.

[0042] like Figure 4 , Figure 5As shown, based on the application requirements of the device for resisting commutation failure, the symmetrical SGCT device meets the requirements of DC system operation. The shutdown capability requirement is low, but the required on-state current is high. Increasing the on-state current can be optimized by adjusting the gate cathode area. The present invention provides a fully controlled thyristor chip, which includes a gate electrode and a plurality of cathode electrodes, wherein the cathode electrode is arranged in a honeycomb shape, including a plurality of hexagonal structures that are arranged around the center of the chip at equal intervals and extend outward in a circular manner, and each of the hexagonal structures includes a plurality of cathode electrode units in the form of regular hexagons, and each cathode electrode unit is evenly arranged on each side of the hexagonal structure, so that the center line of each cathode electrode unit forms a regular hexagonal structure. Among them, the gate electrode and the cathode electrode are isolated from each other, and each cathode electrode unit is connected by an external conductive sheet, and the gate electrodes are directly connected through the same aluminum layer.

[0043] As a preferred embodiment, the side length of each cathode electrode unit ranges from 0.2 to 3 mm.

[0044] As a preferred embodiment, in the cathode electrode, the side length of the cathode electrode unit within 3 to 8 circles close to the gate lead electrode region ranges from 0.5 to 3 mm; the side length of other cathode electrode units far from the gate region ranges from 0.2 to 2.7 mm.

[0045] As a preferred embodiment, the side length interval between two adjacent regular hexagonal cathode electrode units ranges from 0.2 to 0.4 mm.

[0046] The present invention also provides a design method for a fully controlled thyristor chip, which comprises the following steps:

[0047] 1) If Figure 4 As shown, the cathode electrode arrangement of the fully controlled thyristor is designed so that the cathode electrodes are arranged in a honeycomb shape, and are arranged at equal distances around the center of a circle. With each regular hexagon as the center, six sides are evenly spaced to form six regular hexagons that are arranged in a cycle and expand outwards in a honeycomb shape. The overall cathode pattern is regular and the gate pattern is consistent.

[0048] 2) Design the gate electrode arrangement of the fully controlled thyristor;

[0049] 3) Based on the cathode and gate electrode arrangements of the fully-controlled thyristor determined in step 1) and step 2), a honeycomb-arranged photolithography mask is designed, and the designed cathode pattern is transferred to the chip surface through photolithography processing, and other processing processes are matched to complete the production of the entire fully-controlled thyristor chip.

[0050] In the above step 2), the gate electrode arrangement can be a center gate, a ring gate or an edge gate. When the diameter of the fully controlled thyristor chip is ≤3 inches, the center gate arrangement is adopted; when the diameter of the fully controlled thyristor chip is greater than 3 inches, the middle ring gate or edge gate arrangement is usually adopted according to the company's design system.

[0051] like Figure 1a and Figure 1b , Figure 2 to Figure 5 The following are schematic diagrams of uniform rectangular arrangement, uniform circular arrangement, compound partition arrangement, sector circular arrangement and honeycomb arrangement proposed in the present invention. In the honeycomb arrangement proposed in the present invention, the side length of each cathode electrode unit is 1 mm and the area is 2 mm. 2 .

[0052] Table 2 Cathode pattern ratio

[0053] Photoresist type Cathode pattern quantity Cathode effective area The proportion Fan-shaped arc arrangement 7168 5448 41％ Honeycomb layout 3108 8049 62％

[0054] From the above table data, it can be concluded that the side length of the hexagon is 1 mm, the cathode image area of ​​the hexagonal honeycomb arrangement occupies a larger total area than the fan-shaped arc arrangement, and the current-carrying capacity of the device is stronger.

[0055] like Figure 6 and Figure 7 As shown, the cathode pattern honeycomb arrangement method proposed in the present invention is applicable to various fully controlled semiconductor devices, such as IGCT, GTO and composite devices of reverse conducting structure. It is applicable to both the cathode pattern design of the center gate and the cathode pattern design of the edge gate. Specifically, when the cathode pattern design of the center gate is adopted, the gate position is designed according to the chip diameter, 30 to 60 mm for the center gate and 60 mm to 150 mm for the edge gate.

[0056] The above embodiments are only used to illustrate the present invention, wherein the structure, connection mode and manufacturing process of each component may be changed. Any equivalent transformations and improvements based on the technical solution of the present invention should not be excluded from the protection scope of the present invention.

Claims

1. A fully controlled thyristor chip, characterized in that: include: A gate electrode and a plurality of cathode electrodes, wherein the gate electrode and the cathode electrode are isolated from each other, and each cathode electrode unit is connected through an external conductive sheet, and the gate electrodes are directly connected through the same aluminum layer; The cathode electrode is arranged in a honeycomb shape, including a plurality of quasi-hexagonal structures that are arranged cyclically and extended outward at equal intervals around the center of the chip, and each of the quasi-hexagonal structures includes a plurality of cathode electrode units in the form of regular hexagons, and the cathode electrode units are evenly arranged on each side of the quasi-hexagonal structure, so that the center line of each cathode electrode unit forms a regular hexagonal structure; The side length of each cathode electrode unit ranges from 0.2 to 3 mm; The side length of the cathode electrode unit within the range of 3 to 8 circles close to the gate lead-out electrode region is in the range of 0.5 to 3 mm; the side length of the other cathode electrode units far from the gate region is in the range of 0.2 to 2.7 mm.

2. A fully controlled thyristor chip as claimed in claim 1, characterized in that: The side length spacing between two adjacent cathode electrode units ranges from 0.2 to 0.4 mm.

3. A design method for a fully controlled thyristor chip, characterized in that: The following steps are involved: 1) The chip cathode of the fully controlled thyristor is designed so that the chip cathode is arranged in a honeycomb shape, including a plurality of quasi-hexagonal structures that are arranged around the center of the chip at equal intervals and extend outward in a circular manner, and each of the quasi-hexagonal structures includes a plurality of cathode electrode units in the form of regular hexagons, and the cathode electrode units are evenly arranged on each side of the quasi-hexagonal structure, so that the center line of each cathode electrode unit forms a regular hexagonal structure; 2) Design the gate electrode arrangement of the fully controlled thyristor; 3) Based on the cathode and gate electrode arrangements of the fully-controlled thyristor determined in step 1) and step 2), a honeycomb-arranged photolithography mask is designed, and the designed cathode pattern is transferred to the chip surface through photolithography processing, and other processing techniques are matched to complete the production of the entire fully-controlled thyristor chip.

4. A design method for a fully controlled thyristor chip as claimed in claim 3, characterized in that: In the step 2), the gate electrode arrangement adopts a central gate, a ring gate or an edge gate.

5. A design method for a fully controlled thyristor chip as claimed in claim 4, characterized in that: In the step 2), when the diameter of the fully-controlled thyristor chip is ≤ 3 inches, the gate electrode adopts a central gate arrangement mode; When the diameter of the fully-controlled thyristor chip is greater than 3 inches, the gate electrode adopts an intermediate ring gate or a center gate.

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