System on chip and electronic device including the same

Abstract

A system on chip (SoC) includes at least a first core and a second core, a first power gating switch and a second power gating switch, and a first power switch. The first power gating switch is arranged between the first core and a first power rail receiving a first voltage and is selectively turned on in response to a first power gating signal. The second power gating switch is arranged between the second core and a second power rail receiving a second voltage and is selectively turned on in response to a second power gating signal. The first power switch is arranged between the first power rail and the second power rail and is selectively turned on in response to a first power control signal, thereby connecting the first power gating switch or the second power gating switch to both the first power rail and the second power rail.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of Korean Patent Application No. 10-2019-0094022 filed on August 1, 2019, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The present disclosure relates to integrated circuits (ICs), and more particularly, to systems on chips (SoCs) and electronic devices including SoCs. Background Art

[0004] In recent years, in the field of computing, the performance of multimedia requiring multitasking and high-speed computing has become important, and thus multi-core processors including multiple processing cores in one processor have been developed. Meanwhile, a system on a chip (SoC) refers to a technology that integrates various functional blocks such as a central processing unit (CPU), memory, interface, digital signal processing circuit, and analog signal processing circuit into one semiconductor integrated circuit to implement a computing system or other electronic system, or refers to an integrated circuit (IC) produced based on this technology. With the recent improvement in the performance of computing systems or electronic systems, SoCs including multiple processing cores have been developed, and various methods of optimizing power management and the performance of multiple cores included in the SoC have been studied. Summary of the Invention

[0005] One aspect is to provide a system on chip (SoC) for improving power management efficiency of multiple cores and an electronic device including the SoC.

[0006] According to one aspect of an embodiment, a system on chip (SoC) is provided, comprising: a plurality of cores, including at least a first core and a second core; a first power gate switch, arranged between a first power rail transmitting a first voltage and the first core, and selectively turned on in response to a first power gate signal; and a second power gate switch, arranged between a second power rail transmitting a second voltage and the second core, and selectively turned on in response to a first power control signal, such that the first power gate switch or the second power gate switch is connected to both the first power rail and the second power rail.

[0007] According to another aspect of the embodiment, there is provided an electronic device, including: a first voltage regulator configured to provide a first voltage to a first power rail; a second voltage regulator configured to provide a second voltage to a second power rail; a plurality of cores, including at least a first core and a second core; a first power gate switch arranged between the first power rail and the first core and selectively turned on in response to a first power gate signal; a second power gate switch arranged between the second power rail and the second core and selectively turned on in response to the second power gate signal; and a power switch arranged between the first power rail and the second power rail and selectively turned on in response to the first power control signal, so that the first power gate switch or the second power gate switch is connected to both the first power rail and the second power rail.

[0008] According to another aspect of the embodiment, there is provided an electronic device including: a first intellectual property (IP); a second IP; a first voltage regulator connected to the first IP via a first power rail and configured to provide a first voltage to the first IP; a second voltage regulator connected to the second IP via a second power rail and configured to provide a second voltage to the second IP; and a power switch arranged between the first power rail and the second power rail and driven according to a power control signal, wherein when the power control signal is enabled, the power switch is turned on, thereby connecting the first IP or the second IP to both the first power rail and the second power rail. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The embodiments will be more clearly understood through the following detailed description taken in conjunction with the accompanying drawings, in which:

[0010] Figure 1 is a block diagram of an electronic device according to an embodiment;

[0011] Figure 2 is a table illustrating an example of operations of the first power gating switch, the second power gating switch, and the first power switch according to operating states of the first core and the second core according to an embodiment;

[0012] Figure 3 is a layout of a multi-core processor including a first core and a second core according to an embodiment;

[0013] Figure 4 is a block diagram of an electronic device according to an embodiment;

[0014] Figure 5 is a flowchart of a method of operating a system on chip (SoC) according to an embodiment;

[0015] Figure 6 is a detailed flow chart of an operating method of a SoC according to an embodiment;

[0016] Figure 7 is a flowchart of operations between a SoC and a power management integrated circuit (PMIC) according to an embodiment;

[0017] Figure 8 An example of an electronic device including a first core and a second core according to an embodiment is shown;

[0018] Figure 9 An example of a SoC including a first core and a second core according to an embodiment is shown;

[0019] Figure 10 An example of a SoC including a first core, a second core, a third core, and a fourth core according to an embodiment is shown;

[0020] Figure 11 is a table showing an example of operations of the first power switch, the second power switch, the third power switch, and the fourth power switch according to the operating states of the first core, the second core, the third core, and the fourth core;

[0021] Figure 12 is a layout of a multi-core processor including a first core, a second core, a third core, and a fourth core according to an embodiment;

[0022] Figure 13 is a detailed flow chart of an operating method of a SoC according to an embodiment;

[0023] Figure 14 An example of a SoC including a first core, a second core, a third core, and a fourth core according to another embodiment is shown;

[0024] Figure 15 is a block diagram of an electronic device according to an embodiment;

[0025] Figure 16 is a block diagram of an electronic device according to an embodiment; and

[0026] Figure 17 is a block diagram of an electronic device according to an embodiment. DETAILED DESCRIPTION

[0027] Hereinafter, embodiments will be described in detail with reference to the accompanying drawings.

[0028] Figure 1 is a block diagram of an electronic device according to an embodiment.

[0029] refer to Figure 1, the electronic device 10 may include a multi-core processor 110 and a power management integrated circuit (PMIC) 200. The multi-core processor 110 may include a first core (core 1) 110a and a second core (core 2) 110b, and the PMIC 200 may include a first voltage regulator (VR1) 210a and a second voltage regulator (VR2) 210b. Depending on the embodiment, a "core" may be referred to as a processing core, a core processor, a processor, or a central processing unit (CPU).

[0030] A related art PMIC that does not support per-core dynamic voltage management may include a single voltage regulator, and this single voltage regulator may have to provide the maximum current required by the multiple cores included in a multi-core processor. However, since the multiple cores included in a multi-core processor can operate independently according to task scheduling, one core may often not execute a task while another core executes a task based on the characteristics of the application. In order to reduce the power consumption of the cores that are not executing tasks, separate voltages can be provided to the multiple cores. In other words, multiple voltage regulators can be provided.

[0031] According to an embodiment, the PMIC 200 may support per-core dynamic voltage management by including VR1 210a and VR2 210b corresponding to core 1 110a and core 2 110b, respectively. Furthermore, the electronic device 10 may support dynamic frequency management by using a phase-locked loop (PLL) or the like in the multi-core processor 110. With this configuration, the electronic device 10 may implement per-core dynamic voltage frequency scaling (DVFS) through dynamic voltage management and dynamic frequency management.

[0032] Specifically, VR1 210a may generate a first voltage V1 and provide the generated first voltage V1 to core 1 110a via a first power rail PR1. The voltage level of first voltage V1 may vary depending on the operating frequency, operating voltage, or workload of core 1 110a. For example, when core 1 110a performs high-performance or high-speed operations, the operating frequency of core 1 110a may be increased, thereby increasing the voltage level of first voltage V1 provided to core 1 110a. As another example, when core 1 110a performs low-performance or low-speed operations, the operating frequency of core 1 110a may be decreased, thereby decreasing the voltage level of first voltage V1 provided to core 1 110a, thereby reducing power consumption of core 1 110a.

[0033] Similarly, VR2 210b can generate a second voltage V2 and provide the generated second voltage V2 to core 2 110b via the second power rail PR2. Here, the voltage level of second voltage V2 can vary depending on the operating frequency, operating voltage, or workload of core 2 110b. For example, when core 2 110b performs high-performance or high-speed operations, the operating frequency of core 2 110b can be increased, and thus the voltage level of second voltage V2 provided to core 2 110b can be increased. As another example, when core 2 110b performs low-performance or low-speed operations, the operating frequency of core 2 110b can be reduced, and thus the voltage level of second voltage V2 provided to core 2 110b can be reduced, thereby reducing the power consumption of core 2 110b.

[0034] The multi-core processor 110 may further include a first power gating switch SW1 and a second power gating switch SW2. The first power gating switch SW1 may be arranged between the first power rail PR1 and the core 1 110a and may be selectively turned on in response to a first power gating signal S1G. The first power rail PR1 and the core 1 110a may be selectively connected to each other via the first power gating switch SW1. The second power gating switch SW2 may be arranged between the second power rail PR2 and the core 2 110b and may be selectively turned on in response to a second power gating signal S2G. The second power rail PR2 and the core 2 110b may be selectively connected to each other via the second power gating switch SW2.

[0035] The multi-core processor 110 may further include a first power switch SW12. The first power switch SW12 may be disposed between the first power rail PR1 and the second power rail PR2 and may selectively connect the first power rail PR1 to the second power rail PR2 in response to a first power control signal S12G. Through the first power switch SW12, the first power gate switch SW1 or the second power gate switch SW2 may be connected to both the first power rail PR1 and the second power rail PR2. Hereinafter, reference will be made to Figure 2 The operations of the first and second power gate control switches SW1 and SW2 and the first power switch SW12 will be described.

[0036] Figure 2 is a diagram showing the Figure 1 Table 20 shows an example of the operation of the first power gate switch SW1 and the second power gate switch SW2 and the first power switch SW12 of the operating states of the core 1 110a and the core 2 110b.

[0037] Reference together Figure 1 and Figure 2The operating state of core 1 110a may include an active state and an inactive state, and the operating state of core 2 110b may include an active state and an idle state. For example, one of core 1 110a and core 2 110b may stop executing a task and enter a standby mode until the other completes executing a task. In this case, the core that is not processing an operation and is in standby mode may be referred to as an idle core, while the core that is executing a task may be referred to as an active core.

[0038] The power gate switches connected to the active cores of core 1 110a and core 2 110b may be turned on, so that the active cores can normally receive power. Specifically, when core 1 110a is in an active state, the first power gate switch SW1 may be turned on, and the first voltage V1 may be supplied from VR1 210a to core 1 110a. Similarly, when core 2 110b is in an active state, the second power gate switch SW2 may be turned on, and the second voltage V2 may be supplied from VR2 210b to core 2 110b.

[0039] Conversely, the power gating switches of the idle cores connected to core 1 110a and core 2 110b may be turned off, so the idle cores may be power-gated to reduce the power consumption of the idle cores. Specifically, when core 1 110a is in an idle state, the first power gating switch SW1 may be turned off, and the first voltage V1 may not be supplied from VR1 210a to core 1 110a. Similarly, when core 2 110b is in an idle state, the second power gating switch SW2 may be turned off, and the second voltage V2 may not be supplied from VR2 210b to core 2 110b.

[0040] When both core 1 110a and core 2 110b are in an active state or an idle state, the first power switch SW12 can be turned off. In other words, when core 1 110a and core 2 110b are in the same state, the first power switch SW12 can be turned off. When only one of core 1 110a and core 2 110b is in an active state, the first power switch SW12 can be selectively turned on based on the operating voltage, operating frequency, or workload of the active core. For example, when only core 1 110a is in an active state and the operating frequency of core 1 110a is higher than a reference frequency, the first power switch SW12 can be turned on. Therefore, both VR1 210a and VR2 210b can be electrically connected to core 1 110a and can provide a current greater than the current capacity of VR1 210a to core 1 110a. As another example, when only core 2 110b is active and the operating frequency of core 2 110b is higher than the reference frequency, the first power switch SW12 may be turned on. Therefore, both VR1 210a and VR2 210b may be electrically connected to core 2 110b and may provide a current greater than the current capacity of VR2 210b to core 2 110b.

[0041] In this configuration, to support per-core dynamic voltage management, one voltage regulator can be divided into VR1 210a and VR2 210b. The current capacity of one voltage regulator included in a prior art PMIC that does not support per-core dynamic voltage management can correspond to the total maximum current consumption of core 1 110a and core 2 110b, and can be, for example, 8A. The current capacity of each of VR1 210a and VR2 210b included in the PMIC 200 supporting per-core dynamic voltage management can be determined based on the current consumption of each of core 1 110a and core 2 110b. Here, the maximum current consumption of each of core 1 110a and core 2 110b can be greater than half the total maximum current consumption of core 1 110a and core 2 110b (e.g., 8A). When the multi-core processor 110 includes N cores, the maximum current consumption of each core can be greater than 1 / N of the total maximum current consumption of the N cores (where N is a natural number equal to or greater than 2).

[0042] When the maximum current consumption of each of core1 110a and core2 110b is 6 A and each of VR1 210a and VR2 210b is implemented to have a current capacity of 6 A, the total current capacity of VR1 210a and VR2 210b may be 12 A. Here, the total current capacity of VR1 210a and VR2 210b may be greater than the current capacity of a single voltage regulator of the related art (i.e., 8 A), and thus the area of ​​PMIC 200 may be increased. Furthermore, when the total current capacity is increased, the number of passive devices such as inductors or capacitors may be increased, or the value of each passive device such as inductance or capacitance may be increased.

[0043] However, according to an embodiment, since the multi-core processor 110 includes the first power switch SW12, the current capacity of each of VR1 210a and VR2 210b can correspond to half of the total maximum current consumption of core 1 110a and core 2 110b. For example, the current capacity of each of VR1 210a and VR2 210b can be 4A. Therefore, the total current capacity of VR1 210a and VR2 210b can be 8A, which is the same as the current capacity of a previous single voltage regulator. Therefore, while supporting per-core dynamic voltage management, the area of ​​the PMIC 200 can be maintained. In addition, the number of passive components such as inductors and capacitors can be increased, and the value of each passive component, namely the inductor or capacitor, can be increased.

[0044] Figure 3 3 is a layout 30 of a multi-core processor including Core 1 and Core 2 according to an embodiment.

[0045] refer to Figure 3 , the layout 30 of the multi-core processor may correspond to e.g. Figure 1 The layout of the multi-core processor 110 is shown in FIG. The layout 30 of the multi-core processor may include a first region R1, a second region R2, and a third region R3 adjacent to each other in the Y direction. Core 1 may be arranged in the first region R1, and core 2 may be arranged in the second region R2. Each of the first region R1 and the second region R2 may have a specific area extending in the X direction and the Y direction. These regions may be of the same size or of different sizes. The first power switch SW12 may be arranged in the third region R3 between the first region R1 and the second region R2.

[0046] Figure 4 is a block diagram of an electronic device according to an embodiment.

[0047] refer to Figure 4, the electronic device 10′ may include a system on chip (SoC) 100 and a PMIC 200. The SoC 100 may include core 1 110a and core 2 110b, first and second power gate switches SW1 and SW2, a first power switch SW12, and control logic 120. Figure 4 The PMIC 200 is shown as being implemented outside the SoC 100. However, the embodiment is not limited thereto, and in some embodiments, the PMIC 200 may be included in / on the SoC 100. The PMIC 200 may correspond to Figure 1 The PMIC 200, and the electronic device 10' may be Figure 1 Modified example of the electronic device 10. Figures 1 to 3 The aspects described in detail can be applied to Figure 4 The present invention relates to the embodiments shown in FIG, and for the sake of brevity, repeated description of similar elements will not be given.

[0048] The control logic 120 may determine the operating status of core 1 110a and core 2 110b and generate a first power gating signal S1G and a second power gating signal S2G based on the determined operating status. Furthermore, the control logic 120 may monitor the operating frequency of core 1 110a and core 2 110b. The control logic 120 may generate a first power control signal S12G based on the operating status and operating frequency of core 1 110a and core 2 110b.

[0049] The control logic 120 may generate a first voltage control signal VCS1 and a second voltage control signal VCS2 based on the operating state and operating frequency of core 1 110a and core 2 110b. The control logic 120 may provide the generated first voltage control signal VCS1 and second voltage control signal VCS2 to VR1 210a and VR2 210b, respectively. VR1 210a may adjust the voltage level of first voltage V1 based on the first voltage control signal VCS1. VR2 210b may adjust the voltage level of second voltage V2 based on the second voltage control signal VCS2.

[0050] According to some embodiments, when the first power control signal S12G is enabled, that is, when the first power switch SW12 is turned on, the control logic 120 can generate the first voltage control signal VCS1 and the second voltage control signal VCS2 such that the first voltage V1 and the second voltage V2 are identical to each other. Therefore, VR1 210a and VR2 210b can generate the first voltage V1 and the second voltage V2, respectively, and the first voltage V1 and the second voltage V2 have the same voltage level.

[0051] According to an embodiment, SoC 100 may be implemented as a single chip including core 1 110a and core 2 110b, first and second power gate switches SW1 and SW2, first power switch SW12, and control logic 120. However, embodiments are not limited thereto. According to some embodiments, core 1 110a and core 2 110b, first and second power gate switches SW1 and SW2, and first power switch SW12 may be implemented on a first chip, and control logic 120 may be implemented on a second chip. PMIC 200, including VR1 210a and VR2 210b, may be implemented on a different chip from SoC 100. According to an embodiment, each of PMIC 200 and SoC 100 may be implemented on a separate chip and may be included in a single package, such as a system-in-package (SIP).

[0052] Figure 5 is a flowchart of an operating method of a SoC according to an embodiment.

[0053] refer to Figure 5 The operating method of the SoC according to the embodiment may be an operating method of a multi-core processor for per-core dynamic voltage management, and may, for example, include Figure 4 Hereinafter, reference will be made to the sequential operations performed on the SoC 100. Figure 4 and Figure 5 Describe the operation method of the SoC.

[0054] In operation S510, the control logic 120 may determine the operating state of core 1 110a and core 2 110b. For example, the control logic 120 may include scheduler logic configured to schedule tasks for core 1 110a and core 2 110b, and may determine the operating state of core 1 110a and core 2 100b based on the scheduled tasks of core 1 110a and core 2 100b. However, embodiments are not limited thereto. The control logic 120 may receive a task schedule for core 1 110a and core 2 110b from outside the SoC, and may determine the operating state of core 1 110a and core 2 110b based on the received task schedule. For example, in some embodiments, the control logic 120 may receive a task schedule for core 1 110a and core 2 110b from an external scheduler logic.

[0055] In operation S530, the control logic 120 may generate a first power gating signal S1G and a second power gating signal S2G according to the operating states of the core 1 110a and the core 2 110b. For example, the control logic 120 may generate the first power gating signal S1G and the second power gating signal S2G according to the operating states of the core 1 110a and the core 2 110b to drive the first power gating switch SW1 and the second power gating switch SW2, as shown in FIG. Figure 2 As shown in Table 20.

[0056] In operation S550, the control logic 120 may generate a first power control signal S12G based on the operating frequency of the active cores in the core 1 110a and the core 2 110b. However, the embodiment is not limited thereto. The control logic 120 may generate the first power control signal S12G based on the operating voltage or load of the active core. Here, Figure 2 As shown in FIG, when both core 1 110a and core 2 110b are in an active state or an idle state, the control logic 120 may disable the first power control signal S12G.

[0057] In operation S570, the control logic 120 may generate a voltage control signal based on the operating frequency of the active cores in core 1 110a and core 2 110b. However, embodiments are not limited thereto. The control logic 120 may generate the voltage control signal based on the operating voltage or workload of the active core. For example, in some embodiments, the voltage control signal may include a first voltage control signal VCS1 and a second voltage control signal VCS2. Depending on the embodiment, operation S550 and operation S570 may be performed substantially simultaneously. According to another embodiment, the order of operation S550 and operation S570 may be changed, i.e., operation S570 may be performed before operation S550.

[0058] Figure 6 is a detailed flowchart of an operating method of a SoC according to an embodiment.

[0059] refer to Figure 6 The operating method of the SoC according to the embodiment may be an operating method for adjusting a voltage level supplied to each of a plurality of cores included in a multi-core processor, and may, for example, be included in Figure 4 According to an embodiment, the operation of the first power switch may be controlled based on the operating frequency of the active core. However, this is only an example embodiment, and the embodiment is not limited thereto. Figure 4 and Figure 6 Describe the operation method of the SoC.

[0060] In operation S610, the control logic 120 may determine whether only core 1110a of core 1 110a and core 2 110b is in an active state. Based on the result of the determination, when only core 1 110a is in an active state (operation S610, yes), operation S620 may be performed, and when core 1 110a is not in an active state (operation S610, no), operation S660 may be performed. In operation S620, the control logic 120 may monitor the operating frequency of the active core 1 110a.

[0061] In operation S630, the control logic 120 may determine whether the operating frequency of core 1 110a is higher than a reference frequency. For example, when core 1 110a performs high-performance or high-speed operations, the operating frequency of core 1 110a may be higher than the reference frequency. Here, the reference frequency may be defined as a frequency at which core 1 110a requires a current greater than the current capacity of VR1 210a corresponding to core 1 110a. On the other hand, when the operating frequency of core 1 110a is equal to or less than the reference frequency, the current required for the operation of core 1 110a may be equal to or less than the current capacity of VR1 210a.

[0062] Based on the result of the determination, when the operating frequency of core 1 110a is higher than the reference frequency (operation S630, yes), the control logic 120 may turn on the first power switch SW12, turn on the first power gate switch SW1, and turn off the second power gate switch SW2 in operation S640. On the other hand, based on the result of the determination, when the operating frequency of core 1 110a is less than or equal to the reference frequency (operation S630, no), the control logic 120 may turn off the first power switch SW12, turn on the first power gate switch SW1, and turn off the second power gate switch SW2 in operation S650.

[0063] In operation S660, the control logic 120 may determine whether both core 1 110a and core 2 110b are in an active state. Based on the result of the determination, if both core 1 110a and core 2 110b are in an active state (operation S660, yes), the control logic 120 may turn off the first power switch SW12 and turn on the first power gate switch SW1 and the second power gate switch SW2 in operation S670. Based on the result of the determination, if neither core 1 110a nor core 2 110b is in an active state (operation S660, no), the control logic 120 may turn off the first power switch SW12 and turn off the first power gate switch SW1 and the second power gate switch SW2 in operation S680.

[0064] Figure 7 is a flowchart of operations between the SoC 100 and the PMIC 200 according to an embodiment.

[0065] refer to Figure 7 , according to an embodiment, an operation between the SoC 100 and the PMIC 200 for adjusting a voltage level supplied to each of a plurality of cores included in a multi-core processor is shown, and the operation may, for example, include Figure 4 The sequential operations performed between the SoC 100 and the PMIC 200 are described below. Figure 4 and Figure 7 The operation according to the embodiment is described.

[0066] In operation S710, the SoC 100 may determine the operating status of core 1 110a and core 2 110b. In operation S720, the SoC 100 may monitor the operating frequency of the active cores of core 1 110a and core 2 110b. In operation S730, the SoC 100 may generate a voltage control signal based on the operating frequency of the active cores. For example, in some embodiments, the voltage control signal may include a first voltage control signal VCS1 and a second voltage control signal VCS2. In operation S740, the SoC 100 may transmit the voltage control signal to the PMIC 200. For example, in some embodiments, the voltage control signal may include the first voltage control signal VCS1 and the second voltage control signal VCS2. In operation S750, the PMIC 200 may generate a first voltage V1 and a second voltage V2 based on the voltage control signal. In operation S760, the PMIC 200 may provide the first voltage V1 and the second voltage V2 to the SoC 100.

[0067] Figure 8 An example of an electronic device 40 including a core 1 110 a and a core 2 110 b according to an embodiment is shown.

[0068] refer to Figure 8 , the electronic device 40 may include a SoC 100A and a PMIC 200, and the SoC 100A and the PMIC 200 may be mounted on a printed circuit board (PCB) 300. The SoC 100A may correspond to Figure 4 An embodiment of the SoC 100 and the PMIC 200 may correspond to Figure 4 PMIC 200. Reference above Figures 1 to 7 The described aspects can be applied to Figure 8 Example of .

[0069] VR1 210a can be connected to passive components arranged on PCB 300, such as inductor L1 and capacitors C1a and C1b. Depending on the embodiment, the number or inductance of inductor L1 and the number and capacitance of capacitors C1a and C1b can be varied according to the current capacity of VR1 210a. Similarly, VR2 210b can be connected to passive components arranged on PCB 300, such as inductor L2 and capacitors C2a and C2b. Depending on the embodiment, the number or inductance of inductor L2 and the number and capacitance of capacitors C2a and C2b can be varied according to the current capacity of VR2 210b.

[0070] Specifically, current can be charged to inductor L1 and capacitors C1a and C1b according to the output voltage of VR1 210a. Therefore, when the output voltage increases according to the increase in the current capacity of VR1 210a, the inductance of inductor L1 can be increased or the number of capacitors C1a and C1b can be increased. For example, assuming that SoC 100A does not include the first power switch SW12, VR1 210a can be implemented to have a current capacity corresponding to the maximum current consumption of core 1 110a (e.g., 6A). In contrast, SoC 100A according to an embodiment includes the first power switch SW12, and thus SoC 100A can be implemented to have a current capacity corresponding to half the total maximum current consumption of core 1 110a and core 2 110b (e.g., 4A). Therefore, according to an embodiment, per-core dynamic voltage management can be supported without increasing the inductance of inductor L1 or the number of capacitors C1a and C1b.

[0071] SoC 100A may include core 1 110a and core 2 110b, control logic 120a, a first power gate switch SW1, a second power gate switch SW2, and a first power switch SW12. For example, each of the first power gate switch SW1, the second power gate switch SW2, and the first power gate switch SW12 may be implemented as a PMOS transistor. However, embodiments are not limited thereto. For example, at least one of the first power gate switch SW1, the second power gate switch SW2, and the first power switch SW12 may be implemented as an NMOS transistor or a transmission gate. For example, at least one of the first power gate switch SW1, the second power gate switch SW2, and the first power gate switch SW12 may be implemented as a plurality of transistors connected in series, in parallel, or in both series and parallel.

[0072] The control logic 120a may generate a first power gating signal S1G and a second power gating signal S2G based on the operating states of core 1 110a and core 2 110b. For example, when core 1 110a is in an active state, the control logic 120a may generate the first power gating signal S12G as a logic "0." For example, when core 1 110a is in an idle state, the control logic 120a may generate the first power gating signal S12G as a logic "1" and may power gate core 1 110a.

[0073] Control logic 120a may generate a first power control signal S12G based on the operating state and operating frequency of core 1 110a and core 2 110b. For example, when only one of core 1 110a and core 2 110b is active and the operating frequency of the active core is higher than a reference frequency, control logic 120a may generate the first power control signal S12G as an enable level, such as a logic "0." Consequently, first power rail PR1 and second power rail PR2 may be electrically connected to each other, and power may be supplied from VR1 210a and VR2 210b to the active core.

[0074] The control logic 120a may generate the first and second voltage control signals VCS1 and VCS2 based on the operating states and operating frequencies of the core 1 110a and the core 2 110b. For example, when the first power control signal S12G is logic "0," the control logic 120a may generate the first and second voltage control signals VCS1 and VCS2 such that the first and second voltages V1 and V2 have the same voltage level.

[0075] According to an embodiment, each of the SoC 100A and the PMIC 200 may be implemented on a separate chip, and thus the control logic 120a and the VR1 210a and VR2 210b may perform inter-chip communication. For example, the control logic 120a and the VR1 210a and VR2 210b may communicate with each other via an inter-integrated circuit (I2C), an improved inter-integrated circuit (I3C), a system power management interface (SPMI), a general-purpose input / output (GPIO), etc.

[0076] Specifically, the control logic 120a can provide power gating state information of an idle core among cores 1 110a and 2 110b, current request information of an active core among cores 1 110a and 2 110b, output voltage information of VR1 210a and VR2 210b, etc., to VR1 210a and VR2 210b via a bus protocol. For example, when core 1 110a is in an active state and core 2 110b is in an idle state, the control logic 120a can provide a second voltage control signal VCS2 to VR2 210b via inter-chip communication. The second voltage control signal VCS2 includes the power gating state information of core 2 110b, current request information indicating that core 1 110a requests a current equal to or greater than 1 / N current (where N is the number of cores), and output voltage information of VR2 210b.

[0077] Figure 9 An example of a SoC 100B including a core 1 110 a and a core 2 110 b according to an embodiment is shown.

[0078] refer to Figure 9 , SoC 100B may include core 1 110a and core 2 110b, control logic 120b, a first power gate switch SW1 and a second power gate switch SW2, a first power switch SW12, and VR1 130a and VR2 130b. VR1 130a and VR2 130b may correspond to core 1 110a and core 2 110b, respectively, so that SoC 100B can support a per-core dynamic voltage management function. In addition, SoC 100B may further include first and second inductors L1 and L2 and first and second capacitors C1 and C2. SoC 100B according to an embodiment corresponds to Figure 8 The present invention is a modified embodiment of the SoC 100A, and for the sake of brevity, repeated descriptions of similar elements will not be given.

[0079] According to an embodiment, each of VR1 130a and VR2 130b may be implemented as an integrated voltage regulator (IVR) or an on-chip voltage regulator and may be included in SoC 100B. Therefore, control logic 120b may perform on-chip communication with VR1 130a and VR2 130b. For example, control logic 120b and VR1 130a and VR2 130b may communicate with each other via a bus protocol such as ARM Peripheral Bus (APB), ARM High Performance Bus (AHB), etc. Alternatively, control logic 120b and VR1 130a and VR2 130b may communicate with each other via a direct connection using a direct protocol or based on an interface.

[0080] Specifically, the control logic 120b may provide power gating state information of an idle core among cores 1 110a and 2 110b, current request information of an active core among cores 1 110a and 2 110b, output voltage information of VR1 130a and VR2 130b, etc., to VR1 130a and VR2 130b via a bus protocol. For example, when core 1 110a is in an active state and core 2 110b is in an idle state, the control logic 120b may provide a second voltage control signal VCS2 including power gating information of core 2 110b, current request information indicating that core 1 110a requests a current equal to or greater than 1 / N (where N is the number of cores), and output voltage information of VR2 130b to VR2 130b via a bus protocol.

[0081] Figure 10 An example of a SoC 100 c including a core 1 110 a , a core 2 110 b , a core 3 110 c , and a core 4 110 d according to an embodiment is shown.

[0082] refer to Figure 10 , the SoC 100C may include cores 1 110a to 4 110d, a control logic 120c, a first power gate switch SW1, a second power gate switch SW2, a third power gate switch SW3, and a fourth power gate switch SW4, a first power switch SW12, a second power switch SW23, a third power switch Sw34, and a fourth power switch SW41, and VR1 130a, VR2 130b, VR3 130c, and VR4 130d. VR1 130a to VR4 130d may correspond to cores 1 110a to 4 110d, respectively, so that the SoC 100C may support a per-core dynamic voltage management function. Moreover, the SoC 100C may further include a first inductor L1, a second inductor L2, a third inductor L3, and a fourth inductor L4, and a first capacitor C1, a second capacitor C2, a third capacitor C3, and a fourth capacitor C4. The SoC 100C according to the embodiment corresponds to Figure 9 This is a modified embodiment of the SoC 100B, and repeated description of similar elements will not be given.

[0083] VR1 130a to VR4 130d may be connected to first to fourth inductors L1 to L4, respectively, and first to fourth inductors L1 to L4 may charge current based on the output voltages of VR1 130a to VR4 130d, respectively. Furthermore, first to fourth capacitors C1 to C4 may provide voltages corresponding to currents flowing through first, second, third, and fourth power rails PR1, PR2, PR3, and PR4, respectively, to cores 1 110a to 110d.

[0084] The first power gate control switch SW1 may be arranged between the first power line PR1 and core 1 110a and may electrically connect the first power line PR1 to core 1 110a in response to a first power gate control signal S1G. The second power gate control switch SW2 may be arranged between the second power line PR2 and core 2 110b and may electrically connect the second power line PR2 to core 2 110b in response to a second power gate control signal S2G. The third power gate control switch SW3 may be arranged between the third power gate PR3 and core 3 110c and may electrically connect the third power gate PR3 to core 3 110c in response to a third power gate control signal S3G. The fourth power gate control switch SW4 may be arranged between the fourth power line PR4 and core 4 110d and may electrically connect the fourth power line PR4 to core 4 110d in response to a fourth power gate control signal S4G.

[0085] The first power switch SW12 may be arranged between the first power rail PR1 and the second power rail PR2, and may electrically connect the first power rail PR1 and the second power rail PR2 to each other in response to a first power control signal S12G. The second power switch SW23 may be arranged between the second power rail PR2 and the third power rail PR3, and may electrically connect the second power rail PR2 and the third power rail PR3 to each other in response to a second power control signal S23G. The third power switch SW34 may be arranged between the third power rail PR3 and the fourth power rail PR4, and may electrically connect the third power rail PR3 and the fourth power rail PR4 to each other in response to a third power control signal S34G. The fourth power switch SW41 may be arranged between the fourth power rail PR4 and the first power rail PR1, and may electrically connect the fourth power rail PR4 and the first power rail PR1 to each other in response to a fourth power control signal S41G.

[0086] The control logic 120c may generate the first to fourth power gating signals S1G to S4G based on the operating states of cores 1 110a to 4 110d. For example, when core 1 110a is in an active state and cores 2 110b to 4 110d are in an idle state, the control logic 120c may generate the first power gating signal S1G as a logic "0" and the second to fourth power gating signals S2G to S4G as a logic "1."

[0087] The control logic 120c may generate first to fourth power control signals S12G to S41G based on the operating states and operating frequencies of cores 1 110a to 4 110d. According to an embodiment, when the operating frequency of an active core among cores 1 110a to 4 110d is higher than a first reference frequency and lower than a second reference frequency, the control logic 120c may generate the first to fourth power control signals S12G to S41G to turn on one of the power switches connectable to the active core. Furthermore, according to an embodiment, when the operating frequency of an active core among cores 1 110a to 4 110d is higher than the first reference frequency and higher than the second reference frequency, the control logic 120c may generate the first to fourth power control signals S12G to S41G to turn on all power switches connectable to the active core.

[0088] For example, in response to the first power gating signal S1G, the first power control signal S12G, and the fourth power control signal S41G, the first power gating switch SW1 can be electrically connected to the first power rail PR1, the second power rail PR2, and the fourth power rail PR4. Thus, core 1 110a can receive power from three voltage regulators (i.e., VR1 130a, VR2 130b, and VR4 130d). Therefore, when the maximum current consumption of each core is 8A, the current capacity of each of VR1 130a to VR4 130d can be, for example, 2.7A.

[0089] The control logic 120 c may generate a voltage control signal VCS, which includes power gating state information of an idle core among cores 1 110 a to 4 110 d, current request information of an active core among cores 1 110 a to 4 110 d, and output voltage information of VRs 1 130 a to 4 130 d. For example, the voltage control signal VCS may include a first voltage control signal VCS1, a second voltage control signal VCS2, a third voltage control signal VCS3, and a fourth voltage control signal VCS4, and the first voltage control signal VCS1 to the fourth voltage control signal VCS4 may be provided to VRs 1 130 a to 4 130 d, respectively.

[0090] According to an embodiment, each of VR1 130a to VR4 130d may be implemented as an IVR or an on-chip voltage regulator and may be included in SoC 100C. Here, VR1 130a to VR4 130d may perform on-chip communication with control logic 120c. However, embodiments are not limited thereto. According to one or more embodiments, VR1 130a to VR4 130d may be disposed outside SoC 100C. For example, VR1 130a to VR4 130d may be included in a PMIC. Here, VR1 130a to VR4 130d may perform inter-chip communication with control logic 120c.

[0091] Figure 11 is a diagram showing a method based on an embodiment of the present invention. Figure 10 Table 50 shows an example of the operations of the first to fourth power switches SW12 to SW14 of the operating states of cores 1 110a to 4 110d.

[0092] Reference together Figure 10 and Figure 11 The operating state of each of cores 1 110a to 4 110d may include an active state and an idle state. The power gating switch connected to the active core among cores 1 110a to 4 110d may be turned on, so that the active core can receive power supply normally. The power gating switch connected to the idle core among cores 1 110a to 4 110d may be turned off, so that the idle core can be power-gated and the power consumption of the idle core can be reduced.

[0093] When all of the cores Core 1 110a to Core 4 110d are in an active state or in an idle state, the first to fourth power switches SW12 to SW41 may be turned off. When some of the cores Core 1 110a to Core 4 110d are in an active state, at least one of the first to fourth power switches SW12 to SW41 that can be connected to the active core may be selectively turned on based on the operating frequency of the active core.

[0094] For example, when only core 1 110a is active and the operating frequency of core 1 110a is higher than a first reference frequency and lower than a second reference frequency, one of the first power switch SW12 and the fourth power switch SW41 may be turned on. For example, when the first power switch SW12 is turned on, both VR1 130a and VR2 130b may be electrically connected to core 1 110a and may provide a current greater than the current capacity of VR1 130a to core 1 110a. For example, when the fourth power switch SW41 is turned on, both VR1 130a and VR4 130d may be electrically connected to core 1 110a and may provide a current greater than the current capacity of VR1 130a to core 1 110a.

[0095] For example, when only core 1 110a is active and the operating frequency of core 1 110a is higher than the first reference frequency and higher than the second reference frequency, both the first power switch SW12 and the fourth power switch SW41 can be turned on. Therefore, all of VR1 130a, VR2 130b, and VR4 130d can be electrically connected to core 1 110a and can provide a current greater than the current capacity of VR1 130a to core 1 110a. When the operating frequency of core 1 110a is lower than the first reference frequency, all of the first to fourth switches SW12 to SW41 can be turned off.

[0096] In this configuration, to support per-core dynamic voltage management, one voltage regulator may be divided into VR1 130a through VR4 130d. When per-core dynamic voltage management is not supported, the current capacity of a single voltage regulator may correspond to the total maximum current consumption of cores 1 110a through 4 110d. However, when per-core dynamic voltage management is supported, the current capacity of each of VR1 130a through VR4 130d may be determined based on the current consumption of each of cores 1 110a through 4 110d. Here, the maximum current consumption of each of cores 1 110a through 4 110d may be greater than ¼ (e.g., 8A) of the total maximum current consumption of cores 1 110a through 4 110d.

[0097] According to an embodiment, the SoC 100C may include first to fourth power switches SW12 to SW41, and thus the current capacity of each of VR1 130 a to VR4 130 d may be determined to be equal to or greater than 1 / 3 of the total maximum current consumption of cores 1 110 a to 4 110 d. For example, the current capacity of each of VR1 130 a to VR4 130 d may be 2.7 A.

[0098] Figure 12 6 is a layout 60 of a multi-core processor including Core 1 to Core 4 according to an embodiment.

[0099] refer to Figure 12 , the layout 60 of the multi-core processor may correspond to, for example Figure 10 The layout 60 of the multi-core processor may include a first region R1, a second region R2, a third region R3, a fourth region R4, a fifth region R5, a sixth region R6, a seventh region R7, and an eighth region R8. The first to third regions R1 to R3 may be adjacent to each other in the Y direction, the fourth to sixth regions R4 to R6 may be adjacent to each other in the Y direction, and the seventh and eighth regions R7 and R8 may be adjacent to each other in the Y direction.

[0100] Core 1 may be arranged in the first region R1, and core 2 may be arranged in the second region R2. Core 3 may be arranged in the fourth region R4, and core 4 may be arranged in the fifth region R5. Each of the first to fourth regions R1 to R4 may have a specific area extending in the X and Y directions. These areas may be of the same size or different sizes from each other.

[0101] The first power switch SW12 may be disposed in the third region R3 between the first region R1 and the second region R2. The second power switch SW23 may be disposed in the eighth region R8 between the second region R2 and the fourth region R4. The third power switch SW34 may be disposed in the sixth region R6 between the fourth region R4 and the fifth region R5. The fourth power switch SW41 may be disposed in the seventh region R7 between the first region R1 and the fifth region R5.

[0102] Figure 13 is a detailed flowchart of an operating method of a SoC according to an embodiment.

[0103] refer to Figure 13 The operating method of the SoC according to the embodiment may be an operating method for adjusting a voltage level supplied to each of a plurality of cores included in a multi-core processor, and may, for example, be included in Figure 10 According to an embodiment, the operation of the power switch can be controlled based on the operating frequency of the active core. However, this is only an embodiment, and the embodiment is not limited thereto. Figure 10 and Figure 13 The operation of the SoC according to the embodiment is described.

[0104] In operation S1310, control logic 120c may monitor the operating frequency of an active core. For example, the active core may be core 1 110a. In operation S1320, control logic 120c may determine whether the operating frequency of the active core is higher than a first reference frequency. For example, when core 1 110a is performing high-performance or high-speed operations, the operating frequency of core 1 110a may be higher than the first reference frequency. Here, the first reference frequency may be defined as the frequency at which the active core requests a current greater than the current capacity of a single voltage regulator.

[0105] Based on the result of the determination, when the operating frequency is higher than the first reference frequency (operation S1320, yes), operation S1330 may be performed. In operation S1330, control logic 120c may determine whether the operating frequency of the active core is higher than the second reference frequency. Here, the second reference frequency may be higher than the first reference frequency. For example, when core 1 110a performs ultra-high performance operation or ultra-high speed operation, the operating frequency of core 1 110a may be higher than the second reference frequency. Here, the second reference frequency may be defined as the frequency at which the active core requests a current greater than the total current capacity of the two voltage regulators.

[0106] Based on the result of the determination, when the operating frequency is higher than the second reference frequency (operation S1330), in operation S1340, the control logic 120c may turn on the power switches connected to the active core based on the operating status of the cores adjacent to the active core. That is, the control logic 120c may turn on the power switches of all adjacent cores to the active core based on the operating status of the cores adjacent to the active core. For example, based on the operating status of cores 2 110b and 4 110d adjacent to core 1 110a, the control logic 120c may turn on the first power switch SW12 and the fourth power switch SW41 connected to core 1 110a. For example, when cores 2 110b and 4 110d are both in an idle state, the control logic 120c may turn on the first power switch SW12 and the fourth power switch SW41.

[0107] When the operating frequency is higher than the first reference frequency and lower than the second reference frequency (operation S1330, No), in operation S1350, the control logic 120c may turn on one of the power switches connectable to the active core based on the operating state of the core adjacent to the active core. That is, the control logic 120c may turn on the power switch of one of the adjacent cores to the active core based on the operating state of the core adjacent to the active core. For example, based on the operating states of cores 2 110b and 4 110d adjacent to core 1 110a, the control logic 120c may turn on one of the first power switch SW12 and the fourth power switch SW41 connectable to core 1 110a. For example, when core 2 110b is in the active state and core 4 110d is in the idle state, the control logic 120c may turn on the fourth power switch SW41.

[0108] When the operating frequency is not higher than the first reference frequency (operation S1320, No), in operation S1360, control logic 120c may turn off all of the power switches that are connectable to the active core. That is, control logic 120c may turn off the power switches of adjacent cores to the active core. Therefore, when the operating frequency of core 1 110a is not higher than the first reference frequency, the current required for the operation of core 1 110a may be equal to or less than the current capacity of VR1 130a. For example, control logic 120c may turn off both first power switch SW12 and fourth power switch SW41 that are connectable to core 1 110a.

[0109] Figure 14 Another example of a SoC 100D including cores 1 110 a to 4 110 d according to an embodiment is shown.

[0110] refer to Figure 14 , the SoC 100D may include cores 1 110a to 4 110d, control logic 120d, first to fourth power gate switches SW1 to SW4, a first power switch SW12, a second power switch SW23, a third power switch SW34, a fourth power switch SW41, a fifth power switch SW13, and a sixth power switch SW24, and VR1 130a to VR4 130d. VR1 130a to VR4 130d may correspond to cores 1 110a to 4 110d, respectively, so that the SoC 100D may support a per-core dynamic voltage management function. Moreover, the SoC 100D may further include first to fourth inductors L1 to L4 and first to fourth capacitors C1 to C4. The SoC 100D according to the embodiment corresponds to Figure 10 This is a modified embodiment of the SoC 100C, and repeated description of similar elements will not be given.

[0111] The fifth power switch SW13 may be disposed between the first power rail PR1 and the third power rail PR3 and may electrically connect the first power rail PR1 and the third power rail PR3 to each other in response to a fifth power control signal S13G. The sixth power switch SW24 may be disposed between the second power rail PR2 and the fourth power rail PR4 and may electrically connect the second power rail PR2 and the fourth power rail PR4 to each other in response to a sixth power control signal S24G.

[0112] For example, in response to the first power gating signal S1G and the first, fourth, and fifth power control signals S12G, S41G, and S13G, the first power gating switch S1 can be electrically connected to the first to fourth power rails PR1 to PR4. Thus, core 1 110a can receive power from up to four voltage regulators (i.e., VR1 130a to VR4 130d). Therefore, when the maximum current consumption of each core is 8A, the current capacity of each of VR1 130a to VR4 130d can be, for example, 2A.

[0113] The control logic 120D may generate a voltage control signal VCS, which includes power gating state information of an idle core among cores 1 110 a to 4 110 d, current request information of an active core among cores 1 110 a to 4 110 d, and output voltage information of VR1 130 a to VR4 130 d. For example, in some embodiments, the voltage control signal VCS may include first to fourth voltage control signals VCS1 to VCS4, and the first to fourth voltage control signals VCS1 to VCS4 may be provided to VR1 130 a to VR4 130 d, respectively.

[0114] According to an embodiment, each of VR1 130a to VR4 130d may be implemented as an IVR or an on-chip voltage regulator and may be included in SoC 100D. Here, VR1 130a to VR4 130d may perform on-chip communication with control logic 120d. However, embodiments are not limited thereto. According to one or more embodiments, VR1 130a to VR4 130d may be disposed outside SoC 100D and may be included in PMIC 200, for example. Here, VR1 130a to VR4 130d may perform inter-chip communication with control logic 120d.

[0115] Figure 15 is a block diagram of an electronic device 70 according to an embodiment.

[0116] refer to Figure 15, the electronic device 70 may include a PMIC 200 and an application processor (AP) 400, and the AP 400 may include a first intellectual property (IP1) 410a, a second intellectual property (IP2) 410b, and a control logic 420. In this specification, the term "intellectual property" may refer to an intellectual property block or core, where an IP block is a logic, unit, or reusable unit of an integrated circuit of intellectual property as an entity. For example, in some embodiments, the intellectual property block may be considered as a functional block as described below. According to an embodiment, the PMIC 200 and the AP 400 may be integrated into the same chip and may be implemented as, for example, a SoC. According to an embodiment, the PMIC 200 and the AP 400 may be implemented on different chips, respectively. According to an embodiment, the PMIC 200 and the AP 400 may be implemented in the same package, for example, may be implemented as a SIP. The AP 400 according to an embodiment may correspond to Figure 4 The present invention is a modified embodiment of the SoC 100, and repeated description of the same elements will not be given.

[0117] IP1 410a and IP2 410b may be pre-designed functional blocks, each performing a specific function. Depending on the embodiment, IP1 410a and IP2 410b may operate independently under the control of control logic 420. VR1 210a may be connected to IP1 410a via a first power rail PR1 and may provide a first voltage V1 to IP1 410a. VR2 210b may be connected to IP2 410b via a second power rail PR2 and may provide a second voltage V2 to IP2 410b.

[0118] Furthermore, AP 400 may further include a first power gate switch SW1, a second power gate switch SW2, and a first power switch SW12. The first power gate switch SW1 may be disposed between the first power rail PR1 and IP1 410a and may be selectively turned on in response to a first power gate signal S1G. The second power gate switch SW2 may be disposed between the second power rail PR2 and IP2 410b and may be selectively turned on in response to a second power gate signal S2G. The first power switch SW12 may be disposed between the first power rail PR1 and the second power rail PR2 and may be driven in response to a first power control signal SW12G. For example, when the first power control signal SW1G is enabled, the first power switch SW12 may be turned on and may connect IP1 410a or IP2 410b to both the first power rail PR1 and the second power rail PR2.

[0119] Control logic 420 can generate a first power gating signal S1G, a second power gating signal S2G, and a first power control signal S12G. Furthermore, it can generate voltage control signals for controlling the voltage levels of first voltage V1 and second voltage V2 based on the operating states and operating frequencies of IP1 410a and IP2 410b. According to an embodiment, when IP1 410a is active and IP2 410b is idle, and when the operating frequency of IP1 410a is higher than the reference frequency or the operating voltage of IP1 410a is higher than the first voltage V1 provided by VR1 210a, first power control signal S12G can be enabled to turn on first power switch SW12. When first power control signal S12G is enabled, the voltage levels of first voltage V1 and second voltage V2 can be the same.

[0120] Figure 16 is a block diagram of an electronic device 80 according to an embodiment.

[0121] refer to Figure 16 , the electronic device 80 may include a PMIC 200, a memory device 500, and an AP 600. The memory device 500 may include a first voltage region 510a and a second voltage region 510b, and the PMIC 200 may include VR1 210a and VR2 210b corresponding to the first voltage region 510a and the second voltage region 510b, respectively.

[0122] The memory device 500 may further include a first power gate switch SW1 and a second power gate switch SW2. The first power gate switch SW1 may be disposed between a first power rail PR1 and a first voltage region 510a and may electrically connect the first power rail PR1 to the first voltage region 510a in response to a first power gate signal S1G. The second power gate switch SW2 may be disposed between a second power rail PR2 and a second voltage region 510b and may electrically connect the second power rail PR2 to the second voltage region 510b in response to a second power gate signal S2G.

[0123] Furthermore, the memory device 500 may further include a first power switch SW12. The first power switch SW12 may be disposed between the first power rail PR1 and the second power rail PR2 and may electrically connect the first power rail PR1 to the second power rail PR2 in response to a first power control signal S12G. For example, when the first voltage region 510a is active and the second voltage region 510b is idle, the first power switch SW12 may be selectively turned on. Thus, power may be supplied from VR1 210a and VR2 210b to the first voltage region 510a.

[0124] The memory device 500 may include various circuit blocks related to memory operations. Here, the first voltage region 510a may include one or more of the various circuit blocks, and the second voltage region 510b may include other of the various circuit blocks. For example, the first voltage region 510a may include one or more data processing blocks configured to send data to be written to the memory device 500 or data to be read from the memory device 500. For example, the second voltage region 510b may include at least one control block configured to control the data processing blocks included in the first voltage region 510a.

[0125] Depending on the operating mode, the first voltage region 510a may receive the first voltage V1 from VR1 210a or a voltage higher than the first voltage V1 from VR1 210a and VR2 210b. For example, when the first voltage region 510a is in a low power mode, the first power control signal S12G may be disabled, and the first power switch SW12 may be turned off. For example, when the first voltage region 510a is in a normal power mode, in other words, when the first voltage region 510a requires an operating voltage whose voltage level is higher than the voltage level of the first voltage V1, the first power control signal S12G may be enabled, and the first power switch SW12 may be turned on.

[0126] The AP 600 may include control logic 610, wherein the control logic 610 may generate first and second power gating signals S1G and S2G, a first power control signal S12G, and first and second voltage control signals VCS1 and VCS2. However, embodiments are not limited thereto. According to another embodiment, the control logic that generates the first and second power gating signals S1G and S2G, the first power control signal S12G, and the first and second voltage control signals VCS1 and VCS2 may be included in the memory device 500.

[0127] Figure 17 is a block diagram of an electronic device 90 according to an embodiment.

[0128] refer to Figure 17 , the electronic device 90 may include a PMIC 700 and an AP 800. The AP 800 may include a multi-core processor 810 according to the various embodiments described above. The multi-core processor 810 may control the functions of the AP 800 by executing various programs. The PMIC 700 may include multiple voltage regulators (VRs) 710, and the multiple voltage regulators 710 may respectively correspond to the multiple cores in the multi-core processor 810. Therefore, the PMIC 700 may support a per-core dynamic voltage management function.

[0129] The AP 800 may further include a modem module 840, and thus the AP 800 may be referred to as a modem AP (ModAP). The AP 800 may be implemented as an SoC and may further include various types of circuit blocks. For example, the AP 800 may further include a PLL 820 and an internal memory 830. Furthermore, the AP 800 may further include a global navigation satellite system (GNSS) module 850 and another type of communication module, such as a near field communication (NFC) module 860. Figure 17 In addition to the components shown in FIG87 , the AP 800 may further include various types of communication modules, such as WLAN, BT, etc. The components included in the AP 800 may communicate with each other through the bus 870 .

[0130] Various programs for controlling the operation of the AP 800 may be stored in the internal memory 830, and these programs may be executed by various types of processors, such as the multi-core processor 810, the processor included in the modem module 840, the processor included in the GNSS module 850, etc. The PLL 820 may include a clock generator, and the PLL 820 may provide a clock output to the modem module 840, the GNSS module 850, and the NFC module 860. Furthermore, although Figure 17 One PLL 820 is shown included in the AP 800, but in some embodiments, multiple PLLs may be included in the AP 800. The PLL 820 may support per-core dynamic frequency management functionality.

[0131] As described above, example embodiments are disclosed in the drawings and the specification. In this specification, specific terms are used to describe the embodiments. However, the terms used herein are for the purpose of describing specific embodiments only and are not intended to limit the example embodiments. Therefore, it should be understood that many equivalent and modified embodiments may exist that can replace those described in this specification. Therefore, the scope of the embodiments should be defined by the appended claims.

[0132] While the inventive concept has been particularly shown and described with reference to embodiments thereof, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the appended claims.

Claims

1. A system on chip (SoC), comprising: a plurality of cores, including at least a first core and a second core; a first power gating switch disposed between the first core and a first power rail receiving a first voltage, the first power gating switch being selectively turned on in response to a first power gating signal; a second power gate switch disposed between the second core and a second power rail receiving a second voltage, the second power gate switch being selectively turned on in response to a second power gate signal; as well as a first power switch disposed between the first power rail and the second power rail and selectively turned on in response to a first power control signal to connect the first power gate switch or the second power gate switch to both the first power rail and the second power rail; The first power switch is selectively turned on based on an operating frequency or an operating voltage of an active core among the first core and the second core, so that the active core is connected to both the first power rail and the second power rail through the first power switch and a power gate switch connected to the active core among the first power gate switch and the second power gate switch.

2. The SoC according to claim 1, wherein: When the first core is in an active state and the second core is in an idle state, The first power gate switch is turned on to connect the first power rail to the first core power supply, and The second power gate switch is turned off to electrically isolate the second power rail from the second core.

3. The SoC according to claim 1, wherein: When the first core is in an active state and the second core is in an idle state, and When the operating frequency of the first core is higher than the reference frequency or the operating voltage of the first core is higher than the first voltage, The first power control signal is enabled to turn on the first power switch, thereby connecting the first power gate switch to both the first power rail and the second power rail.

4. The SoC according to claim 1, wherein: When the first power control signal is enabled, a voltage level of the first voltage is the same as a voltage level of the second voltage.

5. The SoC according to claim 1, wherein A voltage level of the first voltage and a voltage level of the second voltage can be varied based on at least one of an operating state, an operating frequency, and a workload of the first core and the second core.

6. The SoC according to claim 1, wherein: The first and second power gating signals and the first power control signal are controlled based on at least one of an operating state, an operating frequency, and a workload of the first and second cores.

7. The SoC according to claim 1, further comprising: The control logic is configured to generate the first power gating signal, the second power gating signal, and the first power control signal based on the operating states and operating frequencies of the first core and the second core.

8. The SoC according to claim 1, further comprising: The control logic is configured to generate a voltage control signal for controlling voltage levels of the first voltage and the second voltage.

9. The SoC according to claim 8, wherein: The control logic is further configured to provide the voltage control signal to a power management integrated circuit (PMIC) through inter-chip communication, where the PMIC is disposed outside the SoC.

10. The SoC according to claim 8, further comprising: a first voltage regulator corresponding to the first core and configured to provide the first voltage to the first power rail; as well as a second voltage regulator corresponding to the second core and configured to provide the second voltage to the second power rail; The control logic is further configured to provide the voltage control signal to the first voltage regulator and the second voltage regulator through on-chip communication.

11. The SoC according to claim 1, wherein: The plurality of cores further includes a third core and a fourth core, and The SoC further includes: a third power gate switch disposed between the third core and a third power rail receiving a third voltage, the third power gate switch being selectively turned on in response to a third power gate signal; and A fourth power gate switch is arranged between the fourth core and a fourth power rail receiving a fourth voltage, and the fourth power gate switch is selectively turned on in response to a fourth power gate signal.

12. The SoC according to claim 11, further comprising: a second power switch connected between the second power rail and the third power rail and selectively turned on in response to a second power control signal to connect the second power gate switch or the third power gate switch to both the second power rail and the third power rail; a third power switch connected between the third power rail and the fourth power rail and selectively turned on in response to a third power control signal to connect the third power gate switch or the fourth power gate switch to both the third power rail and the fourth power rail; and a fourth power switch connected between the fourth power rail and the first power rail and selectively turned on in response to a fourth power control signal to connect the fourth power gate switch or the first power gate switch to both the fourth power rail and the first power rail.

13. The SoC according to claim 12, wherein: When the first core is in an active state and the second core, the third core, and the fourth core are in an idle state, and When the operating frequency of the first core is higher than a first reference frequency and less than or equal to a second reference frequency, one of the second power switch and the fourth power switch is turned on, and When the operating frequency of the first core is higher than the second reference frequency, both the second power switch and the fourth power switch are turned on.

14. The SoC according to claim 12, further comprising: a fifth power switch connected between the first power rail and the third power rail and selectively turned on in response to a fifth power control signal to connect the first power gate switch or the third power gate switch to both the first power rail and the third power rail; and a sixth power switch connected between the second power rail and the fourth power rail and selectively turned on in response to a sixth power control signal to connect the second power gate switch or the fourth power gate switch to both the second power rail and the fourth power rail.

15. The SoC according to claim 12, wherein: The first power switch is arranged between the first core and the second core, The second power switch is arranged between the second core and the third core, The third power switch is arranged between the third core and the fourth core, and The fourth power switch is arranged between the fourth core and the first core.

16. The SoC according to claim 1, wherein: The first power switch is arranged between the first core and the second core.

17. An electronic device comprising: a first voltage regulator configured to provide a first voltage to a first power rail; a second voltage regulator configured to provide a second voltage to a second power rail; a plurality of cores, including at least a first core and a second core; a first power gating switch disposed between the first power rail and the first core and selectively turned on in response to a first power gating signal; a second power gating switch disposed between the second power rail and the second core and selectively turned on in response to a second power gating signal; as well as a power switch disposed between the first power rail and the second power rail and selectively turned on in response to a power control signal to connect the first power gate switch or the second power gate switch to both the first power rail and the second power rail, The power switch is selectively turned on based on an operating frequency or an operating voltage of an active core among the first core and the second core, so that the active core is connected to both the first power rail and the second power rail through the power switch and a power gate switch connected to the active core among the first power gate switch and the second power gate switch.

18. The electronic device according to claim 17, wherein The first and second voltage regulators, the plurality of cores, the first and second power gate switches, and the power switch are provided on a same chip.

19. The electronic device according to claim 17, wherein The first voltage regulator and the second voltage regulator are provided on a first chip, and The plurality of cores, the first and second power gate switches, and the power switch are disposed on a second chip.

20. An electronic device comprising: First intellectual property IP; Second IP; a first voltage regulator connected to the first IP via a first power rail and configured to provide a first voltage to the first IP; a second voltage regulator connected to the second IP via a second power rail and configured to provide a second voltage to the second IP; as well as a power switch, arranged between the first power rail and the second power rail and driven according to a power control signal, wherein, when the power control signal is enabled, the power switch is turned on to connect the first IP or the second IP to both the first power rail and the second power rail, and The power switch is selectively turned on based on an operating frequency or an operating voltage of an active IP among the first and second IPs, so that the active IP is connected to both the first power rail and the second power rail through the power switch.

Images