Fin thinning controlled by feedback

Abstract

The present disclosure relates to fin thinning controlled by feedback. A method includes forming isolation regions extending into a semiconductor substrate. A semiconductor strip is located between the isolation regions. The method also includes recessing the isolation regions so that the top of the semiconductor strip protrudes above the top surface of the isolation region to form a semiconductor fin, measuring a fin width of the semiconductor fin, generating an etching scheme based on the fin width, and performing a thinning process on the semiconductor fin using the etching scheme.

Description

Technical Field

[0001] The present disclosure generally relates to controlling fin thinning through feedback. Background Art

[0002] As integrated circuits continue to shrink and the speed requirements for integrated circuits become higher and higher, transistors need to have higher drive currents with smaller and smaller sizes. As a result, fin field effect transistors (FinFETs) have been developed. In a conventional FinFET formation process, semiconductor fins can be formed by etching a silicon substrate to form trenches, filling the trenches with (one or more) dielectric materials to form shallow trench isolation (STI) regions, and then recessing the STI regions. Therefore, the silicon substrate portion between the recessed portions of the STI regions forms a semiconductor fin, on which a FinFET is formed. Summary of the invention

[0003] According to one embodiment of the present disclosure, a method for thinning semiconductor fins is provided, comprising: forming isolation regions extending into a semiconductor substrate, wherein a first semiconductor strip is located between the isolation regions; recessing the isolation regions, wherein a top of the first semiconductor strip protrudes above a top surface of the isolation region to form a first semiconductor fin; measuring a first fin width of the first semiconductor fin; generating a first etching scheme based on the first fin width; and performing a first thinning process on the first semiconductor fin using the first etching scheme.

[0004] According to another embodiment of the present disclosure, a method for thinning semiconductor fins is provided, comprising: forming a first semiconductor fin, the first semiconductor fin protruding higher than a first isolation region on an opposite side of the first semiconductor fin, wherein the first semiconductor fin is formed of a first semiconductor material; forming a second semiconductor fin, the second semiconductor fin protruding higher than a second isolation region on an opposite side of the second semiconductor fin, wherein the second semiconductor fin is formed of a second semiconductor material different from the first semiconductor material; measuring a first fin width of the first semiconductor fin; measuring a second fin width of the second semiconductor fin; thinning the first semiconductor fin based on the first fin width using a first etching chemistry, wherein the second semiconductor fin is exposed to the first etching chemistry when the first semiconductor fin is thinned; and thinning the second semiconductor fin based on the second fin width.

[0005] According to another embodiment of the present disclosure, a method for thinning semiconductor fins is provided, including: forming a first semiconductor region, wherein sidewalls of the first semiconductor region are exposed; measuring a first width of the first semiconductor region; generating a first etching scheme based on the first width of the first semiconductor region and a first target width, wherein the first target width is an expected width of the first semiconductor region; and etching the first semiconductor region using the first etching scheme. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The present disclosure can be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, various features are not drawn to scale. In fact, the size of various features may be arbitrarily increased or reduced for clarity of discussion.

[0007] Figures 1 to 10 Cross-sectional and perspective views illustrate intermediate stages in the formation of a fin field effect transistor (FinFET) with thinned fins, in accordance with some embodiments.

[0008] Figures 11 to 13 A process for thinning semiconductor fins is shown in accordance with some embodiments.

[0009] Fig.14 and Fig.15 is a flow chart for thinning a semiconductor fin according to some embodiments.

[0010] Fig.16 Shown are chemical structures of amine derivatives used in a fin thinning process according to some embodiments.

[0011] Fig.17 Etching semiconductor fins by spraying an etching solution on a wafer is shown in accordance with some embodiments.

[0012] Fig.18 A process flow for forming FinFETs and thinning fins is shown in accordance with some embodiments. DETAILED DESCRIPTION

[0013] The following disclosure provides many different embodiments or examples for implementing the different features of the present invention. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first feature above or on a second feature may include an embodiment in which the first feature and the second feature are formed in direct contact, and may also include an embodiment in which additional features may be formed between the first feature and the second feature so that the first feature and the second feature may not be in direct contact. In addition, the present disclosure may repeat reference numerals and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself represent the relationship between the various embodiments and / or configurations discussed.

[0014] Additionally, spatially relative terms (e.g., "below," "beneath," "below," "above," "upper," etc.) may be used herein to facilitate describing the relationship of one element or feature illustrated in the figures relative to another element(s) or feature(s). These spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.

[0015] According to some embodiments, a method for forming a fin field effect transistor (FinFET) and a corresponding thinning process for a semiconductor fin are provided. Some variations of some embodiments are discussed. In the various views and illustrative embodiments, the same reference numerals are used to represent the same elements. According to some embodiments of the present disclosure, semiconductor fins for n-type FinFETs and p-type FinFETs are formed to achieve a target width. The process for forming a semiconductor fin includes etching an isolation region to form a semiconductor fin, measuring the width of the semiconductor fin, comparing the measured width of the semiconductor fin with the target width, generating an etching scheme based on the measured width and the target width, and using the etching scheme to thin the semiconductor fin. After thinning, the thinned semiconductor fin can be remeasured. Based on the remeasurement results, reprocessing can be performed to thin the semiconductor fin again.

[0016] The embodiments will be described with respect to a specific context, namely, the process of thinning semiconductor fins and forming corresponding FinFETs based on the thinned semiconductor fins. The concepts of the embodiments discussed can also be applied to the construction and processing of other structures with fins, including but not limited to the thinning of the channel region of gate-all-around (GAA) nanowire transistors and nanosheet transistors. The embodiments discussed herein are examples of providing methods of making or using the subject matter of the present disclosure, and those of ordinary skill in the art will readily understand the modifications that can be made while remaining within the intended scope of the different embodiments. Although the method embodiments may be discussed as being performed in a particular order, other method embodiments may be performed in any logical order.

[0017] Figures 1 to 10 1 shows a cross-sectional view of an intermediate stage of forming a first FinFET and a second FinFET in device regions 100 and 200 of a wafer 10, respectively, according to some embodiments of the present disclosure. The corresponding process is also schematically reflected in Fig.18 In the process flow shown in FIG. 1 . According to some embodiments, device region 100 is an n-type FinFET region, where an n-type FinFET will be formed, and device region 200 is a p-type FinFET region, where a p-type FinFET will be formed. According to other embodiments, device regions 100 and 200 may both be n-type FinFET regions, both be p-type FinFET regions, or be a p-type FinFET region and an n-type FinFET region.

[0018] refer to Figure 1 , forming a wafer 10. The corresponding process is Fig.18 400 is shown as process 402. Wafer 10 may include substrate 20, which may be formed of silicon or other semiconductor materials. Substrate 20 may also be a silicon-on-insulator (SOI) substrate, which includes a bottom semiconductor layer, an isolation layer (e.g., formed of silicon oxide) above the bottom semiconductor layer, and a top semiconductor layer above the isolation layer. A p-well region (not shown) may be formed in device region 100. Device region 200 may include substrate 20 and an epitaxial semiconductor layer 21 above substrate 20. Substrate 20 and epitaxial semiconductor layer 21 may be collectively referred to as semiconductor substrate 20'. In addition, substrate 20 in device region 100 and substrate 2' in device region 200 are considered to be portions of the substrate extending into device regions 100 and 200. According to some embodiments of the present disclosure, epitaxial semiconductor layer 21 includes germanium, and may include silicon germanium, or may include germanium without silicon. The percentage of germanium in epitaxial semiconductor layer 21 may be higher than 30%, and may be in a range between about 30% and about 100%. An n-well region (not shown) may be formed in semiconductor substrate 20 ′. The n-well region may or may not extend below epitaxial semiconductor layer 21 .

[0019] refer to Figure 2 , etching the wafer 10 to form the trench 23 and the semiconductor strips 126 and 226. The corresponding process is Fig.18 The process flow 400 shown in FIG. 4 is shown as process 404. In the device region 100, the portion of the substrate 20 between adjacent trenches 23 is referred to as a semiconductor strip 126. In the device region 200, the portion of the substrate 20' between adjacent trenches 23 is referred to as a semiconductor strip 226. In order to form the trench 23, a pad oxide layer 28 and a hard mask layer 29 are first formed as a capping layer on the wafer 10. The pad oxide layer 28 may be a thin film formed of silicon oxide. According to some embodiments of the present disclosure, the pad oxide layer 28 is formed by deposition, for example, using plasma enhanced chemical vapor deposition (PECVD). The pad oxide layer 28 may be used as an etch stop layer for etching the hard mask layer 29. According to some embodiments of the present disclosure, the hard mask layer 29 is formed of silicon nitride, for example, using low pressure chemical vapor deposition (LPCVD), atomic layer deposition (ALD), plasma enhanced chemical vapor deposition (PECVD), etc.

[0020] A photoresist (not shown) is formed on the hard mask layer 29 and then patterned by a photolithography process. The hard mask layer 29 is then patterned using the patterned photoresist as an etching mask to form a Figure 2 Next, the patterned hard mask layer 29 is used as an etching mask to etch the pad oxide layer 28 and the underlying substrate 20 and epitaxial semiconductor layer 21. The resulting structure is as shown in FIG. Figure 2 As shown. The resulting trenches 23 may penetrate the epitaxial semiconductor layer 21 to extend into the underlying semiconductor substrate 20. In the device region 100, the portion of the semiconductor substrate 20 located between the trenches 23 is referred to as a semiconductor strip 126. In the device region 200, the portion of the semiconductor substrate 20 and the epitaxial semiconductor layer 21 located between the trenches 23 is referred to as a semiconductor strip 226.

[0021] According to some embodiments, after forming semiconductor strips 126 and 226 , a fin thinning process may be performed to thin semiconductor strips 126 and 226 in order to improve gate control of the resulting FinFET and reduce fin width variation. Fig.18 The process flow 400 shown in FIG. 4 is shown as process 406. In the following paragraphs, reference is made to Figures 11 to 13 The details of the fin thinning process are discussed in detail. According to other embodiments, the fin thinning process is not performed at this stage. Instead, the fin thinning process may be performed as shown in FIG. Figure 4 After forming the protruding semiconductor fins 126' and 226' as shown, or after Fig. 9The fin thinning process is shown to be performed after the dummy gate stack is removed.

[0022] refer to Figure 3 , forming an isolation region 22, which is alternatively referred to as a shallow trench isolation (STI) region hereinafter. The corresponding process is Fig.18 The process flow 400 shown in FIG. 4 is shown as process 408. By filling the trench 23 ( Figure 2 ), and then a planarization process (e.g., a chemical mechanical polishing (CMP) process or a mechanical grinding process) is performed to remove excess portions of the dielectric material to form the STI region 22. The remaining portion of the (one or more) dielectric materials is the STI region 22. The STI region 22 may include a liner dielectric (not shown), which may be a thermal oxide layer formed by thermal oxidation of a surface layer of the semiconductor material. The liner dielectric may also be a deposited silicon oxide layer, a silicon nitride layer, etc. formed using, for example, ALD, high density plasma chemical vapor deposition (HDPCVD), or chemical vapor deposition (CVD). The STI region 22 may also include a dielectric material above the liner oxide, wherein the dielectric material may be formed using flowable chemical vapor deposition (FCVD), spin coating, etc. According to some embodiments, the dielectric material above the liner dielectric may include silicon oxide. Due to the planarization process, the top surface of the hard mask 29 and the top surface of the STI region 22 may be substantially flush with each other.

[0023] Semiconductor strips 126 and 226 are located between SIT regions 22. It should be understood that the structural differences in semiconductor strips 126 and 226 are examples showing that different materials can be used in device regions 100 and 200. According to some embodiments, each of semiconductor strips 126 and 226 may include a single semiconductor layer formed of the same semiconductor material, or may include multiple semiconductor layers formed of different materials. These materials may include silicon; germanium; compound semiconductors including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; combinations thereof, and / or multiple layers thereof.

[0024] refer to Figure 4 , the STI region 22 is recessed so that the top portions of the semiconductor strips 126 and 226 protrude higher than the top surface 22A of the remaining portion of the STI region 22 to form protruding semiconductor fins 126' and 226', respectively. Fig.184 is shown as process 410 in the process flow 400 shown in FIG. The portions of semiconductor strips 126 and 226 below top surface 22A are still referred to as semiconductor strips 126 and 226, respectively. The etching may be performed using a dry etching process, wherein, for example, HF3 and NH3 are used as etching gases. During the etching process, a plasma may be generated. According to an alternative embodiment of the present disclosure, a wet etching process is used to perform the recessing of STI region 22. For example, the etching chemistry may include an HF solution.

[0025] In the above embodiments, the fins may be patterned by any suitable method. For example, the fins may be patterned using one or more photolithography processes, including double patterning or multi-patterning processes. Typically, the double patterning or multi-patterning process combines photolithography and self-alignment processes, allowing for the creation of patterns having, for example, a smaller pitch than that obtainable using a single direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a photolithography process. Spacers are formed next to the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers or mandrels may then be used to pattern the fins.

[0026] According to some embodiments, after recessing the STI region 22 to form the protruding semiconductor fins 126' and 226', a fin thinning process may be performed to thin the protruding semiconductor fins 126' and / or 226' to improve gate control and reduce fin width variation. Fig.18 The process flow 400 shown in FIG. is shown as process 412. In the following paragraphs, reference is made to Figures 11 to 13 The details of the fin thinning process are discussed in detail. According to other embodiments, the fin thinning process is not performed at this stage. Instead, the fin thinning process may be performed while forming the trench 23 ( Figure 2 ) but after forming the STI region ( Figure 3 ) before, or before Fig. 9 The fin thinning process is shown to be performed after the dummy gate stack is removed.

[0027] According to some embodiments, a silicon cap (not shown) may be epitaxially grown on the protruding semiconductor fins 126 ′ and 226 ′. Figure 5 , the dummy gate stack 30 is formed to extend on the top surface and sidewalls of the (protruding) fins 126' and 226'. The corresponding process is Fig.18The process flow 400 shown in FIG. 4 is shown as process 414. The dummy gate stack 30 may include a dummy gate dielectric 32 and a dummy gate electrode 34 above the dummy gate dielectric 32. The dummy gate electrode 34 may be formed, for example, using polysilicon, or other materials may be used. Each dummy gate stack 30 may also include one (or more) hard mask layers 36 above the dummy gate electrode 34. The hard mask layer 36 may be formed of silicon nitride, silicon oxide, silicon carbonitride, or multiple layers thereof. The dummy gate stack 30 may span a single or multiple of the protruding semiconductor fins 126' and 226' and / or the STI region 22. The dummy gate stack 30 also has a length direction perpendicular to the length direction of the protruding semiconductor fins 126' and 226'.

[0028] Next, a gate spacer 38 is formed on the sidewall of the dummy gate stack 30. The corresponding process is Fig.18 The process flow 400 shown in FIG. 4 is also shown as process 414. According to some embodiments of the present disclosure, the gate spacer 38 is formed of dielectric material(s) such as silicon nitride, silicon carbonitride, etc., and may have a single layer structure or a multi-layer structure including multiple dielectric layers.

[0029] An etching process may be performed to etch portions of the protruding semiconductor fins 126' and 226' that are not covered by the dummy gate stack 30 and the gate spacers 38, thereby producing Figure 6 The corresponding process is shown in Fig.18 4 is shown as process 416 in the process flow 400 shown in FIG. The recess may be anisotropic so that portions of the protruding semiconductor fins 126′ and 226′ directly below the dummy gate stack 30 and the gate spacers 38 are protected and not etched. According to some embodiments, the top surfaces of the recessed semiconductor fins / strips 126 / 126′ and 226 / 226′ may be lower than the top surface 22A of the STI regions 22. The space left by the etched portions of the semiconductor fins / strips 126 / 126′ and 226 / 226′ is referred to as a recess 40, which includes portions on opposite sides of the dummy gate stack 30 and portions between the remaining portions of the protruding semiconductor fins 126′ and 226′.

[0030] Next, epitaxial regions (source / drain regions) 142 and 242 are formed by selectively growing (by epitaxy) semiconductor material in the recess 40, resulting in Figure 7 The corresponding process is Fig.18The process flow 400 shown in is shown as process 418. Depending on whether the resulting FinFET is a p-type FinFET or an n-type FinFET, p-type or n-type impurities can be in-situ doped as the epitaxy proceeds. For example, in the device region 100, silicon phosphorus (SiP), silicon carbon phosphorus (SiCP), etc. can be grown. In the device region 200, silicon germanium boron (SiGeB), silicon boron (SiB), etc. can be grown. According to alternative embodiments of the present disclosure, the epitaxial regions 142 and 242 include other types of semiconductor materials, for example, III-V compound semiconductors such as GaAs, InP, GaN, InGaAs, InAlAs, GaSb, AlSb, AlAs, AlP, GaP, combinations thereof, or multiple layers thereof.

[0031] After the epitaxial process, the epitaxial regions 142 and 242 may be further implanted with n-type impurities and p-type impurities, respectively, to form source and drain regions, which are also respectively labeled using reference numerals 142 and 242. According to an alternative embodiment of the present disclosure, when the epitaxial regions 142 and 242 are in-situ doped with n-type and p-type impurities during epitaxy, the implantation process is skipped.

[0032] Figure 8 FIG. 4 is a perspective view of the structure after forming a contact etch stop layer (CESL) 46 and an interlayer dielectric (ILD) 48. The corresponding process is shown in FIG. Fig.18 400 is shown as process 420. CESL 46 may be formed of silicon oxide, silicon nitride, silicon carbonitride, etc., and may be formed using CVD, ALD, etc. ILD 48 may include a dielectric material formed using, for example, FCVD, spin coating, CVD, or other deposition methods. ILD 48 may be formed of an oxygen-containing dielectric material (which may be a silicon oxide-based material, such as silicon oxide), phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), etc. A planarization process such as a CMP process or a mechanical grinding process may be performed to make the top surfaces of ILD 48, dummy gate stack 30, and gate spacer 38 flush with each other.

[0033] In a subsequent process, the dummy gate stack 30 including the hard mask layer 36, the dummy gate electrode 34 and the dummy gate dielectric 32 is etched to form a trench 52 between the gate spacers 38, such as Fig. 9 The corresponding process is Fig.18 The process flow 400 shown in FIG. 4 is shown as process 422 . The top surfaces and sidewalls of the protruding semiconductor fins 126 ′ and 226 ′ are exposed to the trenches 52 .

[0034] According to some embodiments, after removing the dummy gate stack 30 , a fin thinning process is performed to thin the protruding semiconductor fins 126 ′ and / or 226 ′ to improve gate control and reduce fin width variation. Fig.18 The process flow 400 shown in FIG. is shown as process 424. In the following paragraphs, reference is made to Figures 11 to 13 The details of the fin thinning process are discussed in detail. According to other embodiments, the fin thinning process is not performed at this stage. Instead, the fin thinning process may be performed while forming the trench 23 ( Figure 2 ) but after forming the STI region ( Figure 3 ) before, or before Figure 4 The STI region 22 is shown recessed and then a fin thinning process is performed.

[0035] Next, if Fig.10 As shown, in the groove 52 ( Fig. 9 ) to form replacement gate stacks 160 and 260. The corresponding process is Fig.18 The process flow 400 shown in FIG. 4 is shown as process 426. The gate stack 160 includes a gate dielectric 156 and a gate electrode 158, and the gate stack 260 includes a gate dielectric 256 and a gate electrode 258. According to some embodiments of the present disclosure, each of the gate dielectrics 156 and 256 includes an interfacial layer (IL) as its lower portion. The IL is formed on the exposed surface of the protruding semiconductor fins 126' and 226'. The IL may include an oxide layer, for example, a silicon oxide layer, which is formed by thermal oxidation, chemical oxidation process or deposition process of the protruding semiconductor fins 126' and 226'. The gate dielectrics 156 and 256 may also include (one or more) high-k dielectric layers formed above the corresponding IL. The high-k dielectric layer includes a high-k dielectric material, for example, hafnium oxide, lanthanum oxide, aluminum oxide, zirconium oxide, etc. The dielectric constant (k value) of the high-k dielectric material is higher than 3.9, and may be higher than about 7.0, sometimes up to 21.0 or higher. The high-k dielectric layer is formed as a conformal layer and extends over sidewalls of the protruding semiconductor fins 126' and 226' and sidewalls of the gate spacers 38. According to some embodiments of the present disclosure, the high-k dielectric layer is formed using ALD, CVD, PECVD, molecular beam deposition (MBD), or the like.

[0036] Further references Fig.10 , gate electrodes 158 and 258 are formed on gate dielectrics 156 and 256, respectively. Each of gate electrodes 158 and 258 may include a plurality of stacked metal layers (which may be formed as conformal layers) and a fill metal region that fills the remainder of the corresponding trench 52. The stacked metal layers may include a barrier layer, a work function layer over the barrier layer, and one or more metal capping layers on the work function layer.

[0037] Fig.10 Also shown is the formation of hard masks 162 and 262 according to some embodiments. Fig.18 The process flow 400 shown in FIG. 4 is shown as process 428. The formation of hard masks 162 and 262 may include performing an etching process to recess gate stacks 160 and 260 so that a recess is formed between opposing portions of gate spacers 38, filling the recess with a dielectric material, and then performing a planarization process (e.g., a CMP process or a mechanical grinding process) to remove excess portions of the dielectric material. Hard masks 162 and 262 may be formed of silicon nitride, silicon oxynitride, carbon oxynitride, and the like. Thus, FinFETs 164 and 264 are formed in device regions 100 and 200, respectively. In subsequent processes, source / drain silicide regions, source / drain contact plugs, gate contact plugs, and the like are formed.

[0038] Figures 11 to 13 FIG. 4 shows a cross-sectional view of a fin thinning process according to some embodiments of the present disclosure. The fin thinning process may be performed in various stages. For example, in Figure 2 After forming the groove 23 as shown, Figure 4 After the recessed STI region 22 is shown, or after the dummy gate stack is removed to form the trench 52 ( Fig. 9 ) and then a fin thinning process is performed. During these stages, the sidewalls of the protruding semiconductor fins 126' and 226' or semiconductor strips 126 and 226 are exposed, allowing the fin thinning process to be performed. A cross-sectional view of the structure in the device region 100 ( Figures 11 to 13 ) can be obtained from Figure 4 or Fig. 9 The cross-sectional view of the structure in the device region 200 can be obtained from the reference cross-sectional view AA in FIG. 1 , depending on when the fin thinning process is performed. Figure 4 or Fig. 9 The reference cross section BB in is obtained, depending on when the fin thinning process is performed. It can also be obtained by applying Figures 11 to 13 The process shown in Figure 2 The fin thinning process is performed on the structure shown. The resulting structure is similar to Figure 2 , and the semiconductor strips and corresponding silicon portions and silicon germanium (or germanium) portions are narrowed due to fin thinning.

[0039] Fig.14 A process flow 300 of a fin thinning process according to some embodiments is shown, referring to Figures 11 to 13 The process flow is discussed. Fig.14 In process 302, the protruding semiconductor fins 126' and 226' are formed to protrude higher than the top surface of the adjacent STI region 22, which process also corresponds to Figure 4 and Fig. 9The resulting cross-sectional view is shown in Fig.11 . In addition, in process flow 300, the first type fin (fin for forming the first type FinFET) and the second type fin (fin for forming the second type FinFET) have opposite conductivity types, and the first type fin can be an n-type fin or a p-type fin, and the second type fin can be a p-type fin or an n-type fin. In the example discussed below, it is assumed that the protruding semiconductor fin 126' (first type fin) is formed of silicon and the protruding semiconductor fin 226' (second type fin) is formed of silicon germanium or germanium. It should be understood that the protruding semiconductor fins 126' and 226' can also be formed of other materials.

[0040] References Fig.14 In the process 304 shown, the widths Wm1 and Wm2 of the protruding semiconductor fins 126' and 226' are measured ( Fig.11 ). Optical measurement methods may be used for measurement, for example, critical dimension scanning electron microscopy (CDSEM), optical critical dimension (OCD) spectroscopy, etc. In process 306 ( Fig.14 ), the measured widths Wm1 and Wm2 are compared to the target widths Wt1 and Wt2 of the protruding semiconductor fins 126' and 226', respectively. The target widths Wt1 and Wt2 are the expected widths of the protruding semiconductor fins 126' and 226', respectively. For example, if the fin width difference (Wm1-Wt1) is equal to zero or a negative value, the protruding semiconductor fin 126' is not thinned. If the fin width difference (Wm2-Wt2) is equal to zero or a negative value, the protruding semiconductor fin 226' is not thinned. Otherwise, if one or both of the differences (Wm1-Wt1) and (Wm2-Wt2) are positive values, the corresponding protruding semiconductor fins 126' and 226' are thinned, and the execution is performed. Fig.14 In the process 308. In the example shown, it is assumed that both protruding semiconductor fins 126' and 226' need to be thinned. If one of the protruding semiconductor fins 126' and 226' does not need to be thinned, the corresponding etching scheme generation process, fin thinning process, post-thinning re-measurement process, and re-processing process for the corresponding fin are skipped.

[0041] Based on the measurement results such as the differences (Wm1-Wt1) and (Wm2-Wt2), an etching scheme for thinning the semiconductor fins 126' and 226' is generated, such as Fig.14308 in the process. The etching scheme includes, but is not limited to, etching duration, type of etching chemistry, temperature of etching chemistry and wafer 10, concentration of etching chemistry (when wet etching is used), flow rate and pressure of etching gas (when dry etching is used), etc. For example, if the difference (Wm1-Wt1) is high, a higher temperature, a higher concentration, a longer etching duration, etc. may be used. On the contrary, if the difference (Wm1-Wt1) is small, a lower temperature, a lower concentration, a shorter etching duration, etc. may be used.

[0042] refer to Fig.14 In process 310, the protruding semiconductor fin 126' (first type fin) is thinned using an etching chemistry that etches the protruding semiconductor fin 126', while the etching rate of the protruding semiconductor fin 226' is lower. During etching, the two protruding semiconductor fins 126' and 226' ( Fig.11 ) are exposed to the etching chemistry. Therefore, it is desirable that the first etch selectivity (which is the ratio of the etch rate of the protruding semiconductor fin 126' to the etch rate of the protruding semiconductor fin 226') is as high as possible to keep the etching of the semiconductor fin 226' minimized. For example, the first etch selectivity may be higher than about 5, and may be in a range between about 5 and 20 (or higher).

[0043] According to some embodiments in which the protruding semiconductor fin 126' is a silicon fin, the etching may be performed using a wet etch, and the etching chemistry may include (one or more) organic or inorganic alkaline substances. For example, the etching chemistry may include a metal hydroxide (M n+ (OH - ) n ), amine derivatives or combinations thereof. The metal hydroxide may include NaOH, KOH, LiOH, RbOH, CsOH, or mixtures thereof. An ionic surfactant (e.g., quaternary ammonium (-R4N + ), sulfate (-OSO3 - ), sulfonate (-SO3 - ), phosphate, carboxylate (-COO - ) derivatives) or non-ionic surfactants (e.g., alcohol ethoxylates, alkylphenol ethoxylates, fatty acid ethoxylates, fatty amine ethoxylates, glycol esters, glycerides) to reduce the surface tension of the etching chemicals. The amine derivatives may include ammonia, tetramethylammonium hydroxide (TMAH), tetraethylammonium hydroxide (TEAH), tetradecyltrimethylammonium hydroxide (TTAH), tetrabutylammonium hydroxide (TBAH), etc., or a combination thereof. Fig.16The chemical structure of an amine derivative is shown, which includes an OH group, a nitrogen atom, and R1, R2, R3, and R4 bonded to the nitrogen atom. Each of R1, R2, R3, and R4 may be a hydrogen atom or one of the functional groups C1 to C20. The functional groups C1 to C20 may include amines, alcohols, halides, esters, ketones, acids, alkanes, olefins, alkynes, ethers, sulfides, aldehydes, imines, nitriles, aromatics, thiols, and the like. In the etching process, the temperature of the etching chemical may be in a range between about 5° C. and about 90° C.

[0044] Due to the higher first etch selectivity, the protruding semiconductor fins 226 ′ are substantially not etched even though the protruding semiconductor fins 226 ′ are also exposed to the same etch chemistry as the protruding semiconductor fins 126 ′.

[0045] The protruding semiconductor fins 126' and 226' undergo a fin thinning process such as Fig.12 After the thinning of the protruding semiconductor fin 126', the width Wm1' of the protruding semiconductor fin 126' is measured again, as shown in FIG. Fig.14 310. The measured width Wm1' may then be compared again to the target width Wt1. If the fin width difference (Wm1'-Wt1) is a positive value, the process loops back to process 308 to perform a reprocessing process, which includes processes 308 and 310. Therefore, another etching scheme is generated based on the fin width difference (Wm1'-Wt1), and then the protruding semiconductor fin 126' is etched again using the newly generated etching scheme, which may be different from the etching scheme previously generated for the first etching of the protruding fin 126'. Otherwise, if (Wm1'-Wt1) is equal to or less than 0, no reprocessing is performed, and the process proceeds to thinning of the protruding semiconductor fin 226' instead of looping back to process 308.

[0046] As described above, the etching scheme may include different process conditions. In addition, the generated etching scheme may include different concentrations of etching chemicals. Therefore, when the concentration of the etching chemical is high, the etching rate of the protruding semiconductor fin 126' is high, and when the concentration of the etching chemical is low, the etching rate of the protruding semiconductor fin 126' is low. Different concentrations of etching chemicals can be determined based on the fin width difference (Wm1-Wt1) and (Wm1'-Wt1). For example, since the fin width difference (Wm1-Wt1) is greater than (Wm1'-Wt1), the concentration of the etching chemical when the protruding semiconductor fin 126' is thinned for the first time can be higher than the concentration in the reprocessing process. Fig.17 An apparatus for providing an etching chemistry and adjusting the concentration of the etching chemistry based on the generated recipe is shown.

[0047] refer to Fig.17, a wafer 10 is provided for fin thinning, and an etching chemical 340 is sprayed from a nozzle 348 onto the surface of the wafer 10. A pipe 346 is connected between the nozzle 348 and the storage devices 342 and 344. According to some examples, the storage device 342 is used to store the etching chemical, and the storage device 344 is used to store deionized water. A valve 350 is connected between the storage device 344 and the pipe 346, and is configured to open, close, and regulate the flow of deionized water. During the fin thinning process, the control unit 338 (also in Fig.14 34) controls the operation of valve 350 to increase (or not increase) the desired flow of deionized water. Deionized water enters conduit 346 and mixes with the etching chemistry from storage device 342. The ideal flow rates of etching chemistry and deionized water are determined based on the etching protocol, and when the relative flow of deionized water is greater, the resulting etching chemistry sprayed from nozzle 348 is more diluted and the concentration of the etching chemistry is low, and vice versa.

[0048] After etching and possible reprocessing of the protruding semiconductor fin 126', if the measured width Wm2 ( Fig.11 ) indicates that it needs to be thinned, then the protruding semiconductor fin 226' is thinned. The resulting structure is as follows Fig.13 Otherwise, skip Fig.14 The processes 314, 316 and 318 are shown, and the resulting fins in the final structure have Fig.12 Shape shown. Fig.14 Process 314 in illustrates etching of protruding semiconductor fin 226'. Thinning is performed using an etching chemistry that etches protruding semiconductor fin 226', and the etching rate of protruding semiconductor fin 126' is low. During etching, both protruding semiconductor fins 126' and 226 are exposed to the etching chemistry. Therefore, it is desirable that the second etching selectivity (i.e., the ratio of the etching rate of protruding semiconductor fin 226' to the etching rate of protruding semiconductor fin 126') is as high as possible to keep the etching of semiconductor fin 126' minimized. For example, the second etching selectivity can be higher than about 5, and can be in a range between about 5 and 20 (or higher).

[0049] According to some embodiments in which the protruding semiconductor fin 226' is a silicon germanium fin or a germanium fin, the etching may be performed using wet etching, and the etching chemistry may include (one or more) organic or inorganic alkaline substances and (one or more) oxidants. The (one or more) organic or inorganic alkaline substances may be the same as or different from the (one or more) organic or inorganic alkaline substances used to thin the protruding semiconductor fin 126'. For example, the etching chemistry may include a metal hydroxide (M n+ (OH - ) n), amine derivatives, or combinations thereof. The metal hydroxide may include NaOH, KOH, LiOH, RbOH, CsOH, or mixtures thereof. An ionic surfactant (e.g., quaternary ammonium (-R4N + ), sulfate (-OSO3 - ), sulfonate (-SO3 - ), phosphate, carboxylate (-COO - ) derivatives) or non-ionic surfactants (e.g., alcohol ethoxylates, alkylphenol ethoxylates, fatty acid ethoxylates, fatty amine ethoxylates, glycol esters, glycerides) to reduce the surface tension of the etching chemicals. The amine derivatives may include ammonia, TMAH, TEAH, TTAH, TBAH, etc., or a combination thereof. The oxidant may include dissolved ozone in deionized water (DIO3), hydrogen peroxide (H2O2), or a combination thereof. The etching chemicals used to etch the protruding semiconductor fins 226' do not substantially corrode the protruding semiconductor fins 126'. Therefore, although the protruding semiconductor fins 126' are also exposed to the same etching chemicals as the protruding semiconductor fins 226', the protruding semiconductor fins 126' are substantially not etched. During etching, the temperature of the etching chemicals may be in a range between about 5°C and about 90°C.

[0050] As described above, the (one or more) organic or inorganic alkaline substances used to etch the protruding semiconductor fins 126' do not substantially corrode the protruding semiconductor fins 226'. An oxidant is added to oxidize the protruding semiconductor fins 226', and the resulting silicon germanium oxide or germanium oxide can be etched by the above-mentioned (one or more) organic or inorganic alkaline substances. Therefore, by the oxidation process, the protruding semiconductor fins 226' can also be thinned. On the other hand, the oxidation process also results in the production of silicon oxide on the protruding semiconductor fins 126'. (One or more) organic or inorganic alkaline substances cannot etch silicon oxide. In addition, the oxidation of silicon is significantly slower than silicon germanium and germanium. Therefore, when the protruding semiconductor fins 226' are thinned, the protruding semiconductor fins 126' are substantially not thinned.

[0051] According to some embodiments, (one or more) organic or inorganic alkaline substances and oxidants are mixed in the same etching chemistry to etch the protruding semiconductor fins 226'. According to other embodiments, (one or more) organic or inorganic alkaline substances and oxidants are in separate solutions, wherein the oxidant is first used to oxidize the protruding semiconductor fins 126' and 226' to form an oxide. An alkaline solution is then applied to the wafer 10 to remove the resulting oxide, and then the alkaline solution is removed. The cycle including the oxidant application and the alkaline application may or may not be repeated.

[0052] After thinning of the protruding semiconductor fin 226', the width Wm2' of the protruding semiconductor fin 226' is measured again, as shown in FIG. Fig.14 316 in FIG. 31. The measured width Wm2' is then compared again to the target width Wt2. If the fin width difference (Wm2'-Wt2) has a positive value, the process loops back to process 318, and then back to process 316 to reprocess the thinning of the protruding semiconductor fin 226'. Therefore, another etching scheme is generated based on the fin width difference (Wm2'-Wt2) (process 318), and then the newly generated etching scheme is used to thin the protruding semiconductor fin 226' again. Otherwise, if (Wm2'-Wt2) is equal to or less than 0, no reprocessing is performed.

[0053] According to some embodiments of the present disclosure, instead of measuring and reworking the protruding semiconductor fins 126 ′ before measuring and thinning the protruding semiconductor fins 226 ′, the protruding semiconductor fins 126 ′ may be measured after thinning of the protruding semiconductor fins 226 ′. Fig.15 The corresponding process flow 300' is shown. The process flow 300' is similar to Fig.14 The process flow 300 is similar to that in the process flow 300, except that re-measurement and re-processing (if necessary) of the fin width is performed after both types (n-type and p-type) of fins are thinned (process 310'). Accordingly, the widths of both protruding semiconductor fins 126' and 226' are re-measured, and if one type or both protruding semiconductor fins 126' and 226' require re-processing, the process returns to process 308 to re-process the corresponding protruding semiconductor fins 126' and 226'.

[0054] refer to Fig.13, according to some example embodiments, the structure in the device region 100 is discussed as follows. The structure in the device region 200 may have substantially the same profile, so the profile is not discussed again. According to some embodiments of the present disclosure, in the thinning of the protruding semiconductor fins 126' and 226', the STI region 22 may be slightly recessed, and the sidewalls of the portions of the protruding semiconductor fins 126' and 226' in the recessed portion of the STI region 22 are also exposed. The newly exposed sidewalls of the protruding semiconductor fins 126' and 226' are also etched, forming a transition region 126T. The sidewalls of the transition region 126T are less inclined than the sidewalls of the semiconductor strips 126 below and above the protruding semiconductor fins 126'. According to some embodiments, the inclination angle θ1 of the sidewalls of the transition region 126T is in a range between about 5° and about 85°. The transition angle θ2 is in a range between about 95° and about 175°. The sidewall SW1 of the top of the protruding fin 126' may be in a first plane P1 that is parallel to a second plane P2 of the sidewall SW2 of the semiconductor strip 126. The protruding semiconductor fin 126' may be trimmed by an amount ΔW on each side that is in a range between about 0.2 nm and about 30 nm. The height H3 of the transition region 126T may be equal to or greater than 0.5*ΔW and equal to or less than about 5*ΔW. After fin thinning, the fin width Wm1' may be in a range between about 2 nm and about 50 nm. The height H1 of the STI region 22 may be in a range between about 30 nm and about 100 nm. The fin height H2 may be in a range between about 5 nm and about 100 nm. The bottom width Wb of the semiconductor strip 126 may be in a range between about 2.2 nm and about 80 nm.

[0055] In the fin thinning process, the control unit 338 ( Fig.14 , 15 and 17) for electrically and signally communicating with and controlling various tools used in the fin thinning process. The control unit 338 controls the actions involved in the fin thinning process, including but not limited to: measurement and re-measurement of fin width, determination of whether fin thinning is required, generation of etching schemes, and fin thinning processes. The control unit 338 and the tools combine to form an advanced process control (APC) system for automated measurement, thinning, and reprocessing of fin thinning.

[0056] Embodiments of the present disclosure have some advantageous features. By first measuring the fin width, an etching scheme can be determined to ensure that the width of the etched fin falls within the desired range. An etching scheme can be generated based on the measurement results to customize the etching of each wafer and each type of fin. Re-measurement and reprocessing further improve the accuracy of the fin width. The present application can be applied to a single wafer fin thinning process or a batch fin process, wherein selected sample wafers in a batch of wafers (rather than each wafer) can be measured to increase production. With more precise fin width control, gate control can be improved, current density can be improved, and threshold voltage can be better controlled.

[0057] According to some embodiments of the present disclosure, a method includes: forming an isolation region extending into a semiconductor substrate, wherein a first semiconductor strip is located between the isolation regions; recessing the isolation region, wherein a top of the first semiconductor strip protrudes above a top surface of the isolation region to form a first semiconductor fin; measuring a first fin width of the first semiconductor fin; generating a first etching scheme based on the first fin width; and performing a first thinning process on the first semiconductor fin using the first etching scheme. In an embodiment, the method further includes: re-measuring a second fin width of the first semiconductor fin after the first thinning process. In an embodiment, the method further includes: after re-measuring the second fin width: generating a second etching scheme based on the second fin width; and performing a second thinning process on the first semiconductor fin using the second etching scheme. In an embodiment, the method further includes: measuring a third fin width of the second semiconductor fin, wherein the first semiconductor fin and the second semiconductor fin are formed of different materials; generating a third etching scheme based on the third fin width; and performing a third thinning process on the second semiconductor fin using the third etching scheme. In an embodiment, in a first thinning process, the second semiconductor fin is exposed to a first etching chemistry for the first thinning process and the second semiconductor fin is substantially not thinned, and wherein, in a third thinning process, the first semiconductor fin is exposed to a second etching chemistry for the third thinning process and the first semiconductor fin is substantially not thinned. In an embodiment, generating a first etching scheme includes: determining a difference between a first fin width and a target fin width of the first semiconductor fin; and determining an etching time for the first thinning process based on the difference. In an embodiment, the first thinning process is performed using wet etching. In an embodiment, the method also includes forming a dummy gate stack on the first semiconductor fin thinned by the first thinning process. In an embodiment, the method also includes forming a dummy gate stack on the first semiconductor fin; forming gate spacers on opposite sides of the dummy gate stack; and removing the dummy gate stack to form a groove between the gate spacers, wherein the first thinning process is performed through the groove.

[0058] According to some embodiments of the present disclosure, a method includes: forming a first semiconductor fin that protrudes above a first isolation region on an opposite side of the first semiconductor fin, wherein the first semiconductor fin is formed of a first semiconductor material; forming a second semiconductor fin that protrudes above a second isolation region on an opposite side of the second semiconductor fin, wherein the second semiconductor fin is formed of a second semiconductor material different from the first semiconductor material; measuring a first fin width of the first semiconductor fin; measuring a second fin width of the second semiconductor fin; thinning the first semiconductor fin based on the first fin width using a first etching chemistry, wherein when the first semiconductor fin is thinned, the second semiconductor fin is exposed to the first etching chemistry; and thinning the second semiconductor fin based on the second fin width. In an embodiment, when the first semiconductor fin is thinned, the first semiconductor fin has a first etching rate, and the second semiconductor fin has a second etching rate less than the first etching rate. In an embodiment, the second semiconductor fin is thinned using a second etching chemistry, and when the second semiconductor fin is thinned, the first semiconductor fin is exposed to the second etching chemistry. In an embodiment, when the second semiconductor fin is thinned, the first semiconductor fin has a third etching rate, and the second semiconductor fin has a fourth etching rate greater than the third etching rate. In an embodiment, the method further includes: forming a first gate over a first semiconductor fin; forming a first source / drain region based on the first semiconductor fin and on an opposite side of the first gate; forming a second gate over a second semiconductor fin; and forming a second source / drain region based on the second semiconductor fin and on an opposite side of the second gate, wherein the first source / drain region and the second source / drain region have opposite conductivity types.

[0059] According to some embodiments of the present disclosure, a method includes: forming a first semiconductor region, wherein a sidewall of the first semiconductor region is exposed; measuring a first width of the first semiconductor region; generating a first etching scheme based on the first width of the first semiconductor region and a first target width, wherein the first target width is an expected width of the first semiconductor region; and etching the first semiconductor region using the first etching scheme. In an embodiment, when the first semiconductor region is etched, the first semiconductor region protrudes above a top surface of a bulk semiconductor material below the first semiconductor region, and the top surface is exposed to an etching chemical for etching the first semiconductor region. In an embodiment, when the first semiconductor region is etched, the first semiconductor region protrudes above a top surface of an isolation region, and the top surface of the isolation region is exposed to an etchant for etching the first semiconductor region. In an embodiment, when the first semiconductor region is etched, the first semiconductor region is located in a trench between gate spacers. In an embodiment, etching of the first semiconductor region is performed using a wet etching process. In an embodiment, the first semiconductor region is etched using an etching chemical, and when the first semiconductor region is etched, the sidewall of the second semiconductor region is exposed to the etching chemical, and the method further includes forming an n-type transistor based on the first semiconductor region; and forming a p-type transistor based on the second semiconductor region.

[0060] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art should understand that they can easily use the present disclosure as a basis for designing or modifying other processes and structures to achieve the same purpose of the embodiments or examples introduced herein and / or achieve the same advantages of the embodiments or examples introduced herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and they can make various changes, substitutions and modifications herein without departing from the spirit and scope of the present disclosure.

[0061] Example 1 is a method for thinning semiconductor fins, comprising: forming isolation regions extending into a semiconductor substrate, wherein a first semiconductor strip is located between the isolation regions; recessing the isolation regions, wherein a top of the first semiconductor strip protrudes above a top surface of the isolation region to form a first semiconductor fin; measuring a first fin width of the first semiconductor fin; generating a first etching scheme based on the first fin width; and performing a first thinning process on the first semiconductor fin using the first etching scheme.

[0062] Example 2 is the method of Example 1, further comprising: re-measuring a second fin width of the first semiconductor fin after the first thinning process.

[0063] Example 3 is the method of Example 2, further comprising, after re-measuring the second fin width: generating a second etching scheme based on the second fin width; and performing a second thinning process on the first semiconductor fin using the second etching scheme.

[0064] Example 4 is the method described in Example 1, further comprising: measuring a third fin width of a second semiconductor fin, wherein the first semiconductor fin and the second semiconductor fin are formed of different materials; generating a third etching scheme based on the third fin width; and performing a third thinning process on the second semiconductor fin using the third etching scheme.

[0065] Example 5 is the method described in Example 4, wherein, in the first thinning process, the second semiconductor fin is exposed to a first etching chemistry used for the first thinning process and the second semiconductor fin is substantially not thinned, and wherein, in the third thinning process, the first semiconductor fin is exposed to a second etching chemistry used for the third thinning process and the first semiconductor fin is substantially not thinned.

[0066] Example 6 is the method of Example 1, wherein generating the first etching scheme includes: determining a difference between the first fin width and a target fin width of the first semiconductor fin; and determining an etching time of the first thinning process based on the difference.

[0067] Example 7 is the method of Example 1, wherein the first thinning process is performed using wet etching.

[0068] Example 8 is the method of Example 1, further comprising: forming a dummy gate stack on the first semiconductor fin thinned by the first thinning process.

[0069] Example 9 is the method described in Example 1, further comprising: forming a dummy gate stack on the first semiconductor fin; forming a gate spacer on an opposite side of the dummy gate stack; and removing the dummy gate stack to form a groove between the gate spacers, wherein the first thinning process is performed through the groove.

[0070] Example 10 is a method for thinning a semiconductor fin, comprising: forming a first semiconductor fin, the first semiconductor fin protruding above a first isolation region on an opposite side of the first semiconductor fin, wherein the first semiconductor fin is formed of a first semiconductor material; forming a second semiconductor fin, the second semiconductor fin protruding above a second isolation region on an opposite side of the second semiconductor fin, wherein the second semiconductor fin is formed of a second semiconductor material different from the first semiconductor material; measuring a first fin width of the first semiconductor fin; measuring a second fin width of the second semiconductor fin; thinning the first semiconductor fin based on the first fin width using a first etching chemistry, wherein the second semiconductor fin is exposed to the first etching chemistry when the first semiconductor fin is thinned; and thinning the second semiconductor fin based on the second fin width.

[0071] Example 11 is the method of Example 10, wherein when the first semiconductor fin is thinned, the first semiconductor fin has a first etch rate and the second semiconductor fin has a second etch rate less than the first etch rate.

[0072] Example 12 is the method of Example 10, wherein the second semiconductor fin is thinned using a second etch chemistry, and the first semiconductor fin is exposed to the second etch chemistry while the second semiconductor fin is thinned.

[0073] Example 13 is the method of Example 12, wherein the first semiconductor fin has a third etch rate when the second semiconductor fin is thinned, and the second semiconductor fin has a fourth etch rate greater than the third etch rate.

[0074] Example 14 is the method described in Example 10, further including: forming a first gate above the first semiconductor fin; forming a first source / drain region based on the first semiconductor fin and on an opposite side of the first gate; forming a second gate above the second semiconductor fin; and forming a second source / drain region based on the second semiconductor fin and on an opposite side of the second gate, wherein the first source / drain region and the second source / drain region have opposite conductivity types.

[0075] Example 15 is a method for thinning a semiconductor fin, comprising: forming a first semiconductor region, wherein sidewalls of the first semiconductor region are exposed; measuring a first width of the first semiconductor region; generating a first etching scheme based on the first width of the first semiconductor region and a first target width, wherein the first target width is an expected width of the first semiconductor region; and etching the first semiconductor region using the first etching scheme.

[0076] Example 16 is the method described in Example 15, wherein, when the first semiconductor region is etched, the first semiconductor region protrudes above a top surface of a bulk semiconductor material underlying the first semiconductor region, and the top surface is exposed to an etching chemical used to etch the first semiconductor region.

[0077] Example 17 is the method described in Example 15, wherein when the first semiconductor region is etched, the first semiconductor region protrudes higher than a top surface of an isolation region, and the top surface of the isolation region is exposed to an etchant used to etch the first semiconductor region.

[0078] Example 18 is the method of Example 15, wherein when the first semiconductor region is etched, the first semiconductor region is located in a trench between gate spacers.

[0079] Example 19 is the method of Example 15, wherein etching the first semiconductor region is performed using a wet etching process.

[0080] Example 20 is the method described in Example 15, wherein the first semiconductor region is etched using an etching chemical, and when the first semiconductor region is etched, the sidewalls of the second semiconductor region are exposed to the etching chemical, and the method further includes: forming an n-type transistor based on the first semiconductor region; and forming a p-type transistor based on the second semiconductor region.

Claims

1. A method for thinning a semiconductor fin, comprising: forming isolation regions extending into the semiconductor substrate, wherein the first semiconductor strip is located between the isolation regions; recessing the isolation region, wherein a top portion of the first semiconductor strip protrudes above a top surface of the isolation region to form a first semiconductor fin; measuring a first fin width of the first semiconductor fin; generating a first etching scheme based on the first fin width; and performing a first thinning process on the first semiconductor fin using the first etching scheme, Wherein, generating the first etching scheme includes: determining a difference between the first fin width and a target fin width of the first semiconductor fin; and An etching time of the first thinning process is determined based on the difference.

2. The method according to claim 1, further comprising: After the first thinning process, a second fin width of the first semiconductor fin is remeasured.

3. The method according to claim 2, further comprising, after re-measuring the second fin width: generating a second etching scheme based on the second fin width; and A second thinning process is performed on the first semiconductor fin using the second etching scheme.

4. The method according to claim 1, further comprising: measuring a third fin width of a second semiconductor fin, wherein the first semiconductor fin and the second semiconductor fin are formed of different materials; generating a third etching scheme based on the third fin width; and A third thinning process is performed on the second semiconductor fin using the third etching scheme.

5. The method according to claim 4, wherein: In the first thinning process, the second semiconductor fin is exposed to a first etch chemistry for the first thinning process and the second semiconductor fin is substantially not thinned, and wherein, in the third thinning process, the first semiconductor fin is exposed to a second etch chemistry for the third thinning process and the first semiconductor fin is substantially not thinned.

6. The method according to claim 1, wherein: The first thinning process is performed using wet etching.

7. The method according to claim 1, further comprising: A dummy gate stack is formed on the first semiconductor fin thinned by the first thinning process.

8. The method according to claim 1, further comprising: forming a dummy gate stack on the first semiconductor fin; forming gate spacers on opposite sides of the dummy gate stack; as well as The dummy gate stack is removed to form a groove between the gate spacers, wherein the first thinning process is performed through the groove.

9. A method for thinning a semiconductor fin, comprising: forming a first semiconductor fin that protrudes above first isolation regions on opposite sides of the first semiconductor fin, wherein the first semiconductor fin is formed of a first semiconductor material; forming a second semiconductor fin that protrudes above a second isolation region on an opposite side of the second semiconductor fin, wherein the second semiconductor fin is formed of a second semiconductor material different from the first semiconductor material; measuring a first fin width of the first semiconductor fin; measuring a second fin width of the second semiconductor fin; thinning the first semiconductor fin based on the first fin width using a first etch chemistry, wherein the second semiconductor fin is exposed to the first etch chemistry while the first semiconductor fin is thinned; and The second semiconductor fin is thinned based on the second fin width.

10. The method according to claim 9, wherein: When the first semiconductor fin is thinned, the first semiconductor fin has a first etch rate, and the second semiconductor fin has a second etch rate that is less than the first etch rate.

11. The method according to claim 9, wherein: The second semiconductor fin is thinned using a second etch chemistry, and the first semiconductor fin is exposed to the second etch chemistry while the second semiconductor fin is thinned.

12. The method according to claim 11, wherein: When the second semiconductor fin is thinned, the first semiconductor fin has a third etch rate, and the second semiconductor fin has a fourth etch rate greater than the third etch rate.

13. The method according to claim 9, further comprising: forming a first gate over the first semiconductor fin; forming a first source / drain region based on the first semiconductor fin and on opposite sides of the first gate; forming a second gate over the second semiconductor fin; as well as A second source / drain region is formed based on the second semiconductor fin and on an opposite side of the second gate, wherein the first source / drain region and the second source / drain region have opposite conductivity types.

14. A method for thinning a semiconductor fin, comprising: forming a first semiconductor region, wherein a sidewall of the first semiconductor region is exposed; measuring a first width of the first semiconductor region; generating a first etching scheme based on the first width and a first target width of the first semiconductor region, wherein the first target width is an expected width of the first semiconductor region; and etching the first semiconductor region using the first etching scheme, Wherein, generating the first etching scheme includes: determining a difference between the first width of the first semiconductor region and the first target width; and An etching time for etching the first semiconductor region is determined based on the difference.

15. The method according to claim 14, wherein: When the first semiconductor region is etched, the first semiconductor region protrudes above a top surface of a bulk semiconductor material underlying the first semiconductor region, and the top surface is exposed to an etching chemistry used to etch the first semiconductor region.

16. The method according to claim 14, wherein: When the first semiconductor region is etched, the first semiconductor region protrudes higher than a top surface of the isolation region, and the top surface of the isolation region is exposed to an etchant for etching the first semiconductor region.

17. The method according to claim 14, wherein: When the first semiconductor region is etched, the first semiconductor region is located in the trenches between the gate spacers.

18. The method according to claim 14, wherein: The etching of the first semiconductor region is performed using a wet etching process.

19. The method according to claim 14, wherein: The first semiconductor region is etched using an etching chemistry, and when the first semiconductor region is etched, a sidewall of the second semiconductor region is exposed to the etching chemistry, and the method further comprises: forming an n-type transistor based on the first semiconductor region; and A p-type transistor is formed based on the second semiconductor region.

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