Method for forming a self-aligned interconnect structure

Abstract

The present disclosure relates to a method for forming a self-aligned interconnect structure. The present disclosure provides a method for forming an interconnect structure. The method includes: providing a semiconductor structure, the semiconductor structure including a substrate and a conductive feature formed in a top portion of the substrate; depositing a resist layer on the substrate, wherein the resist layer has an exposure threshold; providing radiation with an incident exposure dose to the resist layer, wherein the incident exposure dose is configured to be less than the exposure threshold of the resist layer, and the sum of the reflected exposure dose and the incident exposure dose from the top surface of the conductive feature is greater than the exposure threshold of the resist layer, thereby forming a latent resist pattern on the conductive feature; and developing the resist layer to form a patterned resist layer.

Description

Technical Field

[0001] The present disclosure relates to methods for forming self-aligned interconnect structures. Background Art

[0002] The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advances in IC materials and design have produced generations of ICs, each with smaller and more complex circuits than the previous one. Over the course of IC evolution, functional density (i.e., the number of interconnected devices per unit chip area) has generally increased, while geometry size (i.e., the smallest component (or line) that can be created using a manufacturing process) has decreased. This shrinking process generally provides benefits by increasing production efficiency and reducing associated costs. This shrinking has also increased the complexity of processing and manufacturing ICs.

[0003] ICs are typically formed by depositing a series of material layers, some of which are formed using a photolithography process. It is very important that the patterned layers are properly aligned or overlapped with adjacent layers. As modern IC geometries decrease, proper alignment and overlap become increasingly difficult. For interconnect structures, overlay errors may reduce the contact area (i.e., the contact area between the via and the metal line) and introduce resistance drift. In addition, overlay errors may cause short circuits, which can lead to chip failure. In addition, the photolithography process is a significant factor in the overall manufacturing cost, including processing time and the cost of the masks (also called photomasks or reticles) used in the process. Therefore, a photolithography method is needed to reduce the impact of overlay errors as the process overlap margins shrink with advancements in technology nodes. Summary of the invention

[0004] According to one embodiment of the present disclosure, a method for photolithography patterning is provided, comprising: providing a semiconductor structure, the semiconductor structure comprising a substrate and a conductive feature formed in a top portion of the substrate; depositing a resist layer over the substrate, wherein the resist layer has an exposure threshold; providing radiation having an incident exposure dose to the resist layer, wherein the incident exposure dose is configured to be less than the exposure threshold of the resist layer, and the sum of the incident exposure dose and a reflected exposure dose from a top surface of the conductive feature is greater than the exposure threshold of the resist layer, thereby forming a latent resist pattern over the conductive feature; and developing the resist layer to form a patterned resist layer.

[0005] According to another embodiment of the present disclosure, a method for photolithographic patterning is provided, comprising: forming a first conductive feature in a top portion of a substrate; forming a dielectric layer above the substrate; partially recessing the dielectric layer to form a groove above the first conductive feature; coating a resist layer above the dielectric layer, the resist layer filling the groove; exposing the resist layer to radiation, wherein an incident exposure dose of the radiation is configured to form a latent resist pattern in the groove; developing the resist layer to form an opening in the resist layer; etching the dielectric layer through the opening in the resist layer so that a portion of the groove extends through the dielectric layer; and forming a second conductive feature in the groove and contacting the second conductive feature with the first conductive feature.

[0006] According to another embodiment of the present disclosure, a semiconductor structure is provided, comprising: a substrate; a first conductive feature embedded in a top portion of the substrate; a dielectric layer located above the substrate; and a second conductive feature surrounded by the dielectric layer and in contact with the first conductive feature, the second conductive feature having a first sidewall and a second sidewall opposite to the first sidewall, wherein the first sidewall has a straight profile and is located above the first conductive feature, and wherein the second sidewall has a stepped profile and a top portion of the stepped profile is horizontally offset from an edge of the first conductive feature. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] When with Figure 1 When read together, various aspects of the present disclosure will be best understood from the following detailed description. It is emphasized that, in accordance with standard industry practice, various features are not drawn to scale. In fact, the size of various features may be arbitrarily increased or reduced for clarity of discussion.

[0008] Figure 1 is a cross-sectional view of a semiconductor structure in a semiconductor manufacturing process according to some embodiments of the present disclosure.

[0009] Figure 2 is a top view of a photomask having an integrated circuit (IC) design pattern according to some embodiments of the present disclosure.

[0010] Figure 3 and Figure 4 is a graphical view of various exposure dose curves in a photolithography exposure process according to various embodiments of the present disclosure.

[0011] Figure 5A , 5B and 5C are cross-sectional views of conductive features with high reflectivity according to some embodiments of the present disclosure.

[0012] Figure 6 is a diagrammatic view of a reflected exposure dose intensity distribution in a region above a semiconductor device in a photolithography exposure process according to some embodiments of the present disclosure.

[0013] Figure 7 is a flow chart of a method for fabricating a semiconductor structure having a self-aligned interconnect structure according to some embodiments of the present disclosure.

[0014] Figure 8 , 9 , 10, 11, 12, 13, 14, 15, 16, 17 and 18 are cross-sectional views of semiconductor structures using a single photolithography patterning process according to some embodiments of the present disclosure.

[0015] Fig.19A and 19B A flow chart of another method for fabricating a semiconductor structure having a self-aligned interconnect structure according to some embodiments of the present disclosure is shown.

[0016] Fig. 20 , 21 , 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34 and 35 are cross-sectional views of semiconductor structures using a double lithography patterning process according to some embodiments of the present disclosure.

[0017] Fig.36A , 36B , 36C, and 36D are various cross-sectional views of interfaces between conductive features and interconnect features according to some embodiments of the present disclosure. DETAILED DESCRIPTION

[0018] The following disclosure provides many different embodiments or examples for realizing different features of the subject matter provided. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are just examples and are not intended to be limiting. For example, in the following description, forming a first feature on or on a second feature may include an embodiment in which the first feature and the second feature are directly contacted to form, and may also include an embodiment in which additional features may be formed between the first feature and the second feature, so that the first feature and the second feature may not be in direct contact. In addition, the present disclosure may repeat figure numerals and / or letters in various examples. This repetition is for the purpose of simplicity and clarity and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0019] In addition, for ease of description, spatially relative terms, such as "below", "beneath", "lower", "above", "upper", etc., may be used herein to describe the relationship of one element or feature to another (or multiple) elements or features as shown in the figures. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially relative descriptors used herein may also be interpreted accordingly. In addition, when "approximately", "approximately", etc. are used to describe a number or a series of numbers, unless otherwise specified, the term is intended to include numbers within the range of + / -10% of the described number. For example, the term "approximately 5 nanometers" encompasses a size range of 4.5 nanometers to 5.5 nanometers.

[0020] The present disclosure relates generally to photolithography, and more specifically to photolithography patterning using a self-aligned method to form interconnect features in a semiconductor structure. Various embodiments discussed herein allow the formation of interconnect features with reduced size and spacing, and allow the reduction or avoidance of effects caused by overlapping displacement during photolithography, such as via-induced metal bridges (VIMB) and via-to-via leakage effects. In some embodiments, photolithography patterning includes exposing a resist layer (also referred to as a photoresist layer), and the exposure dose is configured to be less than the exposure threshold of the resist layer so that the potential resist pattern is not formed by direct exposure itself. At the same time, the conductive feature below reflects a portion of the incident radiation (also referred to as the reflected exposure dose) back to the resist layer. The resist layer absorbs the direct incident exposure dose and the reflected exposure dose. The sum of the incident exposure dose and the reflected exposure dose is configured to be greater than the exposure threshold of the resist layer. Since the reflection occurs in the adjacent area just above the conductive feature below, the potential resist pattern is self-aligned with the position of the conductive feature below. In some embodiments, the underlying conductive features may use a highly reflective metal-containing material or be coated with a reflective layer to increase the reflective intensity, which in turn increases the exposure contrast at the edges of the underlying conductive features. It should be noted that the various embodiments discussed herein are not limited to forming interconnect features in semiconductor structures, but may also be used to form other structures with alignment and overlay shift issues.

[0021] refer to Figure 1 , a portion of a semiconductor structure 10 is shown. The semiconductor structure 10 includes a semiconductor substrate 102, a conductive feature 104 formed in a top portion of the semiconductor substrate 102, and a dielectric layer 106 formed over the semiconductor substrate 102.

[0022] The semiconductor substrate 102 may include silicon (Si). Alternatively or additionally, the substrate 102 may include other elemental semiconductors, such as germanium (Ge). The substrate 102 may also include compound semiconductors, such as silicon carbide, gallium arsenide, indium arsenide, and indium phosphide. The substrate 102 may include alloy semiconductors, such as silicon germanium, silicon germanium carbide, gallium arsenic phosphide, and gallium indium phosphide. In some embodiments, the substrate 102 includes an epitaxial layer. For example, the substrate 102 may have an epitaxial layer covering a bulk semiconductor. In some embodiments, the substrate 102 may include a semiconductor on an insulator (SOI) structure. For example, the substrate 102 may include a buried oxide layer formed by other suitable techniques such as separation by implanting oxygen or such as wafer bonding and grinding.

[0023] The substrate 102 may also include various p-type doped regions and / or n-type doped regions, which are implemented by processes such as ion implantation and / or diffusion. These doped regions include n-wells, p-wells, lightly doped regions (LDDs), heavily doped sources and drains (S / Ds), and various channel doping profiles configured to form various integrated circuit (IC) devices (e.g., complementary metal oxide semiconductor field effect transistors (CMOSFETs), imaging sensors, and / or light emitting diodes (LEDs)). The substrate 102 may also include other functional features, such as resistors or capacitors formed in and on the substrate. In some embodiments, the substrate 102 may also include lateral isolation features, which are provided for separating various devices formed in the substrate 102. The isolation features may include shallow trench isolation (STI) features to define and electrically isolate functional features. In some examples, the isolation region may include silicon oxide, silicon nitride, silicon oxynitride, air gaps, other suitable materials, or combinations thereof. The isolation region may be formed by any suitable process. Various IC devices may also include other features, such as silicides disposed on the S / Ds and gate stacks covering the channels.

[0024] The semiconductor structure 10 may also include a plurality of dielectric layers and conductive features that are integrated to form an interconnect structure that is configured to couple various p-type and n-type doped regions and other functional features (e.g., gate electrodes) to produce a functional integrated circuit. In some embodiments, the substrate 102 may include a portion of the interconnect structure and is collectively referred to as the substrate 102.

[0025] As described above, the semiconductor structure 10 may include an interconnect structure. The interconnect structure includes a multi-layer interconnect (MLI) structure and an interlayer dielectric (ILD) integrated with the MLI structure, thereby providing electrical wiring for coupling various devices in the substrate 102 to input / output power and signals. The interconnect structure includes various metal lines, contacts, and via features (or via plugs). The metal lines provide horizontal electrical wiring. The contacts provide vertical connections between the substrate 102 and the metal lines. The via features provide vertical connections between metal lines in different metal layers.

[0026] Still refer to Figure 1 , the semiconductor structure 10 includes a conductive feature 104. In some embodiments, the conductive feature 104 may include a metal contact, a metal via, or a metal line. In some embodiments, the conductive feature 104 may be further surrounded by a barrier layer (not shown) to prevent diffusion and / or provide material adhesion. In some examples, the conductive feature 104 includes aluminum (Al), copper (Cu), or tungsten (W). The barrier layer may include titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), titanium silicon nitride (TiSiN), or tantalum silicon nitride (TaSiN). The conductive feature 104 and the barrier layer may be formed by a process including photolithography, etching, and deposition. In some embodiments, the conductive feature 104 includes an electrode of a capacitor, a resistor, or a portion of a resistor. Alternatively, the conductive feature 104 includes a doped region (e.g., a source or drain) or a gate electrode (e.g., a metal gate of a FinFET). In some embodiments, the conductive feature 104 includes a silicide feature disposed on a corresponding source, drain, or gate electrode. The silicide feature may be formed by a self-aligned silicide (salicide) technique.

[0027] Still refer to Figure 1, the semiconductor structure 10 includes a dielectric layer 106 deposited on a semiconductor substrate 102. The dielectric layer 106 may have various material layers, such as an etch stop layer (ESL) 108, a low-k dielectric layer 110, and a hard mask layer 112, which are sequentially formed in a direction away from the substrate 102. In some embodiments, the ESL 108 is formed on the conductive feature 104. The ESL 108 may include a dielectric material similar to the dielectric material in the low-k dielectric layer 110. However, the dielectric constant of the ESL 108 may be greater than the dielectric constant of the low-k dielectric layer 110 deposited on the ESL 108. The dielectric material in the ESL 108 may be selected to have a higher etching selectivity on the low-k dielectric layer 110 so that a suitable subsequent etching process is used to form a through-hole (or contact) trench. For example, in an etching process, the ESL 108 may have a lower etching rate than the low-k dielectric layer 110 on the ESL 108. In some embodiments, ESL 108 can be deposited using any suitable technique, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or an epitaxial growth process. In some embodiments, ESL 108 includes an oxide layer comprising carbon, oxygen, silicon, and / or other suitable materials or combinations thereof.

[0028] A low-k dielectric layer 110 is formed on the ESL 108. The low-k dielectric layer 110 may be an interlayer dielectric (ILD) layer or an intermetallic dielectric (IMD) layer. The low-k dielectric layer may include a low-k dielectric material having a k value (e.g., less than about 4.0 or even 2.0). In some embodiments, the low-k dielectric layer 110 may be made of, for example, phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), fluorosilicate glass (FSG), SiO x C y , spin glass, spin polymer, silicon carbon material, compounds thereof, composites thereof, combinations thereof, etc. The low-k dielectric layer 110 can be formed by any suitable method, such as spin coating, CVD, plasma enhanced CVD (PECVD), PVD, etc.

[0029] A hard mask (HM) layer 112 is formed on the low-k dielectric layer 110. The HM layer 112 may include a single material layer or multiple material layers. In some embodiments, the HM layer 112 includes a lower HM layer and an upper HM layer (not shown). The lower HM layer may include a dielectric material similar to the dielectric material of the low-k dielectric layer 110, but having a dielectric constant greater than that of the low-k dielectric layer 110. In some embodiments, the lower HM layer includes an oxide layer containing carbon, oxygen, silicon and / or other suitable materials and combinations thereof. For example, the lower HM layer includes a silicon oxide (SiO2) layer. The lower HM layer may be formed by a deposition process, such as a CVD process. In some embodiments, the lower HM layer may have a greater hardness than the low-k dielectric layer 110. In some embodiments, the lower HM layer may have a polishing rate higher than that of the low-k dielectric layer 110, so that the lower HM layer can be used as a buffer layer in a subsequent polishing process. The upper HM layer is formed on the lower HM layer. In some embodiments, the upper HM layer includes titanium nitride (TiN), titanium oxide (TiO2), and / or other suitable oxide materials or combinations thereof. In some embodiments, the upper HM layer is formed using any suitable technique (e.g., CVD, PECVD, or PVD). The upper HM layer can be used to transfer IC design patterns from a photomask (e.g., Figure 2 It should be understood that the HM layer 112 may also include a single material layer or alternatively include more than two material layers, which may be used to transfer one or more IC design patterns from the photomask to the low-k dielectric layer 110.

[0030] Still refer to Figure 1 , a photoresist layer 120 is formed on the dielectric layer 106. The photoresist layer 120 can be formed by depositing a photoresist composition on the dielectric layer 106. The photoresist layer 120 may include a photoresist material and a solvent. In some embodiments, the photoresist material includes a polymer. In one example, the molecular weight of the photoresist material can be controlled for the quality of the photolithography exposure process. In another example, the molecular weight of the photoresist material is between about 1000 and 20000. In some embodiments, the photoresist layer 120 may also include a quencher and / or other additives.

[0031] In some embodiments, the photoresist material of the photoresist layer 120 includes a chemically amplified (CA) resist material. The CA resist material can be a positive polarity CA resist material, which includes an acid-decomposable polymer that is converted into a developer (e.g., an alkaline solution) after being decomposed by an acid (e.g., an acid generated by a photoacid generator (PAG)). In one example, the acid-decomposable polymer decomposed by the acid becomes more hydrophilic and can be soluble in an alkaline solution. For example, the acid-decomposable polymer decomposed by the acid can be dissolved in a tetramethylammonium hydroxide (TMAH) developer. In another example, the TMAH developer includes a TMAH solution having an appropriate concentration range of about 0% to 15% (by weight). In yet another example, the TMAH developer includes a TMAH solution having a concentration of about 2.38% (by weight). In a further embodiment, when a CA resist material is used, the photoresist material of the photoresist layer 120 may include a photoacid generator (PAG) distributed in the photoresist layer 120. When absorbing radiation energy, the PAG decomposes and forms a small amount of acid. The concentration range of the PAG may be between about 1% and 30% (by weight) of the photoresist layer 120. In some embodiments, the PAG may be an ionic (iodine salt), such as a metal-containing or sulfonate. Alternatively, the PAG may be non-ionic, such as a sulfonate, a 2-nitrobenzyl ester, an organic halide, an aromatic sulfonate, an oxime sulfonate, an N-sulfonyloxyimide, a sulfonyloxyketone, or a diazabenzoquinone (DNQ) 4 sulfonate. The photoresist layer 120 may additionally include other components, such as a quencher. In the example, the quencher is alkaline and is capable of neutralizing the acid. In whole or in lieu thereof, the quencher can inhibit other active components of the photoresist layer 120, for example, inhibiting the reaction of photoacids. Examples of optional additives also include photodecomposable quenchers (PDQs), photobase generators (PBGs) that can be used to inhibit the activity of acids generated by exposure, thermal base generators, thermal acid generators, acid multipliers, chromophores, other suitable materials, and / or combinations thereof.

[0032] The photoresist layer 120 may be deposited by spin coating or other suitable techniques. Other steps (eg, baking) may follow the application of the photoresist layer 120. In some embodiments, the solvent of the photoresist layer 120 may be partially evaporated by a soft bake process.

[0033] Figure 2is a top view of a photomask (also referred to as a mask or reticle) 200 having a photomask substrate 202 and an IC design pattern 204 according to some embodiments of the present disclosure. It should be understood that the photomask 200 and the included IC design pattern 204 may actually be part of a larger and more complex photomask (not shown). The photomask 200 may be used to pattern one or more layers in a photolithography patterning process. In some embodiments, the IC design pattern 204 may be used to form interconnect features (e.g., vias, contacts, or plugs) using a photolithography process. In the illustrated embodiment, the IC design pattern 204 has an elliptical shape in the top view, which may be associated with a via feature defined by the IC design pattern 204. The width of the ellipse in the X direction is d1. In further embodiments, the elliptical shape is associated with a via feature that is formed to connect and electrically couple to a conductive feature (e.g., a metal line) in a layer below the via, such as formed on the semiconductor substrate 102 ( Figure 1 )Conductive features 104 in the top portion.

[0034] The photomask 200 includes a photomask substrate 202 and an IC design pattern 204 formed thereon. In some embodiments, when photolithography techniques such as ultraviolet (UV) or deep ultraviolet (DUV) are used to pattern features on a wafer, the photomask substrate 202 includes a transparent substrate such as fused silica. The IC design pattern 204 is formed on the photomask substrate 202 and is defined in an opaque material layer such as chromium (Cr). The photomask 200 allows UV or DUV radiation to penetrate the transparent portions defined by the IC design pattern 204. In some alternative embodiments, when extreme ultraviolet (EUV) photolithography techniques are used, the photomask 200 is different from Figure 2 . In the exemplary reflective photomask, the photomask substrate 202 is made of a low thermal expansion material (LTEM), a reflective multilayer is deposited on the substrate 202, and an absorber layer is deposited on the reflective multilayer and is further patterned to define an IC design pattern 204. In EUV lithography, the reflective multilayer reflects EUV radiation, and the light path is different from that of UV or DUV lithography. It should be understood that other configurations and the inclusion or omission of various items are possible. For example, a cap layer can be formed between the reflective multilayer and the absorber layer. In another example, a protective layer can be formed on the absorber layer. In yet other alternative embodiments, the photomask 200 can be a phase shift mask (PSM) for enhancing imaging resolution, such as an attenuated PSM or an alternating PSM.

[0035] Alternatively, photolithography techniques may be performed without the use of a photomask, e.g. Figure 2The photomask 200 in the embodiment is referred to as maskless lithography. In an exemplary maskless lithography, an IC design pattern may be defined in a lithography patterning data file, and the IC design pattern may be transferred to a material (e.g., photoresist) layer by other exposure systems (e.g., charged particle beams (including electron beams (E-beams)) in a suitable pattern (e.g., direct writing in a raster mode or a vector mode, or using a digital pattern generator). In electron beam lithography, the photoresist layer is generally referred to as an electron beam sensitive resist layer.

[0036] refer to Figure 3 , showing a conventional photolithography exposure process 300, which will be referred to below Figure 4 1. The embodiment of the self-aligned lithography exposure process discussed in the present invention is compared. The lithography exposure process 300 uses a photomask 200 having an IC design pattern 204 to expose the photoresist layer 120, thereby forming a latent resist pattern in a region 304 of the photoresist layer 120. The latent resist pattern refers to a portion of the photoresist layer that has been exposed but not yet developed. In the example shown, an overlap shift occurs in the X direction, resulting in a misalignment between the photomask 200 and the conductive feature 104, so that the edge of the IC design pattern 204 is offset from the edge of the conductive feature 104 by a distance Δx.

[0037] Regarding the photoresist material in the photoresist layer 120, it has an exposure threshold (denoted as T) for radiation (e.g., UV, DUV, EUV, or electron beam radiation). When the exposure intensity (also referred to as exposure component or exposure dose) is equal to or greater than the exposure threshold T, the corresponding portion of the photoresist undergoes a chemical change to form a latent photoresist pattern, and the latent photoresist pattern will be developed (e.g., removed by a developer) in a development process. When the exposure intensity is less than the exposure threshold T, the corresponding portion of the photoresist does not undergo a chemical change for development (e.g., does not form a latent resist pattern, and remains unchanged in the development process). It should be understood that the term "chemical change" means that the photoresist has undergone sufficient changes to react differently, for example, the reaction of the exposed photoresist in the development process. In an example where the photoresist is a positive tone, in the development process, only the portion of the photoresist exposed to an exposure intensity equal to or greater than the exposure threshold T is removed by a suitable developer. The portion of the photoresist that is not exposed or exposed with an exposure intensity less than the exposure threshold T remains after the development process. In another example where the photoresist is negative, the portion of the photoresist that is not exposed or exposed with an exposure intensity less than the exposure threshold T is removed by a suitable developer during the development process. The portion of the photoresist that is exposed with an exposure intensity equal to or greater than the exposure threshold T remains after the development process.

[0038] Still refer to Figure 3 The exposure intensity of radiation 302 (directly emitted from the radiation source to the photoresist layer 120) is called the incident exposure dose, denoted as E 入射 . E 入射 There is a distribution curve, also called an exposure dose curve. Figure 3 Also shown is the E of the photoresist layer 120 exposed during the photolithography exposure process 300. 入射 Example of an exposure dose curve for . In the example, E 入射 The exposure dose curve of shows the exposure intensity at the bottom surface of the photoresist layer 120. The area of ​​the photoresist layer 120 near the center of the IC design pattern 204 may receive a higher exposure dose (e.g., E1) than the area away from the center of the IC design pattern 204 (e.g., E2 near the edge of the IC design pattern 204). Generally, the photolithography exposure process 300 applies an incident exposure dose greater than the exposure threshold T of the photoresist layer 120. According to E 入射 According to the exposure dose curve of , the lowest exposure dose received by the region 304 of the photoresist layer 120 is E2. In some embodiments, E2 is greater than or equal to the exposure threshold T of the photoresist layer 120, so that a latent resist pattern is formed in the region 304 under the radiation 302. However, since the exposure dose curve is mainly defined by the radiation intensity from the light source and the geometric structure of the IC design pattern 204, and is basically independent of the position of the underlying conductive feature 104, the overlay error of the offset Δx is transferred to the position of the latent resist pattern in the region 304, and subsequently to the interconnect feature to be formed in the dielectric layer 106. The offset Δx may cause the interconnect feature to be electrically shorted with other adjacent conductive features in the dielectric layer 106.

[0039] refer to Figure 4 , showing an embodiment of the self-aligned photolithography exposure process of the present disclosure. The photolithography exposure process 400 uses a photomask 200 having an IC design pattern 204 to expose the photoresist layer 120, thereby forming a latent resist pattern in the photoresist layer 120. Figure 3 Compared to the potential resist pattern shown, Figure 4 The position of the latent resist pattern in is defined by the position of the underlying conductive feature 104, such that the latent resist pattern is confined to a region 404 substantially directly above the conductive feature 104. Figure 3 Compared with the conventional photolithography exposure process 300 in FIG. 1 , regardless of the overlap shift occurring in the positive X direction or the negative X direction, in FIG. Figure 4 The position of the latent resist pattern formed in the photoresist layer 120 in is not sensitive to the overlay error. To illustrate this point, Figure 4In [description], the IC design pattern 204 in the photomask 200 is drawn larger than the underlying conductive feature 104 such that the two edges of the IC design pattern 204 are offset from the corresponding edges of the conductive feature 104 by a distance Δx.

[0040] The photoresist material in the photoresist layer 120 has an exposure threshold T'. The exposure intensity of the radiation 402 directly emitted from the radiation source onto the photoresist layer 120 is denoted as E 入射 . E 入射 's exposure dose curve represents its distribution curve. Figure 4 Also shown in [description] is an example of the exposure dose curve of E when the photoresist layer 120 is exposed during the photolithographic exposure process 400. In the example, the exposure dose curve of E 入射 shows the exposure intensity at the bottom of the photoresist layer 120. One difference compared to the photolithographic exposure process 300 shown in 入射 is that the exposure dose used in the photolithographic exposure process 400 in [description] is configured to be less than the exposure threshold T'. Even though the region of the photoresist layer 120 closer to the center of the IC design pattern 204 may receive a higher exposure dose (e.g., E1 near the edge of the conductive feature 104) than the region farther from the center of the IC design pattern 204 (e.g., E2 near the edge of the IC design pattern 204), the entire exposure dose curve of E Figure 3 is below the exposure threshold T' (i.e., E1 < T' and E2 < T'). Therefore, the exposure dose directly emitted from the radiation source onto the photoresist layer 120 is not sufficient to form a latent resist pattern.

[0041] Another difference compared to the photolithographic exposure process 300 in Figure 3 is that the underlying conductive feature 104 in [description] has a higher reflectivity for the incident radiation 402 at its top surface, which has a substantial impact on the total radiation received by the photoresist layer 120. The term "reflectivity" refers to the fraction of the incident radiation that is reflected at the interface, denoted as R. For the photolithographic exposure process 300 shown in Figure 4 , the reflectivity R may be small, e.g., less than about 5%, and the reflected radiation can be ignored. For example, at a DUV radiation wavelength of 193 nm, the reflectivity of copper (Cu) is about 2% (R ≈ 2%). That is, if the conductive feature 104 is made of Cu, about 2% of the incident DUV radiation reaching the top surface of the conductive feature 104 will be reflected back to the upper layer. The total radiation received by the photoresist layer 120 is the sum of the incident radiation and the reflected radiation. But for copper, since the reflected radiation is only 2% of the incident radiation, this small fraction is usually negligible, and thus the total radiation is still determined by the intensity of the incident radiation. ​​​​​​

[0042] While metal-containing materials such as copper may have poor reflectivity under certain radiation (e.g., under 193nm DUV radiation, for Au, R < 1%; for Ni, R ≈ 2%; for Cr, R ≈ 1%), some other metal-containing materials or alloys may have strong reflectivity. For example, under DUV radiation with a wavelength of 193nm, the reflectivity of aluminum (Al) is about 65%, and the reflectivity of aluminum and copper alloy (AlCu) is about 71%. That is, if the conductive feature 104 is made of Al, then about 65% of the incident DUV radiation reaching the top surface of the conductive feature 104 will be reflected back to the layers above. Figure 4 In the illustrated embodiment, the conductive features 104 have a reflectivity of at least about 5%. As described above, for reflectivities less than about 5%, it is difficult for the reflected radiation to have a substantial effect on the total radiation intensity.

[0043] Still refer to Figure 4 The intensity of the reflected radiation 408 returning from the top surface of the conductive feature 104 to the photoresist layer 120 is represented by E 反射 . E 反射 It has a distribution curve, also called the reflected exposure dose curve. Figure 4 The example also shows exposure of the photoresist layer 120 from the underlying conductive feature 104. 反射 In this example, E 反射 The reflective exposure curve of shows the exposure intensity at the bottom surface of the photoresist layer 120, which is located a distance from the conductive feature by the thickness (denoted as H) of the dielectric layer 106. In various embodiments, the thickness H may be in the range of about 1 nm to about 100 nm, for example about 10 nm.

[0044] according to Figure 4 E shown in 入射 In the reflected exposure dose curve, the area of ​​the photoresist layer 120 located directly above the conductive feature 104 (e.g., E1' at the edge of the conductive feature 104) receives a higher reflected exposure dose than the area offset from the edge of the conductive feature 104 (e.g., E2' at the edge of the IC design pattern 204). 反射 YesE 入射 part of E 反射 The reflected exposure dose curve is lower than E 入射 ', which is further below the exposure threshold T'.

[0045] The total exposure dose (denoted as E 总 ) is the incident exposure dose E 入射 and reflected exposure dose E 反射 The sum of (E总 =E 入射 +E 反射 ). 总 The total exposure dose curve is also as follows Figure 4 At the edge of the conductive feature 104, the total exposure dose is approximately E1+E1'. At the edge of the IC design pattern area 404 offset from the edge of the conductive feature 104, the total exposure dose is approximately E2+E2'.

[0046] In the photolithography exposure process 400, the incident radiation directly from the radiation source is configured such that E1+E1' is greater than or equal to the exposure threshold T', so that a latent resist pattern is formed in the region 404 directly above the conductive feature 104, while E2+E2' is less than the exposure threshold T', so that no latent resist pattern is formed in the transition region 406 offset from the conductive feature 104. By effecting the reflected exposure dose to change the total exposure dose from being below the exposure threshold T' to being above the exposure threshold T', the latent resist pattern formed in the region 404 is self-aligned with the underlying conductive feature 104. Therefore, by defining the position of the latent resist pattern, the interconnect feature subsequently formed in the dielectric layer 106 will also be substantially self-aligned with the underlying conductive feature 104.

[0047] The greater the exposure contrast, the more flexible the design of the photolithography process. The exposure contrast (denoted as γ) refers to the slope of the exposure dose curve in the transition region of the photoresist layer. The exposure contrast γ describes the ability of the resist to distinguish between light and dark areas. 总 The exposure contrast γ at the transition region 406 can be approximately expressed as the difference between the total exposure dose at the edge of the conductive feature 104 (approximately E1+E1') and the total exposure dose at the edge of the IC design pattern 204 (approximately E2+E2') divided by the offset distance Δx, that is, γ≈(E1+E1'-E2-E2') / Δx. Since both E1 and E2 are exposure doses directly below the IC design pattern 204, the difference between the incident exposure doses E1 and E2 is very small (E1≈E2), so the expression of the exposure contrast γ can be further simplified to γ≈(E1'-E2') / Δx. In other words, the exposure contrast γ is mainly determined by E1. 反射 The slope of the reflected exposure dose curve is defined.

[0048] To increase the slope of the reflected exposure dose curve in the transition region 406 to enhance the exposure contrast γ, one way is to increase the reflectivity R at the top surface of the conductive feature 104, such as by using a metal material with a higher reflectivity to form the conductive feature 104. For a higher reflectivity, the reflected exposure dose curve in the central region directly above the conductive feature 104 will be further shifted upward, thereby rolling off faster outside the edge of the conductive feature 104.

[0049] Figure 5A -C shows various embodiments of conductive features 104. In some embodiments, as Figure 5A As shown, the conductive feature 104 is a uniform layer of a bulk metal-containing material (eg, aluminum (Al), tantalum (Ta), titanium (Ti), or a metal-containing alloy (eg, AlCu)) having a high reflectivity.

[0050] In some other embodiments, the conductive feature 104 has a double-layer arrangement, with a bulk metal layer 114a at the bottom portion of the conductive feature 104, and a reflective layer 114b coated on the bulk metal layer 114a, such as Figure 5B As shown. The bulk metal layer 114a may include a metal-containing material having relatively high conductivity but low reflectivity, such as copper (Cu), gold (Au), tungsten (W), chromium (Cr), cobalt (Co), nickel (Ni). The reflective layer 114b is formed of a material having high reflectivity, such as Al, Ta, Ti, AlCu, TiN, CrSi2 or other suitable materials. The reflective layer 114b may be conductive, or alternatively non-conductive. As will be further described in detail below, when the reflective layer 114b is non-conductive, an additional etching step may be applied to the reflective layer 114b to expose the underlying bulk metal layer 114a in a photolithography process.

[0051] In some other embodiments, the reflective layer 114b coated on the bulk metal layer 114a is a reflective multilayer, such as a plurality of alternating layers of a first material layer 116a and a second material layer 116b, such as Figure 5CAs shown. The reflective multilayer is configured to effectively reflect radiation within a predetermined wavelength range, such as deep ultraviolet (DUV) (from about 100 nm to about 300 nm) or EUV (from about 13.2 nm to about 13.8 nm). For example, the reflective layer 114b may include a plurality of alternating layers having a relatively high refractive index for radiation scattering and a relatively low refractive index for radiation emission. Pairing these two materials together can produce resonant reflectivity. In some embodiments, the reflective multilayer configuration includes a plurality of molybdenum / silicon (Mo / Si) pairs (e.g., a layer of Mo above or below a layer of silicon in each pair) or a plurality of molybdenum compound / silicon compound pairs. In some embodiments, the reflective multilayer 114b includes a plurality of molybdenum / beryllium (Mo / Be) pairs or other suitable material pairs (e.g., Ru / Si pairs, Pd / Si pairs, or Rh / Si pairs) having a refractive index difference to result in high reflectivity (e.g., from about 10% to about 60%) to selected radiation. In some embodiments, each layer of the reflective multilayer has a thickness of about 2 nm to about 5 nm. The thickness is adjusted to achieve maximum constructive interference of selected radiation diffracted at each interface and minimum absorption of selected radiation. In further description of some embodiments where the reflective multilayer 114b includes Mo / Si pairs, the thickness of the silicon or silicon compound layer can be about 4nm, and the thickness of the molybdenum or molybdenum compound layer can be about 3nm. In some embodiments, the reflective multilayer 114b includes a plurality of pairs ranging from about 3 to about 20. In some instances, a plurality of pairs less than 3 can reduce reflectivity. In some instances, a plurality of pairs greater than 20 increases the likelihood of contact with foreign particles and / or the occurrence of defects. In some embodiments where the reflective multilayer 114b includes Mo / Si pairs, the number of pairs is from about 3 to 10, for example 4. In at least one embodiment, the conductive feature 104 also includes a backside coating (not shown) stacked between the reflective multilayer 114b and the bulk metal layer 114a. In some instances, the backside coating is a metal-containing film or a polysilicon film.

[0052] Reference Figure 4 In order to enhance the exposure contrast γ, in addition to increasing the reflectivity of the underlying conductive feature 104, the inventors of the present disclosure also observed that the distance between the photoresist layer 120 and the conductive feature 104 (ie, defined by the thickness H of the dielectric layer 106) is an adjustment factor.

[0053] refer to Figure 6 , shows a diagrammatic view of a reflective exposure dose intensity distribution in a region above a conductive feature 104 according to some embodiments of the present disclosure. The coordinates are set at the top surface (Z=0) of the conductive feature 104. In the illustrated embodiment, the top surface of the conductive feature 104 has a reflectivity R of approximately 25%. Figure 6Also included are reflected exposure dose intensity levels labeled with various intensity levels represented by various gray levels. In this example, for simplicity, the units of exposure intensity are relative units expressed as a percentage, ranging from 0 to 100%. In this case, "25%" means that the reflected exposure dose is 25% of the incident exposure dose from the exposure system. Along line L1 perpendicular to the top surface of substrate 102 and aligned with the edge of conductive feature 104, the reflected exposure dose generally decreases at a greater vertical distance from conductive feature 104. Figure 6 In the illustrated embodiment, for example, when Z=0, the reflected exposure dose is approximately equal to the reflectivity R, which is approximately 25%; when Z=H1, the reflected exposure dose (E1') becomes smaller, which is approximately 23%; when Z=H2, farther from the conductive feature 104, the reflected exposure dose (E1") is further reduced to approximately 22%. However, the decreasing relationship between the reflected exposure dose and the vertical distance is different from that at other positions because, in view of the diffraction and interference effects, the energy of the reflected radiation is generally not linearly distributed in space. For example, along a line perpendicular to the substrate 104, the reflected radiation is not linearly distributed in space. 2 but offset from the conductive feature 104 at a distance Δx, the reflected exposure dose does not decrease monotonically as the distance from the conductive feature 104 increases. Instead, at a greater distance, the reflected exposure dose may instead increase. For example, along line L2, at Z=0, the reflected exposure dose is about 12% at its minimum; at Z=H1, the reflected exposure dose intensity (E2') increases to about 18%; at Z=H2 (which is farther from the conductive feature 104), the reflected exposure dose (E2') further increases to about 21%.

[0054] As mentioned above, the expression of exposure contrast γ can be simplified to γ≈(E1'-E2') / Δx. When Z=H1, γ≈(23%-18%) / Δx=5% / Δx; when Z=H2, γ≈(22%-21%) / Δx=1% / Δx, which is significantly smaller than γ when Z=H1. Therefore, in order to increase E 反射 The slope of the reflected exposure dose curve of , the distance between the photoresist layer 120 and the conductive feature 104 (ie, defined by the thickness H of the dielectric layer 106) is an adjustment factor and generally needs to be less than a threshold distance H th That is, in a self-aligned lithography process, the photoresist layer may need to be spaced from the underlying reflective conductive features by less than a threshold distance H th The threshold distance H th The threshold distance H is affected by many factors, such as the wavelength of the radiation, the reflectivity of the conductive features, and the geometry of the photomask. In some embodiments, under DUV radiation, the threshold distance H th It can be from about 5 nm to about 20 nm, for example about 10 nm. In some embodiments, under EUV radiation, the threshold distance H thIt may be from about 1 nm to about 10 nm, for example about 5 nm.

[0055] In various embodiments, by appropriately selecting the incident exposure dose, adjusting the position of the photoresist layer relative to the underlying conductive features, selecting the reflectivity of the underlying conductive features, adjusting the exposure threshold by adjusting the composition of the photoresist material, or a combination thereof, a latent resist pattern that is self-aligned with the underlying conductive features as shown in the present disclosure can be formed. In addition, in some embodiments, the photolithography exposure process uses photons, such as UV, DUV or EUV radiation. In alternative embodiments, charged particles are used as a radiation beam during the photolithography exposure process. In this case, the IC design pattern can be defined in a data file, and the sensitive resist material is selected to be sensitive to the charged particles (e.g., electron beam).

[0056] Methods of forming self-aligned interconnect features and semiconductor structures fabricated thereby are further described below according to various embodiments.

[0057] Figure 7 700 is a flow chart of a method 700 for fabricating a semiconductor structure using a self-aligned photolithography exposure process according to one or more embodiments of the present disclosure. The method 700 is merely an example and is not intended to limit the present disclosure beyond the scope expressly recited in the claims. Additional steps may be provided before, during, and after the method 700, and some of the steps described may be moved, replaced, or eliminated for additional embodiments of the method 700. Figure 8-18 To describe Figure 7 , Figure 8-18 are cross-sectional views of semiconductor structure 20 at various stages of fabrication according to method 700 .

[0058] The semiconductor structure 20 may be an intermediate device fabricated during processing of an integrated circuit (IC) or a portion thereof, which may include static random access memory (SRAM) and / or logic circuits, passive components (e.g., resistors, capacitors, and inductors) and active components (e.g., p-type FETs (pFETs), n-type field effect transistors (nFETs), FinFETs, metal oxide semiconductor field effect transistors (MOSFETs), and complementary metal oxide semiconductor (CMOS) transistors, bipolar transistors, high voltage transistors, high frequency transistors, other memory cells, and combinations thereof. In addition, various features (including transistors, gate stacks, active regions, isolation structures), and other features in various embodiments of the present disclosure are provided for simplicity and ease of understanding, and do not necessarily limit the embodiments to any type of device, any number of devices, any number of regions or structures, or any configuration of regions.

[0059] At operation 702, method 700 ( Figure 7) provides a semiconductor structure 20, such as Figure 8 The various components and material layers of the semiconductor structure 20 are similar to those in the above reference Figure 1 104a and 104b, and are not formed on the conductive feature 104c. The conductive feature 104c may be a portion of a wiring within a layer or may have an interconnect feature elsewhere.

[0060] In one embodiment, semiconductor substrate 102 is a silicon substrate. Semiconductor substrate 102 may include another elemental semiconductor, such as germanium; a compound semiconductor, including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; an alloy semiconductor, including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; or a combination thereof. In yet another alternative, semiconductor substrate 102 is a semiconductor on insulator (SOI).

[0061] Semiconductor substrate 102 includes a plurality of conductive features 104. Conductive features 104 may be IC features, such as metal lines, metal contacts, or metal vias. In some embodiments, conductive features 104 include electrodes of capacitors or resistors. Alternatively, conductive features 104 may include doped regions (such as sources or drains) or gate electrodes (such as metal gates of FinFETs).

[0062] The conductive features 104 include a conductive material composition, such as a highly conductive metal, a low resistance metal, an elemental metal, a transition metal, etc. In some embodiments, the conductive features 104 may be further surrounded by a barrier layer to prevent diffusion and / or provide material adhesion. The conductive features 104 may be deposited by electroplating techniques, although any formation method may alternatively be used. In an embodiment, the conductive features 104 include a metal-containing material having a relatively high reflectivity, such as Al, Ta, Ti, or a metal-containing alloy (e.g., AlCu), similar to the above reference 104. Figure 5A In another embodiment, the conductive feature 104 has a dual-layer arrangement including a bulk metal layer 114a and a reflective layer 114b coated on the bulk metal layer 114a, which is similar to the above reference 104. Figure 5BThe bulk metal layer 114a may be formed of Cu, but other materials such as W, Al, Au, etc. may be used instead. The reflective layer 114b is formed of a material having a relatively high reflectivity, such as Al, Ta, Ti, AlCu, TiN, CrSi2, or other suitable materials. The reflective layer 114b may be conductive, or alternatively non-conductive. In yet another embodiment, the reflective layer 114b may be a reflective multilayer (e.g., a plurality of alternating layers of a first material layer and a second material layer), similar to the above reference numerals. Figure 5C As discussed above with respect to the reflective layer 114b in FIG.

[0063] The dielectric layer 106 may have various material layers formed on the substrate 102, such as an etch stop layer (ESL), a low-k dielectric layer (such as an ILD layer or an IMD layer), and a hard mask layer sequentially formed in a direction away from the substrate 102, similar to the above reference numerals. Figure 1 In various embodiments, the dielectric layer 106 has a distance H less than a threshold value determined in a subsequent photolithography exposure process. th The thickness H of the substrate may be about 5 nm to about 20 nm, for example about 10 nm, for a lithography exposure process using DUV radiation. th In the example of about 10 nm, H may range from about 5 nm to about 10 nm, such as about 8 nm. For a lithography exposure process using EUV radiation, the thickness H may range from about 1 nm to about 10 nm, such as about 5 nm. th In the example of about 5 nm, H may range from about 1 nm to about 5 nm, such as about 3 nm.

[0064] At operation 704, method 700 ( Figure 7 ) A photoresist layer 120 is formed on the dielectric layer 106, such as Fig. 9 As shown. The formation of the photoresist layer 120 includes coating a photoresist solution on the dielectric layer 106 by a suitable technique (e.g., spin coating). Other manufacturing steps (e.g., soft baking) may be further applied to the photoresist layer 120. The photoresist layer 120 may include a positive photoresist material that becomes soluble in a developer solution after exposure to a radiation source. In some alternative embodiments, the photoresist layer 120 may include a negative photoresist material that becomes insoluble in a developer solution after exposure to a radiation source. The photoresist layer 120 has a predetermined exposure threshold. For example, the composition of the photoresist layer 120 can be adjusted by changing the ratio of carbon, hydrogen, and oxygen to have a suitable exposure threshold for the photolithography exposure process discussed later in this disclosure. The thickness of the photoresist layer 120 can range from about To date between.

[0065] At operation 706, method 700 ( Figure 7 ) Perform a photolithography exposure process 900 to form a latent resist pattern in the photoresist layer 120, such as Fig.10 . The photolithography exposure process 900 uses a photomask 200 having a first IC design pattern 204a and a second IC design pattern 204b (collectively referred to as IC design patterns 204) to expose the photoresist layer 120 with radiation 920, thereby forming a latent photoresist pattern in the photoresist layer 120. The IC design patterns 204a and 204b are used to form interconnect features (e.g., vias, contacts, or plugs) in the dielectric layer 106. In the illustrated embodiment, the IC design pattern 204a is aligned with the underlying conductive feature 104a, while an overlay error occurs in the IC design pattern 204b, such that the edge of the IC design pattern 204b is offset from the edge of the underlying conductive feature 104b by a distance Δx. The overlay error may be caused by the following reasons: misalignment between the photomask 200 and the semiconductor structure 20, inaccurate geometry of the IC design pattern 204b during the manufacture of the photomask 200, inaccurate calibration in the optical device used in the photolithography exposure process 900, or other reasons.

[0066] The exposure source for photolithographic exposure to produce radiation 920 may include any suitable source, such as UV, DUV, EUV, or charged particles (e.g., electron beam). In some alternative embodiments, the IC design pattern is defined in a data file and transferred to the photoresist layer by direct write or other suitable technology (e.g., digital pattern generator). Other steps may be implemented before, during, or after the exposure process. In some embodiments, a post-exposure bake process may be applied to the photoresist layer 120 after the photolithographic exposure process.

[0067] In the illustrated embodiment, the radiation 920 is configured such that the incident exposure dose from the radiation 920 directly to the photoresist layer 120 is less than the exposure threshold of the photoresist layer 120, so that a latent resist pattern is not formed in the photoresist layer 120 by absorbing the incident exposure dose alone. A portion of the radiation 920 reaches the top surface of the conductive features 104a and 104b and is reflected back to the photoresist layer 120 as reflected radiation 922. The reflected exposure dose is mainly controlled by the reflectivity R of the top surface of the conductive features 104 and the intensity of the incident exposure dose. In some embodiments, the thickness H of the dielectric layer 106 is adjusted to control the reflected exposure dose. The sum of the incident exposure dose and the reflected exposure dose is configured to be greater than or at least equal to the exposure threshold of the photoresist layer 120. Therefore, a latent resist pattern is formed in the portion of the photoresist layer 120 that receives both the incident exposure dose and the reflected exposure dose. The reflected radiation occurs at the portion of the top surface of the conductive features 104 reached by the incident radiation 920. In other parts of the top surface of the conductive feature 104, where the incident radiation 920 does not reach or deviates from the top surface of the conductive feature 104, the intensity of the reflected exposure dose is sharply reduced. In other words, only a portion of the photoresist layer 120 (e.g., regions 904a and 904b, which are located directly below the corresponding IC pattern 204 in the photomask 200 and also directly above the conductive feature 104) receives the sum of the incident exposure dose and the reflected exposure dose, so that the chemical change forms a latent resist pattern. With regard to the region 904c adjacent to the region 904b (offset from the edge of the conductive feature 104b), the region substantially only receives the incident radiation 920, but does not receive the reflected radiation 922, which is not strong enough to expose the region 904c. Therefore, the latent resist pattern formed in the region 904b does not extend into the region 904c. Therefore, the latent resist pattern formed in the region 904b is self-aligned with the conductive feature 104b below.

[0068] At operation 708, method 700 ( Figure 7 ) developing the photoresist layer 120 to form a patterned photoresist layer 122, such as Fig.11 In the embodiment shown, the photoresist layer 120 is positive, so the portions of the photoresist layer 120 associated with the latent resist pattern in the regions 904a and 904b are removed by the corresponding developer to form openings in the regions 904a and 904b. The region 904c offset from the conductive feature 104b does not receive an exposure dose above the exposure threshold and remains undeveloped.

[0069] At operation 710, method 700 ( Figure 7 ) The dielectric layer 106 is etched by using the patterned photoresist layer 122 as an etching mask, thereby transferring the pattern in the patterned photoresist layer 122 to the dielectric layer 106, such as Fig.12 As shown. Operation 710 may include one or more etching processes to remove different portions of dielectric layer 106, such as a hard mask layer, a low-k dielectric layer, and an etch stop layer, to extend the openings in regions 904a and 904b down to the top surfaces of conductive features 104a and 104b. In some embodiments, conductive features 104 are metal lines, and the openings in regions 904a and 904b are referred to as via trenches. The top surfaces of conductive features 104a and 104b are exposed in the corresponding via trenches. The etching process may include any suitable etching technique, such as dry etching, wet etching, or a combination thereof. Other operations may then be performed. For example, patterned photoresist layer 122 may be removed by a wet stripping or plasma ashing process, such as Fig.13 The plasma ashing process may include using oxygen (O2) plasma or carbon dioxide (CO2) plasma.

[0070] In some embodiments, the conductive feature 104 is formed of a continuous metal-containing material or the reflective layer 114b is conductive. Figure 7 ) Optionally, operation 710 may proceed to operation 714 by depositing a metal layer 130 to fill the via trenches in regions 904a and 904b and cover the dielectric layer 106, as shown in FIG. Fig.14 As shown. Metal layer 130 is in direct contact with the top surface of conductive features 104a and 104b. In some embodiments, metal layer 130 includes Cu, Al, W or other suitable conductive materials. In some embodiments, metal layer 130 includes a Cu alloy, such as copper magnesium (CuMn), copper aluminum (CuAl) or copper silicon (CuSi). In some embodiments, metal layer 130 is deposited by PVD. In some examples, metal layer 130 is formed by depositing a corresponding metal seed layer using PVD and then forming a bulk metal layer by electroplating.

[0071] At operation 716, method 700 ( Figure 7 ) performs a chemical mechanical polishing (CMP) process to remove excess metal layer 130, thereby forming interconnect features 140a and 140b, such as through holes 140a and 140b, as shown in FIG. Fig.15As shown. The CMP process may also remove a top portion of the dielectric layer 106, such as a hard mask layer. The substantially coplanar top surfaces of the interconnect features 140a and 140b and the dielectric layer 106 may be formed after the CMP process. Due to the self-aligned lithography exposure process, the sidewalls S1 and S2 of the interconnect features 140a and 140b are both connected to (landing on) the top surfaces of the corresponding conductive features 104a and 104b. The sidewall S1 of the interconnect feature 140b has a connection point (landing point) P substantially located at the edge of the conductive feature 104b, for example, within a lateral distance from the edge of the conductive feature 104b of about 20% of the CD size of the interconnect feature. For example, for a diameter of a through-hole feature with a CD (critical dimension) of 20nm, the connection point P is approximately within a lateral distance of 4nm (20nm×20%=4nm) from the edge of the conductive feature 104b. Therefore, the sidewall S1 of the interconnect feature 140b is also referred to as being substantially aligned with the edge of the conductive feature 104b.

[0072] In some embodiments, the reflective layer 114b of the conductive feature 104 is formed of a highly etch-resistant material, a non-conductive material, or a reflective multilayer, and the method 700 ( Figure 7 ) Optionally, operation 710 may proceed to operation 712 by selectively etching the reflective layer 114b to expose the underlying highly conductive bulk metal layer 114a in the openings, such as Fig.16 As shown. Operation 712 includes a selective etching process to remove the portion of the reflective layer 114b exposed in the through-hole trench. The etching process and etchant are appropriately selected for selective etching without damaging the dielectric layer 106. The etching process may include any suitable etching technology, such as dry etching, wet etching, or a combination thereof. The etching process stops at the bulk metal layer 114a. In the illustrated embodiment, after operation 712, portions of the reflective layer 114b remain at both ends of the conductive feature 104a, while portions of the reflective layer 114b remain only at one end of the conductive feature 104b.

[0073] refer to Fig.17 and Fig.18 , method 700( Figure 7) Then proceed to operations 714 and 716 to deposit metal layer 130 to fill the via trenches in regions 904a and 904b, and perform a CMP process to remove excess metal layer 130, thereby forming interconnect features 140a and 140b. Due to the self-aligned photolithography exposure process, the sidewalls S1 and S2 of interconnect features 140a and 140b are connected to the top surfaces of corresponding conductive features 104a and 104b. The sidewall S1 of interconnect feature 140b can be substantially aligned with the edge of conductive feature 104b. The bottom portion of the sidewall S1 and S2 of interconnect feature 140a is covered by reflective layer 114b. The bottom portion of the sidewall S2 of interconnect feature 140b is covered by reflective layer 114b. The bottom portion of the sidewall S1 of interconnect feature 140b is covered by the top portion of substrate 102. The upper portions of the sidewalls S1 and S2 of interconnect features 140a and 140b are covered by dielectric layer 106.

[0074] Fig.19A and 19B A flow chart of a method 1000 for fabricating a semiconductor structure using a self-aligned photolithography exposure process according to one or more alternative embodiments of the present disclosure is shown. The method 1000 is merely an example and is not intended to limit the present disclosure beyond the scope expressly recited in the claims. Additional steps may be provided before, during, and after the method 1000, and some of the steps described may be moved, replaced, or eliminated for additional embodiments of the method 1000. Figure 20-35 To describe Fig.19A and Fig.19B , which are cross-sectional views of semiconductor structure 30 at various fabrication stages according to method 1000 .

[0075] At operation 1002, method 1000 ( Fig.19A ) provides a semiconductor structure 30, such as Fig. 20 As shown. The semiconductor structure 30 includes a semiconductor substrate 102, a plurality of conductive features 104a-c (collectively referred to as conductive features 104) formed in a top portion of the semiconductor substrate 102, and a dielectric layer 106 above the semiconductor substrate 102. As described below, in the illustrated embodiment, interconnect features (e.g., vias, contacts, or plugs) will be formed to contact and electrically couple with the conductive features 104a and 104b, but not formed on the conductive feature 104c. The conductive feature 104c may be part of an intra-layer wiring or have an interconnect feature elsewhere. The various components and material layers of the semiconductor structure 30 are similar to those described above with reference to Figure 8 The semiconductor structure 20 and Figure 1 The semiconductor structure 10 in FIG. 1 is discussed above and will be briefly discussed below for convenience. Reference numerals are repeated for ease of understanding. Some differences will be emphasized.

[0076] In various embodiments, in a subsequent photolithography exposure process, the dielectric layer 106 has a distance greater than the threshold distance H th The thickness H'. For the photolithography exposure process using DUV radiation, the threshold distance H th The range of H can be from about 5 nm to about 20 nm, for example about 10 nm. th In the example of about 10 nm, H' may range from about 15 nm to about 50 nm, for example about 20 nm. For a lithography exposure process using EUV radiation, the threshold distance H th The range of Hth may be from about 1 nm to about 10 nm, for example, about 5 nm. In an example where Hth is about 5 nm, the range of H' may be from about 10 nm to about 50 nm, for example, about 15 nm. Figure 4-6 When the distance between the photoresist layer and the underlying conductive feature is greater than the threshold distance H th When the exposure contrast is poor, and further affects the critical dimension (CD) of the potential resist pattern formed in the photoresist layer. As will be discussed below, method 1000 uses a first photolithography exposure process to partially recess dielectric layer 106 to below a threshold distance H. th A second photolithography exposure process is then applied to form self-aligned interconnect features.

[0077] At operation 1004, method 1000 ( Fig.19A ) A first photoresist layer 120a is formed on the dielectric layer 106, such as Fig.21 As shown. The formation of the photoresist layer 120a includes coating a photoresist solution on the dielectric layer 106 by a suitable technique (e.g., spin coating). Other manufacturing steps (e.g., soft baking) may be further applied to the first photoresist layer 120a. The first photoresist layer 120a may include a positive photoresist material that becomes soluble in a developer solution after exposure to a radiation source. In some alternative embodiments, the photoresist layer 120a may include a negative photoresist material that becomes insoluble in a developer solution after exposure to a radiation source. The first photoresist layer 120a has a predetermined exposure threshold T1. The thickness of the first photoresist layer 120a may range from about 100 to about 1000 Å. To date between.

[0078] At operation 1006, method 1000 ( Fig.19A ) Perform a first photolithography exposure process 900a to form a latent photoresist pattern in the photoresist layer 120a, such as Fig. 22. The photolithography exposure process 900a uses a photomask 200 having a first IC design pattern 204a and a second IC design pattern 204b (collectively referred to as IC design patterns 204) to expose the photoresist layer 120a with radiation 920a, thereby forming a latent photoresist pattern in the photoresist layer 120. The IC design patterns 204a and 204b are used to form interconnect features (e.g., vias, contacts, or plugs) in the dielectric layer 106. In the illustrated embodiment, the IC design pattern 204a is aligned with the underlying conductive feature 104a, while an overlay error occurs in the IC design pattern 204b, such that the edge of the IC design pattern 204b is offset from the edge of the underlying conductive feature 104b by a distance Δx. The overlay error may be caused by the following reasons: misalignment between the photomask 200 and the semiconductor structure 30, inaccurate geometry of the IC design pattern 204b during the manufacture of the photomask 200, inaccurate calibration in the optical device used in the photolithography exposure process 900a, or other reasons.

[0079] The exposure source for photolithographic exposure to produce radiation 920a may include any suitable source, such as UV, DUV, EUV or charged particles (e.g., electron beam). In some alternative embodiments, the IC design pattern is defined in a data file and transferred to the photoresist layer by direct write or other suitable technology (e.g., digital pattern generator). Other steps may be implemented before, during, or after the exposure process. In some embodiments, a post-exposure bake process may be applied to the photoresist layer 120a after the photolithographic exposure process.

[0080] The radiation 920a is configured such that the incident exposure dose directly from the radiation 920a to the photoresist layer 120 is greater than the exposure threshold T1 of the photoresist layer 120a. Therefore, the portion of the photoresist layer 120 directly below the IC design patterns 204a and 204b receives an incident exposure dose greater than the exposure threshold T1, which results in a chemical change that forms a latent resist pattern. The latent resist pattern is formed in the regions 904a and 904b, as well as in an adjacent region 904c that is offset from the underlying conductive feature 104b.

[0081] At operation 1008, method 1000 ( Fig.19A ) developing the photoresist layer 120a to form a patterned photoresist layer 122a, such as Fig.23In the embodiment shown, the photoresist layer 120a is positive, so the portion of the photoresist layer 120a associated with the latent resist pattern in the regions 904a, 904b, and 904c is removed by the corresponding developer to form an opening. Since the photoresist layer 120a in the region 904c receives an incident exposure dose higher than the exposure threshold T1, the photoresist layer 120a is developed even though it is offset from the conductive feature 104b.

[0082] At operation 1010, method 1000 ( Fig.19A ) The dielectric layer 106 is partially recessed during the etching process, such as Fig.24 The etching process uses the patterned photoresist layer 122a as an etching mask. Operation 1010 may include one or more etching processes to remove different portions of the dielectric layer 106, such as the hard mask layer, the low-k dielectric layer, and the etch stop layer (eg, Figure 1 ) to form a via trench, and extend the via trench in region 904a and the via trenches in regions 904b and 904c down to conductive features 104a and 104b, respectively. In some embodiments, a suitable etching process is used, such as using a CH based etching process. x F y CF x After operation 1010, the distance between the bottom surface 952 of the via trench and the top surface of the conductive feature 104 (denoted as H") is less than the threshold distance H. th (H” <H th In one embodiment, the etching process uses a time pattern to control the etching depth (H'-H") so that the low-k dielectric layer (not shown) of the dielectric layer 106 is partially etched but not penetrated, and the bottom surface 952 of the via trench stops within the low-k dielectric layer. In another embodiment, the etching process etches through the low-k dielectric layer and stops at an etch stop layer (not shown) of the dielectric layer 106 so that the distance H" is defined by the thickness of the etch stop layer. Other operations may then be implemented. For example, the patterned photoresist layer 122a may be removed by a wet stripping or plasma ashing process, such as Fig.25 The plasma ashing process may include using oxygen (O2) plasma or carbon dioxide (CO2) plasma.

[0083] At operation 1012, method 1000 ( Fig.19A ) A second photoresist layer 120b is formed over the dielectric layer 106 and fills the via trenches in the regions 904a-c, as shown in FIG. Fig.26As shown. As discussed with respect to operation 1004, the formation of the second photoresist layer 120b can be substantially similar to the formation of the first photoresist layer 120a. In some embodiments, the formation of the second photoresist layer 120b includes coating a photoresist solution on the dielectric layer 106 by a suitable technique (e.g., spin coating). Other manufacturing steps (e.g., soft baking) can be further applied to the second photoresist layer 120b. In some embodiments, the second photoresist layer 120b includes the same composition as the first photoresist layer 120a. In some embodiments, the second photoresist layer 120b includes a different composition from the first photoresist layer 120a. For example, the composition of the second photoresist layer 120b can be adjusted by changing the ratio of carbon, hydrogen, and oxygen to have different exposure thresholds for the second photolithography exposure process, as will be discussed later in this disclosure. The composition of the second photoresist layer 120b can also be adjusted to be sensitive to a different wavelength of radiation than the first photoresist layer 120a. The second photoresist layer 120b has a predetermined exposure threshold T2. The thickness H' of the second photoresist layer 120a is res The range can be approximately to approximately between.

[0084] At operation 1014, method 1000 ( Fig.19B ) Perform a second photolithography exposure process 900b to form a latent resist pattern in the photoresist layer 120b, such as Fig. 27As shown. In some embodiments, the second lithography exposure process 900b uses the same mask as the first lithography exposure 900a, such as the mask 200 discussed with respect to operation 1006. In the illustrated embodiment, the second lithography exposure process 900b is a blanket lithography exposure process. In other words, the second lithography exposure process 900b does not use a mask, and it exposes the entire semiconductor structure 30. The blanket exposure process helps to reduce the overall cost of manufacturing, such as reducing mask costs and processing time. The exposure source used for the second lithography exposure to generate radiation 920b may include any suitable source, such as UV, DUV, EUV or charged particles, such as an electron beam. In some alternative embodiments, the IC design pattern is defined in a data file, and the IC design pattern is transferred to the photoresist layer by direct writing or other suitable techniques (such as digital pattern generation). The first lithography exposure process 900a and the second lithography exposure process 900b can use the same radiation source. Alternatively, the first lithography exposure process 900a and the second lithography exposure process 900b can use different radiation sources, such as at different radiation wavelengths. In one example, the first photolithography exposure process 900a uses 248nm DUV radiation and the second photolithography exposure process 900b uses 193nm DUV radiation. In another example, the first photolithography exposure process 900a uses DUV radiation and the second photolithography exposure process 900b uses EUV radiation. Other steps can be implemented before, during or after the exposure process. In some embodiments, after the second photolithography exposure process 900b, a post-exposure bake process can be applied to the photoresist layer 120b.

[0085] In the illustrated embodiment, the radiation 920b is configured such that the incident exposure dose from the radiation 920b directly to the photoresist layer 120b is less than the exposure threshold T2 of the photoresist layer 120b, so that a latent photoresist pattern is not formed in the photoresist layer 120b by absorbing the incident exposure dose alone. A portion of the radiation 920b reaches the top surface of the conductive features 104a and 104b and is reflected back to the photoresist layer 120b as reflected radiation 922, and the reflected exposure dose is mainly controlled by the top surface reflectivity R of the conductive features 104 and the intensity of the incident exposure dose. In some embodiments, the thickness H" of the dielectric layer 106 under the via trench is adjusted to control the reflected exposure dose. The sum of the incident exposure dose and the reflected exposure dose is configured to be greater than or at least equal to the exposure threshold T2 of the photoresist layer 120b. Therefore, a latent resist pattern is formed in a portion of the photoresist layer 120b that receives both the incident exposure dose and the reflected exposure dose. Reflected radiation occurs at a portion of the top surface of the conductive feature 104 reached by the incident radiation 920b. At other portions of the top surface of the conductive feature 104 where the incident radiation 920b does not reach or deviates from the top surface of the conductive feature 104, the intensity of the reflected exposure dose is sharply reduced. As discussed with respect to operation 1010, by partially recessing the dielectric layer 106 to reduce the distance between the photoresist layer 120b and the conductive feature 104 to below the threshold distance H th (H” <H th ), the exposure contrast is increased. In other words, only a portion of the photoresist layer 120b (e.g., regions 904a and 904b located directly above the conductive feature 104) receives the sum of the incident exposure dose and the reflected exposure dose, which causes a chemical change to form a latent resist pattern. With respect to a region 904c adjacent to region 904b (offset from the edge of the conductive feature 104b), the region substantially only receives incident radiation 920b, but does not receive reflected radiation 922, the intensity of which is insufficient to expose region 904c. Therefore, the latent resist pattern formed in region 904b does not extend into region 904c. Therefore, the latent resist pattern formed in region 904b is self-aligned with the conductive feature 104b below.

[0086] At operation 1016, method 1000 ( Fig.19B ) Develop the photoresist layer 120b to form a patterned photoresist layer 122b, such as Fig.28As shown. In the illustrated embodiment, the photoresist layer 120 is positive, so the portion of the photoresist layer 122b associated with the latent resist pattern in the regions 904a and 904b is removed by the corresponding developer to expose the via trenches in the regions 904a and 904b. The photoresist layer 120 in the region 904c offset from the conductive feature 104b does not receive an exposure dose above the exposure threshold and remains undeveloped. In other words, the via trench portion above the conductive feature 104b is filled with photoresist.

[0087] At operation 1018, method 1000 ( Fig.19B ) The dielectric layer 106 is etched by using the patterned photoresist layer 122b as an etching mask, thereby transferring the pattern in the patterned photoresist layer 122b to the dielectric layer 106, as shown in FIG. Fig.29 Operation 1020 may include one or more etching processes to remove different portions of dielectric layer 106, such as the low-k dielectric layer and the etch stop layer, to extend the via trenches in regions 904a and 904b down to the top surfaces of conductive features 104a and 104b. The top surfaces of conductive features 104a and 104b are exposed in the corresponding via trenches. The etching process may include any suitable etching technique, such as dry etching, wet etching, or a combination thereof. Other operations may then be performed. For example, patterned photoresist layer 122b may be removed by a wet stripping or plasma ashing process, such as Fig.30 The plasma ashing process may include using oxygen (O2) plasma or carbon dioxide (CO2) plasma.

[0088] In some embodiments, the conductive feature 104 is formed of a continuous metal-containing material or the reflective layer 114b is conductive. Fig.19B ) Optionally, operation 1022 may be proceeded from operation 1018 by depositing a metal layer 130 to fill the via trenches in regions 904a-c and cover the dielectric layer 106, as shown in FIG. Fig.31 As shown. Metal layer 130 is in direct contact with the top surface of conductive features 104a and 104b. In some embodiments, metal layer 130 includes Cu, Al, W or other suitable conductive materials. In some embodiments, metal layer 130 includes a Cu alloy, such as copper magnesium (CuMn), copper aluminum (CuAl) or copper silicon (CuSi). In some embodiments, metal layer 130 is deposited by PVD. In some examples, metal layer 130 is formed by depositing a corresponding metal seed layer using PVD and then forming a bulk metal layer by electroplating.

[0089] At operation 1024, method 1000 ( Fig.19B) performs a chemical mechanical polishing (CMP) process to remove excess metal layer 130, thereby forming interconnect features 140a and 140b, such as through holes 140a and 140b, as shown in FIG. Fig.32 As shown. The CMP process may also remove a top portion of the dielectric layer 106, such as a hard mask layer. The substantially coplanar top surface of the interconnect features 140a and 140b and the dielectric layer 106 may be formed after the CMP process. The interconnect feature 140a has two opposing sidewalls S1 and S2, both of which are connected to the top surface of the conductive feature 104a. Both the sidewalls S1 and S2 of the interconnect feature 140a have a straight profile. The interconnect feature 140b has two opposing sidewalls S1 and S2, both of which are connected to the top surface of the conductive feature 104b. The sidewall S2 of the interconnect feature 104b has a straight profile. The sidewall S1 of the interconnect feature 104b has a stepped profile. The stepped profile includes two vertical sidewall portions S12 and S11 and a horizontal sidewall portion connecting the vertical sidewall portions S12 and S11. The upper sidewall portion S12 is offset from the edge of the conductive feature 104b by a distance Δx. Due to the self-aligned photolithography exposure process, the lower sidewall portion S11 is substantially aligned with the edge of the conductive feature 104 b .

[0090] In some embodiments, the reflective layer 114b of the conductive feature 104 is formed of a highly etch-resistant material, a non-conductive material, or a reflective multilayer, and the method 1000 ( Fig.19B ) Optionally, operation 1018 may proceed to operation 1020 by selectively etching the reflective layer 114b to expose the underlying highly conductive bulk metal layer 114a in the trenches, such as Fig.33 104a and 104b. Operation 1018 includes a selective etching process to remove portions of the reflective layer 114b in the trenches exposed in the regions 904a and 904b. The etching process and etchant are appropriately selected for selective etching without damaging the dielectric layer 106. The etching process may include any suitable etching technique, such as dry etching, wet etching, or a combination thereof. The etching process stops at the bulk metal layer 114a. In the illustrated embodiment, after operation 1020, portions of the reflective layer 114b remain at both ends of the conductive feature 104a, while portions of the reflective layer 114b remain only at one end of the conductive feature 104b.

[0091] refer to Fig.34 and 35 , method 1000( Fig.19B) Then proceed to 1022 and 1024, to deposit metal layer 130 to fill the grooves in region 904a-c, and perform CMP process to remove excess metal layer 130, thereby forming interconnection features 140a and 140b. Interconnection feature 140a has two opposite sidewalls S1 and S2, both of which are connected to the top surface of conductive feature 104a. Both sidewalls S1 and S2 of interconnection feature 140a have straight profiles. Interconnection feature 140b has two opposite sidewalls S1 and S2, both of which are connected to the top surface of conductive feature 104b. Sidewall S2 of interconnection feature 104b has a straight profile. Sidewall S1 of interconnection feature 104b has a stepped profile. The stepped profile includes two vertical sidewall portions S12 and S11 and a horizontal sidewall portion connecting vertical sidewall portions S12 and S11. The upper sidewall portion S12 is offset from the edge of the conductive feature 104b by a distance Δx. Due to the self-aligned lithography exposure process, the lower sidewall portion S11 is substantially aligned with the edge of the conductive feature 104b. The bottom portions of the sidewalls S1 and S2 of the interconnect feature 140a are covered by the reflective layer 114b. As shown in the region 180 surrounding the interface between the interconnect feature 140b and the conductive feature 104b, the bottom portion of the sidewall S2 of the interconnect feature 140b is covered by the reflective layer 114b. The bottom portion of the sidewall S1 of the interconnect feature 140b is covered by the top portion of the substrate 102. The upper portions of the sidewalls S1 and S2 of the interconnect features 140a and 140b are covered by the dielectric layer 106.

[0092] Fig.36A Various embodiments of the interface between interconnect feature 140b and conductive feature 104b in region 180 are shown in -D. As described above, interconnect feature 140b has two opposing sidewalls S1 and S2, where sidewall S1 has an upper sidewall portion S12 offset from an edge of conductive feature 104b and has a lower sidewall portion S11. Fig.36A -D, the upper side wall portion S12 is omitted. Fig.36A , both sidewalls S2 and S11 are substantially perpendicular to the top surface of conductive feature 104b. Sidewall S2 is connected in the middle of the top surface of conductive feature 104b, while sidewall S11 is connected at point P, which is substantially located at the edge of conductive feature 104b (i.e., within a lateral distance of ±4nm of the edge of conductive feature 104b, which is less than 20% of the 20nm through-hole feature CD size). The bottom portion of sidewall S2 is covered by reflective layer 114b, which in various embodiments can be a single reflective layer or a reflective multilayer. The bottom portion of sidewall S11 is covered by the top portion of substrate 102. The upper portions of sidewalls S2 and S11 are covered by dielectric layer 106. In Fig.36BIn FIG. 1 , sidewalls S2 and S11 are inclined relative to the top surface of conductive feature 104 b, which may be caused by the etching process used to form the via trench. Sidewall S11 is connected at point P, which is located at the edge of conductive feature 104 b. Fig.36C In the embodiment, the sloped sidewall S11 may be connected at a point P that is slightly offset from the edge of the conductive feature 104b. In some embodiments, the offset may range from about 1 nm to about 5 nm (depending on the size of the through-hole feature CD), which leaves enough margin to avoid shorting the interconnect feature 140b with the adjacent conductive feature. Fig.36D In the embodiment, the inclined sidewall S11 may be connected to a point P on the top surface of the conductive feature 104b, which is connected to the conductive feature 104b. Fig.36C Point P in the figure is slightly offset in the opposite direction. In some embodiments, the offset can range from about 1 nm to about 5 nm. Fig.36D As shown, the inclined sidewall S11 can cut the top portion of the reflective layer 114b, so that the bottom surface of the sidewall S11 can be covered by the bottom portion of the reflective layer 114b and the top portion of the semiconductor substrate 102. The bottom portion of the reflective layer 114b on the sidewall S11 is lower than the reflective layer 114b on the opposite sidewall S2.

[0093] Although one or more embodiments of the present disclosure are not intended to be limiting, these embodiments provide many benefits for semiconductor devices and their formation. For example, embodiments of the present disclosure provide self-aligned interconnect structures that can reduce or avoid the effects caused by overlapping shifts in photolithography processes. The present disclosure provides a photolithography method that relies on the reflected radiation from the underlying conductive features being the correct amount of exposure dose when forming a latent resist pattern in a resist layer. The latent resist pattern is confined to the area directly above the underlying conductive features. The self-alignment method makes an important contribution to reducing overall manufacturing costs (including processing time and mask costs used in photolithography processes). In addition, the various embodiments discussed herein are not limited to forming interconnects in semiconductor structures, but can also be used to form other structures with alignment and overlapping shift problems.

[0094] In one exemplary aspect, the present disclosure relates to a method for photolithographic patterning. The method includes: providing a semiconductor structure, the semiconductor structure including a substrate and a conductive feature formed in a top portion of the substrate; depositing a resist layer on the substrate, wherein the resist layer has an exposure threshold; providing radiation with an incident exposure dose to the resist layer, wherein the incident exposure dose is configured to be less than the exposure threshold of the resist layer, and the sum of the reflected exposure dose and the incident exposure dose from the top surface of the conductive feature is greater than the exposure threshold of the resist layer, thereby forming a latent resist pattern on the conductive feature; and developing the resist layer to form a patterned resist layer. In some embodiments, the latent resist pattern is located directly above the conductive feature. In some embodiments, the conductive feature includes a reflective layer coated on a bulk metal. In some embodiments, the reflective layer includes a first metal different from the bulk metal. In some embodiments, the reflective layer includes a metal-containing alloy. In some embodiments, the reflective layer includes a plurality of alternating repeating layers. In some embodiments, the method further comprises: forming a dielectric layer over the substrate before depositing the resist layer; after developing the resist layer, etching the dielectric layer using the patterned resist layer as an etching mask to form an opening exposing the top surface of the conductive feature; and depositing a conductive material in the opening to form a conductive structure connected to the conductive feature. In some embodiments, the conductive feature comprises a reflective layer coated on a bulk metal, and the method further comprises: partially etching the reflective layer to expose the bulk metal so that the conductive structure is connected to the bulk metal. In some embodiments, the method further comprises, before depositing the resist layer, partially recessing a portion of the resist layer to form a trench over the conductive feature, wherein the resist layer fills the trench. In some embodiments, the radiation is one of deep ultraviolet (DUV) radiation, extreme ultraviolet (EUV) radiation, and electron beam (E-beam) radiation.

[0095] In another exemplary aspect, the present disclosure relates to a method for photolithographic patterning. The method includes: forming a first conductive feature in a top portion of a substrate; forming a dielectric layer over the substrate; partially recessing the dielectric layer to form a groove over the first conductive feature; applying a resist layer over the dielectric layer, the resist layer filling the groove; exposing the resist layer to radiation, wherein the incident exposure dose of the radiation is configured to form a latent resist pattern in the groove; developing the resist layer to form an opening in the resist layer; etching the dielectric layer through the opening in the resist layer so that a portion of the groove extends through the dielectric layer; and forming a second conductive feature in the groove and contacting the second conductive feature with the first conductive feature. In some embodiments, the top portion of the first conductive feature includes a reflective layer. In some embodiments, the reflective layer includes a plurality of alternating first and second material layers. In some embodiments, the method also includes partially etching the reflective layer to expose a bottom portion of the first conductive feature. In some embodiments, the incident exposure dose of the radiation is configured to be less than an exposure threshold of the resist layer, while the sum of the reflected exposure dose and the incident exposure dose from the top surface of the first conductive feature is greater than the exposure threshold of the resist layer. In some embodiments, the radiation is blanket radiation without using a mask. In some embodiments, the radiation is extreme ultraviolet (EUV) radiation.

[0096] In another exemplary aspect, the present disclosure is directed to a semiconductor structure comprising: a substrate; a first conductive feature embedded in a top portion of the substrate; a dielectric layer located above the substrate; and a second conductive feature surrounded by the dielectric layer and in contact with the first conductive feature, the second conductive feature having a first sidewall and a second sidewall opposite the first sidewall, wherein the first sidewall has a straight profile and is located above the first conductive feature, and wherein the second sidewall has a stepped profile and a top portion of the stepped profile is horizontally offset from an edge of the first conductive feature. In some embodiments, the first conductive feature includes a reflective layer, and wherein a bottom portion of the first sidewall is covered by the reflective layer. In some embodiments, the bottom portion of the stepped profile is substantially aligned with an edge of the first conductive feature.

[0097] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art should understand that they can easily use the present disclosure as a basis for designing or modifying other processes and structures to achieve the same purpose and / or achieve the same advantages of the embodiments introduced herein. Those skilled in the art should also recognize that such equivalent structures do not deviate from the spirit and scope of the present disclosure, and they can make various changes, substitutions and modifications in the present disclosure without departing from the spirit and scope of the present disclosure.

[0098] Example 1. A method for photolithographic patterning, comprising: providing a semiconductor structure, the semiconductor structure including a substrate and a conductive feature formed in a top portion of the substrate; depositing a resist layer over the substrate, wherein the resist layer has an exposure threshold; providing radiation having an incident exposure dose to the resist layer, wherein the incident exposure dose is configured to be less than the exposure threshold of the resist layer, and the sum of the incident exposure dose and a reflected exposure dose from the top surface of the conductive feature is greater than the exposure threshold of the resist layer, thereby forming a latent resist pattern over the conductive feature; and developing the resist layer to form a patterned resist layer.

[0099] Example 2. The method of Example 1, wherein the latent resist pattern is located directly above the conductive feature.

[0100] Example 3. The method of Example 1, wherein the conductive feature comprises a reflective layer coated on a bulk metal.

[0101] Example 4. The method of Example 3, wherein the reflective layer comprises a first metal different from the bulk metal.

[0102] Example 5. The method of Example 3, wherein the reflective layer comprises a metal-containing alloy.

[0103] Example 6. The method of Example 3, wherein the reflective layer comprises a plurality of alternating repeating layers.

[0104] Example 7. The method according to Example 1 further includes: forming a dielectric layer above the substrate before depositing the resist layer; after developing the resist layer, etching the dielectric layer using the patterned resist layer as an etching mask to form an opening exposing the top surface of the conductive feature; and depositing a conductive material in the opening to form a conductive structure connected to the conductive feature.

[0105] Example 8. A method according to Example 7, wherein the conductive feature includes a reflective layer coated on a bulk metal, and the method further includes: partially etching the reflective layer to expose the bulk metal so that the conductive structure is connected to the bulk metal.

[0106] Example 9. The method according to Example 7 further includes: before depositing the resist layer, partially recessing a portion of the resist layer to form a trench above the conductive feature, wherein the resist layer fills the trench.

[0107] Example 10. The method of Example 1, wherein the radiation is one of deep ultraviolet (DUV) radiation, extreme ultraviolet (EUV) radiation, and electron beam (E-beam) radiation.

[0108] Example 11. A method for photolithographic patterning, comprising: forming a first conductive feature in a top portion of a substrate; forming a dielectric layer over the substrate; partially recessing the dielectric layer to form a groove over the first conductive feature; coating a resist layer over the dielectric layer, the resist layer filling the groove; exposing the resist layer to radiation, wherein an incident exposure dose of the radiation is configured to form a latent resist pattern in the groove; developing the resist layer to form an opening in the resist layer; etching the dielectric layer through the opening in the resist layer so that a portion of the groove extends through the dielectric layer; and forming a second conductive feature in the groove and contacting the second conductive feature with the first conductive feature.

[0109] Example 12. The method of Example 11, wherein a top portion of the first conductive feature includes a reflective layer.

[0110] Example 13. The method of Example 12, wherein the reflective layer comprises a plurality of alternating first material layers and second material layers.

[0111] Example 14. The method of Example 12, further comprising: partially etching the reflective layer to expose a bottom portion of the first conductive feature.

[0112] Example 15. A method according to Example 11, wherein the incident exposure dose of the radiation is configured to be less than an exposure threshold of the resist layer, and the sum of the incident exposure dose and the reflected exposure dose from the top surface of the first conductive feature is greater than the exposure threshold of the resist layer.

[0113] Example 16. The method of Example 11, wherein the radiation is blanket radiation without using a mask.

[0114] Example 17. The method of Example 11, wherein the radiation is extreme ultraviolet (EUV) radiation.

[0115] Example 18. A semiconductor structure comprising: a substrate; a first conductive feature embedded in a top portion of the substrate; a dielectric layer located above the substrate; and a second conductive feature surrounded by the dielectric layer and in contact with the first conductive feature, the second conductive feature having a first sidewall and a second sidewall opposite to the first sidewall, wherein the first sidewall has a straight profile and is located above the first conductive feature, and wherein the second sidewall has a stepped profile and a top portion of the stepped profile is horizontally offset from an edge of the first conductive feature.

[0116] Example 19. The semiconductor structure of Example 18, wherein the first conductive feature comprises a reflective layer, and wherein a bottom portion of the first sidewall is covered by the reflective layer.

[0117] Example 20. The semiconductor structure of Example 18, wherein a bottom portion of the stepped profile is substantially aligned with the edge of the first conductive feature.

Claims

1. A method for photolithography patterning, comprising: providing a semiconductor structure comprising a substrate and a conductive feature formed in a top portion of the substrate; forming a dielectric layer over the substrate; Depositing a resist layer on the substrate, wherein the resist layer has an exposure threshold; providing radiation having an incident exposure dose to the resist layer through a photomask, wherein the incident exposure dose is configured to be less than the exposure threshold of the resist layer, and a sum of the incident exposure dose and a reflected exposure dose from a top surface of the conductive feature is greater than the exposure threshold of the resist layer, thereby forming a latent resist pattern over the conductive feature; developing the resist layer to form a patterned resist layer; etching the dielectric layer using the patterned resist layer as an etch mask to form openings exposing the top surfaces of the conductive features; and A conductive material is deposited in the opening to form a conductive structure connected to the conductive feature, wherein the conductive feature includes a reflective layer coated on a bulk metal.

2. The method according to claim 1, wherein: The latent resist pattern is located directly over the conductive feature.

3. The method according to claim 1, wherein: The conductive features include a reflective layer coated on a bulk metal.

4. The method according to claim 3, wherein: The reflective layer includes a first metal different from the bulk metal.

5. The method according to claim 3, wherein: The reflective layer includes a metal-containing alloy.

6. The method according to claim 3, wherein: The reflective layer includes a plurality of alternating repeating layers.

7. The method according to claim 1, further comprising: The reflective layer is partially etched to expose the bulk metal, so that the conductive structure is connected to the bulk metal.

8. The method according to claim 1, further comprising: Prior to depositing the resist layer, a portion of the dielectric layer is partially recessed to form a trench over the conductive feature, wherein the resist layer fills the trench.

9. The method according to claim 1, wherein: The radiation is one of deep ultraviolet (DUV) radiation, extreme ultraviolet (EUV) radiation, and electron beam (E-beam) radiation.

10. A method for photolithographic patterning, comprising: forming a first conductive feature in a top portion of the substrate; forming a dielectric layer over the substrate; partially recessing the dielectric layer to form a trench over the first conductive feature; Coating a resist layer on the dielectric layer, wherein the resist layer fills the trench; exposing the resist layer to radiation, wherein an incident exposure dose of the radiation is configured to form a latent resist pattern in the trench; developing the resist layer to form openings in the resist layer; etching the dielectric layer through the opening in the resist layer such that a portion of the trench extends through the dielectric layer; and A second conductive feature is formed in the trench and in contact with the first conductive feature.

11. The method according to claim 10, wherein: A top portion of the first conductive feature includes a reflective layer.

12. The method according to claim 11, wherein: The reflective layer includes a plurality of alternating first material layers and second material layers.

13. The method according to claim 11, further comprising: The reflective layer is partially etched to expose a bottom portion of the first conductive feature.

14. The method according to claim 10, wherein: The incident exposure dose of the radiation is configured to be less than an exposure threshold of the resist layer, while a sum of the incident exposure dose and a reflected exposure dose from a top surface of the first conductive feature is greater than the exposure threshold of the resist layer.

15. The method according to claim 10, wherein: The radiation is blanket radiation without the use of a mask.

16. The method according to claim 10, wherein: The radiation is extreme ultraviolet EUV radiation.

17. A semiconductor structure comprising: substrate; a first conductive feature embedded in a top portion of the substrate, the first conductive feature having a first edge and a second edge opposite the first edge; a dielectric layer disposed on the substrate; as well as A second conductive feature is surrounded by the dielectric layer and in contact with the first conductive feature, the second conductive feature having a first sidewall and a second sidewall opposite to the first sidewall, wherein the second sidewall is adjacent to the second edge of the first conductive feature and away from the first edge of the first conductive feature, wherein the first sidewall has a straight profile and is directly located above the first conductive feature and horizontally offset from the first edge of the first conductive feature, and wherein the second sidewall has a stepped profile and a top portion of the stepped profile is horizontally offset from the second edge of the first conductive feature.

18. The semiconductor structure according to claim 17, wherein: The first conductive feature includes a reflective layer, and wherein a bottom portion of the first sidewall is covered by the reflective layer.

19. The semiconductor structure according to claim 17, wherein: A bottom portion of the stepped profile is substantially aligned with the second edge of the first conductive feature.

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