Semiconductor device, semiconductor wafer and method of manufacturing the same

Abstract

The present disclosure relates to semiconductor devices, semiconductor wafers, and methods of manufacturing the same. A semiconductor device is provided. The semiconductor device includes a semiconductor substrate and a first deep trench isolation (DTI) structure filled with a dielectric material formed on the semiconductor substrate. The first DTI structure is disposed in a first seal ring region and extends into the semiconductor substrate. The semiconductor substrate has a pixel array region and the first seal ring region. The first seal ring region is proximate to an edge of the semiconductor substrate and surrounds the pixel array region. The first DTI structure is formed in the first seal ring region and surrounds the pixel array region.

Description

Technical Field

[0001] This application relates to semiconductor devices, semiconductor wafers, and methods of manufacturing the same. Background Technology

[0002] During a dicing or dicing operation on a wafer (by means of, for example, sawing or cutting techniques, which may include lasers, diamond saws, or one or more other suitable techniques), a sealing ring may be introduced in the outer region surrounding the active region of each die or chip to protect the circuitry formed in the active region from damage or cracking caused by the dicing or dicing operation.

[0003] However, sealing rings may not be effective in preventing damage or cracks from propagating to the active areas of each die / chip. Summary of the Invention

[0004] In some embodiments, this disclosure provides a semiconductor device. The semiconductor device includes a semiconductor substrate and a first deep trench isolation (DTI) structure, the first DTI structure being filled with a dielectric material and extending into the semiconductor substrate. The semiconductor substrate has a pixel array region and a first sealing ring region. The first sealing ring region is located near an edge of the semiconductor substrate and surrounds the pixel array region. The first DTI structure surrounds the pixel array region.

[0005] In some embodiments, the semiconductor device may further include a first sealing ring formed in the first sealing ring region. The first sealing ring is disposed near the edge of the semiconductor substrate and is vertically separated from the first DTI structure by a certain distance.

[0006] In one embodiment, the first sealing ring and the first DTI structure are separated by at least one dielectric layer.

[0007] In some embodiments, this disclosure provides a semiconductor device. The semiconductor device includes a semiconductor substrate and a plurality of first deep trench isolation (DTI) structures filled with a dielectric material. Each of the plurality of first DTI structures extends into the semiconductor substrate. The semiconductor substrate has a pixel array region and a first sealing ring region. The first sealing ring region is located near an edge of the semiconductor substrate and surrounds the pixel array region. The plurality of first DTI structures surround the pixel array region.

[0008] In some embodiments, this disclosure provides a semiconductor wafer. The semiconductor wafer includes at least one semiconductor device as described above and a dicing region surrounding the at least one semiconductor device.

[0009] In some embodiments, this disclosure provides a method for manufacturing a semiconductor device. The method includes providing a semiconductor substrate having a first surface and a second surface. The method further includes forming a plurality of sealing rings on the first surface of the semiconductor substrate. The method further includes forming a plurality of first DTI structures from the second surface of the semiconductor substrate corresponding to the sealing rings. Attached Figure Description

[0010] When with attachment Figure 1 When reading the following detailed description, various aspects of this disclosure can be readily understood from it. It should be noted that the various features may not necessarily be drawn to scale. In fact, for clarity of discussion, the dimensions of the various features may be arbitrarily increased or decreased.

[0011] Figure 1 A plan view of a semiconductor wafer according to some embodiments of the present disclosure is shown;

[0012] Figure 2 Examples of embodiments according to this disclosure are shown. Figure 1 An enlarged top view of the portion within the dashed box A shown;

[0013] Figure 3 Examples of embodiments according to this disclosure are shown. Figure 1 An enlarged bottom view of the portion within the dashed box A shown;

[0014] Figure 4 Examples of embodiments according to this disclosure are shown below. Figure 2 The cross-sectional view taken by line AA' shown;

[0015] Figure 5 Cross-sectional views of semiconductor devices according to some embodiments of the present disclosure are shown;

[0016] Figure 6 Examples of embodiments according to this disclosure are shown. Figure 5 An enlarged view of the structure within the dashed box B shown;

[0017] Figures 7A-7E The operation of a semiconductor manufacturing apparatus at various stages according to some embodiments of the present disclosure is illustrated. Detailed Implementation

[0018] The following disclosure provides numerous different embodiments or instances for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below. Of course, these are merely examples and are not intended to be limiting. In this disclosure, references to forming a first feature on or over a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features such that the first and second features are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in various instances of this disclosure. Such repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0019] Throughout this specification, references to "example" or "embodiment" mean that a feature, structure, or characteristic described in connection with the example is included in at least one example of the invention. Therefore, the phrases "in an example" or "in an embodiment" appearing in various places throughout this specification do not necessarily all refer to the same example or embodiment. Furthermore, features, structures, or characteristics may be combined in any suitable manner in one or more examples.

[0020] As used herein, the terms “have,” “may have,” “include,” “may contain,” or “include” indicate the presence of a corresponding feature (e.g., a number, function, operation, or element) and do not exclude the presence of other features.

[0021] Terms such as “first,” “second,” and “third” are used in this specification to avoid confusion between components and do not set or limit the order and / or priority. For example, a first element may be referred to as a second element without departing from the scope of this disclosure, and vice versa.

[0022] The terminology used herein is not intended to limit this disclosure, but rather to describe particular exemplary embodiments. Unless otherwise stated, singular terms may include plural forms. The terms used herein (including technical or scientific terms) have the same meaning as understood by one of skill in the art. Commonly used terms as defined in dictionaries may be interpreted as having the same or similar meaning in the context of their definition in the relevant field, and should not be interpreted in an idealized or overly formal sense unless explicitly defined otherwise. Depending on the circumstances, even terms defined herein should not be construed as excluding exemplary embodiments of this disclosure.

[0023] Embodiments of this disclosure are discussed in detail below. However, it should be understood that this disclosure provides many applicable concepts that can be embodied in a wide variety of specific contexts. The specific embodiments discussed are merely illustrative and do not limit the scope of this disclosure.

[0024] Figure 1A plan view of a semiconductor wafer 100 according to some embodiments of the present disclosure is shown.

[0025] Semiconductor wafer 100 may include a semiconductor substrate ( Figure 1 (Not shown in the image). The semiconductor substrate may comprise, for example, but not limited to, silicon, germanium, or one or more other semiconductor materials. The semiconductor substrate may be doped with impurities. In one embodiment, the semiconductor substrate may be a silicon substrate doped with a p-type dopant (e.g., but not limited to boron). In another example, the semiconductor substrate may be a silicon substrate doped with an n-type dopant (e.g., but not limited to phosphorus or arsenic).

[0026] Semiconductor wafer 100 may include one or more dies or semiconductor devices 102 formed thereon. Semiconductor wafer 100 may have scribe lines 104 surrounding the semiconductor devices 102. The scribe line width of each scribe line in scribe line 104 may be, for example, between 50 micrometers (μm) and 130 μm. The scribe line depth of each scribe line in scribe line 104 may be, for example, between 2 μm and 3 μm. Without departing from the scope of this disclosure, semiconductor wafer 100 may not include scribe lines 104, or may have scribe lines 104 with a depth of zero. In some embodiments, scribe line 104 may be referred to as scribe region 104 or scribe line region 104.

[0027] Semiconductor device 102 may include, for example, but not limited to, a back-illuminated (BSI) die or a back-illuminated (BSI) image sensor.

[0028] The dicing groove 104 may surround the semiconductor device 102. The dicing groove 104 may separate one semiconductor device 102 from another semiconductor device. The dicing groove 104 may be disposed or formed near the edge or periphery of the semiconductor device 102.

[0029] Single-cut or dicing operations can be performed along the dicing groove 104. For example, diamond sawing or cutting techniques can be applied along the dicing groove 104 to separate or divide the semiconductor wafer 100 into one or more individual dies or semiconductor devices 102.

[0030] Figure 2 Examples of embodiments according to this disclosure are shown. Figure 1 An enlarged top view of the portion within the dashed box A shown.

[0031] refer to Figure 2 Semiconductor device 102 ( Figure 2 (Not shown in the image) can be formed within the area enclosed by the dashed line 106b. The semiconductor device 102 may include a semiconductor substrate 112.

[0032] The semiconductor substrate 112 has a pixel array region, an outer sealing ring region (or a first sealing ring region), and an inner sealing ring region (or a second sealing ring region) defined thereon. For example, the pixel array region can be defined as the region surrounded by dashed line 108a. The inner sealing ring region can be defined as the region between dashed lines 108a and 106a. The outer sealing ring region can be defined as the region between dashed lines 106a and 106b.

[0033] The pixel array region defined on the semiconductor substrate 112 may include one or more pixel regions 112a. The one or more pixel regions 112a may be formed as an array and spaced apart at a certain pitch. In one example, the pitch may be 2.1 μm. The one or more pixel regions 112a may be formed within the region enclosed by dashed line 108a. The region enclosed by dashed line 108a may be located within or defined within the region enclosed by dashed line 106a. The region enclosed by dashed line 106a is relatively larger than the region enclosed by dashed line 108a. In other words, the area of ​​the region enclosed by dashed line 106a on the semiconductor substrate 112 is larger than the area enclosed by dashed line 108a. For clarity and to avoid obscuring the invention, details of some known pixel elements, such as photodiode regions, transfer transistors, floating diffusion regions, source followers, reset transistors, bit lines, control and readout circuitry systems, are omitted from the figures.

[0034] Each pixel region 112a may include a photosensitive or detector structure for generating an image signal in response to incident light. In one example, the pixel array region may include multiple deep trench isolation (DTI) structures, such as DTI structures 128, 130, 132 (more details provided later), formed on a semiconductor substrate 112 to provide isolation between one or more adjacent pixel regions 112a. The multiple DTI structures, such as DTI structures 128, 130, and 132, define a unit pixel region or area of ​​one or more photosensitive or detector structures. In one example, the pixel region 112a may include a DTI structure formed around the one or more photosensitive or detector structures.

[0035] DTI structures 128, 130, and 132 can be disposed in the region enclosed by dashed line 108a. DTI structures 128, 130, and 132 can be filled with a dielectric material, such as an oxide material.

[0036] Semiconductor substrate 112 may contain some DTI structures in a region near or adjacent to scribe groove 104. Semiconductor substrate 112 may contain some DTI structures in a region near or adjacent to the periphery or edge of semiconductor device 102. An outer sealing ring region is defined near the edge of semiconductor substrate 112, for example, near dashed line 106b. The outer sealing ring region surrounds the inner sealing ring region and the pixel array region. The inner sealing ring region is defined between the outer sealing ring region and the pixel array region, and therefore surrounds the one or more pixel regions 112a. The inner sealing ring region and the outer sealing ring region may each contain sealing ring structures formed therein as stress relief structures, crack arresters, and / or moisture / contaminant barriers to protect active device regions such as pixel regions 112a in the pixel array region.

[0037] like Figure 2 As shown, the outer sealing ring region may contain one or more DTI structures, such as DTI structures 118, 120, 122, 124, and 126. Each DTI structure surrounds the pixel array region and extends a distance from the surface of the semiconductor substrate 112 into the semiconductor substrate 112. Each DTI structure is filled with a dielectric material to further buffer or mitigate stress encountered during die dicing or splitting operations. The dielectric material may include, but is not limited to, oxides or dielectric materials with a dielectric constant greater than 3.9.

[0038] The DTI structures 118, 120, 122, 124, and 126 in the outer sealing ring region can be formed simultaneously with the DTI structures 128, 130, and 132 in the pixel array region. The spacing between each DTI structure in the outer sealing ring region can be the same as the spacing between each DTI structure in the pixel array region.

[0039] In one example, the outer sealing ring region of the semiconductor substrate 112 may contain a DTI structure, such as DTI structure 118. DTI structure 118 may surround or enclose the region enclosed by dashed line 106a. DTI structure 118 may surround or enclose the region enclosed by dashed line 108a. DTI structure 118 may be filled with a dielectric material, such as an oxide material. DTI structure 118 may surround or enclose a pixel array region. DTI structure 118 may surround DTI structure 128. DTI structure 118 may surround or enclose DTI structure 130. DTI structure 118 may surround or enclose DTI structure 132.

[0040] In one example, the outer sealing ring region of the semiconductor substrate 112 may further include DTI structures 120, 122, 124, and 126. Each of the DTI structures 120, 122, 124, and 126 may be filled with a dielectric material. DTI structure 120 may surround DTI structure 118. DTI structure 122 may surround DTI structure 120. DTI structure 124 may surround DTI structure 122. DTI structure 126 may surround DTI structure 124. In other words, DTI structure 118 may be surrounded by DTI structure 120. DTI structure 120 may be surrounded by DTI structure 122. DTI structure 122 may be surrounded by DTI structure 124. DTI structure 124 may be surrounded by DTI structure 126.

[0041] The dicing groove 104 or dicing area 104 may not contain any DTI structure.

[0042] Despite Figure 2 Only DTI structures 118, 120, 122, 124, 126, 128, 130, and 132 are shown in the figure. However, it is contemplated that, according to some other embodiments of this disclosure, the outer sealing ring region of the semiconductor substrate 112 may contain more or fewer DTI structures. Those skilled in the art will understand that although five DTI structures are shown between dashed lines 106a and 106b in the figure, the number of DTI structures formed in the outer sealing ring region may depend more or less on the area of ​​the outer sealing ring region, for example, the area enclosed between dashed lines 106a and 106b, and the spacing or pitch between each DTI structure in the DTI structure. For example, more (relatively smaller-spaced) DTI structures may be formed in the region enclosed by dashed line 108a to define a relatively small-spaced pixel region. For example, more DTI structures with relatively small spacing or pitch may be formed between dashed lines 106a and 106b.

[0043] Each DTI structure in DTI structures 118, 120, 122, 124, 128, 130, and 132 can be surrounded by DTI structure 126. Each DTI structure in DTI structures 118, 120, 122, 128, 130, and 132 can be surrounded by DTI structure 124. Each DTI structure in DTI structures 118, 120, 128, 130, and 132 can be surrounded by DTI structure 122. Each DTI structure in DTI structures 118, 128, 130, and 132 can be surrounded by DTI structure 120. Each DTI structure in DTI structures 128, 130, and 132 can be surrounded by DTI structure 118.

[0044] DTI structure 126 can be placed next to DTI structure 124. DTI structure 124 can be placed next to DTI structure 122. DTI structure 122 can be placed next to DTI structure 120. DTI structure 120 can be placed next to DTI structure 118. DTI structure 128 can be placed next to DTI structure 130. DTI structure 130 can be placed next to DTI structure 132.

[0045] DTI structures 118, 120, 122, 124, and 126 can be laterally spaced. In one example, the spacing between DTI structures 118, 120, 122, 124, and 126 can be the same as the spacing between each pixel region 112a, for example, spaced apart by the same pixel pitch. The groove width of DTI structures 118, 120, 122, 124, and 126 can be... Figure 2 The groove widths shown are the same; however, those skilled in the art will understand that DTI structures 118, 120, 122, 124, and 126 may have different groove widths based on desired isolation and stress relief performance.

[0046] In one embodiment, DTI structure 126 may be referred to as the outermost DTI structure in the outer sealing ring region, and DTI structure 118 may be referred to as the innermost DTI structure in the outer sealing ring region. DTI structure 126 may be laterally spaced from the scribbling region 104.

[0047] Figure 3 Examples of embodiments according to this disclosure are shown. Figure 1 An enlarged bottom view of the portion within the dashed box A shown.

[0048] refer to Figure 3 Semiconductor device 102 ( Figure 3 (Not shown in the text) can be formed within the area enclosed by the dashed line 106b.

[0049] Semiconductor device 102 may include region 110. Region 110 may be surrounded by dashed line 108a. Region 110 may correspond to a pixel array region and may include one or more such regions. Figure 2 The pixel region 112a is shown. Region 110 can further enclose the vertically corresponding to, for example... Figure 2 The area shown is pixel region 112a.

[0050] Semiconductor device 102 may include conductive interconnects 111 (e.g., stacked conductive structures 111 or metal wires 111) formed in region 110 for providing necessary pixel circuitry connections associated with the one or more pixel regions. To avoid obscuring the invention, only relevant details of the conductive interconnects 111 are provided.

[0051] In one embodiment, the semiconductor device 102 may further include a metal stack 114 or a metal ring 114. The metal ring 114 may be disposed adjacent to or near region 110. The metal ring 114 may be disposed in an inner sealing ring region or in the region enclosed by the dashed line 106a. The metal ring 114 may surround or enclose region 110. The metal ring 114 may surround or enclose the conductive interconnect 111. The metal ring 114 may be referred to as an inner sealing ring.

[0052] In one embodiment, the semiconductor device 102 may further include a metal stack 116 or a metal ring 116. The metal ring 116 may be disposed in the region between dashed lines 106a and 106b, i.e., the metal ring 116 may be disposed in the outer sealing ring region. The metal ring 116 may surround or enclose region 110. The metal ring 116 may surround or enclose conductive interconnect 111. The metal ring 116 may surround or enclose metal ring 114. The metal ring 116 may be referred to as the outer sealing ring.

[0053] Metal rings 114 and 116 may be formed of metallic materials, including but not limited to aluminum, tungsten, copper, or alloy metals. Metal rings 114 and 116 may be included to act as stress relief elements, crack arresters, and / or moisture / contaminant barriers.

[0054] Semiconductor device 102 may include a dielectric material forming one or more dielectric layers 156, known as interlayer dielectric (ILD) layers, for separating adjacent metal interconnect layers of metal stacks 114, 116 and conductive interconnects 111.

[0055] Figure 4 Some embodiments according to this disclosure are shown below. Figure 2 The cross-sectional view taken by the A-A' line shown.

[0056] refer to Figure 4 The semiconductor device 102, which can be surrounded or enclosed by the dicing groove 104, may include a semiconductor substrate 112. The thickness of the semiconductor substrate 112 may range from 4 μm to 10 μm. In one embodiment, the thickness of the semiconductor substrate 112 may range from 6 μm to 8 μm.

[0057] Semiconductor substrate 112 has a first side 112s1 (e.g., back side), a second side 112s2 (e.g., front side) opposite to the first side 112s1, and a third side 112s3 extending from the first side 112s1 to the second side 112s2. Semiconductor substrate 112 may have an active region 110 (e.g., pixel array region), a first sealing ring region 106 (e.g., outer sealing ring region), and a second sealing ring region 108 (e.g., inner sealing ring region). Active region 110 may include one or more pixel regions 112a. Each pixel region in the one or more pixel regions 112a may include one or more photodetectors or photosensitive elements operable to generate charge in response to incident light from the first side 112s1. Incident light can enter through the first side 112s1 and can be sensed by the one or more photodetectors in the active region 110. In other words, the one or more photodetectors formed in the semiconductor substrate 112 can operatively sense or detect incident light entering through the surface of the first side 112s1. The first side 112s1 may be referred to as the light-receiving side of the semiconductor substrate 112.

[0058] Conductive interconnects 111 may be formed within the active region 110. The semiconductor device 102 may include a dielectric layer 156 formed on the second side 112s2. The dielectric layer 156 may be formed by depositing a dielectric material (e.g., an oxide material such as silicon oxide) on the surface of the second side 112s2, for example, via a chemical vapor deposition process. In some embodiments, the conductive interconnects 111 may be referred to as metal interconnects.

[0059] Semiconductor device 102 may include conductive interconnects 111 formed on a second side 112s2 of semiconductor substrate 112 and embedded in dielectric layer 156. In one embodiment, semiconductor device 102 may have conductive interconnects 111 surrounded by dielectric material.

[0060] Semiconductor device 102 may include a metal stack 114 formed on a second side 112s2 of semiconductor substrate 112 and embedded in dielectric layer 156. Alternatively, the metal stack 114 may be surrounded and embedded in dielectric material. The metal stack 114 may be, for example, an internal sealing ring structure. In one embodiment, the metal stack 114 may serve as a sealing and support structure. In another embodiment, the metal stack 114 may be configured to route signals between pixel array circuitry and associated peripheral logic circuitry.

[0061] Semiconductor device 102 may include a metal stack 116 formed on a second side 112s2 of semiconductor substrate 112 and embedded in dielectric layer 156. The metal stack 116 is surrounded by dielectric material. The metal stack 116 may be, for example, an external sealing ring structure.

[0062] Metal stack 114 may be formed within the second sealing ring region 108. Metal stack 116 may be formed within the first sealing ring region 106. In one embodiment, the distance between dashed lines 106a and 106b ranges from about 4 μm to about 12 μm. In another embodiment, the distance between dashed lines 106a and 106b ranges from about 6 μm to about 10 μm.

[0063] Conductive interconnects 111 may be disposed on a second side 112s2 of the semiconductor substrate 112. A metal stack 114 formed in the dielectric layer 156 may be disposed on the second side 112s2 of the semiconductor substrate 112. A metal stack 116 formed in the dielectric layer 156 may be disposed near the second side 112s2 of the semiconductor substrate 112. The metal stacks 114 and 116 formed above the surface of the second side 112s2 of the semiconductor substrate 112 may be vertically or vertically separated from the surface of the second side 112s2 of the semiconductor substrate 112 by the dielectric layer 156. A portion of the dielectric layer 156 is disposed or interposed between the metal stack 114 and each of the DTI structures 118, 120, 122, 124, and 126. A portion of the dielectric layer 156 is disposed or interposed between the metal stack 116 and each of the DTI structures 118, 120, 122, 124, and 126.

[0064] The conductive interconnect 111 may comprise multiple conductive interconnect layers, wherein a dielectric layer 156 separates adjacent conductive interconnect layers. The dielectric layer 156 further separates adjacent metal interconnect layers of the metal stacks 114 and 116.

[0065] The metal stack 116 may be disposed near the edge or periphery of the semiconductor substrate 112. The edge or periphery of the semiconductor substrate 112 may also be the edge or periphery of the semiconductor device 102. The metal stack 116 may surround the metal stack 114. The metal stack 116 may enclose the metal stack 114. The metal stack 116 may be laterally spaced from the metal stack 114. The metal stack 116 may be horizontally spaced from the metal stack 114.

[0066] exist Figure 4 In the embodiments described, dielectric layer 156 is a single dielectric layer, but without departing from the scope of this disclosure, dielectric layer 156 may be a multi-dielectric-layer structure, such as a three- or four-dielectric-layer stacked structure. Figure 4 Each of the metal stacks 114 and 116 contains three metal interconnect layers, but in other embodiments, each of the metal stacks 114 and 116 may contain more or fewer metal interconnect layers, depending on the requirements of the internal and external sealing ring structures of the semiconductor device 102.

[0067] The semiconductor substrate 112 may have DTI structures 118, 120, 122, 124, 126, 128, 130 and 132 formed thereon.

[0068] Viewed from the first side 112s1 of the semiconductor substrate 112, DTI structures 118, 120, 122, 124, and 126 can be vertically formed above the metal stack 116. Specifically, DTI structure 118 can be formed above the metal stack 116. DTI structure 118 can be vertically aligned with the metal stack 116. DTI structure 120 can be formed above the metal stack 116. DTI structure 122 can be formed above the metal stack 116. DTI structure 124 can be formed above the metal stack 116. DTI structure 126 can be formed above the metal stack 116. DTI structure 118 can be formed within the first sealing ring region 106. DTI structure 120 can be formed within the first sealing ring region 106. DTI structure 122 can be formed within the first sealing ring region 106. DTI structure 124 can be formed within the first sealing ring region 106. DTI structure 126 can be formed within the first sealing ring region 106.

[0069] DTI structure 118 can be vertically aligned with metal stack 116. DTI structure 120 can be vertically aligned with metal stack 116. DTI structure 122 can be vertically aligned with metal stack 116. DTI structure 124 can be vertically aligned with metal stack 116. DTI structure 126 can be vertically aligned with metal stack 116. In a plan view, DTI structures 118, 120, 122, 124, and 126 can overlap with metal stack 116. DTI structures 118, 120, 122, 124, and 126 and metal stack 116 are formed in different layers and therefore do not contact metal stack 116; that is, a first vertical space exists between DTI structures 118, 120, 122, 124, and 126 and metal stack 116. The range of the first vertical distance between each of the DTI structures 118, 120, 122, 124, and 126 and metal stack 116 can be between and between.

[0070] In one embodiment, each of the metal stack 116 and the DTI structures 118, 120, 122, 124, 126 is vertically separated by at least one interlayer dielectric layer (such as dielectric layer 156). In other words, each of the DTI structures 118, 120, 122, 124, 126 can be positioned on the interlayer dielectric layer and is not in contact with the metal stack 116.

[0071] It is worth noting that by forming a first distance between the DTI structures 118, 120, 122, 124, 126 formed in the first sealing ring region (e.g., the outer sealing ring region) and the metal stack 116, the DTI structures 118, 120, 122, 124, 126 do not need to be vertically or laterally aligned with the metal stack 116. In other words, the spacing and associated groove widths between the DTI structures 118, 120, 122, 124, 126 can be configured more flexibly. For example, the spacing and groove widths associated with the DTI structures 118, 120, 122, 124, 126 can be configured based on stress relief or treatment requirements.

[0072] Furthermore, the DTI structures 118, 120, 122, 124, and 126 disposed in the first sealing ring region and the DTI structures 128, 130, and 132 disposed in the active region 110 can be formed using the same process, i.e., simultaneously using the same mask, because the DTI structures 118, 120, 122, 124, and 126 can be configured to have the same trench characteristics as the DTI structures 128, 130, and 132 (e.g., the same trench depth, the same trench width, or the same trench spacing). Thus, no additional process is required to form the DTI structures 118, 120, 122, 124, and 126.

[0073] exist Figure 4 In the perspective view, the one or more DTI structures can be formed on the surface of a first side 112s1 (e.g., the back side) of the semiconductor substrate 112 and extend from the surface of the first side 112s1 into the semiconductor substrate 112. According to some other embodiments of this disclosure, one or more DTI structures in the inner sealing ring region 108 can be formed above or on the metal stack 114 at a second vertical distance. Similarly, the range of the second vertical distance between the DTI structure in the inner sealing ring region and the metal stack 114 can be between... and Between. In one embodiment, the second vertical distance may be the same as the first vertical distance. In other embodiments, the second vertical distance may be different from the first vertical distance. In one embodiment, the one or more DTI structures may be formed to be vertically aligned with the metal stack 114. Although in Figure 4 As not shown in the figure, but according to some other embodiments of the present disclosure, the semiconductor substrate 112 may include one or more DTI structures in the second sealing ring region 108.

[0074] Each of the DTI structures 118, 120, 122, 124, 126, 128, 130, and 132 may be laterally or horizontally spaced from each other. Any DTI structure in the DTI structures (e.g., DTI structures 118, 120, 122, 124, and 126) may be laterally or horizontally spaced from the dicing region 104. In other words, the dicing region 104 may not contain any DTI structures.

[0075] In one embodiment, DTI structure 126 may be referred to as the outermost DTI structure in the first sealing ring region 106, and DTI structure 118 may be referred to as the innermost DTI structure in the first sealing ring region 106. DTI structure 126 may be laterally spaced from the scribbling region 104.

[0076] DTI structures 118, 120, 122, 124, 126, 128, 130, and 132 may be laterally spaced apart by a pitch P, which may range from approximately 0.8 μm to approximately 2.5 μm. It is contemplated that, according to some other embodiments of this disclosure, the pitch P may be varied or changed as needed, for example, based on the pixel spacing between pixel regions 112a. Although Figure 4 The DTI structures 118, 120, 122, 124, 126, 128, 130, and 132 shown may have the same spacing P; however, it is contemplated that the distance between any two adjacent DTI structures does not have to be the same. For example, the distance between DTI structure 126 and DTI structure 124 may be different from the distance between DTI structure 122 and DTI structure 124. Similarly, the distance between DTI structure 126 and DTI structure 124 may be different from the distance between DTI structure 130 and DTI structure 132.

[0077] The aspect ratio of the DTI structure (e.g., DTI structure 118, 120, 122, 124, or 126) formed in the first sealing ring region 106 may be substantially the same as the aspect ratio of the DTI structure (e.g., DTI structure 128, 130, or 132) in region 110. In one embodiment, the DTI structure (e.g., DTI structure 118, 120, 122, 124, or 126) formed in the first sealing ring region 106 may be vertically aligned with the metal stack (or the first sealing ring structure) 116.

[0078] In one embodiment, the aspect ratio (i.e., the ratio of trench depth to trench width) of the DTI structure (e.g., DTI structures 118, 120, 122, 124, 126, 128, 130, or 132) can range from 10 to 30.

[0079] In some embodiments, dielectric layers 171 and 172 may be formed on a first side 112s1 of the semiconductor substrate 112. Dielectric layers 171 and 172 may be deposited on the first side 112s1 by chemical vapor deposition (CVD), atomic vapor deposition (AVD), or physical vapor deposition (PVD). Dielectric layers 171 and 172 may be silicon oxide or a dielectric material with a dielectric constant greater than 3.9 or a high-k dielectric material, including but not limited to hafnium dioxide (HfO2), aluminum oxide (Al2O3), zirconium dioxide (ZrO2), and titanium dioxide (TiO2).

[0080] In some embodiments, dielectric layers 171 and 172 may be formed of the same dielectric material.

[0081] In some embodiments, dielectric layers 171 and 172 may be formed of different dielectric materials. For example, dielectric layer 172 may be formed of a high-k dielectric material, and dielectric layer 171 may be formed of silicon oxide.

[0082] In some embodiments, the same dielectric material may be arranged or deposited in DTI structures 118, 120, 122, 124, 126, 128, 130 and 132 and along the first side 112s1 of the semiconductor substrate 112.

[0083] In other embodiments, the dielectric material deposited in the DTI structures 118, 120, 122, 124, 126 of the first sealing ring region 106 and the DTI structure of the second sealing ring region 108 may be different from the dielectric material deposited in the DTI structures 128, 130, and 132 of the active region 110. For example, the dielectric material deposited in the DTI structures 118, 120, 122, 124, 126 of the first sealing ring region 106 and the DTI structure of the second sealing ring region 108 may be silicon oxide, while the dielectric material deposited in the DTI structures 128, 130, and 132 may comprise a high-k dielectric material layer and a silicon oxide layer.

[0084] In some other embodiments, although not in Figure 4 The present disclosure is shown in the figure, but may be combined with other methods. Figure 4 The semiconductor device 102 shown and described is similar to other semiconductor devices, except... Figure 4 The DTI structures 118, 120, 122, 124, and 126 of the first sealing ring region 106 shown can be replaced by a sealing ring support structure. The sealing ring support structure can contact the metal stack 116.

[0085] To provide a robust support for the metal stack 116, the sealing ring support structure may need to be aligned relatively precisely with the metal stack 116. Therefore, manufacturing the sealing ring support structure may require relatively high costs to align one or more openings to form a sealing ring support structure with the metal stack 116, thereby ensuring relatively effective contact between the sealing ring support structure and the metal stack 116.

[0086] Furthermore, one or more materials of the sealing ring support structure can be different from those of the sealing ring support structure. Figure 4 The material of the DTI structure shown. Therefore, the sealing ring support structure must be manufactured in accordance with... Figure 4 The DTI structure shown is formed in different processing stages (e.g., before or after). Therefore, the characteristics of the sealing ring support structure can differ. Figure 4 The characteristics of the DTI structure shown.

[0087] Figure 5 A cross-sectional view of a semiconductor device 102' according to some embodiments of the present disclosure is shown.

[0088] Semiconductor device 102' is similar to a combination Figure 4 The semiconductor device 102 is shown and described, therefore, for the sake of brevity, detailed descriptions of the same parts are omitted. Semiconductor device 102' differs from semiconductor device 102 in that it further includes a layer 150 on the surface of a first side 112s1 of the semiconductor substrate 112 and a layer 152 on the layer 150. Semiconductor device 102' may further include one or more light-shielding structures 154 formed in layer 152.

[0089] Layer 150 may include, for example, but not limited to, a buffer layer and / or a planarization layer. Layer 152 may include, for example, but not limited to, a color filter array. The color filter array includes multiple color filters, and the color filters may be arranged according to a Bayer pattern. Layer 152 may further include multiple light-shielding structures 154 (e.g., a metal grid structure) formed therein. The light-shielding structures 154 may be formed between the color filters.

[0090] In some embodiments, the light-shielding structure 154 is used to prevent optical crosstalk between adjacent pixels by absorption, reflection, and refraction. In some embodiments, the light-shielding structure 154 is used to block or reflect light reflected by layer 150. In some embodiments, the light-shielding structure 154 may comprise aluminum, tungsten, or a combination thereof. In some embodiments, the light-shielding structure 154 may comprise a dielectric material with a low refractive index, such as an oxide. In some embodiments, the light-shielding structure 154 may comprise a combination of dielectric and metallic materials.

[0091] In some embodiments, the semiconductor device 102' further includes a microlens array having a plurality of microlenses formed on top of a first side 112s1 of the semiconductor substrate 112. In some embodiments, the microlens array may be formed above a color filter in region 110. In some embodiments, the plurality of microlenses may be positioned or positioned corresponding to pixel region 112a. In some embodiments, the plurality of microlenses focus incident light onto the corresponding pixel region 112a.

[0092] Figure 6 Examples of embodiments according to this disclosure are shown. Figure 5 An enlarged view of the structure within the dashed box B shown.

[0093] Some such as Figure 5 The semiconductor device 102' shown can be along... Figure 1 The dicing groove 104 shown is formed after the semiconductor wafer 100 is divided or diced.

[0094] During a single-cut operation, cracks or damage (which may be caused by, but is not limited to, stress (mechanical stress, thermal stress, etc.)) may occur from, for example, ... Figure 4 The diced region 104 shown propagates to the semiconductor device 102'.

[0095] An external sealing ring (such as a metal stack 116) can protect the area surrounded by the sealing ring (e.g., conductive interconnects, dielectric materials or other structures) from damage or cracking during a single-cut operation.

[0096] DTI structures (e.g., DTI structures 118, 120, 122, 124, or 126) can serve as reinforcing walls to prevent, mitigate, alleviate, or minimize the propagation of cracks or damage during single-cut operations.

[0097] For example, refer to Figure 6 Following a single-cut or dicing operation, cracks or damage 170 may be observed in the semiconductor substrate 112, and these cracks or damage may be relatively fragile. Cracks 170 can propagate through dielectric layers 171 and 172 to the DTI structure 126. The propagation of cracks 170 can be stopped in or at the DTI structure 126. In other words, the DTI structure 126 can stop, mitigate, reduce, or minimize crack propagation. Although in Figure 6 Not shown in the diagram, but it is contemplated that crack 170 may be observed at DTI structure 124. Although in Figure 6 Not shown in the diagram, but it is contemplated that crack 170 may be observed at DTI structure 122. Although in Figure 6 Not shown in the diagram, but it is contemplated that crack 170 may be observed at DTI structure 120. Although in Figure 6It is not shown in the diagram, but it is contemplated that crack 170 may be observed at DTI structure 118.

[0098] The surface roughness of the third side 112s3 can be relatively greater than that of the first side 112s1 or the second side 112s2, because the third side 112s3 can be formed after the dicing or dicing operation of the semiconductor wafer 100.

[0099] Figures 7A-7E The operation of a semiconductor manufacturing apparatus at various stages according to some embodiments of the present disclosure is illustrated.

[0100] refer to Figure 7A A semiconductor wafer 100 may be provided. The semiconductor wafer 100 may include a semiconductor substrate 112.

[0101] A dielectric layer 156 may be formed on the surface of the second side 112s2 of the semiconductor substrate 112. In one embodiment, the dielectric layer 156 may be formed by depositing a dielectric layer on the surface of the second side 112s2 of the semiconductor substrate 112. In another embodiment, the dielectric layer 156 may be formed by depositing a plurality of dielectric layers on the second side 112s2 of the semiconductor substrate 112.

[0102] Conductive interconnects 111 can be formed on the second side 112s2 of the semiconductor substrate 112, and the conductive interconnects can be embedded in the dielectric layer 156. A metal stack 114 can be formed on the second side 112s2 of the semiconductor substrate 112. A metal stack 116 can be formed on the surface of the second side 112s2 of the semiconductor substrate 112. The conductive interconnects 111, the metal stack 114, and the metal stack 116 can be formed using the same process.

[0103] refer to Figure 7B It can be flipped up and down or moved as follows Figure 7A The structure shown has the first side 112s1 facing upwards and the second side 112s2 facing downwards.

[0104] refer to Figure 7C Optionally, a thinning operation, such as chemical polishing or planarization, can be performed on the second side 11s2 of the semiconductor substrate 112. A thinning operation can be performed on the dielectric layer 156 to expose the conductive interconnect 111. A thinning operation can be performed on the dielectric layer 156 to expose the metal stack 114. A thinning operation can be performed on the dielectric layer 156 to expose the metal stack 116.

[0105] refer to Figure 7DMultiple DTI structures (e.g., DTI structures 118, 120, 122, 124, 126, 128, 130, and 132) can be formed extending from the first side 112s1 into the semiconductor substrate 112. For example, the first side 112s1 of the semiconductor substrate 112 can be patterned and etched to form the multiple DTI structures. DTI structures 118, 120, 122, 124, and 126 can be formed from the first side 112s1 of the semiconductor substrate 112 to correspond to the metal stack 116. The DTI structures (e.g., DTI structures 118, 120, 122, 124, 126, 128, 130, and 132) can be formed in a single operation.

[0106] The one or more DTI structures may be formed in region 106. According to some other embodiments of this disclosure, the one or more DTI structures may be formed in region 108. The one or more DTI structures may be formed in region 110. No DTI structures are formed in diced region 104.

[0107] DTI structures (e.g., DTI structures 118, 120, 122, 124, 126, 128, 130 and / or 132) can be formed by: etching a first side 112s1 of a semiconductor substrate 112 through a mask to form a plurality of openings (or trenches); diffusing a dopant in the openings; forming a dielectric layer (e.g., dielectric layers 171 and 172) in the openings (or trenches); filling the openings with a dielectric material; and removing some of the dielectric material.

[0108] The DTI structures 118, 120, 122, 124, 126 disposed in the first sealing ring region and the DTI structures 128, 130, 132 disposed in the active region 110 can be formed using the same process as discussed above (e.g., multiple trenches can be patterned and etched using a mask to form such a pattern). Figure 7D The DTI structures shown are configured such that each of the DTI structures 118, 120, 122, 124, 126, 128, 130 and 132 can have the same trench characteristics as each other (e.g., the same trench depth, the same trench width or the same trench spacing).

[0109] In one embodiment, Figures 7A-7CThe formation of the dielectric layer 156, conductive interconnects 111, and metal stacks 114, 116 shown can occur prior to the formation of the plurality of DTI structures. For example, a process for forming the dielectric layer 156 can be performed first, wherein the conductive interconnects 111 and the metal stacks 114, 116 are arranged within the dielectric layer 156 on a second side 112s2 (e.g., the front or non-photodetector side) of the semiconductor substrate 112. Subsequently, the semiconductor substrate 112 can be flipped to form the plurality of DTI structures formed on a first side 112s1 (e.g., the back or photodetector side).

[0110] In one embodiment, the one or more photodetectors 112a formed in the semiconductor substrate 112 may be formed prior to the formation of the dielectric layer 156, conductive interconnects 111, and metal stacks 114, 116. Details regarding the formation of the one or more photodetectors 112a are omitted to avoid obscuring the invention, as the process for forming the photodetectors is well known and is not the focus of this invention.

[0111] refer to Figure 7E Layers 150 and 152, as well as a light-shielding structure 154, are formed on the first side 112s1 of the semiconductor substrate 112. Then, a dicing or single-cutting operation can be performed to form a structure such as... Figure 5 The semiconductor device 102' shown.

[0112] Segmentation or single-cutting operations can be performed along the dicing groove region 104.

[0113] As used herein, spatial relative terms such as “below,” “under,” “lower,” “above,” “upper,” “lower,” “left,” and “right” may be used for ease of description to describe the relationship between one element or feature as shown in the accompanying drawings and one or more other elements or features. In addition to the orientations depicted in the accompanying drawings, the spatial relative terms are also intended to cover different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptive terms used herein may be interpreted accordingly. It should be understood that when an element is referred to as “connected to” or “coupled to” another element, it may be directly connected to or coupled to the other element, or there may be an intermediate element present.

[0114] As used herein, the terms “approximately,” “substantially,” “essentially,” and “about” are used to describe and explain small variations. When used in conjunction with an event or situation, the terms may refer to instances where the event or situation occurs precisely or instances where the event or situation is close to occurring. As used herein with respect to a given value or range, the term “about” generally means within ±10%, ±5%, ±1%, or ±0.5% of the given value or range. A range may be expressed herein as from one endpoint to another or between two endpoints. All ranges disclosed herein include endpoints unless otherwise specified. The term “substantially coplanar” may mean that the positional difference between two surfaces located along the same plane is within a few micrometers (μm), such as within 10 μm, 5 μm, 1 μm, or 0.5 μm when located along the same plane. When a numerical value or characteristic is referred to as “substantially” the same, the term may refer to a value within ±10%, ±5%, ±1%, or ±0.5% of the average of said values.

[0115] The foregoing has summarized the features of several embodiments and detailed aspects of this disclosure. The embodiments described in this disclosure can readily serve as the basis for designing or modifying other processes and structures to achieve the same or similar purposes and / or realize the same or similar advantages of the embodiments described herein. Such equivalent constructions do not depart from the spirit and scope of this disclosure, and various changes, substitutions, and modifications can be made without departing from the spirit and scope of this disclosure.

Claims

1. A semiconductor device comprising: A semiconductor substrate having a pixel array region and a first sealing ring region, wherein the first sealing ring region is adjacent to an edge of the semiconductor substrate and surrounds the pixel array region, and wherein the first sealing ring region includes a first sealing ring; and A first deep trench isolation structure, the first deep trench isolation structure being filled with a dielectric material formed on the semiconductor substrate, the first deep trench isolation structure being disposed in the first sealing ring region and extending into the semiconductor substrate, wherein the first deep trench isolation structure is a continuous trench structure surrounding the pixel array region, and A second deep trench isolation structure, filled with a dielectric material, is disposed in the first sealing ring region and between the first deep trench isolation structure and the pixel array region, wherein the second deep trench isolation structure is a continuous trench structure surrounding the pixel array region. The semiconductor substrate includes a second sealing ring region between the pixel array region and the first sealing ring region, wherein a second sealing ring is disposed within the second sealing ring region surrounding the pixel array region.

2. The semiconductor device according to claim 1, wherein: The first sealing ring is vertically separated from the first deep groove isolation structure by a certain vertical distance.

3. The semiconductor device of claim 2, wherein the first sealing ring and the first deep trench isolation structure are separated by a dielectric layer.

4. The semiconductor device of claim 1, wherein the second deep trench isolation structure is surrounded by the first deep trench isolation structure and laterally spaced from the first deep trench isolation structure.

5. The semiconductor device of claim 4, wherein the semiconductor substrate has a first side and a second side opposite to the first side, the first deep trench isolation structure and the second deep trench isolation structure have openings formed on the first side of the semiconductor substrate, and the first sealing ring is formed on the second side of the semiconductor substrate.

6. The semiconductor device of claim 4, wherein the pixel array region comprises a pixel array including a plurality of pixels, the plurality of pixels being spaced apart by a certain pixel pitch, and the first deep trench isolation structure and the second deep trench isolation structure being laterally spaced apart by the pixel pitch.

7. The semiconductor device of claim 1, wherein the dielectric material comprises an oxide material.

8. The semiconductor device of claim 1, wherein the dielectric material comprises a material with a dielectric constant greater than 3.

9.

9. The semiconductor device of claim 1, wherein the second deep trench isolation structure is surrounded by the first deep trench isolation structure.

10. The semiconductor device of claim 1, wherein the first deep trench isolation structure has a crack.

11. A semiconductor wafer comprising: At least one semiconductor device, the at least one semiconductor device being formed on the semiconductor wafer, the semiconductor device comprising: A semiconductor substrate having a pixel array region and a first sealing ring region, wherein the first sealing ring region is adjacent to an edge of the semiconductor substrate and surrounds the pixel array region; and A plurality of first deep trench isolation structures are disposed in the first sealing ring region, each of the plurality of first deep trench isolation structures being filled with a dielectric material and extending into the semiconductor substrate, wherein each of the plurality of first deep trench isolation structures is a continuous trench structure configured to surround the pixel array region; and A dicing region, wherein the dicing region is disposed near the edge of the semiconductor device and configured to surround the semiconductor device. The semiconductor substrate includes a second sealing ring region between the pixel array region and the first sealing ring region, wherein a second sealing ring is disposed within the second sealing ring region surrounding the pixel array region.

12. The semiconductor wafer of claim 11, wherein the plurality of first deep trench isolation structures includes an outermost first deep trench isolation structure configured to surround other first deep trench isolation structures, and the outermost first deep trench isolation structure is laterally spaced from the dicing region.

13. The semiconductor wafer of claim 11, further comprising: A first sealing ring is formed in the first sealing ring region and is disposed near the edge of the semiconductor substrate and is vertically separated from the plurality of first deep trench isolation structures by a certain vertical distance.

14. The semiconductor wafer of claim 13, wherein the first sealing ring and the plurality of first deep trench isolation structures are separated by a dielectric layer.

15. The semiconductor wafer of claim 11, wherein the dielectric material comprises an oxide material.

16. A method for manufacturing a semiconductor device, the method comprising: A semiconductor substrate is provided, the semiconductor substrate having a first surface and a second surface opposite to the first surface; A plurality of sealing rings are formed on the first surface of the semiconductor substrate, the plurality of sealing rings surrounding the pixel array; A second sealing ring of the sealing ring is formed between the pixel array and the first sealing ring of the sealing ring, wherein the second sealing ring of the sealing ring surrounds the pixel array, and the first sealing ring is formed to surround the second sealing ring; as well as A plurality of first deep trench isolation structures are formed on the second surface of the semiconductor substrate to correspond to the first sealing ring of the sealing ring. The first deep trench isolation structures extend from the second surface to the first surface. Each of the plurality of first deep trench isolation structures is separated from the first sealing ring of the sealing ring by a certain vertical distance. Each first deep trench isolation structure is a continuous trench surrounding the pixel array.

17. The method of claim 16, further comprising: A plurality of second deep trench isolation structures are formed from the second surface of the semiconductor substrate, wherein each of the plurality of second deep trench isolation structures is arranged to be surrounded by each of the plurality of first deep trench isolation structures; as well as Dielectric material is deposited into each of the plurality of second deep trench isolation structures, wherein the second deep trench isolation structures are continuous trench structures surrounding the pixel array.

18. The method of claim 17, wherein the plurality of first deep trench isolation structures and the second deep trench isolation structures are formed using the same process.

19. The method of claim 18, further comprising separating the plurality of first deep trench isolation structures along a slit region excluding the first deep trench isolation structure and the second deep trench isolation structure.

20. The method of claim 16, further comprising: A dielectric layer is formed between the first deep trench isolation structure and the sealing ring.

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