Low stress asymmetric double-sided module

Abstract

The present invention is entitled "Low Stress Asymmetric Double-Sided Module". An embodiment of a semiconductor package may include: a first substrate having two or more tube cores coupled to a first side; a clamp coupled to each of the two or more tube cores on the first substrate; and a second substrate having two or more tube cores coupled to the first side of the second substrate. The clamp may be coupled to each of the two or more tube cores on the second substrate. The package may include: two or more spacers, the two or more spacers coupled to the first side of the first substrate; and a lead frame, the lead frame between the first substrate and the second substrate; and a molding compound. The second side of each of the first substrate and the second substrate may be exposed through the molding compound. When coupled through the two or more spacers, the perimeter of the first substrate and the perimeter of the second substrate may not completely overlap.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of the filing date of U.S. Provisional Patent Application No. 62 / 882,119 to Chew et al., entitled “LOW STRESSASYMMETRIC DUAL SIDE MODULE,” filed on August 2, 2019, the disclosure of which is hereby incorporated by reference in its entirety. Technical Field

[0003] Aspects of this document generally relate to modular semiconductor packages, such as power semiconductor packages with double-sided cooling capabilities. More particular embodiments relate to leadframes. Background Art

[0004] A power semiconductor package typically includes multiple stacked substrates. A heat sink may be coupled to the external terminals of the device. Some power semiconductor packages may include a heat sink having a fin array structure. Summary of the Invention

[0005] An embodiment of a semiconductor package may include: a first substrate, wherein two or more dies are coupled to a first side of the first substrate. A clamp may be coupled to each of the two or more dies on the first substrate. The package may also include a second substrate, wherein two or more dies are coupled to the first side of the second substrate. A clamp may be coupled to each of the two or more dies on the second substrate. The package may include two or more spacers, wherein the two or more spacers are coupled to the first side of the first substrate. The package may also include: a lead frame, wherein the lead frame is between the first substrate and the second substrate; and a molding compound, wherein the molding compound encapsulates the lead frame. The second side of each of the first substrate and the second substrate may be exposed through the molding compound. When coupled through the two or more spacers, the periphery of the first substrate and the periphery of the second substrate may not completely overlap.

[0006] Embodiments of the semiconductor package may include one, all, or any of the following:

[0007] The two or more dies may include an insulated gate bipolar transistor (IGBT) die and a fast recovery die (FRD).

[0008] The first substrate and the second substrate may include a direct bonded copper substrate (DBC) having alumina (Al2O3) ceramic doped with zirconium dioxide (ZrO2), silicon nitride (Si3N4) ceramic, aluminum nitride (AlN) ceramic, high strength AlN (H-AlN) ceramic, or any combination thereof.

[0009] The semiconductor package may further include a heat spreader coupled to the second side of the first die, the second side of the second die, or any combination thereof.

[0010] The two or more spacers may be made of a conductive material and may electrically couple the first substrate to the second substrate.

[0011] The first substrate and the second substrate may include a direct bond copper substrate (DBC), an insulated metal substrate technology (IMST) substrate, an active metal bonding (AMB) substrate, or any combination thereof.

[0012] Embodiments of a semiconductor package may include: a leadframe; and a first substrate mechanically and electrically coupled to a first side of the leadframe. Two or more dies are coupled to the first side of the first substrate. A clamp may be coupled to each of the two or more dies coupled to the first side of the first substrate. The package may also include a second substrate mechanically and electrically coupled to the second side of the leadframe. Two or more dies are coupled to the first side of the second substrate, and a clamp is coupled to each of the two or more dies. The package may also include two or more spacers coupled to a first side of each of the first substrate and the second substrate. A molding compound may encapsulate the first and second sides of the leadframe. The first side of the first substrate and the first side of the second substrate may be asymmetrically coupled via the two or more spacers.

[0013] Embodiments of the semiconductor package may include one, all, or any of the following:

[0014] The two or more dies may include an insulated gate bipolar transistor (IGBT) die and a fast recovery die (FRD).

[0015] The first substrate and the second substrate may include a direct bonded copper substrate (DBC) having alumina (Al2O3) ceramic doped with zirconium dioxide (ZrO2), silicon nitride (Si3N4) ceramic, aluminum nitride (AlN) ceramic, high strength AlN (H-AlN) ceramic, or any combination thereof.

[0016] The package may further include a heat spreader coupled to one of the second side of the first die, the second side of the second die, or any combination thereof.

[0017] The two or more spacers may be made of a conductive material and electrically couple the first substrate to the second substrate.

[0018] The first substrate and the second substrate may include a direct bond copper substrate (DBC), an insulated metal substrate technology (IMST) substrate, an active metal bonding (AMB) substrate, or any combination thereof.

[0019] Embodiments of a semiconductor package may be manufactured by a method of forming a semiconductor package. Various method embodiments may include providing a first panel having a first substrate and a second panel having a second substrate. The method may also include printing a first conductive bonding material on a first side of the first panel of substrates and a second side of the first panel of substrates in predetermined locations, and coupling two or more dies to each substrate of the first panel of substrates and to each substrate of the second panel of substrates at the predetermined locations. The method may also include dispensing a second conductive material onto the second side of each of the two or more dies, and coupling a fixture to each of the two or more dies. The method may include singulating each of the first panel and the second panel into a plurality of first substrates and a plurality of second substrates, respectively. The method may include dispensing solder onto a plurality of predetermined locations on the first side of each of the plurality of first substrates and each of the plurality of second substrates. The method may also include coupling a first substrate of the plurality of first substrates to a first side of a lead frame, and coupling two or more spacers to the first side of the first substrate. The method may also include coupling a first side of a second substrate of the plurality of second substrates to the two or more spacers and to a second side of the leadframe.

[0020] Implementations of methods of forming a semiconductor package may include one, all, or any of the following:

[0021] The method may further include trimming the lead frame to expose a plurality of leads and forming the leads.

[0022] The method may further include encapsulating the lead frame on the first side and the second side, wherein the second side of each substrate of the plurality of first substrates and the plurality of second substrates is exposed.

[0023] The first panel having the first substrate and the second panel having the second substrate may each include a direct bond copper substrate (DBC), an insulated metal substrate technology (IMST) substrate, an active metal bonding (AMB) substrate, or any combination thereof.

[0024] The method may also include coupling a heat spreader to one of the second side of the first die, the second side of the second die, or any combination thereof.

[0025] The method may further include coupling a heat sink to the second side of a first substrate of the plurality of first substrates, the second side of a second substrate of the plurality of second substrates, or any combination thereof.

[0026] The two or more spacers may be made of a conductive material and may electrically couple the first substrate to the second substrate.

[0027] The first side of the first substrate and the first side of the second substrate may be asymmetrically coupled by the two or more spacers.

[0028] The first conductive material and the second conductive material may include solder paste or sintering paste.

[0029] The foregoing and other aspects, features, and advantages will be apparent to those skilled in the art from the description and drawings, and from the claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Embodiments will be described below with reference to the accompanying drawings, in which like reference numerals represent like elements, and:

[0031] Figure 1 is a side view of an embodiment of a semiconductor package;

[0032] Figure 2 is a top perspective view of an embodiment of a semiconductor package;

[0033] Figure 3 is a top perspective view of an embodiment of the lead frame before coupling a second substrate to the lead frame;

[0034] Figure 4 is a top perspective view of an embodiment of a first substrate;

[0035] Figure 5 is a top perspective view of an embodiment of a second substrate;

[0036] Figure 6 is a top perspective view of an embodiment of a panel of a substrate;

[0037] Figure 7 is a top perspective view of an embodiment of a panel having a substrate of conductive material coupled in predetermined locations;

[0038] Figure 8is a top perspective view of an embodiment of a panel having a substrate with two dies coupled to predetermined locations;

[0039] Figure 9 is a top perspective view of an embodiment of a conductive material coupled to each of two dies;

[0040] Figure 10 is a top perspective view of an embodiment of two clamps coupled to each of two dies;

[0041] Figure 11 is a top perspective view of an embodiment of the clamp;

[0042] Figure 12 is a top perspective view of an embodiment of wire bonds coupled to two dies;

[0043] Figure 13 is a top perspective view of an embodiment of a panel of substrates cut into three substrates;

[0044] Figure 14 is a top perspective view of an embodiment of a first substrate after dicing;

[0045] Figure 15 is a top perspective view of an embodiment of a second substrate after dicing;

[0046] Figure 16 is a top perspective view of an embodiment of a first substrate coupled to a lead frame and a second substrate before being coupled to the lead frame;

[0047] Figure 17 is a close-up view of an embodiment of a spacer;

[0048] Figure 18 is a top perspective view of an embodiment of a second side of the leadframe after a second substrate is coupled to the leadframe;

[0049] Figure 19 is a top perspective view of an embodiment of a first side of a lead frame;

[0050] Figure 20 is a side view of an embodiment of a semiconductor package;

[0051] Figure 21 is a top view of an embodiment of a semiconductor package after encapsulation; and

[0052] Figure 22 is a perspective view of an embodiment of a semiconductor package after lead trimming and forming. DETAILED DESCRIPTION

[0053] The present disclosure, its aspects, and embodiments are not limited to the specific components, assembly processes, or method elements disclosed herein. Many additional components, assembly processes, and / or method elements known in the art that are consistent with the intended semiconductor package will readily be used with the specific embodiments of the present disclosure. Thus, for example, although the present disclosure discloses specific embodiments, such embodiments and implementation components may include any shape, size, style, type, model, version, measurement, concentration, material, quantity, method element, step, and / or the like known in the art for such semiconductor packages and implementation components and methods that are consistent with the intended operation and method.

[0054] See also Figure 1 , shows a side view of an embodiment of a semiconductor package 2. As shown, the semiconductor package includes a first substrate 4 coupled to a first side 6 of a leadframe 8. The first substrate 4 couples two dies 10 and 12, which are coupled to the first substrate 4 in two predetermined locations. In various embodiments, more than two dies may be coupled to the first substrate. As non-limiting examples, the dies may include insulated gate bipolar transistors (IGBTs), fast recovery dies (FRDs), any other semiconductor dies, or any combination thereof. The semiconductor package also includes a second substrate 14 coupled to a second side 16 of the leadframe 8. The leadframe 8 is coupled between the first substrate 4 and the second substrate 14. The second substrate couples two dies 18 and 20, which are coupled to two predetermined locations on the first side of the second substrate. In various embodiments, as non-limiting examples, the two dies coupled to the second substrate may include insulated gate bipolar transistors (IGBTs), fast recovery dies (FRDs), any other semiconductor dies, or any combination thereof.

[0055] Figure 1Each of the first and second substrates shown in the figure is a directly bonded copper substrate (DBC) comprising a ceramic substrate, wherein a copper plate is coupled to a first side and a second side of the ceramic substrate. In various embodiments, the DBC may include an aluminum oxide (Al2O3) ceramic (HPS) doped with zirconium dioxide (ZrO2). In other embodiments, the ceramic may be made of other materials, such as silicon nitride (Si3N4) ceramic, aluminum nitride (AlN) ceramic, high-strength AlN (H-AlN) ceramic, or any combination thereof. In some embodiments, the thickness of each layer of the Cu / HPS / Cu DBC substrate may include 0.30 mm of Cu, 0.32 mm of ceramic / HPS, and 0.30 mm of Cu. In other embodiments, the thickness may be varied based on electrical requirements, thermal requirements, package height control, and other parameters of the device. In other embodiments, the first substrate, the second substrate, or both the first substrate and the second substrate may be made of another substrate material, such as, as non-limiting examples, active metal brazing (AMB) substrates, insulated metal substrate technology (IMST), laminate substrates, substrates having a metal layer on only one surface of the substrate, any combination thereof, and any other substrate type.

[0056] See also Figure 2 , shows a top view of an embodiment of a semiconductor package 22. In this view, the second side 24 of the leadframe is shown as having a second substrate 28 coupled thereto. The second substrate 28 can be coupled to the leadframe 24 via leads 30 formed in an upward position. As shown, a first substrate 32 is coupled to the first side 26 of the leadframe opposite the second substrate. A portion of the first side of the first substrate 32 faces a portion, but not all, of the first side of the second substrate. In addition, as shown, when coupled to the leadframe and spacers, the perimeter of the first substrate and the perimeter of the second substrate do not completely overlap. The first substrate and the second substrate are therefore coupled to the leadframe asymmetrically.

[0057] See also Figure 3, shows an embodiment of a lead frame 34. The lead frame can be formed by imprinting the leads so that the contact with the first substrate and the second substrate is offset. The first substrate 40 is coupled to the first side of the lead frame 34 via leads 36 and wire bonds 38. In various embodiments, the lead frame can be coupled to the first substrate via other conductive materials (such as solder or die attach materials). The first substrate includes two clamps, which are coupled to the first side of the first substrate via conductive bonding materials. In various embodiments, as non-limiting examples, the conductive bonding material can include lead-free (Pb) solder paste, sintered silver paste, other conductive bonding materials, or any combination thereof. Two spacers 42 and 44 can be formed of one or more conductive materials and can provide electrical contacts between the first substrate and the second substrate. In various embodiments, the spacers can be formed of copper or a copper alloy.

[0058] like Figure 3 As shown in , the first side of the second substrate 46 is coupled to the device through leads on the lead frame and through two spacers 42 and 44, as shown by dotted lines 48 and 50. The second substrate couples two semiconductor dies 52 and 54, which are coupled to the first side of the substrate by conductive material. In various embodiments, the two dies may include IGBTs, FRDs, or any other dies described herein. Clamps 56 and 58 are coupled to the first side of each of the two dies. In various embodiments, the clamps may have a thickness of approximately 0.3 mm. In other embodiments, the thickness of the clamps may vary based on electrical requirements, thermal requirements, or other design parameters of the device. In various embodiments, the clamps may be formed of copper or a copper alloy.

[0059] See also Figure 4 , shows an embodiment of a first substrate 60. In various embodiments, the first substrate may include a direct bonded copper substrate. In various embodiments, the thickness of each layer of the substrate may be approximately 0.30 mm Cu, approximately 0.32 mm ceramic, and approximately 0.30 mm Cu. In some embodiments, the thickness of each layer may vary based on the parameters / structure of the device. The first substrate 60 includes a first die 62, which is coupled to a first side 65 of the substrate. A clamp 64 is coupled to the first side of the first die 62. In various embodiments, the first die may be an FRD die. As shown, the first substrate 60 also includes a second die 66, which is coupled to the first side 65 of the first substrate 60. In some embodiments, the second die may include an IGBT die. The clamp 68 is coupled to the first side of the second die 66 via a conductive material. In various embodiments, the clamp may be formed of copper, a copper alloy, or another conductive material.

[0060] See also Figure 5, shows an embodiment of a second substrate 70. In various embodiments, the second substrate may include a direct bond copper (DBC) substrate. In some embodiments, the DBC may include an aluminum oxide (Al2O3) ceramic doped with zirconium dioxide (ZrO2) or any other combination described herein. The second substrate 70 includes a first die 72 coupled to a first side 74 of the substrate. In various embodiments, the first die may be an FRD die. As shown, a clamp 76 is coupled to the first side of the first die 72. In various embodiments, the clamp may be formed from copper, a copper alloy, or any other material described herein for a clamp. In various embodiments, the clamp may have a thickness of approximately 0.3 mm. In other embodiments, the thickness of the clamp may be greater or lesser depending on the electrical and thermal requirements of the device. As shown, the second substrate 70 also includes a second die 78 coupled to the first side 74 of the second substrate 70. In some embodiments, the second die may include an IGBT die. A clamp 80 is coupled to the first side of the second die 78 via a conductive material. In various embodiments, the conductive material that couples the clamp to the die may be a high temperature solder or a high temperature sintering paste. The solder and sintering paste may include any of the die bonding or electrical coupling material types described herein. Figure 4 The first substrate 60 and Figure 5 When comparing the first substrate 70 with the second substrate 70, it should be noted that the clamp has a different orientation on each substrate. This orientation difference can help offset the substrate when it is coupled to the lead frame.

[0061] The semiconductor package described herein can be manufactured by various embodiments of a method of forming a semiconductor package. The method can include providing a panel having a first substrate. The method can include a module subassembly (MSA) in panel form, the panel form including two sets of panels: a first panel having the first substrate and a second panel having the second substrate. See Figure 6 , a panel 82 having a plurality of first substrates 84 is shown. The method may also include providing a panel having a plurality of second substrates. For ease of illustration, only panels having a first substrate are shown, although the method of preparing panels having a second substrate is similar. Again, see Figure 4 and Figure 5, the first substrate 60 and the second substrate 70 do have slightly different orientations and positions when the fixture is coupled and the conductive material is coupled to the first side of each substrate. Each of the first substrate and the second substrate may include a DBC substrate. In various embodiments, the initial thickness of each of the layers of the substrate may include approximately 0.30 mm of Cu, approximately 0.32 mm of ceramic, and approximately 0.30 mm of Cu. In some embodiments, the ceramic layer may include Al2O3 ceramic doped with ZrO2. In other embodiments, the ceramic layer may include silicon nitride (Si3N4) ceramic, aluminum nitride (AlN) ceramic, high strength AlN (H-AlN) ceramic, or any combination thereof. In yet other embodiments, the first substrate and the second substrate may include insulated metal substrate technology (IMST), active metal brazing (AMB) substrates, or any other substrate mentioned herein.

[0062] The method may also include printing a first conductive bonding material on a first side of each of the first panel of the substrate and the second panel of the substrate in a predetermined location. In various embodiments, the conductive material may include a high temperature solder or a high temperature sintering paste. In some embodiments, the solder may be a lead-free solder, such as SnAg comprising 96.5% tin (Sn) and 3.5% silver (Ag). 3.5 Or SAC305 including 96.5% Sn, 3% Ag and 0.5% copper (Cu). In other embodiments, the conductive bonding material may include sintered silver paste. Figure 7 , shows a first panel of substrate 82 after coupling conductive material 85 in predetermined locations 86 to each of a plurality of first substrates 88 .

[0063] The method may also include coupling two or more dies to each of the first panel of the substrate and the second panel of the substrate. The two or more dies may be coupled to the substrate in predetermined locations of the conductive bonding material. In various embodiments, the dies may include IGBTs, FRDs, or any other semiconductor dies described herein. Figure 8 , shows a panel 82 of a substrate 84 after coupling two dies 90 and 92 to each of two predetermined locations 86 and 88. The method may also include dispensing a second conductive material onto a second side or exposed surface of each of the two or more dies. In various embodiments, the second conductive material may be the same material printed onto the first side of the substrate or any other conductive material disclosed in this document. See Figure 9 , shows panel 82 of substrate 84 after dispensing a second conductive material 94 onto the second side of each of the two dies 90 and 92 .

[0064] The method may further include coupling a clamp to each of the two or more dies via a second conductive material. In some embodiments, the clamp may be coupled to the dies by pressure sintering. Figure 10 , shows panel 82 of substrate 84 after clamps 96 and 98 have been coupled to dies 90 and 92 via conductive material. Various embodiments of this method can allow for uniform pressure to be applied to the substrate because the clamps are installed prior to assembly in the semiconductor package. As shown, the clamps are positioned perpendicular to the leads of the leadframe. See Figure 11 , showing an embodiment of a clamp. In various embodiments, the clamp can have a thickness of approximately 0.3 mm, but in other embodiments, the thickness of the clamp can be greater or lesser based on the electrical or thermal requirements of the device. In various embodiments of similar sized dies, the clamp can be flexible, which can reduce stress on the die. In some embodiments, the clamp can be formed from copper or a copper alloy.

[0065] The method may further include reflowing the solder or sintering paste and flux cleaning the substrate surface. The method may then include electrically coupling two or more dies to each of the plurality of first substrates and the plurality of second substrates. Figure 12 As shown in FIG, die 90 may be coupled to substrate 88 via wire bonds 102. In various embodiments, the wire bonds may be formed of aluminum or other conductive materials. Although the use of wire bonds is Figure 12 Although shown in FIG, in other embodiments, other electrical connectors may be used to connect the clamp, such as, by way of non-limiting example, bumps, stud bumps, posts, or any other electrical connector type.

[0066] The method may further include cutting the first panel having a substrate and the second panel having a substrate into a plurality of first and second substrates. In various embodiments, the panel of substrates may have a score line between each of the plurality of substrates (or may be scored first using a stylus to form such a line), and the substrates may be cut by breaking on the score line. In other embodiments, the plurality of substrates may be cut by laser cutting. In still other embodiments, the panel may be cut into the plurality of substrates by sawing. See Figure 13 , shows panel 82 after some of a plurality of substrates 84 have been cut from the panel. In various embodiments, each of the substrates can be probed before cutting or after cutting and before coupling the substrate to a lead frame.

[0067] The method may further include dispensing solder onto a plurality of predetermined locations on the first side of each of the first substrate and the second substrate. In various embodiments, the solder may be a low temperature solder. Figure 14 and Figure 15, shows each of the first substrate 104 and the second substrate 106 after solder is dispensed in the predetermined location 108. The method may also include coupling the first substrate to the first side of the lead frame. The first side of the first substrate may be coupled to the lead frame at the predetermined location by solder. Leads coupled to the first substrate may be formed toward the first side of the lead frame. See Figure 16 , shows the lead frame after coupling the first substrate 104 to the first side of the lead frame 110 .

[0068] The method may further include coupling two or more spacers to the first side of the first substrate at predetermined locations not coupled to the lead frame. The clamp may be formed of a conductive material. The spacers may electrically couple the first substrate to the second substrate. Because the first substrate and the second substrate are coupled only through the spacers, less stress may be present on components of the semiconductor package during assembly, reflow, and other manufacturing processing steps. Still referring to Figure 16 , two spacers 112 are shown coupled to the first side of the first substrate 104 by solder. Figure 17 An enlarged view of the spacer 112 is shown. In various embodiments, the spacer can be formed of a conductive material such as copper. The method further includes coupling the first side of the second substrate 106 to the two spacers and to the second side of the lead frame, such as Figure 16 As shown by the dotted line 114 in FIG. A lead coupled to the second substrate is formed toward the second side surface of the lead frame.

[0069] See also Figure 18 , shows an embodiment of a semiconductor package 116 after the first side of the second substrate 106 is coupled to two spacers and to the second side of the lead frame 110. As shown, the first side of the first substrate and the first side of the second substrate are asymmetrically coupled via the two spacers. This structure can exert less stress on the internal components of the package. Figure 19 , showing a first side of the lead frame 110. In this view, the second side 118 of the first substrate 104 and the first side of the second substrate 106 are visible. The second side of each of the first and second substrates is exposed to act as a heat sink for the semiconductor package.

[0070] See also Figure 20, shows a side view of a semiconductor package 120. In this view, a leadframe 122 is shown having a first substrate 124 coupled to a first side of the leadframe 122 and a second substrate 126 coupled to a second side of the leadframe 122. The first substrate 124 and the second substrate 126 are mechanically and electrically coupled to the leadframe 122 via leads 128 formed toward the respective substrates. The first substrate 124 is coupled to two dies 130 and 132, which are coupled to the first side of the first substrate 124. Clips 134 and 136 are coupled to each of the two dies 130 and 132. The structure of the semiconductor package allows the clips to be vertically coupled to the leads of the leadframe.

[0071] The semiconductor package also includes spacers 138 and 140 that mechanically and electrically couple the first substrate 124 to the second substrate 126. The first side of the first substrate and the first side of the second substrate are asymmetrically coupled via two or more spacers. The second substrate 126 couples two dies 142 and 144, which are coupled to the first side of the second substrate 126. Two clamps 146 and 148 are coupled to the two dies 142 and 144. Asymmetrically coupling the first substrate to the second substrate via the spacers reduces stress on the clamps and dies of the semiconductor package. The use of a lead frame and the use of spacers allows for a structure in which the substrates and dies are not coupled in a stacked configuration.

[0072] The method of manufacturing a semiconductor package may further include encapsulating the lead frame on the first side and the second side. In various embodiments, the package may be encapsulated by transfer molding using an epoxy molding compound or by a liquid process using a liquid sealant. In various embodiments, the molding compound may include epoxy, resin, or other encapsulating materials. The second side of each of the first and second substrates 106 is exposed after encapsulation 150, as shown in FIG. Figure 21 The structure of the semiconductor package 120 may also provide better molding flow during the molding process. The method may also include trimming and forming the leads 152 of the semiconductor package 120 so that they are oriented in a desired direction or directions, such as Figure 22 In various embodiments, the method may further include coupling a heat spreader to the second side of the first substrate, the second side of the second substrate, the second side of the first die, the second side of the second die, or any combination thereof.

[0073] An embodiment of a method of forming a semiconductor package may include wherein the first panel of the first substrate and the second panel of the second substrate each include one of a direct bonded copper substrate (DBC), an insulated metal substrate technology (IMST) substrate, an active metal bonding (AMB) substrate, or any combination thereof.

[0074] Embodiments of a method of forming a semiconductor package may include wherein the two or more spacers may include a conductive material and electrically couple the first substrate to the second substrate.

[0075] Embodiments of a method of forming a semiconductor package may include where the first conductive material and the second conductive material include one of a solder paste or a sinter paste.

[0076] Embodiments of the semiconductor package may include where the two or more dies include an insulated gate bipolar transistor (IGBT) and a fast recovery die (FRD).

[0077] Embodiments of the semiconductor package may include wherein the first substrate and the second substrate include a direct bonded copper substrate having one of an aluminum oxide (Al2O3) ceramic doped with zirconium dioxide (ZrO2), a silicon nitride (Si3N4) ceramic, an aluminum nitride (AlN) ceramic, a high strength AlN (H-AlN) ceramic, or any combination thereof.

[0078] Embodiments of a semiconductor package may include wherein the two or more spacers may include a conductive material and electrically couple the first substrate to the second substrate.

[0079] Where reference is made in the above description to specific embodiments of semiconductor packages and implementation components, sub-components, methods and sub-methods, it should be apparent that various modifications may be made without departing from the essence thereof, and that these embodiments, implementation components, sub-components, methods and sub-methods may be applied to other semiconductor packages.

Claims

1. A semiconductor package, comprising: a first substrate, wherein two or more dies are coupled to a first side of the first substrate, wherein a first clamp is coupled to each of the two or more dies coupled to the first side of the first substrate; a second substrate, wherein two or more dies are coupled to a first side of the second substrate, wherein a second clamp is coupled to each of the two or more dies coupled to the first side of the second substrate; two or more spacers coupled to the first side of the first substrate; and a lead frame, the lead frame included between the first substrate and the second substrate; a molding compound encapsulating the lead frame, wherein a second side of each of the first substrate and the second substrate being exposed through the molding compound; and Wherein, when the first substrate and the second substrate are coupled by the two or more spacers, the perimeter of the first substrate only partially overlaps with the perimeter of the second substrate, and the perimeter of the second substrate only partially overlaps with the perimeter of the first substrate. 2 . The semiconductor package of claim 1 , further comprising a heat sink coupled to one of the second side of the first substrate, the second side of the second substrate, or any combination thereof. 3 . The semiconductor package of claim 1 , wherein the two or more spacers are composed of a conductive material and electrically couple the first substrate to the second substrate.

4. A semiconductor package comprising: lead frame; a first substrate mechanically and electrically coupled to a first side of the leadframe, wherein two or more die are coupled to the first side of the first substrate, wherein a first clamp is coupled to each of the two or more die on the first side of the first substrate; a second substrate mechanically and electrically coupled to a second side of the leadframe, wherein two or more die are coupled to a first side of the second substrate, wherein a second clamp is coupled to each of the two or more die on the first side of the second substrate; two or more spacers coupled to the first side of each of the first substrate and the second substrate; and a molding compound, the molding compound encapsulating the first side surface and the second side surface of the lead frame; wherein the first substrate and the second substrate are asymmetrically coupled via the two or more spacers, and The perimeter of the first side of the first substrate extends beyond the perimeter of the first side of the second substrate, and the perimeter of the first side of the second substrate extends beyond the perimeter of the first side of the first substrate. 5 . The semiconductor package of claim 4 , further comprising a heat sink coupled to one of the second side of the first substrate, the second side of the second substrate, or any combination thereof.

6. A method of forming a semiconductor package, the method comprising: providing a first panel having a first substrate and a second panel having a second substrate; printing a first conductive bonding material on a first side of the first panel of a substrate and a second side of the first panel of a first substrate in predetermined locations; coupling two or more dies to each substrate of the first panel of a first substrate and to each substrate of the second panel of a second substrate at the predetermined locations; dispensing a second conductive material onto a second side of each of the two or more dies; coupling a clamp to each of the two or more dies; electrically coupling the two or more dies to each substrate of the first panel of a first substrate and to each substrate of the second panel of a second substrate; cutting each of the first panel and the second panel into a plurality of first substrates and a plurality of second substrates, respectively; dispensing solder onto a plurality of predetermined locations on the first side of each of the plurality of first substrates and each of the plurality of second substrates; coupling a first substrate of the plurality of first substrates to a first side of the lead frame; coupling two or more spacers to the first side of the first substrate; as well as A first side of a second substrate of the plurality of second substrates is coupled to the two or more spacers and to a second side of the lead frame.

7. The method according to claim 6, further comprising: The lead frame is trimmed to expose a plurality of leads and the leads are formed.

8. The method according to claim 6, further comprising: The lead frame is encapsulated on the first side and the second side, wherein the second side of each of the plurality of first substrates and the plurality of second substrates is exposed.

9. The method according to claim 6, further comprising: A heat sink is coupled to one of the second side of the first substrate of the plurality of first substrates, the second side of the second substrate of the plurality of second substrates, or any combination thereof. 10 . The method of claim 6 , wherein the first side of the first substrate and the first side of the second substrate are asymmetrically coupled by the two or more spacers.

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