Vertical memory device

Abstract

Disclosed are a vertical memory device and a method of manufacturing the same. The vertical memory device includes a substrate having a cell block region, a block separation region, and a boundary region; a plurality of stack structures arranged in the cell block region and the boundary region such that insulating intermediate layer patterns and electrode patterns are alternately stacked on the substrate. The stack structures are spaced apart in a third direction by the block separation region. A plurality of channel structures extend through the stack structures to the substrate in a first direction in the cell block region and are connected to the substrate. A plurality of dummy channel structures extend through an upper portion of each of the stack structures in the boundary region and are connected to a dummy bottom electrode pattern spaced apart from the substrate. Accordingly, bridging defects near the substrate are substantially prevented.

Description

TECHNICAL FIELD

[0001] Example embodiments relate to a vertical memory device and a method of manufacturing a vertical memory device, and more particularly, to a vertical NAND flash memory device and a method of manufacturing a vertical NAND flash memory device. BACKGROUND

[0002] A vertical NAND (VNAND) flash memory device includes a plurality of memory cells stacked vertically on a substrate, and thus the storage capacity of the VNAND memory device can be increased. The memory cells can be stacked around a single vertical channel, and a plurality of vertical channels can be provided in the VNAND memory device.

[0003] Since the storage capacity of the VNAND memory device depends on the number of vertical channels, various methods for increasing the number of vertical channels in a cell block in the VNAND memory device have been studied.

[0004] Generally, a stack layer structure can be formed on a substrate and a mask pattern can be formed on the stack layer structure in such a way that a block separation region of the stack layer structure can be covered by the mask pattern and a cell block region of the stack layer structure can be exposed. Then, a plurality of channel holes for vertical channels can be formed in the cell block region through the stack layer structure.

[0005] Recently, as the number of stacks of the stack layer structure increases and the number of vertical memory cells of the VNAND memory device increases in the vertical direction, the aspect ratio of the channel holes significantly increases. The high aspect ratio of the channel holes can cause insufficient etching around each bottom of the channel holes, and thus a not-open defect can occur at a bottom position of the channel holes in the block separation region. Thus, the substrate of the block separation region can not be sufficiently exposed in the block separation region. SUMMARY

[0006] Example embodiments of the inventive concept provide a CDS-type vertical memory device in which dummy channel structures are arranged at an upper portion of a stack structure, and the vertical profile of sidewalls of a block separation trench is sufficiently uniform despite a high aspect ratio.

[0007] Other example embodiments of the inventive concept provide a method of manufacturing the above-described vertical memory device.

[0008] According to some embodiments of the present inventive concepts, a vertical memory device is provided that includes a substrate including a cell block region, a block separation region, and a boundary region between the cell block region and the block separation region; and a plurality of stack structures arranged in the cell block region and the boundary region. The plurality of stack structures are stacked in a first direction substantially perpendicular to the substrate such that insulating intermediate layer patterns are alternately stacked with electrode patterns on the substrate. The stack structures are spaced apart from each other in a third direction substantially perpendicular to the first direction by the block separation region. The vertical memory device includes a plurality of channel structures extending through respective ones of the stack structures to the substrate in the cell block region such that the plurality of channel structures can traverse the electrode patterns and the insulating intermediate layer patterns in the first direction. The vertical memory device includes a plurality of dummy channel structures extending through upper portions of respective ones of the stack structures in the boundary region such that respective ones of the dummy channel structures can traverse the electrode patterns and the insulating intermediate layer patterns in the first direction and can be connected to a dummy bottom electrode pattern, the dummy bottom electrode pattern including one of the electrode patterns spaced apart from the substrate.

[0009] According to some embodiments of the present inventive concepts, a vertical memory device is provided that includes a substrate including a cell block region, a block separation region, and a boundary region between the cell block region and the block separation region; and a plurality of stack structures arranged in the cell block region and the boundary region. The plurality of stack structures are stacked in a first direction substantially perpendicular to the substrate such that insulating intermediate layer patterns are alternately stacked with electrode patterns on the substrate. The stack structures are spaced apart from each other in a third direction substantially perpendicular to the first direction by the block separation region. The vertical memory device includes a plurality of channel structures extending through respective ones of the stack structures to the substrate in the cell block region such that the plurality of channel structures can traverse the electrode patterns and the insulating intermediate layer patterns in the first direction. The vertical memory device includes a plurality of block separation structures on the substrate in the block separation region between adjacent ones of the plurality of stack structures to separate the stack structures in a third direction substantially perpendicular to the first direction in a storage block; and a plurality of dummy channel structures extending through upper portions of respective ones of the stack structures in the boundary region such that each of the plurality of dummy channel structures traverses the electrode patterns and the insulating intermediate layer patterns and is connected to a dummy bottom electrode pattern, the dummy bottom electrode pattern being one of the electrode patterns spaced apart from the substrate.

[0010] According to some embodiments of the present inventive concepts, a vertical memory device is provided that includes a substrate and a plurality of stack structures stacked in a first direction substantially perpendicular to the substrate such that insulating intermediate layer patterns and electrode patterns are alternately stacked on the substrate. The stack structures are spaced apart from each other by block separation regions. The vertical memory device includes a plurality of channel structures extending through respective ones of the stack structures such that the plurality of channel structures penetrate the electrode patterns and the insulating intermediate layer patterns, and a plurality of dummy channel structures extending through upper portions of respective ones of the stack structures and through some of the electrode patterns and some of the insulating intermediate layer patterns. The electrode patterns among the electrode patterns in the upper portions of the stack structures include extension portions adjacent to the dummy channel structures among the plurality of dummy channel structures. The extension portions have a first thickness that is greater than a second thickness of remaining portions of the electrode patterns.

[0011] According to some embodiments of the present inventive concepts, a method of manufacturing the above-described vertical memory device is provided. A molded stack structure can be formed on a substrate by alternately stacking insulating intermediate layers and sacrificial layers in a first direction. The substrate includes a cell block region, a boundary region, and block separation regions, and the molded stack structure can be formed on the entire substrate regardless of the cell block region, the boundary region, and the block separation regions. Then, dummy channel stops can be formed at upper portions of the molded stack structure in such a manner that the dummy channel stops can extend from the block separation regions to the cell block region around the boundary region and be in horizontal contact with the sacrificial layers. The dummy channel stops can have a smaller etch resistance than the insulating intermediate layers. Then, a plurality of channel holes and a plurality of dummy holes can be simultaneously formed in the cell block region and in the boundary region and the block separation regions, respectively, in such a manner that the channel holes can penetrate the molded stack structure to the substrate and the dummy channels can penetrate the upper portions of the molded stack structure to bottoms of the dummy channel stops. Then, channel structures and preliminary dummy channel structures can be simultaneously formed in the channel holes and the dummy holes, respectively. The channel structures can be connected to the substrate and can selectively trap charges in response to a signal, and the preliminary dummy channel structures can not trap charges. Then, the preliminary dummy channel structures, the dummy channel stops, the insulating intermediate layers, and the sacrificial layers can be removed from the block separation regions of the substrate, thereby forming the molded stack structure into separate stack patterns, the dummy channel structures and the residual stops formed at the upper portions of each of the stack patterns in the boundary region, and the block separation trenches formed in a third direction separating the stack patterns and exposing the substrate in the block separation regions.

[0012] According to some embodiments of the present inventive concepts, there can be no residual channels left on the substrate at lower portions of the block separation trenches, and thus, although the dummy holes can be continuously formed with the channel holes in the same hole etching process, bridging defects can be sufficiently prevented.

[0013] By the sequential etching steps of the first trench etching process for the upper portion of the mold stack structure and the second trench etching process for the lower portion of the mold stack structure, the block separation trench can be formed. Accordingly, the block separation trench can be formed in a sufficiently small aspect ratio, and the sidewall of the block separation trench can be sufficiently uniform in the first direction, so that a uniform vertical profile of the block separation trench is obtained in the first direction despite a high number of stack of the electrode pattern.

[0014] Further, the dummy trench structure can be formed only at the upper portion of the stack structure at a dummy gap distance from the substrate, so that there can be no residual trench left on the substrate at the lower portion of the block separation trench. Accordingly, due to the uniform vertical profile of the block separation trench and the dummy trench structure spaced apart from the substrate, a bridging defect between adjacent gate lines at the lower portion of the block separation trench can be sufficiently prevented. BRIEF DESCRIPTION OF DRAWINGS

[0015] These and other features of the present inventive concepts will become more apparent from the following detailed description, taken in conjunction with the accompanying drawings, in which:

[0016] Figure 1 is a plan view illustrating a vertical memory device according to an example embodiment of the present inventive concepts;

[0017] Figure 2A is Figure 1 is a cross-sectional view taken along line I-I' of the vertical memory device in

[0018] Figure 2B is Figure 1 is a cross-sectional view taken along line II-II' of the vertical memory device in

[0019] Figure 3A is a perspective view illustrating a trench structure of the vertical memory device shown in Figure 2A and Figure 2B

[0020] Figure 3B is a perspective view illustrating a dummy trench structure of the vertical memory device shown in Figure 2A and Figure 2B

[0021] Figures 4A-19B is a cross-sectional view illustrating process steps of a method for manufacturing the vertical memory device shown in Figures 1-3B according to an example embodiment of the present inventive concepts. DETAILED DESCRIPTION

[0022] ​​A continuous dummy hole (CDH) process is introduced to avoid unopened defects in the block separation region. In the CDH process, a single hole process for forming a trench hole is continuously performed along the entire surface of the stacked layer structure in the cell block region and the block separation region. Accordingly, a plurality of holes are continuously arranged on the entire stacked layer structure in a single arrangement rule. The holes in the cell block region are provided as trench holes, and the holes in the block separation region are provided as dummy holes. Accordingly, the trench holes and the dummy holes are continuously arranged on the stacked layer structure in a single arrangement rule.

[0023] When the hole process is completed, a block separation process is performed on the stacked layer structure of the block separation region to remove a portion of the stacked layer structure from the substrate, thereby forming a block separation trench that exposes the substrate. Accordingly, the stacked layer structure is divided into a plurality of cell blocks and adjacent cell blocks are spaced apart by the block separation trench, and a plurality of trench holes are arranged in each cell block. Accordingly, a group of vertical channel structures is arranged on the substrate in units of cell blocks, and a group of dummy channel structures is arranged on the substrate in units of separated blocks.

[0024] The dummy channel structures are removed from the substrate together with the stacked layer structure in the block separation process. However, the dummy channel structures are not sufficiently removed from the substrate in the block separation trench, and dummy residues of the dummy channel structures remain at a boundary region of a lower portion of the block separation trench. Since the dummy residues include the same conductive structure as the channel structures, some of the adjacent vertical channel structures can be electrically connected to each other through the dummy residues at the boundary region of the lower portion of the block separation trench. That is, the adjacent vertical cells are not separated (i.e., cell separation defects) in the lower portion of the block separation trench.

[0025] Reference will now be made to example embodiments, examples of which are illustrated in the accompanying drawings, wherein like reference numerals can refer to like parts throughout.

[0026] Figure 1 is a plan view showing a vertical memory device according to an example embodiment of the inventive concept. Figure 2A is Figure 1 is a cross-sectional view taken along line I-I' of the vertical memory device in Figure 2B is Figure 1 is a cross-sectional view taken along line II-II' of the vertical memory device in. In Figure 1 , a plurality of channel structures and a plurality of dummy channel structures are shown.

[0027] Hereinafter, a direction perpendicular to an upper surface of the substrate is defined as a first direction x, and a pair of directions parallel to the upper surface of the substrate and perpendicular to each other are defined as a second direction y and a third direction z, respectively. The first direction x, the second direction y, and the third direction z can be perpendicular to each other.

[0028] Referring to Figure 1 ,Figure 2A and Figure 2B According to some embodiments of the inventive concept, a vertical memory device 500 can include a substrate 100 divided into a cell block region C, a block separation region BS, and a boundary region BA between the cell block region C and the block separation region BS; a plurality of stack structures SS arranged in the cell block region C and the boundary region BA and stacked in a first direction x such that the insulating intermediate layer patterns 112 can be alternately stacked with the electrode patterns 300 on the substrate 100 and the stack structures SS are spaced apart in a third direction z by the block separation region BS; a plurality of channel structures 230 extending through each of the stack structures SS to the substrate 100 in the cell block region C such that the channel structures 230 can penetrate the electrode patterns 300 and the insulating intermediate layer patterns 112 in the first direction x and can be connected to the substrate 100; and a plurality of dummy channel structures 250 extending through an upper portion UA of each of the stack structures SS in the boundary region BA such that the dummy channel structures 250 can penetrate the electrode patterns 300 and the insulating intermediate layer patterns 112 in the first direction x and can be connected to a dummy bottom electrode pattern DBE, which can be one of the electrode patterns 300 spaced apart from the substrate 100. The vertical memory device 500 can further include a plurality of block separation structures BSS arranged on the substrate 100 in the block separation region BS between adjacent stack structures SS, thereby separating the stack structures SS in the third direction z by a storage block.

[0029] The substrate 100 can include a silicon substrate, a germanium (Ge) substrate, a silicon-on-insulator (SOI) substrate, and / or a germanium-on-insulator (GOI) substrate. In some embodiments, the substrate 100 can include a composite substrate including a combination of a group III element and a group V element.

[0030] A plurality of storage cells MC are provided vertically in the stack structures SS on the cell block region C of the substrate 100 in the first direction x, and a plurality of dummy cells are provided vertically in the upper portion UA of the stack structures SS on the boundary region BA of the substrate 100. The plurality of stack structures SS can be separated from each other by the block separation structures BSS that can be arranged in the block separation region of the substrate 100.

[0031] For example, the storage cells MC in the same stack structure SS that can be defined by the block separation structure BSS can be provided as a storage block B of the vertical memory device 500. In the vertical memory device 500, data erasing and data programming can be performed in units of the storage block B.

[0032] The stack structure SS can include the insulating intermediate layer pattern 112 and the electrode pattern 300, which can be repeatedly stacked on the cell block region C and the boundary region BA of the substrate 100 in the first direction x, alternately to each other. The block separation structure BSS can be interposed between the adjacent stack structures SS on the block separation region BS of the substrate 100, and the stack structure SS can not be provided in the block separation region BS of the substrate 100. Accordingly, the adjacent stack structures SS can be separated from each other in the third direction z by the block separation structure BSS.

[0033] For example, the insulating intermediate layer pattern 112 can be shaped as a plate defined by the second direction y and the third direction z throughout the cell block region C and the boundary region BA of the substrate 100.

[0034] In some embodiments, the insulating intermediate layer pattern 112 can include a first insulating intermediate layer pattern 112a on the substrate 100, and second to twelfth insulating intermediate layer patterns 112b, 112c, 112d, 112e, 112f, 112g, 112h, 112i, 112j, 112k, and 112l which can be sequentially stacked on the first insulating intermediate layer pattern 112a alternately with the electrode pattern 300. That is, a plurality of insulating plates can be stacked on the substrate 100 in the first direction x with the same or similar gap distance. The thickness of each of the insulating intermediate layer patterns 112a to 112l can be the same as or different from each other according to the structure and requirements of the vertical memory device 500.

[0035] The number of the insulating intermediate layer patterns 112 can vary according to the storage capacity of the vertical memory device 500. Hereinafter, the entire insulating intermediate layer patterns can be denoted as reference numeral 112, and the individual insulating intermediate layer patterns can be denoted as one of reference numerals 112a to 112l.

[0036] Since each of the electrode patterns 300 can be stacked alternately with each of the insulating intermediate layer patterns 112a to 112l, each of the electrode patterns 300 can be interposed between two adjacent insulating intermediate layer patterns among the insulating intermediate layer patterns 112a to 112l. In particular, each of the insulating intermediate layer patterns 112a to 112l can be covered by or overlap with the second barrier pattern 301 in the first direction x perpendicular to the substrate 100 (for example, perpendicular to the upper surface of the substrate 100), and thus the upper and lower surfaces of each of the electrode patterns 300 can also be covered by or overlap with the second barrier pattern 301.

[0037] For example, the insulating intermediate layer pattern 112 can include an insulating material such as silicon oxide, and thus each electrode pattern 300 interposed between the insulating intermediate layer patterns 112 can be electrically insulated from each other. Thus, each electrode pattern 300 can individually function as a gate electrode of a memory cell MC.

[0038] The electrode pattern 300 can be alternately arranged with the insulating intermediate layer pattern 112 in the first direction x. Like the insulating intermediate layer pattern 112, the electrode pattern 300 can also be shaped as a plate, i.e., shaped as an electrode plate, and can have the same size or a similar size as the insulating intermediate layer pattern 112.

[0039] In some embodiments, the electrode pattern 300 can include eleven electrodes from a lowermost electrode covering the first insulating intermediate layer pattern 112a to an uppermost electrode covering the eleventh insulating intermediate layer pattern 112k. The number of the electrode pattern 300 and the insulating intermediate layer pattern 112 can vary depending on the storage capacity of the vertical memory device 500. Hereinafter, the entire electrode pattern can be denoted by reference numeral 300, and can be grouped by a first gate line 310, a second gate line 320, and a third gate line 330. The second gate line 320 can include a first word line 321, a second word line 322, a third word line 323, a fourth word line 324, a fifth word line 325, a sixth word line 326, a seventh word line 327, and an eighth word line 328, and the third gate line 330 can include a lower string selection line 331 and an upper string selection line 332. The first gate line 310 can be provided as a ground select line (GSL).

[0040] The electrode pattern 300 can include a low-resistance conductive material such as tungsten (W), tantalum (Ta), and platinum (Pt). Although not shown in the drawing, each electrode pattern 300 can also include a barrier metal pattern interposed between adjacent insulating intermediate layer patterns 112.

[0041] Thus, the insulating intermediate layer pattern 112 and the electrode pattern 300 can be alternately stacked with each other on the substrate 100, and a stack structure SS of the insulating intermediate layer pattern 112 and the electrode pattern 300 can be separated from each other in the third direction z by a block separation structure BSS.

[0042] A lower portion LA of the stack structure SS can be lower than the dummy channel structure 250, and can be relatively close to the substrate 100. An upper portion UA of the stack structure SS can be at substantially the same level as the dummy channel structure 250, and can be relatively far from the substrate 100 as compared to the lower portion LA.

[0043] In particular, a side surface of the plate-shaped electrode pattern 300 (which is referred to as a third cut surface S3) can be in contact with the block separation structure BSS, and another side surface of the plate-shaped electrode pattern 300 can be in contact with the second barrier pattern 301.

[0044] In some embodiments, the electrode pattern 300 can include a first gate line 310, a second gate line 320, and a third gate line 330. The first gate line 310 can be provided as a ground select line (GSL), the second gate line 320 can be provided as a word line (WL). The third gate line 330 can be provided as a string select line (SSL).

[0045] In particular, some of the electrode patterns 300 in the upper portion UA of the stack structure SS can include an extension portion 300u that encloses the dummy channel structure 250 on the boundary area BA of the substrate 100. Each extension portion 300u can have a greater thickness than the rest of the corresponding upper electrode pattern 300. That is, while most of the electrode patterns 300 can have a first thickness tl in the vertical memory device 500, the extension portion 300u of the upper electrode pattern 300 can be partially extended in the first direction x and can have a second thickness t2 that is greater than the first thickness tl in the boundary area BA of the substrate 100.

[0046] For example, the extension portion 300u can include a plurality of side extension portions 300ul arranged alternately with the insulating intermediate layer pattern 112 and spaced apart from each other in the first direction x, and a bottom extension portion 300u2 adjacent to the bottom of the dummy channel structure 250. In particular, the side extension portion 300ul can be adjacent to the dummy channel structure 250, and the bottom extension portion 300u2 can have a recess for holding the dummy channel structure 250 or the bottom of the dummy bottom electrode pattern DBE.

[0047] The plurality of channel structures 230 can be arranged in the cell block area C of the substrate 100, and the plurality of dummy channel structures 250 can be arranged in the boundary area BA of the substrate 100. The channel structure 230 can extend through the electrode pattern 300 and the insulating intermediate layer pattern 112 in the upper portion UA and the lower portion LA (or a portion of the lower portion LA) of the stack structure SS, and the dummy channel structure 250 can extend through the electrode pattern 300 and the insulating intermediate layer pattern 112 in the upper portion UA of the stack structure SS. Accordingly, the channel structure 230 can extend to or into the substrate 100 (or an additional channel pattern 210 on the substrate 100), and the dummy channel structure 250 can extend to or into the dummy bottom electrode pattern DBE. The plurality of memory cells MC can be arranged along the channel structure 230 in the first direction x.

[0048] The channel holes CH can be arranged or run through the electrode pattern 300 and the insulating intermediate layer pattern 112 in the cell block region C in a configuration in which the substrate 100 is exposed through the channel holes CH. The dummy holes DH can be arranged or run through the electrode pattern 300 and the insulating intermediate layer pattern 112 in the upper portion UA of the stack structure SS in the border region BA in a configuration in which one of the electrode patterns 300 is exposed through the dummy holes DH, which can be spaced apart from the substrate 100. The channel holes CH can be filled with the channel structures 230, and the dummy holes DH can be filled with the dummy channel structures 250.

[0049] The channel holes CH can have a first height hi running through the stack structure SS, and the dummy holes DH can have a second height h2 running through the upper portion UA of the stack structure SS. The second height h2 can be smaller than the first height hi.

[0050] In particular, the plurality of channel holes CH and the plurality of dummy holes DH can be arranged on the stack structure SS in a single hole arrangement rule and can be provided as a single hole array on the stack structure SS.

[0051] As will be described in detail, the hole etching process can be performed on the entire stack structure SS regardless of the cell block region C, the border region BA, and the block separation region BS, and thus the dummy holes DH can be sequentially continuously formed as continuous dummy holes (CDH) with the channel holes CH in the same hole etching process.

[0052] The plurality of channel holes CH and the plurality of dummy holes DH can be arranged in the stack structure SS and spaced apart from each other in the third direction z by a hole pitch as a hole array row HAR in such a configuration that the hole array rows HAR arranged in the second direction y can be sequentially offset by half a hole pitch in the third direction z. Accordingly, the plurality of channel holes CH and the plurality of dummy holes DH can be arranged in the stack structure SS in the second direction y as a hole array column HAC, respectively, by a double hole pitch.

[0053] Accordingly, the hole array HA can be arranged in the stack structure SS in a zigzag matrix in which a plurality of hole array rows HAR having a hole pitch can be arranged in the second direction y, and the hole array rows HAR can be sequentially offset by half a hole pitch in the third direction z. Accordingly, adjacent channel holes CH can be spaced apart in the second direction y by a double hole pitch, and thus the hole array column HAC can have a double hole pitch.

[0054] The channel structure 230 can extend through the stack structure SS in the first direction x and can contact the substrate 100 (or an additional channel pattern 210 on the substrate 100) at a channel bottom CB, and a plurality (e.g., ten) of memory cells MC can be arranged in the first direction x at a region of the channel structure 230 adjacent to the plurality of electrode patterns 300. Accordingly, the plurality of memory cells MC can be arranged perpendicularly along the channel structure 230.

[0055] Figure 3A is a perspective view illustrating Figure 2A and Figure 2B a channel structure 230 of the vertical memory device 500 illustrated in FIG. 1.

[0056] Referring to Figure 3A , the channel structure 230 can include a charge trap pattern 232 to at least partially cover an inner surface of a channel hole CH extending through the stack structure SS in the first direction x or on the inner surface to expose the substrate 100 in the cell block region C in a configuration in which the charge trap pattern 232 can be alternately surrounded by the electrode pattern 300 and the insulating intermediate layer pattern 112, a channel 234 shaped as a cylinder extending in the first direction x on the inner surface of the charge trap pattern 232 from the channel bottom CB, and a first fill pillar 236 filling the channel hole CH on the channel 234.

[0057] The charge trap pattern 232 can include a triple pattern structure in which a tunnel insulating pattern, a charge storage pattern including nitride, and a first blocking pattern can be sequentially stacked from the channel 234. The channel 234 can include one or more semiconductor materials such as polysilicon and / or doped polysilicon. The first fill pillar 236 can include an insulating material such as oxide.

[0058] In response to a signal that can be applied from the electrode pattern 300, some electrons can be selectively trapped in the charge trap pattern 232. Accordingly, the electrode pattern 300, the charge trap pattern 232, and the channel 234 can be provided as a unit memory cell MC of a flash memory device. A plurality of memory cells MC can be arranged in the first direction x along the channel structure 230.

[0059] Although the example embodiment discloses that the channel structure 230 can be shaped as a cylinder, the shape and configuration of the channel structure 230 can vary according to the channel hole CH in the first direction x. For example, the channel structure 230 can be shaped as a polygonal cylinder such as a rectangular cylinder and / or a pentagonal cylinder.

[0060] Since the channel structure 230 can be connected to the substrate 100, the channel bottom CB can contact the substrate 100 or an additional channel pattern 210 on the substrate 100.

[0061] For example, the additional channel pattern 210 can include a semiconductor pattern that can be disposed between the channel bottom CB and the substrate 100. In this case, the channel bottom CB can extend into the additional channel pattern 210. For example, the additional channel pattern 210 can include a polysilicon pattern having a top surface located at a level between the upper surface and the lower surface of the second insulating intermediate layer pattern 112b.

[0062] Although the present example embodiment discloses that the additional channel pattern 210 can extend upward in the channel hole CH, the additional channel pattern 210 can be disposed at other positions according to the structure of the vertical memory device 500. For example, the additional channel pattern 210 can be positioned outside the channel hole CH.

[0063] For example, when the substrate 100 can include a silicon-on-insulator (SOI) substrate, a semiconductor layer of the SOI substrate can also be formed as the additional channel pattern 210. In this case, the channel bottom CB can be provided in the substrate 100.

[0064] The dummy channel structure 250 can penetrate the upper portion UA of the stack structure SS in the boundary area BA of the substrate 100, and can be connected to a dummy bottom electrode pattern DBE that can be spaced apart from the substrate 100. The dummy channel structure 250 can have a first cut surface S1 adjacent to the block separation structure BSS in the upper portion UA of the stack structure SS.

[0065] Figure 3B is a perspective view showing Figure 2A and Figure 2B a dummy channel structure 250 of the vertical memory device 500 shown in FIG. 1.

[0066] Referring to Figure 3B , the dummy channel structure 250 can include a barrier trap pattern 257 covering at least a portion of or on an inner surface of a dummy hole DH extending through the upper portion UA of the stack structure SS in the first direction x to expose the dummy bottom electrode pattern DBE in the boundary area BA. The dummy channel structure 250 can be alternately surrounded by the electrode pattern 300 and the insulating intermediate layer pattern 112 in the upper portion UA of the stack structure SS, and can include the barrier trap pattern 257, a dummy channel 254 covering or on the inner surface of the barrier trap pattern 257 and the dummy bottom electrode pattern DBE, and a second fill pillar 256 filling the dummy hole DH on the dummy channel 254.

[0067] In some embodiments, the dummy channel structure 250 can have substantially the same structure as the channel structure 230, except that the blocking trap pattern 257 can include a triple pattern structure in which the tunnel insulating pattern T1, the second blocking pattern 301, and the first blocking pattern T3 can be sequentially stacked from the dummy channel 254 and can each include an oxide. In some embodiments, at least one of the tunnel insulating pattern T1, the second blocking pattern 301, and the first blocking pattern T3 can include an oxide. That is, the blocking trap pattern 257 in the boundary area BA can be obtained by replacing the charge storage pattern T2 including a nitride with the second blocking pattern 301 including an oxide.

[0068] In particular, the dummy channel structure 250 can be positioned only at the upper portion UA of the stack structure SS, and thus can be adjacent to the block separation structure BSS only at the upper portion UA of the stack structure SS. That is, the dummy channel structure 250 can not be adjacent to the block separation structure BSS at the lower portion LA of the stack structure SS.

[0069] According to a conventional CDH-type vertical memory device, a dummy channel structure extends to a substrate with a cut surface extending through the entire stack structure at a boundary area. However, the dummy channel structure of the conventional vertical memory device is not sufficiently removed from the substrate at a lower portion of the stack structure in a block separation process, and thus a residue of the dummy channel structure can remain on the substrate at the boundary area as a residual channel. Accordingly, adjacent vertical memory cells are generally connected to each other at the boundary area by the residual channel at the lower portion of the block separation structure. That is, adjacent vertical gate electrodes of the conventional vertical memory device can not be sufficiently separated due to the residual channel, thereby generating a bridging defect around the boundary area of the substrate in the lower portion of the block separation structure BSS.

[0070] However, the dummy channel structure 250 can be positioned at the upper portion UA of the stack structure SS and spaced apart from the substrate 100, and thus there can be no residual channel remaining on the substrate 100 in the lower portion of the block separation structure BSS at the boundary area BA of the substrate 100. Accordingly, the block separation structure BSS can be sufficiently filled in the block separation trench at the lower portion of the block separation structure BSS to sufficiently separate the stack structure SS in the third direction z, thereby substantially preventing or reducing a bridging defect around the substrate at the lower portion of the block separation structure BSS.

[0071] The second height h2 can vary according to the dummy channel stopper 140 in Figure 8B Figure 4B ​In contrast to the sacrificial layer 120, the dummy channel stopper 140 can have a relatively large etch resistance. Thus, when some of the sacrificial layer 120 in the upper portion UA of the stack structure SS can be replaced with the dummy channel stopper 140, due to the etch selectivity of the dummy channel stopper 140 in the hole etching process, the dummy hole DH that penetrates the dummy channel stopper 140 can have a second height h2 that is smaller than a first height hi of the channel hole CH.

[0072] Thus, the dummy channel structure 250 can be positioned in the dummy hole DH having the second height h2, and can be connected to the dummy bottom electrode pattern DBE that can be spaced apart from the substrate 100 by a dummy gap distance d in the first direction x.

[0073] In particular, the dummy gap distance d can indicate a distance, such as a substantially largest distance, by which the electrode pattern 300 and the insulating intermediate layer pattern 112 can not be etched away at the boundary area BA in the hole etching process for forming the channel hole CH that penetrates the stack structure SS in the cell block region C.

[0074] In some embodiments, the dummy gap distance d between the substrate 100 and the dummy bottom DB or the dummy bottom electrode pattern DBE can be determined by the following equation (1).

[0075] d = (0.5 ~ 0.7) * H (1)

[0076] (where d denotes the dummy gap distance from the substrate 100, and H denotes the height of the stack structure SS on the substrate 100). The range of 0.5 to 0.7 can be described as a variable k, and can be used to scale the height H of the stack structure SS.

[0077] When the dummy gap distance d is greater than about 0.7 times the height H of the stack structure SS, the dummy channel structure 250 can extend to the lower portion LA of the stack structure SS, thus the dummy channel structure 250 tends to stay on the substrate 100 at the boundary area BA in the hole etching process, and a bridge defect can occur at the lower portion of the block separation structure BSS. In contrast, when the dummy gap distance d is less than about 0.5 times the height H of the stack structure SS, it is difficult to obtain such a proper etch selectivity of the dummy channel stopper 140 with respect to the sacrificial layer 120 that the dummy hole DH can have the second height h2 while the channel hole CH can have the first height hi.

[0078] Thus, according to some embodiments, the dummy gap distance d between the substrate 100 and the dummy bottom electrode pattern DBE can be in the range of about 50% to about 70% of the height H of the stack structure SS.

[0079] Because no residual trench can remain on the substrate 100, the dummy trench structure 250, the electrode pattern 300, and the insulating intermediate layer pattern 112 can be substantially uniformly adjacent to the block separation structure BSS along the first direction x. That is, the first cross-sectional surface S1 of the dummy trench structure 250, the second cross-sectional surface S2 of the insulating intermediate layer pattern 112, and the third cross-sectional surface S3 of the electrode pattern 300 can be positioned at substantially the same position in the third direction z, and the first to third cross-sectional surfaces S1, S2, and S3 can be substantially uniformly adjacent to the block separation structure BSS along the first direction x.

[0080] The block separation structure BSS can include a linear trench spacer TS covering or overlapping the first to third cross-sectional surfaces S1, S2, and S3 and extending in the first direction x, a doped layer 101 doped with an impurity at a surface portion of the substrate 100 that can be exposed between a pair of facing trench spacers TS, and a conductive block separation line 350 filling a block separation trench between the pair of facing trench spacers TS and in contact with the doped layer 101.

[0081] The trench spacer TS can include silicon nitride, and the block separation line 350 can include one or more of a low-resistance metal, a nitride of a low-resistance metal, an oxide of a low-resistance metal, and a silicide of a low-resistance metal.

[0082] Accordingly, the stacked structures SS including a plurality of memory cells MC can be separated from each other in the third direction z by the block separation structure BSS, and each separated stacked structure SS can function as a memory block B.

[0083] The plurality of upper insulating patterns 160, 260, 360, and 460 (see Figure 19A ) can be arranged on the memory block B and the block separation structure BSS in a configuration in which a top surface of the upper insulating pattern 460 can be planarized. The cap pattern 240 can be arranged on the trench structure 230, the boundary pattern 240a can be arranged on the dummy trench structure 250, and the contact plug 410 can contact the cap pattern 240 through the upper insulating patterns 260 and 360. Then, a wiring 490 such as a bit line can be arranged on the upper insulating pattern 360 and can contact the contact plug 410.

[0084] According to an example embodiment of the vertical memory device 500, a plurality of dummy channel structures 250 may be positioned across the upper portion UA ​​of the stacked structure SS in the boundary region BA of the substrate 100, and a plurality of channel structures 230 may be positioned across the entire stacked structure SS in the cell block region C of the substrate 100. In particular, in some embodiments, no residual channels may remain on the substrate 100 in the lower portion of the block separation structure BSS, thereby substantially preventing or reducing bridging defects attributable to residual channels in the vertical memory device 500.

[0085] In the following text, reference will be made to Figures 4A-19B Detailed description of the manufacturing process Figures 1-3B The process steps of the method for the vertical storage device 500 shown.

[0086] Figures 4A-19B This illustrates the manufacture of some exemplary embodiments of the invention. Figures 1-3B A cross-sectional view of the process steps of the method for the vertical storage device 500 shown. Figures 4A-19B In the figures, the letters "A", "B", and "C" respectively represent top views showing the process steps of a method for manufacturing vertical storage devices, top views represented by the letter "A", and top views of the same type. Figure 1 The sectional view corresponding to line I-I', and the enlarged top view of part A in the sectional view represented by the letter "B".

[0087] Reference Figure 4A and Figure 4B Insulating intermediate layers 110a, 110b, 110c, 110d, 110e, 110f, 110g, 110h, 110i, 110j, 110k and 110l, and sacrificial layers 120a, 120b, 120c, 120d, 120e, 120f, 120g, 120h, 120i, 120j and 120k can be alternately stacked on substrate 100 to form a molded stacked structure SS' on substrate 100.

[0088] For example, a first insulating intermediate layer 110a can be formed on the substrate 100, and then first sacrificial layers 120a to eleventh sacrificial layers 120k can be alternately formed on the first insulating intermediate layer 110a along the first direction x with second insulating intermediate layers 110b to twelfth insulating intermediate layers 110l. Therefore, multiple sacrificial layers 120a to 120k can be stacked on the substrate 100 and can be insulated from each other by their respective insulating intermediate layers 110a to 110l. The uppermost sacrificial layer 120k can be covered by or overlap with the uppermost insulating intermediate layer 110l. The uppermost insulating intermediate layer 110l can be replaced by a mask layer.

[0089] The number of the sacrificial layers and the insulating intermediate layers can vary depending on the storage capacity of the vertical memory device 500.

[0090] Hereinafter, as with the insulating intermediate layer pattern 112, the entire insulating intermediate layers can be denoted by reference numeral 110, and the individual insulating intermediate layers can be denoted by one of reference numerals 110a to 1101. In the same manner, the entire sacrificial layers can be denoted by reference numeral 120, and the individual sacrificial layers can be denoted by one of reference numerals 120a to 120k.

[0091] The substrate 100 can include a cell block region C, a block separation region BS, and a boundary region BA between the cell block region C and the block separation region BS. A plurality of memory cells MC to be formed later can be formed in a stack structure SS that can be disposed on the cell block region C of the substrate 100, and a plurality of dummy hole structures in the dummy hole DH can be disposed in the stack structure SS that can be disposed on the boundary region BA of the substrate 100.

[0092] For example, the insulating intermediate layers 110 and the sacrificial layers 120 can be formed on the substrate 100 by a deposition process such as a chemical vapor deposition (CVD) process and / or an atomic layer deposition (ALD) process. In particular, the first insulating intermediate layer 110a can be formed on the substrate 100 by a thermal oxidation process rather than a deposition process.

[0093] The insulating intermediate layers 110 can include oxides such as PE-TEOS and HDP and silicon oxides such as PEOX, and the sacrificial layers 120 can have a material having etch selectivity with respect to the insulating intermediate layers 110, such as silicon nitride.

[0094] In particular, the respective thickness of each of the insulating intermediate layers 110 can vary depending on the requirements of the vertical memory device 500 and process conditions.

[0095] Referring to Figure 5A and Figure 5B A portion of the insulating intermediate layers 110 and a portion of the sacrificial layers 120 can be removed from the upper portion UA' of the molded stack structure SS' at the block separation region BS of the substrate 100, thereby forming an upper trench UT, the etch stop sacrificial layer 120h' can be exposed through the upper trench UT, and the upper trench UT can extend in the second direction y.

[0096] For example, the first mask pattern Ml can be formed on the molding stack structure SS', and a dry etching process can be applied to the molding stack structure SS' to a trench depth TD until a portion of the sacrificial layer 120 and a portion of the insulating intermediate layer 110 can be sequentially removed downward. Accordingly, the upper trench UT can be formed at the upper portion UA' of the molding stack structure SS' in a line shape extending in the second direction y, and an etch stop portion of the sacrificial layer 120h' at a central portion of the block separation area BS can be exposed in the upper trench UT. For example, the etching process can include a plasma etching process.

[0097] In particular, the etching process can be stopped at the sacrificial layer 120 in a manner that the sacrificial layer 120 is available as an etch stopper. Accordingly, a specific sacrificial layer 120 can be provided at a bottom of the upper trench UT. Accordingly, the upper trench UT can have a bottom in contact with the sacrificial layer 120, and sidewalls alternately surrounded by a preliminary insulating intermediate layer pattern 111 formed from the insulating intermediate layer 110 and a preliminary sacrificial pattern 121 formed from the sacrificial layer 120.

[0098] The trench depth TD of the upper trench UT can be determined by a position of the etch stop sacrificial layer 120h', and the trench depth TD of the upper trench UT can determine a second height h2 of the dummy hole DH. Accordingly, the position of the etch stop sacrificial layer 120h' can be selected in view of the second height h2 of the dummy hole DH. In some embodiments, the eighth sacrificial layer 120h can be selected as the etch stop sacrificial layer 120h'.

[0099] Accordingly, in the upper portion UA' of the molding stack structure SS', a portion of the insulating intermediate layer 110 can be formed as the preliminary insulating intermediate layer pattern 111, and a portion of the sacrificial layer 120 can be formed as the preliminary sacrificial pattern 121. The preliminary insulating intermediate layer pattern 111 can include a preliminary twelfth insulating intermediate layer pattern 111l, a preliminary eleventh insulating intermediate layer pattern 111k, a preliminary tenth insulating intermediate layer pattern 111j, and a preliminary ninth insulating intermediate layer pattern 111i. The preliminary sacrificial pattern 121 can include a preliminary eleventh sacrificial pattern 121k, a preliminary tenth sacrificial pattern 121j, and a preliminary ninth sacrificial pattern 121i.

[0100] In particular, the eighth sacrificial layer 120h can be used as an etch stopper for a dry etching process for forming the upper trench UT, and thus the eighth sacrificial layer 120h can be recessed and provided at a bottom of the upper trench UT. Accordingly, the eighth sacrificial layer 120h can not be formed as the eighth sacrificial pattern, but can be formed as the etch stop sacrificial layer 120h'.

[0101] Although the present example embodiment discloses that the eighth sacrificial layer 120h can be provided as the etch stop sacrificial layer 120h', any other sacrificial layer 120 higher or lower than the eighth sacrificial layer 120h can also be used as the etch stop sacrificial layer for the etching process for forming the upper trench UT.

[0102] Accordingly, the upper trench UT defined by the preliminary insulating intermediate layer pattern 111, the preliminary sacrificial pattern 121, and the etch stop sacrificial layer 120h' can be formed in the block separation region BS at the upper portion UA' of the molded stack structure SS'.

[0103] Referring to Figure 6A and Figure 6B The preliminary eleventh sacrificial pattern 121k, the preliminary tenth sacrificial pattern 121j, the preliminary ninth sacrificial pattern 121i, and the etch stop sacrificial layer 120h' can be partially removed from the stack structure SS in parallel with the upper surface of the substrate 100, thereby forming a plurality of horizontal recesses HR between the adjacent preliminary insulating intermediate layer patterns 111 and between the eighth insulating intermediate layer 110h and the preliminary ninth insulating intermediate layer pattern 111i. The horizontal recesses HR can be adjacent to or can be joined to the upper trench UT, and can extend in the second direction y and the third direction z. In particular, the etch stop sacrificial layer 120h' can also be partially removed from the stack structure SS, and the etch stop sacrificial layer 120h' can be formed as the preliminary eighth sacrificial pattern 121h. The preliminary sacrificial pattern 121 can further include the preliminary eighth sacrificial pattern 121h.

[0104] For example, a wet etching process can be performed on the preliminary sacrificial pattern 121 and the etch stop sacrificial layer 120h' by using an aqueous solution of phosphoric acid or an aqueous solution of sulfuric acid as an etchant having a high etching selectivity with respect to the preliminary insulating intermediate layer pattern 111. In some embodiments, the wet etching process can be performed as a back-etching process from a boundary surface of the preliminary sacrificial pattern 121 having the upper trench UT.

[0105] For example, the horizontal recesses HR can horizontally extend from a central portion of the block separation region BS to the boundary region BA in a manner that the horizontal recesses HR can span to the cell block region C around the boundary region BA.

[0106] Referring to Figure 7A and Figure 7B The dummy channel stopper 140 can be formed in the horizontal recesses HR in a configuration that the dummy channel stopper 140 can extend to the boundary region BA and be exposed to the upper trench UT. The dummy channel stopper 140 can include a stopper material having an etching selectivity with respect to the preliminary insulating intermediate layer pattern 111.

[0107] For example, the horizontal recess HR can be at least partially filled with the stopper material via the upper trench UT by a high gap fill deposition process in such a way that a surface of the upper trench UT can be covered or overlapped with the stopper material. In some embodiments, the high gap fill deposition process can include a high density plasma (HDP) deposition process and an atomic layer deposition (ALD) process.

[0108] For example, the stopper material for the dummy channel stopper 140 can include polysilicon that can be etched more than the oxide of the preliminary insulating intermediate layer pattern 111. However, any other stopper material can be used for the dummy channel stopper 140 as long as the stopper material can be etched sufficiently well compared to the oxide of the preliminary insulating intermediate layer pattern 111.

[0109] In particular, the stopper material filled in the horizontal recess HR defined by the eighth preliminary sacrificial pattern 121h can be formed as a single bottom pattern 144 at a bottom of the upper trench UT, and the stopper material filled in the horizontal recess HR defined by the ninth preliminary sacrificial pattern 121i, the tenth preliminary sacrificial pattern 121j, and the eleventh preliminary sacrificial pattern 121k can be formed as a plurality of side patterns 142 surrounding sidewalls of the upper trench UT. The dummy channel stopper 140 can include the bottom pattern 144 and the plurality of side patterns 142.

[0110] Accordingly, the upper trench UT can be surrounded by the plurality of side patterns 142 and the bottom pattern 144 that can be stacked in the first direction x alternately with the preliminary insulating intermediate layer pattern 111.

[0111] Accordingly, the dummy channel stopper 140 can extend from the block separation region BS to the boundary region BA at the upper portion UA' of the molded stack structure SS', and can be in contact with the preliminary sacrificial pattern 121. The preliminary insulating intermediate layer pattern 111 can have an etching selectivity with respect to the dummy channel stopper 140.

[0112] Referring to Figure 8A and Figure 8B The fill body 150 can be formed in the upper trench UT surrounded by the dummy channel stopper 140.

[0113] For example, a fill layer (not shown) can be formed on the preliminary twelfth insulating intermediate layer pattern 111l until the upper trench UT can be sufficiently filled with the fill layer.

[0114] Then, the fill layer can be partially removed by a planarization process until an upper surface of the preliminary twelfth insulating intermediate layer pattern 111l can be exposed, thereby forming the fill body 150 in the upper trench UT. The planarization process can include a chemical mechanical polishing (CMP) process and / or a back-etching process.

[0115] Referring to Figure 9A and Figure 9B A single hole etching process can be performed on the molded stack structure SS' having the dummy channel stoppers 140 and the fillers 150, thereby forming a plurality of channel holes CH in the cell block regions C and a plurality of dummy holes DH in the boundary regions BA and the block separation regions BS. The channel holes CH can extend through the entire molded stack structure SS' to the substrate 100, and the dummy holes DH can extend through the upper portion UA' of the molded stack structure SS' to the bottom pattern 144. The channel holes CH and the dummy holes DH can be formed in the molded stack structure SS' in the CDH process by the same etching process.

[0116] The first upper insulating pattern 160 can be formed on the preliminary twelfth insulating intermediate layer pattern 1111 and on the fillers 150 in such a configuration that the preliminary twelfth insulating intermediate layer pattern 1111 can be partially exposed by the first upper insulating pattern 160 in the cell block regions C and in the boundary regions BA and the block separation regions BS. The first upper insulating pattern 160 can include a layout of openings corresponding to the single hole array HA of the channel holes CH and the dummy holes DH. Then, a hole etching process can be performed on the molded stack structure SS' by using the first upper insulating pattern 160 as an etching mask.

[0117] The hole etching process can be performed on the entire molded stack structure SS' regardless of the cell block regions C, the boundary regions BA and the block separation regions BS, so that the channel holes CH and the dummy holes DH can be formed in the single hole array HA. Accordingly, the channel holes CH can be formed in the molded stack structure SS' at the cell block regions C, and the dummy holes DH can be formed in the upper portion UA' of the molded stack structure SS' in the boundary regions BA and the block separation regions BS.

[0118] The preliminary insulating intermediate layer patterns 111 and the preliminary sacrificial patterns 121 at the upper portion UA' of the molded stack structure SS' and the insulating intermediate layer 110 and the sacrificial layer 120 at the lower portion LA' of the molded stack structure SS' can be partially removed from the substrate 100 by the hole etching process, thereby forming the channel holes CH having the first height h1. Accordingly, the channel holes CH can be surrounded by the molded stack structure SS' in the cell block regions C, and the substrate 100 can be exposed through the channel holes CH.

[0119] The preliminary insulating intermediate layer pattern 111 and the dummy channel stopper 140 can be partially removed from the upper portion UA' of the mold stack structure SS' in the boundary area BA and the block separation area BS by a hole etching process, thereby forming a dummy hole DH having a second height h2. The dummy hole DH can be alternately surrounded by the preliminary insulating intermediate layer pattern 111 and the dummy channel stopper 140, and the bottom pattern 144 can be exposed through the dummy hole DH.

[0120] In particular, when the channel hole CH has the first height h1 in the cell block area C by the hole etching process, the dummy channel DH can have the second height h2 in the boundary area BA and the block separation area BS by the hole etching process due to the high etch resistance of the dummy channel stopper 140. That is, when the hole etching process is performed until the substrate 100 is exposed in the cell block area C, the hole etching process can be performed until the bottom pattern 144 is exposed in the boundary area BA and the block separation area BS due to the high etch resistance of the dummy channel stopper 140. Accordingly, an etch recess can be formed on the bottom pattern 144 by the hole etching process.

[0121] The second height h2 of the dummy hole DH can vary depending on the etch selectivity of the dummy channel stopper 140 with respect to the sacrificial layer 120 and the aspect ratio of the channel hole CH.

[0122] The dummy hole DH can be formed as a continuous dummy hole (CDH) which can be continuously formed in the cell block area C, the boundary area BA, and the block separation area BS with the channel hole CH in the same hole arrangement rule.

[0123] The channel hole CH and the dummy hole DH can be arranged in a Z-shaped arrangement matrix in which a plurality of hole array rows HAR having a hole pitch P can be arranged in the second direction y and the hole array rows HAR can be sequentially offset by half a hole pitch 0.5P in the third direction z. Accordingly, adjacent channel holes CH can be spaced apart by a double hole pitch 2P in the second direction y, and thus a hole array column HAC can have a double hole pitch 2P.

[0124] Referring to Figures 10A-10B The additional channel pattern 210 can be formed on the substrate 100 which can be exposed through the channel hole CH. The additional channel pattern 210 can extend a channel region between the substrate 100 and a channel structure 230 which will be formed later.

[0125] For example, an amorphous silicon layer can be formed on the exposed substrate 100 in the channel hole CH, and then a laser epitaxial growth (LEG) process or a solid phase epitaxy (SPE) process can be performed on the amorphous silicon layer. Accordingly, a semiconductor pattern can be formed on the substrate 100 as the additional channel pattern 210 in the channel hole CH.

[0126] In contrast, a selective epitaxial growth (SEG) process can be performed on the substrate 100 by using the upper surface of the substrate 100 as a seed layer, thereby forming a semiconductor pattern as the additional channel pattern 210. In this case, a barrier layer (not shown) can be formed on the bottom pattern 144, and thus the semiconductor pattern can be sufficiently prevented from growing from the bottom pattern 144 in the SEG process.

[0127] In some embodiments, the additional channel pattern 210 can be formed in such a manner that the top surface of the additional channel pattern 210 can be positioned at a level between the upper surface and the lower surface of the second insulating intermediate layer 110b.

[0128] However, according to the requirements of the vertical memory device, the additional channel pattern 210 can be disposed in the substrate 100, and the additional channel pattern 210 can be exposed through the channel hole CH.

[0129] For example, a silicon-on-insulator (SOI) substrate can be provided as the substrate 100, and the channel hole CH can be formed in such a manner that an upper semiconductor layer of the SOI substrate can be exposed through the channel hole CH. In this case, the channel structure 230 to be formed later can extend into the substrate 100, and the additional channel pattern can not be provided on the channel bottom CB.

[0130] Referring to Figures 11A-11C The charge trap pattern 232 and the preliminary dummy trap pattern 252a can be formed on the sidewalls or the sidewalls and the bottoms of the channel hole CH and the dummy hole DH, respectively.

[0131] For example, a trap layer (not shown) and a hole spacer layer (not shown) can be sequentially formed on the first upper insulating pattern 160 along the surface profile of the channel hole CH and the dummy hole DH. Accordingly, the trap layer and the hole spacer layer can be stacked on the sidewalls and the bottoms of the channel hole CH and the dummy hole DH, respectively. Then, the hole spacer layer can be partially removed from the molded stack structure SS' in such a manner that the hole spacer layer can remain only on the sidewalls of the channel hole CH and the dummy hole DH as the hole spacer HS, by an anisotropic etching process.

[0132] Then, a continuous etching process can be performed on the trap layer by using the hole spacer HS as an etching mask, so that the trap layer can be removed from the first upper insulating pattern 160, the additional channel pattern 210, and the bottom pattern 144. Accordingly, the trap layer can remain on the sidewalls of the channel hole CH and the dummy hole DH, thereby forming the charge trap pattern 232 covered by the hole spacer HS in the channel hole CH and forming the preliminary dummy trap pattern 252a covered by the hole spacer HS in the dummy hole DH.

[0133] In the continuous etching process of forming the charge trap pattern 232 and the preliminary dummy trap pattern 252a, the additional channel pattern 210 and the bottom pattern 144 can be further etched away at the channel bottom CB and the dummy bottom DB, respectively. Accordingly, a plurality of channel bottom recesses CBR can be formed on the additional channel pattern 210, and a plurality of dummy bottom recesses DBR can be formed on the bottom pattern 144. Since the bottom pattern 144 can have a greater etch resistance than the additional channel pattern 210 including a semiconductor material, the size of the channel bottom recess CBR can be formed to be greater than the size of the dummy bottom recess DBR.

[0134] The charge trap pattern 232 can have substantially the same configuration and composition as the preliminary dummy trap pattern 252a. Accordingly, both the charge trap pattern 232 and the preliminary dummy trap pattern 252a can include a tunnel insulating pattern T1 including an oxide and in contact with a hole spacer HS, a charge trap pattern T2 including a nitride and in contact with the tunnel insulating pattern T1, and a first blocking pattern T3 including an oxide and in contact with the charge trap pattern T2.

[0135] Referring to Figures 12A-12C , the channel 234 and the first fill pillar 236 can be formed in the channel hole CH, and the preliminary dummy channel 254a and the preliminary fill pillar 256a can be formed in the dummy hole DH simultaneously with the channel 234 and the first fill pillar 236.

[0136] The hole spacer HS can be removed from the charge trap pattern 232 and the preliminary dummy trap pattern 252a. Then, a channel layer (not shown) can be formed on the first upper insulating pattern 160 in accordance with the surface profile of the channel hole CH and the dummy hole DH. Thereafter, a hole fill layer (not shown) can be formed on the channel layer, and can be formed to a sufficient thickness to at least partially fill the channel hole CH and the dummy hole DH on the channel layer.

[0137] Then, the hole fill layer and the channel layer can be sequentially partially removed by a planarization process until an upper surface of the first upper insulating pattern 160 can be exposed, so that the hole fill layer and the channel layer can be formed as the channel 234 in contact with the charge trap pattern 232 and the first fill pillar 236 in contact with the channel 234 and filling the channel hole CH, and as the preliminary dummy channel 254a in contact with the preliminary dummy trap pattern 252a and the preliminary fill pillar 256a in contact with the preliminary dummy channel 254a and filling the dummy hole DH.

[0138] For example, the channel 234 and the preliminary dummy channel 254a can include amorphous silicon, or polycrystalline silicon doped with impurities or not doped with impurities. The first fill pillar 236 and the preliminary fill pillar 256a can include an oxide such as silicon oxide.

[0139] Accordingly, the channel holes CH can be filled with the channel structures 230 having the charge-trap pattern 232, the channel 234, and the first fill pillar 236, and the dummy holes DH can be filled with the preliminary dummy channel structures 250a having the preliminary dummy-trap pattern 252a, the preliminary dummy channel 254a, and the preliminary fill pillar 256a.

[0140] Thereafter, the channel structures 230 and the preliminary dummy channel structures 250a can be further subjected to an additional etching process or a back-etching process, so that the upper portions of the channel structures 230 can be removed from the channel holes CH, and the upper portions of the preliminary dummy channel structures 250a can be removed from the dummy holes DH. That is, the channel structures 230 and the preliminary dummy channel structures 250a can be retracted from the top of the channel holes CH and the top of the dummy holes DH, respectively, by the additional etching process or the back-etching process.

[0141] Then, the cap patterns 240 can be formed on each of the channel structures 230 and the preliminary dummy channel structures 250a in a manner that the channel structures 230 and the preliminary dummy channel structures 250a can be separated from the surrounding environment.

[0142] For example, the cap patterns 240 can include single-crystal silicon, or polycrystalline silicon doped with impurities or not doped with impurities, and can serve as contact pads for the channel structures 230.

[0143] Referring to Figures 13A-13C The second upper insulating patterns 260 can be formed on the first upper insulating patterns 160 and the cap patterns 240. The molded stack structure SS' and the second upper insulating patterns 260, the first upper insulating patterns 160, the cap patterns 240, the preliminary dummy channel structures 250a, the dummy channel stoppers 140, and the fill bodies 150 can be removed from the substrate 100 in the block separation region BS, thereby forming a block separation trench ST shaped as a line extending in the second direction y and exposing the substrate 100.

[0144] For example, the second upper insulating patterns 260, the first upper insulating patterns 160, the cap patterns 240, the preliminary dummy channel structures 250a, the dummy channel stoppers 140, the fill bodies 150, and the preliminary insulating intermediate layer patterns 111 can be removed from the substrate 100 at the upper portion UA' of the molded stack structure SS' by a first trench etching process, thereby forming a first block separation trench ST1 extendable in the second direction y at the upper portion of the block separation trench ST. Then, the insulating intermediate layer 110 and the sacrificial layer 120 can be continuously removed from the substrate 100 at the lower portion of the molded stack structure SS' by a second trench etching process, thereby forming a second block separation trench ST2 extendable in the second direction y at the lower portion of the block separation trench ST.

[0145] For example, the plasma etch process can be performed as a first trench etch process under first etch conditions and then can be performed as a second trench etch process under second etch conditions. The plasma etch process can be used to remove both polysilicon and oxide.

[0146] The preliminary dummy trench structure 250a can be partially cut away in the first trench etch process, thereby forming a dummy trench structure 250 having a dummy trap pattern 252, a dummy trench 254, and a second fill pillar 256. In particular, the dummy trench structure 250 can include a first cut surface SI that is exposed to and serves as a sidewall of the first block separation trench ST1.

[0147] Further, the preliminary insulating intermediate layer pattern 111 and the preliminary sacrificial pattern 121 can be formed as an insulating intermediate layer pattern 112 and a sacrificial pattern 122 at an upper portion of the mold stack structure SS'. The dummy trench stopper 140 can also be partially removed by the first trench etch process at the upper portion UA' of the mold stack structure SS', thereby forming a residual stopper 140a including a residual bottom pattern 144a and a plurality of residual side patterns 142a.

[0148] The insulating intermediate layer 110 and the sacrificial layer 120 can also be formed as the insulating intermediate layer pattern 112 and the sacrificial pattern 122 at a lower portion LA' of the mold stack structure SS'. Thus, the insulating intermediate layer pattern 112 (including the insulating intermediate layer patterns 112a, 112b, 112c, 112d, 112e, 112f, 112g, 112h, 112i, 112j, 112k, and 1121) and the sacrificial pattern 122 (including the sacrificial patterns 122a, 122b, 122c, 122d, 122e, 122f, 122g, 122h, 122i, 122j, and 122k) can be formed throughout the mold stack structure SS' at the cell block region C and the boundary region BA.

[0149] In particular, the insulating intermediate layer pattern 112 and the sacrificial pattern 122 can have a second cut surface S2 that can be exposed to and can serve as a sidewall of the second block separation trench ST2. Because the preliminary dummy trench structure 250a and the dummy trench stopper 140 having a relatively high etch resistance can be positioned only at the upper portion UA' of the mold stack structure SS', the second trench etch process can be uniformly performed at the lower portion LA' of the mold stack structure SS' for the insulating intermediate layer 110 and the sacrificial layer 120 having a relatively low aspect ratio. Thus, the second cut surface S2 can be sufficiently uniform in the first direction x without any residue around the substrate 100.

[0150] Further, since the second trench etching process can be performed continuously with the first trench etching process, the second cut surface S2 can be continuous and substantially coplanar with the first cut surface S1.

[0151] According to a conventional process for fabricating a CDH-type vertical memory device, the preliminary dummy channel structure 250a extends to the substrate 100 like the channel structure 230. Thus, as the aspect ratio of the block separation trench ST becomes larger as the total height H of the stacked structure SS increases, the preliminary dummy channel structure 250a can inevitably remain on the substrate 100 as a remaining channel at a lower portion of the block separation trench ST. Since the remaining channel can include the conductive material of the preliminary dummy channel 254a, the adjacent electrode pattern or gate pattern can be connected in a subsequent electrode formation process, which is widely known as a bridging defect.

[0152] However, according to the present method of fabricating the vertical memory device 500, since the preliminary dummy channel structure 250a can be positioned only at the upper portion of the molded stacked structure SS', the second trench etching process can be uniformly performed on the insulating intermediate layers 110 and the sacrificial layers 120 having a reduced aspect ratio. Thus, although the dummy holes DH can be formed continuously with the channel holes CH in the same hole etching process, there can be no residue of the preliminary dummy channel structure 250a remaining on the substrate at the lower portion of the block separation trench ST, and the bridging defect can be substantially prevented.

[0153] Further, since the block separation trench ST can be formed by the sequential etching steps of the upper portion UA' and the lower portion LA' of the molded stacked structure SS', the block separation trench ST can be formed with a sufficiently small aspect ratio, and the sidewall of the block separation trench ST can be substantially uniform in the first direction x. Thus, the first cut surface S1 and the second cut surface S2 can be substantially uniform and coplanar with each other in the first direction x, and thus the sidewall of the block separation trench ST can have a substantially uniform vertical profile in the first direction x.

[0154] Due to the trench etching process, the molded stacked structure SS' can be formed in the cell block region C and the boundary region BA in a stacked pattern SP. Thus, the stacked pattern SP can include a plurality of insulating intermediate layer patterns 112 and a plurality of sacrificial layer patterns 122 that can be alternately stacked in the first direction x.

[0155] Referring to Figures 14A-14CThe residual stopper 140a and the sacrificial pattern 122 can be removed from the stacked pattern SP, thereby forming a plurality of gap spaces GS defined by the adjacent insulating intermediate layer patterns 112 substantially in parallel with the substrate 100 (e.g., in parallel with the upper surface of the substrate 100). Thus, the plurality of gap spaces GS can be arranged in the first direction x alternately with the insulating intermediate layer patterns 112.

[0156] For example, because the etch resistance of the residual stopper 140a and the sacrificial pattern 122 can be smaller than the insulating intermediate layer pattern 112 and can be exposed to the block separation trench ST, the residual stopper 140a and the sacrificial pattern 122 can be removed from the stacked pattern SP by a back-etching process using a phosphoric acid aqueous solution or a sulfuric acid aqueous solution as an etchant.

[0157] In particular, because the etch resistance of the residual stopper 140a can be greater than the sacrificial pattern 122, the insulating intermediate layer pattern 112 in contact with the residual stopper 140a can be removed more than the insulating intermediate layer pattern 112 in contact with the sacrificial pattern 122. Thus, the insulating intermediate layer pattern 112 of the upper portion UA' of the stacked pattern SP in the boundary area BA can have a smaller thickness in the first direction x than the insulating intermediate layer pattern 112 of the upper portion UA' of the stacked pattern SP in the cell block area C and the insulating intermediate layer pattern 112 of the lower portion LA' of the stacked pattern SP in the cell block area C and the boundary area BA.

[0158] Thus, although the gap spaces GS can be uniform throughout the cell block area C and the boundary area BA at the lower portion LA' of the stacked pattern SP, at the upper portion UA' of the stacked pattern SP, the gap spaces GS in the boundary area BA can have a greater thickness in the first direction x than the gap spaces GS in the cell block area C. That is, the gap spaces GS at the upper portion UA' of the stacked pattern SP can be enlarged as enlarged spaces ES at the boundary area BA.

[0159] Further, the charge storage pattern T2 of the dummy trap pattern 252 can also be removed together with the sacrificial pattern 122, and thus, a trap void TO can be formed in the dummy trap pattern 252. Because the charge trap pattern T2 can include nitride, the charge trap pattern T2 can be removed together with the sacrificial pattern 122. Thus, when the charge trap pattern T2 can include a material different from the sacrificial pattern 122, a trap void can not be formed in the dummy trap pattern 252.

[0160] Referring to Figures 15A-15CThe second barrier layer 301a can be formed on the second upper insulating pattern 260 along the surface profile of the block separation trench ST and the gap space GS. The conductive layer 300a can be formed on the second barrier layer 301a to a sufficient thickness to fill the block separation trench ST and the gap space GS.

[0161] Because of exposure to the gap space GS, the side surfaces of the charge trap pattern 232 and the dummy trap pattern 252, the side surface of the additional channel pattern 210, and the surface of the insulating intermediate layer pattern 112 can be covered with the second barrier layer 301a. In addition, the second upper insulating pattern 260 and the substrate 100 exposed to the block separation trench ST can be covered with the second barrier layer 301a. The conductive layer 300a can be introduced or filled into the remaining portion of the gap space GS defined by the second barrier layer 301a. Although not shown in the drawing, the conductive layer 300a can further include a gate barrier layer on the second barrier layer 301a.

[0162] For example, the second barrier layer 301a can include a metal oxide, and the conductive layer 300a can include a low-resistance metal. Examples of the metal oxide can include aluminum oxide, hafnium oxide, lanthanum oxide, lanthanum aluminum oxide, lanthanum hafnium oxide, hafnium aluminum oxide, titanium oxide, tantalum oxide, zirconium oxide, etc. Examples of the low-resistance metal can include tungsten (W), titanium (Ti), tantalum (Ta), platinum (Pt), etc. These low-resistance metals can be used alone or in combination thereof.

[0163] In particular, because the block separation trench ST can be in communication with the trap void T0, the trap void T0 can also be filled with the second barrier layer 301a. Accordingly, the dummy trap pattern 252 can change to a barrier trap structure 255 including a tunnel insulating pattern T1, the second barrier layer 301a, and a first barrier pattern T3. Accordingly, the dummy trap pattern 252, which can be formed as a triple pattern structure of oxide-nitride-oxide, can change to the barrier trap structure 255, which can be formed as a triple pattern structure of oxide.

[0164] Because the first cut surface Sl and the second cut surface S2 can be substantially uniform in the first direction x, the second barrier layer 301a and the conductive layer 300a can be uniformly formed on the first cut surface Sl and the second cut surface S2, which can serve as sidewalls of the block separation trench ST.

[0165] Referring to Figures 16A-16C The conductive layer 300a can be partially removed from the block separation trench ST and can remain only in the gap space GS, thereby forming a plurality of electrode patterns 300 in the gap space GS. The stack pattern SP can be provided as a stack structure SS.

[0166] For example, the conductive layer 300a can be removed from the block separation trench ST by a wet etching process, and can be separated in units of the gap space GS such that the conductive layer 300a can remain only in the gap space GS between adjacent insulating intermediate layer patterns 112. The conductive layer 300a separated in each gap space GS can be surrounded by the insulating intermediate layer pattern 112 and electrically separated from each other such that the conductive layer 300a in each gap space GS can be provided as an electrode pattern 300. Each electrode pattern 300 can function as a separate gate electrode of the vertical memory device 500. In this case, each electrode pattern 300 can be recessed from the second cross-sectional surface S2, thereby substantially preventing or reducing a bridging defect between vertically adjacent electrode patterns 300.

[0167] For example, the electrode pattern 300 can be shaped as a plate parallel to the substrate 100, and a plurality of electrode patterns 300 can be positioned alternately with a plurality of insulating intermediate layer patterns 112. The electrode pattern 300 can include a third cross-sectional surface S3 facing the block separation trench ST, and a side surface of the electrode pattern 300 opposite the third cross-sectional surface S3 can be in contact with the second barrier layer 301a. The plurality of electrode patterns 300 in the stack structure SS can be separated from each other in the third direction z by the block separation trench ST, and can function as a gate electrode group of the memory block B.

[0168] The electrode pattern 300 can include a first gate line 310, a second gate line 320, and a third gate line 330 which can be sequentially stacked in the first direction x. The first gate line 310 can be provided as a ground select line (GSL), the second gate line 320 can be provided as a word line (WL) of the vertical memory device 500. The third gate line 330 can be provided as a string select line (SSL) of the vertical memory device 500.

[0169] In some embodiments, the second gate line 320 can include first to eighth word lines 321 to 328, and the third gate line 330 can include a lower string select line 331 and an upper string select line 332.

[0170] In particular, due to the enlarged space ES, some of the electrode patterns 300 surrounding the dummy channel structure 250 in a top view can have a relatively large thickness such that the electrode pattern 300 can include an extension portion 300u at an upper portion UA of the stack structure SS in the boundary area BA. Most of the electrode patterns 300 can have a first thickness t1 in the stack structure SS, and the extension portion 300u can have a second thickness t2 greater than the first thickness t1 around the dummy channel structure 250 in the boundary area BA.

[0171] Accordingly, the channel structure 230 can penetrate the electrode pattern 300 at the upper portion UA and the lower portion LA of the stack structure SS, and the dummy channel structure 250 can penetrate the extended portion 300u of the electrode pattern 300 at the upper portion UA of the stack structure SS.

[0172] For example, the extended portion 300u of the electrode pattern 300 can include a plurality of side extended portions 300u1 adjacent to one side of the dummy channel structure 250 and spaced apart from each other by the same gap distance in the first direction x, and a bottom extended portion 300u2 adjacent to a bottom of the dummy channel structure 250. The bottom extended portion 300u2 can include a recess corresponding to the recess of the remaining bottom pattern 144a, i.e., a dummy bottom recess DBR.

[0173] The memory cells MC can be arranged at points at which the electrode pattern 300 can be adjacent to the channel structure 230, such that a plurality of memory cells MC can be arranged along the channel structure 230 extending in the first direction x, and the electrode pattern 300 can be respectively provided as the first, second, and third gate lines 310, 320, and 330 in the memory block B.

[0174] Referring to Figures 17A-17C The trench spacers TS can be formed at the sidewalls of the block separation trenches ST, and impurities can be injected into the substrate 100 by using the trench spacers TS as a doping mask. Accordingly, the doped layer 101 can be formed at the surface portion of the substrate 100 in the block separation trenches ST.

[0175] For example, a trench spacer layer (not shown) can be formed on the second blocking layer 301a in such a way that the sidewalls and the bottom of the block separation trenches ST are covered with the trench spacer layer. Then, the trench spacer layer can be partially removed from the second blocking layer 301a by an anisotropic etching process. Accordingly, the trench spacer layer can be left only on the sidewalls of the block separation trenches ST, and the second blocking layer 301a on the substrate 100 can be exposed in the block separation trenches ST, thereby forming the trench spacers TS covering the sidewalls of the block separation trenches ST.

[0176] The trench spacers TS can be shaped as lines extending in the second direction y, and the electrode pattern 300 can be covered with or overlapped with the trench spacers TS. Accordingly, the electrode pattern 300 can be separated and insulated from the surrounding environment, and the block separation trenches ST can be changed to reduced trenches RT whose width can be reduced by the trench spacers TS.

[0177] For example, the trench spacers TS can include at least one of an oxide, a nitride, an oxynitride, and any combination thereof.

[0178] Then, impurities can be implanted into the substrate 100 exposed by the reduced trenches RT by using the trench spacers TS as an ion implantation mask. Then, a doped layer 101 can be formed at the surface portion of the substrate 100 and extend into the substrate 100. For example, the impurities can include n-type dopants such as phosphorus and arsenic.

[0179] Referring to Figures 18A-18C , the reduced trenches RT can be filled with a conductive material, thereby forming a block separation line 350 in the reduced trenches RT in contact with the doped layer 101. The block separation line 350 can be used as a common source line of the vertical memory device 500.

[0180] For example, a block separation layer (not shown) can be formed on the second barrier layer 301a to a sufficient thickness to fill the reduced trenches RT. The block separation layer can include a conductive material such as a low-resistance metal, a nitride of a low-resistance metal, an oxide of a low-resistance metal, and / or a silicide of a low-resistance metal.

[0181] Then, the block separation layer can be planarized by a planarization process until an upper surface of the second upper insulating pattern 260 can be exposed, thereby forming the block separation line 350 filled in the reduced trenches RT and extending in the second direction y.

[0182] In particular, the second barrier layer 301a can also be removed from the second upper insulating pattern 260 in the planarization process, so that the second barrier layer 301a can be changed to a second barrier pattern 301 that surrounds the electrode pattern 300 in the gap space GS and is in contact with the trench spacer TS in a top view.

[0183] In particular, the barrier trap structure 255 including the second barrier layer 301a can also be changed to a barrier trap pattern 257 including the second barrier pattern 301. Accordingly, the barrier trap pattern 257 can include the tunnel insulating pattern Tl, the second barrier pattern 301, and the first barrier pattern T3. Accordingly, the dummy channel structure 250 can include the barrier trap pattern 257, the dummy channel 254, and the second fill pillar 256.

[0184] Referring to Figures 19A-19B , a third upper insulating pattern 360, a fourth upper insulating pattern 460, and a wiring structure 400 can be formed.

[0185] For example, a third upper insulating layer (not shown) can be formed on the second upper insulating pattern 260 and the block separation line 350, and then the third upper insulating layer and the second upper insulating pattern 260 can be patterned to have openings through which the cap pattern 240 is exposed. The patterned third upper insulating layer can be provided as the third upper insulating pattern 360. Then, a contact plug 410 can be formed in the openings and can be in contact with the cap pattern 240.

[0186] A fourth upper insulating layer (not shown) can be formed on the third upper insulating pattern 360 and the contact plug 410, and can be patterned into a fourth upper insulating pattern 460. The fourth upper insulating pattern 460 can include linear wiring trenches extending in the third direction z and exposing the contact plug 410. A plurality of wiring trenches can be arranged in the second direction y at the same gap distance.

[0187] Thereafter, a conductive material can be filled into the wiring trenches, and a plurality of wirings 490 can be formed in the wiring trenches. Accordingly, the wirings 490 can extend in the third direction z, and the plurality of wirings 490 can be spaced apart by the same gap distance in the second direction y. The wirings 490 can be in contact with the contact plug 410.

[0188] Accordingly, the wirings 490 separated from each other by the fourth upper insulating pattern 460 and the contact plug 410 in contact with the cap pattern 240 can be provided as a wiring structure 400. In some embodiments, the wirings 490 can include bit lines for detecting a signal from a selected memory string in the vertical memory device 500.

[0189] Thereafter, a plurality of metal structures (not shown) and a plurality of contact pads (not shown) in contact with the metal structures can be formed on the fourth upper insulating pattern 460. A passivation layer (not shown) can be formed for covering the metal structures and the contact pads, thereby fabricating the vertical memory device 500.

[0190] According to example embodiments of the inventive concept, there can be no residual trenches left on the substrate at the lower portion of the block separation trench, and thus, although dummy holes can be formed continuously with the trench holes in the same hole etching process, a bridging defect can be substantially prevented.

[0191] The block separation trench ST can be formed by the sequential etching steps of the first trench etching process on the upper portion UA' of the mold stack structure SS' and the second trench etching process on the lower portion LA' of the mold stack structure SS'. Accordingly, the block separation trench ST can be formed in a sufficiently small aspect ratio, and the sidewalls of the block separation trench ST can be sufficiently uniform in the first direction x, thereby obtaining a uniform vertical profile of the block separation trench ST in the first direction x despite a high number of stacks of the electrode pattern 300.

[0192] Further, the dummy channel structures 250 can be formed only at the upper portion UA of the stack structure SS at a dummy gap distance from the substrate, so there can be no residual channel left on the substrate 100 at the lower portion of the block separation trench ST. Thus, due to the uniform vertical profile of the block separation trench and the dummy channel structures 250 spaced apart from the substrate 100, bridging defects between adjacent gate lines at the lower portion of the block separation trench ST can be substantially prevented.

[0193] The foregoing is a detailed description of example implementations, and is not to be interpreted as limiting. While some example implementations have been described above, it will be appreciated that many modifications can be made of the example implementations without departing from the novel teachings and advantages of the present disclosure. Accordingly, all such modifications are intended to be included within the scope of the present disclosure as defined in the claims. In the claims, means-plus-function clauses are intended to cover the structures described herein as performing the recited functions and not only structural equivalents but also equivalent structures. Accordingly, it will be appreciated that the foregoing is a description of various example implementations, and is not intended to be limited to the specific example implementations disclosed. Modifications to the disclosed example implementations, and other example implementations, are intended to be within the scope of the claims. The description is intended to cover all alternatives, modifications, and equivalents of the methods and compositions disclosed herein, including those that are currently or later become known or desired to be protected by copyright.

[0194] This application claims priority to Korean Patent Application No. 10-2019-0089420, filed on July 24, 2019, in the Korean Intellectual Property Office, the contents of which are incorporated herein in its entirety by reference.

Claims

1. A vertical memory device, comprising: a substrate including a cell block region, a block separation region, and a boundary region between the cell block region and the block separation region; a plurality of stack structures in the cell block region and the boundary region, wherein the plurality of stack structures are stacked in a first direction substantially perpendicular to the substrate, such that insulating intermediate layer patterns and electrode patterns are alternately stacked on the substrate, and wherein the stack structures are spaced apart from each other in a third direction substantially perpendicular to the first direction by the block separation region; a plurality of channel structures extending through respective ones of the stack structures in the cell block region to the substrate, such that the plurality of channel structures traverse the electrode patterns and the insulating intermediate layer patterns in the first direction; a plurality of dummy channel structures extending through upper portions of respective ones of the stack structures in the boundary region, such that the plurality of dummy channel structures traverse the electrode patterns and the insulating intermediate layer patterns in the first direction and are connected to a dummy bottom electrode pattern, the dummy bottom electrode pattern including one of the electrode patterns spaced apart from the substrate; and a second blocking pattern adjacent to the dummy channel structures and the insulating intermediate layer patterns, wherein a dummy channel structure of the plurality of dummy channel structures includes a first surface at an upper portion of the stack structure, the first surface facing a space on the block separation region, wherein the first surface is substantially perpendicular to the substrate, wherein an insulating intermediate layer pattern of the insulating intermediate layer patterns includes a second surface at a lower portion of the stack structure, wherein the first surface and the second surface are co-planar in the first direction, and wherein the first surface and the second surface overlap the second blocking pattern along the third direction.

2. The vertical memory device of claim 1, wherein the dummy channel structure includes: a blocking trap pattern on an inner surface of a dummy hole extending through the upper portion of the stack structure in the first direction, wherein the blocking trap pattern is adjacent to the electrode patterns and the insulating intermediate layer patterns; a dummy channel on side surfaces of the blocking trap pattern and on the dummy bottom electrode pattern; and a second fill pillar filling the dummy hole on the dummy channel, and wherein the channel structure includes: a charge trap pattern on an inner surface of a channel hole extending through the stack structure in the first direction, wherein the charge trap pattern is adjacent to the electrode patterns and the insulating intermediate layer patterns; a channel in a cylindrical shape and extending in the first direction, and on side surfaces of the charge trap pattern and on a bottom of the channel hole; and a first fill pillar filling the channel hole on the channel.

3. The vertical memory device of claim 2, wherein the blocking trap pattern includes a first triple pattern structure in which a tunnel insulating pattern, the second blocking pattern, and a first blocking pattern are sequentially stacked from the dummy channel, and wherein the dummy channel structure includes a second triple pattern structure in which a second tunnel insulating pattern, the first blocking pattern, and a second blocking pattern are sequentially stacked from the channel. ​ wherein at least one of the tunnel insulating pattern, the second blocking pattern, and the first blocking pattern includes an oxide.

4. The vertical memory device of claim 3, wherein the charge trapping pattern includes a second triple pattern structure in which the tunnel insulating pattern, a charge storage pattern including a nitride, and the first blocking pattern are sequentially stacked from the channel.

5. The vertical memory device of claim 1, wherein each of the electrode patterns in the upper portion of the stack structure includes a plurality of extended portions adjacent to a respective one of a plurality of dummy channel structures in the boundary region, such that the respective extended portion has a first thickness in the first direction that is greater than a second thickness of a remaining portion of the electrode pattern.

6. The vertical memory device of claim 5, wherein the plurality of extended portions include: a plurality of side extended portions adjacent to a side of the dummy channel structure and spaced apart from each other in the first direction; and a bottom extended portion adjacent to a bottom of the dummy channel structure.

7. The vertical memory device of claim 1, wherein the dummy channel structures are arranged in the stack structure of the boundary region in a second direction substantially perpendicular to the first direction and the third direction, and are spaced apart from each other.

8. The vertical memory device of claim 1, wherein the dummy bottom electrode pattern is spaced apart from the substrate by a dummy gap distance d, such that d = (k) * H, where k is in a range of 0.5-0.7, where d is the dummy gap distance from the substrate, and where H is a height of the stack structure on the substrate.

9. A vertical memory device, comprising: a substrate including a cell block region, a block separation region, and a boundary region between the cell block region and the block separation region; a plurality of stack structures in the cell block region and the boundary region, wherein the plurality of stack structures are stacked in a first direction substantially perpendicular to the substrate, such that insulating intermediate layer patterns are alternately stacked with electrode patterns on the substrate, and wherein the stack structures are spaced apart from each other in a third direction substantially perpendicular to the first direction by the block separation region; a plurality of channel structures in the cell block region extending through respective ones of the stack structures to the substrate, such that the plurality of channel structures traverse the electrode patterns and the insulating intermediate layer patterns in the first direction; a plurality of block separation structures on the substrate in the block separation region between adjacent ones of the plurality of stack structures to separate the stack structures in the third direction substantially perpendicular to the first direction by a storage block. ​ a plurality of dummy channel structures extending through upper portions of respective ones of the stack structures in the boundary region, such that each of the plurality of dummy channel structures traverses the electrode pattern and the insulating interlayer pattern and is connected to a dummy bottom electrode pattern, the dummy bottom electrode pattern being one of the electrode patterns spaced apart from the substrate; and a second barrier pattern adjacent to the dummy channel structures and the insulating interlayer pattern, wherein the dummy channel structures include first surfaces adjacent to block separation structures of the plurality of block separation structures at the upper portions of the stack structures, wherein insulating interlayer patterns of the insulating interlayer pattern include second surfaces adjacent to the block separation structures at lower portions of the stack structures, such that the first surfaces and the second surfaces are coplanar in the first direction, wherein the second barrier pattern is between a plurality of first surfaces including the first surfaces and the block separation structures, and wherein the second barrier pattern is between a plurality of second surfaces including the second surfaces and the block separation structures.

10. The vertical memory device of claim 9, wherein the channel structure includes a charge-trap pattern on an inner surface of a channel hole extending through the stack structures in the first direction, wherein the charge-trap pattern is adjacent to the electrode pattern to selectively trap charge, and wherein the dummy channel structure includes a barrier-trap pattern on an inner surface of a dummy hole extending through the upper portions of the stack structures in the first direction and adjacent to the electrode pattern in the boundary region.

11. The vertical memory device of claim 10, wherein the charge-trap pattern includes a first triple pattern structure including a first barrier pattern including a first oxide, a charge storage pattern including a nitride, and a tunnel insulating pattern including a second oxide, stacked in that order from the inner surface of the channel hole, and wherein the barrier-trap pattern includes a second triple pattern structure including the first barrier pattern, the second barrier pattern including an oxide, and the tunnel insulating pattern, stacked in that order from the inner surface of the dummy hole.

12. The vertical memory device of claim 9, wherein each of the electrode patterns in the upper portions of the stack structures includes a plurality of extension portions adjacent to respective ones of the dummy channel structures at the boundary region, such that the respective extension portions have a first thickness greater than a second thickness of remaining portions of the electrode patterns.

13. The vertical memory device of claim 12, wherein the plurality of extension portions includes: a plurality of side extension portions adjacent to sides of the dummy channel structure and spaced apart from each other in the first direction; and a bottom extension portion adjacent to the dummy bottom electrode pattern.

14. The vertical memory device of claim 9, wherein the block separation structures include: ​ trench spacers on sidewalls of the stack structures, the trench spacers extending in the first direction and in the block separation region, wherein the substrate is exposed to a block separation trench defined by a pair of the trench spacers between the pair of the trench spacers, wherein the electrode pattern, the insulating intermediate layer pattern, and the plurality of dummy channel structures are adjacent to at least one of the trench spacers; a doped layer extending from a surface of the substrate into the substrate, wherein the doped layer is exposed to the block separation trench between the pair of the trench spacers in the block separation region; and a block separation line comprising an electrically conductive material in the block separation trench such that the block separation line is in contact with the doped layer and extends in the first direction.

15. A vertical memory device, comprising: a substrate; a plurality of stack structures stacked in a first direction substantially perpendicular to the substrate such that an insulating intermediate layer pattern is alternately stacked with an electrode pattern on the substrate, wherein the stack structures are spaced apart from each other by a block separation region; a plurality of channel structures extending through respective ones of the stack structures such that the plurality of channel structures penetrate the electrode pattern and the insulating intermediate layer pattern; and a plurality of dummy channel structures extending through an upper portion of respective ones of the stack structures and through some of the electrode pattern and some of the insulating intermediate layer pattern, wherein an electrode pattern of the electrode pattern in the upper portion of the stack structures comprises an extension portion adjacent to a dummy channel structure of the plurality of dummy channel structures, and wherein the extension portion has a first thickness that is greater than a second thickness of a remaining portion of the electrode pattern.

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