Semiconductor device and manufacturing method

Abstract

The present disclosure relates to semiconductor devices and manufacturing methods. A semiconductor device having multiple silicide regions is provided. In an embodiment, a first silicide precursor and a second silicide precursor are deposited on a source / drain region. A first silicide having a first phase is formed, and the second silicide precursor is insoluble in the first phase of the first silicide. The first phase of the first silicide is modified to a second phase of the first silicide, and the second silicide precursor is soluble in the second phase of the first silicide. A second silicide is formed using the second silicide precursor and the second phase of the first silicide.

Description

Technical Field

[0001] The present disclosure relates to semiconductor devices and methods of manufacturing. Background Art

[0002] Semiconductor devices are used in a variety of electronic applications, such as personal computers, cellular phones, digital cameras, and other electronic devices. Semiconductor devices are typically manufactured by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductor material layers over a semiconductor substrate, and patterning the various material layers using photolithography to form circuit components and elements thereon.

[0003] The semiconductor industry continues to improve the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by continuously reducing the minimum feature size, which allows more components to be integrated into a given area. However, as the minimum feature size decreases, other problems arise that should be addressed. Summary of the Invention

[0004] According to one embodiment of the present disclosure, a method for manufacturing a semiconductor device is provided, the method comprising: depositing a first silicide precursor and a second silicide precursor on a source / drain region, wherein the deposition also forms a metal-rich silicide having a metal-rich phase, and the second silicide precursor is insoluble in the metal-rich phase of the metal-rich silicide; changing the metal-rich phase of the metal-rich silicide into a semiconductor-rich phase by thermal annealing, the second silicide precursor being soluble in the semiconductor-rich phase due to the additional semiconductor material formed in the silicide; and forming a second silicide using the second silicide precursor and the semiconductor-rich phase.

[0005] According to another embodiment of the present disclosure, a method for manufacturing a semiconductor device is provided, the method comprising: forming a first source / drain region adjacent to a first gate stack; forming a second source / drain region adjacent to a second gate stack; depositing a first material layer on both the first source / drain region and the second source / drain region, the first material layer comprising a first silicide precursor and a second silicide precursor; forming a first silicide on both the first source / drain region and the second source / drain region, wherein the first silicide is metal-rich, and wherein the first silicide is formed using the first silicide precursor but not the second silicide precursor, and the first silicide has a first phase; removing the first silicide precursor and the second silicide precursor from the first source / drain region without removing the second silicide precursor from the second source / drain region; and changing the first phase of the first silicide to the second phase of the first silicide.

[0006] According to another embodiment of the present disclosure, a semiconductor device is provided, including: a first source / drain region, the first source / drain region being separated from a second source / drain region; a first silicide, the first silicide being located on the first source / drain region, the first silicide including a first group of elements; and a second silicide being located on the second source / drain region, the second silicide including the first group of elements and a first element, wherein the first element is insoluble in a first phase of the silicide including the first group of elements, and the first element is soluble in a second phase of the silicide including the first group of elements. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Various aspects of the present disclosure may be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industry practice, various features are not drawn to scale. In fact, the dimensions of various features may be arbitrarily increased or decreased for clarity of discussion.

[0008] Figure 1 An example of a FinFET in a three-dimensional view is shown in accordance with some embodiments.

[0009] Figure 2 、 Figure 3 、 Figure 4 、 Figure 5 、 Figure 6 、 Figure 7 、 Figure 8A 、 Figure 8B 、 Figure 9A 、 Figure 9B 、 Figure 10A 、 Figure 10B 、 Figure 10C 、 Figure 11A 、 Figure 11B 、 Figure 11C 、 Figure 12A 、 Figure 12B 、 Figure 13A 、 Figure 13B 、 Figure 14A 、 Figure 14B 、 Figure 14C 、 Figure 15A 、 Figure 15B 、 Figure 16A ,and Figure 16B is a cross-sectional view of an intermediate stage in FinFET fabrication according to some embodiments.

[0010] Figures 17A-17C Deposition of a first bi-material silicide precursor layer is shown in accordance with some embodiments.

[0011] Figure 18 Partial removal of the first bi-material silicide precursor layer is shown in accordance with some embodiments.

[0012] Figure 19A and Figure 19B An annealing process according to some embodiments is shown.

[0013] Figure 20 Deposition of a glue layer is shown according to some embodiments.

[0014] Figure 21 The formation of contacts according to some embodiments is shown. DETAILED DESCRIPTION

[0015] The following disclosure provides many different embodiments or examples for implementing the different features of the present invention. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first feature above or on a second feature may include an embodiment in which the first feature and the second feature are formed in direct contact, and may also include an embodiment in which an additional feature may be formed between the first feature and the second feature so that the first feature and the second feature may not be in direct contact. In addition, the present disclosure may repeat reference numerals and / or letters in various examples. This repetition is for the purpose of simplicity and clarity and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0016] Furthermore, spatially relative terms (e.g., "below," "beneath," "below," "above," "upper," etc.) may be used herein to facilitate describing the relationship of one element or feature relative to another element or feature(s) illustrated in the figures. These spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein should be interpreted accordingly.

[0017] Embodiments will now be described with respect to specific embodiments in which separate silicide regions are formed using a single process. However, the embodiments described herein are intended to be illustrative in nature and are not intended to be limiting to those descriptions found herein.

[0018] Figure 1An example of a FinFET in a three-dimensional view according to some embodiments is shown. The FinFET includes a fin 52 located on a substrate 50 (e.g., a semiconductor substrate). Isolation regions 56 are provided in the substrate 50, and the fins 52 protrude above and between adjacent isolation regions 56. Although the isolation regions 56 are described / illustrated as being separate from the substrate 50, as used herein, the term "substrate" may be used to refer only to the semiconductor substrate or the semiconductor substrate including the isolation regions. In addition, although the fin 52 is shown as a single continuous material as the substrate 50, the fin 52 and / or the substrate 50 may include a single material or multiple materials. In this case, the fin 52 refers to the portion extending between adjacent isolation regions 56.

[0019] Gate dielectric layer 92 is located along the sidewalls of fin 52 and over the top surface of fin 52, and gate electrode 94 is located over gate dielectric layer 92. Source / drain regions 82 are disposed on opposite sides of fin 52 relative to gate dielectric layer 92 and gate electrode 94. Figure 1 Reference cross sections used in subsequent figures are further illustrated. Cross section AA is along the longitudinal axis of gate electrode 94 and is oriented perpendicularly to, for example, the direction of current flow between the source / drain regions 82 of the FinFET. Cross section BB is perpendicular to cross section AA and is along the longitudinal axis of fin 52 and is oriented perpendicularly to, for example, the direction of current flow between the source / drain regions 82 of the FinFET. Cross section CC is parallel to cross section AA and extends through the source / drain regions of the FinFET. For clarity, subsequent figures refer to these reference cross sections.

[0020] Some embodiments discussed herein are discussed in the context of FinFETs formed using a gate-last process. In other embodiments, a gate-first process may be used. Similarly, some embodiments contemplate aspects for use in planar devices (e.g., planar FETs).

[0021] Figures 2 to 16B is a cross-sectional view of an intermediate stage in FinFET fabrication according to some embodiments. Figures 2 to 7 Shown Figure 1 Reference cross-section AA shown in , except for multiple fins / FinFETs. Figure 8A 、 Figure 9A 、 Figure 10A 、 Figure 11A 、 Figure 12A 、 Figure 13A 、 Figure 14A 、 Figure 15A 、 Figure 16A and Figure 17A It is along Figure 1The reference cross section AA shown in FIG is illustrated, and Figure 8B 、 Figure 9B 、 Figure 10B 、 Figure 11B 、 Figure 12B 、 Figure 13B 、 Figure 14B 、 Figure 14C 、 Figure 15B 、 Figure 16B and Figure 17B It is along Figure 1 A similar cross section BB as shown in FIG is illustrated, except for multiple fins / FinFETs. Figure 10C It is along Figure 1 The reference cross section CC shown in FIG.

[0022] exist Figure 2 In the embodiment, a substrate 50 is provided. The substrate 50 may be a semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, etc., which may be doped (e.g., with p-type or n-type dopants) or undoped. The substrate 50 may be a wafer, such as a silicon wafer. Typically, an SOI substrate is a layer of semiconductor material formed on an insulator layer. The insulator layer may be, for example, a buried oxide (BOX) layer, a silicon oxide layer, etc. The insulator layer is disposed on a substrate, which is typically a silicon or glass substrate. Other substrates may also be used, such as multilayer or gradient substrates. In some embodiments, the semiconductor material of the substrate 50 may include: silicon; germanium; compound semiconductors including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors including silicon-germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide, and / or gallium indium arsenide; or combinations thereof.

[0023] Substrate 50 has region 50N and region 50P. Region 50N can be used to form an n-type device, such as an NMOS transistor, such as an n-type FinFET. Region 50P can be used to form a p-type device, such as a PMOS transistor, such as a p-type FinFET. Region 50N can be physically separated from region 50P (as shown by separator 51), and any number of device features (e.g., other active devices, doped regions, isolation structures, etc.) can be disposed between region 50N and region 50P.

[0024] exist Figure 3 In the embodiment of the present invention, fins 52 are formed in substrate 50. Fins 52 are semiconductor strips. In some embodiments, fins 52 can be formed in substrate 50 by etching trenches in substrate 50. The etching process can be any acceptable etching process, such as reactive ion etching (RIE), neutral beam etching (NBE), etc., or a combination thereof. The etching process can be anisotropic.

[0025] The fins may be patterned by any suitable method. For example, the fins may be patterned using one or more photolithographic processes, including double patterning or multi-patterning processes. Typically, double patterning or multi-patterning processes combine photolithography and self-alignment processes, allowing for the creation of patterns having, for example, a smaller pitch than that obtainable using a single direct photolithographic process. For example, in one embodiment, a sacrificial layer is formed over the substrate and patterned using a photolithographic process. Spacers are formed next to the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers may then be used to pattern the fins. In some embodiments, the mask (or other layer) may remain on the fin 52.

[0026] exist Figure 4 In the embodiment shown, an insulating material 54 is formed above the substrate 50 and between adjacent fins 52. The insulating material 54 can be an oxide, such as silicon oxide, nitride, etc., or a combination thereof, and can be formed by high-density plasma chemical vapor deposition (HDP-CVD), flowable CVD (FCVD) (for example, CVD-based material deposition in a remote plasma system and post-curing to convert it into another material, such as an oxide), etc., or a combination thereof. Other insulating materials formed by any acceptable process can be used. In the embodiment shown, the insulating material 54 is silicon oxide formed by an FCVD process. Once the insulating material is formed, an annealing process can be performed. In an embodiment, the insulating material 54 is formed so that excess insulating material 54 covers the fins 52. Although the insulating material 54 is shown as a single layer, some embodiments may use multiple layers. For example, in some embodiments, a liner (not shown) can first be formed along the surface of the substrate 50 and the fins 52. Thereafter, a filler material such as the one discussed above can be formed over the liner.

[0027] exist Figure 5 In the embodiment of the present invention, a removal process is applied to the insulating material 54 to remove excess insulating material 54 above the fin 52. In some embodiments, a planarization process may be used, such as chemical mechanical polishing (CMP), an etch-back process, a combination thereof, etc. The planarization process exposes the fin 52 so that after the planarization process is completed, the top surfaces of the fin 52 and the insulating material 54 are level. In embodiments in which a mask remains on the fin 52, the planarization process may expose the mask or remove the mask so that after the planarization process is completed, the top surfaces of the mask or the fin 52, respectively, are level with the insulating material 54.

[0028] exist Figure 650N and 50P protrude from between adjacent STI regions 56. Insulating material 54 is recessed to form shallow trench isolation (STI) regions 56. Insulating material 54 is recessed so that the upper portions of fins 52 in regions 50N and 50P protrude from between adjacent STI regions 56. In addition, the top surface of STI regions 56 can have a flat surface as shown, a convex surface, a concave surface (e.g., a groove), or a combination thereof. By appropriate etching, the top surface of STI regions 56 can be formed to be flat, convex and / or concave. STI regions 56 can be recessed using an acceptable etching process, for example, an etching process that is selective to the material of insulating material 54 (e.g., etches the material of insulating material 54 at a faster rate than the material of fin 52). For example, oxide removal using an acid such as diluted hydrofluoric acid (dHF) can be used.

[0029] about Figures 2 to 6 The process described is only one example of how the fin 52 may be formed. In some embodiments, the fin may be formed by an epitaxial growth process. For example, a dielectric layer may be formed over the top surface of the substrate 50, and a trench may be etched through the dielectric layer to expose the substrate 50 below. A homoepitaxial structure may be epitaxially grown in the trench, and the dielectric layer may be recessed so that the homoepitaxial structure protrudes from the dielectric layer to form the fin. Additionally, in some embodiments, a heteroepitaxial structure may be used for the fin 52. For example, Figure 5 The fin 52 in the substrate 50 can be recessed, and a material different from the fin 52 can be epitaxially grown over the recessed fin 52. In such an embodiment, the fin 52 includes a recessed material, and an epitaxially grown material disposed over the recessed material. In a further embodiment, a dielectric layer can be formed over the top surface of the substrate 50, and a trench can be etched through the dielectric layer. A heteroepitaxial structure can then be epitaxially grown in the trench using a material different from that of the substrate 50, and the dielectric layer can be recessed so that the heteroepitaxial structure protrudes from the dielectric layer to form the fin 52. In some embodiments, a homoepitaxial structure or a heteroepitaxial structure is epitaxially grown. The epitaxially grown material can be doped in situ during growth, which can avoid previous and subsequent implantations, but in-situ doping and implantation doping can be used together.

[0030] Furthermore, it may be advantageous to epitaxially grow a different material in region 50N (eg, NMOS region) than in region 50P (eg, PMOS region). In various embodiments, the upper portion of fin 52 may be made of silicon germanium (SiGe). x Ge 1-x, where x can be in the range of 0 to 1), silicon carbide, pure or substantially pure germanium, III-V compound semiconductors, II-VI compound semiconductors, etc. For example, available materials for forming III-V compound semiconductors include, but are not limited to, indium arsenide, aluminum arsenide, gallium arsenide, indium phosphide, gallium nitride, indium gallium arsenide, aluminum indium arsenide, gallium antimonide, aluminum antimonide, aluminum phosphide, gallium phosphide, etc.

[0031] In addition, Figure 6 In the embodiment of the present invention, appropriate wells (not shown) may be formed in the fin 52 and / or the substrate 50. In some embodiments, a P-well may be formed in the region 50N, and an N-well may be formed in the region 50P. In some embodiments, either a P-well or an N-well may be formed in both the region 50N and the region 50P.

[0032] In embodiments with different well types, a photoresist or other mask (not shown) may be used to implement different implantation steps for regions 50N and 50P. For example, a photoresist may be formed over the fins 52 and STI regions 56 in region 50N. The photoresist is patterned to expose regions 50P of substrate 50, e.g., the PMOS region. The photoresist may be formed using a spin coating technique and may be patterned using acceptable photolithography techniques. Once the photoresist is patterned, an n-type impurity implantation is performed in region 50P and the photoresist may be used as a mask to substantially prevent n-type impurities from being implanted into region 50N, e.g., the NMOS region. The n-type impurity may be an NMOS region at a density equal to or less than 10 nm. 18 cm -3 (For example, at about 10 16 cm -3 and about 10 18 cm -3 Phosphorus, arsenic, antimony, etc. are implanted into the region at a concentration between 0.01 and 0.11. After implantation, the photoresist is removed, for example, by an acceptable ashing process.

[0033] After implanting region 50P, a photoresist is formed over fin 52 and STI region 56 in region 50P. The photoresist is patterned to expose region 50N of substrate 50, e.g., an NMOS region. The photoresist may be formed using a spin coating technique and may be patterned using an acceptable photolithography technique. Once the photoresist is patterned, a p-type impurity implant is performed in region 50N, and the photoresist may be used as a mask to substantially prevent the p-type impurity from being implanted into region 50P, e.g., a PMOS region. The p-type impurity may be a density equal to or less than 10 18 cm -3 (For example, at about 10 16 cm -3 and about 1018 cm -3 Boron, boron fluoride, indium, etc. are implanted into the region at a concentration between 0.01 and 0.11. After implantation, the photoresist is removed, for example, by an acceptable ashing process.

[0034] After implantation of regions 50N and 50P, annealing may be performed to repair implantation damage and activate the implanted p-type and / or n-type impurities. In some embodiments, the grown material of the epitaxial fins may be in-situ doped during growth, which may avoid implantation, but both in-situ and implantation doping may be used together.

[0035] exist Figure 7 In the embodiment of the present invention, a dummy dielectric layer 60 is formed on the fin 52. The dummy dielectric layer 60 can be, for example, silicon oxide, silicon nitride, a combination thereof, etc., and can be deposited or thermally grown according to an acceptable technique. A dummy gate layer 62 is formed above the dummy dielectric layer 60, and a mask layer 64 is formed above the dummy gate layer 62. The dummy gate layer 62 can be deposited on the dummy dielectric layer 60 and then planarized, for example by CMP. The mask layer 64 can be deposited above the dummy gate layer 62. The dummy gate layer 62 can be a conductive or non-conductive material and can be selected from a group including amorphous silicon, polysilicon, polycrystalline silicon germanium (poly-SiGe), metal nitride, metal silicide, metal oxide, and metal. The dummy gate layer 62 can be deposited by physical vapor deposition (PVD), CVD, sputtering deposition, or other techniques known in the art and used to deposit the selected material. The dummy gate layer 62 can be made of other materials with high etch selectivity from etching of the isolation region. Mask layer 64 may include, for example, silicon nitride, silicon oxynitride, or the like. In this example, a single dummy gate layer 62 and a single mask layer 64 are formed across region 50N and region 50P. Note that for illustrative purposes only, dummy dielectric layer 60 is shown covering only fin 52. In some embodiments, dummy dielectric layer 60 may be deposited such that dummy dielectric layer 60 covers STI region 56, extending between dummy gate layer 62 and STI region 56.

[0036] 8A to 16B Various additional steps in the fabrication of example devices are shown. 8A to 16B The features of either region 50N or region 50P are shown. For example, 8A to 16B The structure shown in FIG5 is applicable to both region 50N and region 50P. The differences, if any, in the structure of region 50N and region 50P are described in the text associated with each figure.

[0037] exist Figure 8A and Figure 8B In the embodiment, the mask layer 64 (see Figure 7) is patterned to form a mask 74. The pattern of the mask 74 can then be transferred to the dummy gate layer 62. In some embodiments (not shown), the pattern of the mask 74 can also be transferred to the dummy dielectric layer 60 using an acceptable etching technique to form a dummy gate 72. The dummy gate 72 covers the corresponding channel region 58 of the fin 52. The pattern of the mask 74 can be used to physically separate each dummy gate 72 from the adjacent dummy gate. The dummy gate 72 can also have a length direction that is substantially perpendicular to the length direction of the corresponding epitaxial fin 52.

[0038] In addition, Figure 8A and Figure 8B In the embodiment of the present invention, a gate sealing spacer 80 may be formed on the exposed surface of the dummy gate 72, the mask 74, and / or the fin 52. Thermal oxidation or deposition followed by anisotropic etching may form the gate sealing spacer 80. The gate sealing spacer 80 may be formed of silicon oxide, silicon nitride, silicon oxynitride, or the like.

[0039] After forming the gate sealing spacer 80, an implantation of lightly doped source / drain (LDD) regions (not explicitly shown) may be performed. In embodiments with different device types, similar to the above, Figure 6 50P, and an appropriate type (e.g., p-type) of impurities can be implanted into the exposed fins 52 in regions 50P. The mask can then be removed. Subsequently, a mask (e.g., photoresist) can be formed over regions 50P, while exposing regions 50N, and an appropriate type (e.g., n-type) of impurities can be implanted into the exposed fins 52 in regions 50N. The mask can then be removed. The n-type impurity can be any of the n-type impurities discussed previously, and the p-type impurity can be any of the p-type impurities discussed previously. The lightly doped source / drain regions can have a density of about 10 15 cm -3 and about 10 19 cm -3 Annealing can be used to repair implant damage and activate the implanted impurities.

[0040] exist Figure 9A and 9B In the embodiment of the present invention, gate spacers 86 are formed on the gate sealing spacers 80 along the sidewalls of the dummy gate 72 and the mask 74. The gate spacers 86 can be formed by conformally depositing an insulating material and then anisotropically etching the insulating material. The insulating material of the gate spacers 86 can be silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, or a combination thereof.

[0041] Note that the above disclosure generally describes processes for forming spacers and LDD regions. Other processes and sequences may be used. For example, fewer or more spacers may be used, and a different order of steps may be used; for example, the gate sealing spacer 80 may not be etched prior to forming the gate spacer 86, resulting in an "L-shaped" gate sealing spacer, or spacers may be formed and removed, etc. Furthermore, n-type and p-type devices may be formed using different structures and steps. For example, the LDD region for an n-type device may be formed prior to forming the gate sealing spacer 80, while the LDD region for a p-type device may be formed after forming the gate sealing spacer 80.

[0042] exist Figure 10A 、 Figure 10B and Figure 10C In the embodiment of the present invention, epitaxial source / drain regions 82 are formed in the fins 52 to apply stress in each channel region 58 to improve performance. The epitaxial source / drain regions 82 are formed in the fins 52 so that each dummy gate 72 is disposed between a corresponding pair of adjacent epitaxial source / drain regions 82. In some embodiments, the epitaxial source / drain regions 82 may extend into the fins 52 and may also penetrate the fins 52. In some embodiments, gate spacers 86 are used to separate the epitaxial source / drain regions 82 from the dummy gates 72 by an appropriate lateral distance so that the epitaxial source / drain regions 82 do not short-circuit the gates of subsequently formed FinFETs.

[0043] The epitaxial source / drain regions 82 in the region 50N (e.g., NMOS region) can be formed by masking the region 50P (e.g., PMOS region) and etching the source / drain regions of the fin 52 in the region 50N to form recesses in the fin 52. The epitaxial source / drain regions 82 in the region 50N are then epitaxially grown in the recesses. The epitaxial source / drain regions 82 can include, for example, any acceptable material suitable for an n-type FinFET. For example, if the fin 52 is silicon, the epitaxial source / drain regions 82 in the region 50N can include a material that applies tensile strain in the channel region 58, such as silicon, silicon carbide, phosphorus-doped silicon carbide, silicon phosphide, etc. The epitaxial source / drain regions 82 in the region 50N can have surfaces that are raised from the corresponding surfaces of the fin 52 and can have facets.

[0044] The epitaxial source / drain regions 82 in the region 50P (e.g., the PMOS region) can be formed by masking the region 50N (e.g., the NMOS region) and etching the source / drain regions of the fin 52 in the region 50P to form recesses in the fin 52. The epitaxial source / drain regions 82 in the region 50P are then epitaxially grown in the recesses. The epitaxial source / drain regions 82 can include, for example, any acceptable material suitable for a p-type FinFET. For example, if the fin 52 is silicon, the epitaxial source / drain regions 82 in the region 50P can include a material such as silicon or a material that applies compressive strain in the channel region 58, such as silicon germanium, boron-doped silicon germanium, germanium, germanium tin, etc. The epitaxial source / drain regions 82 in the region 50P can also have surfaces that are raised from the corresponding surfaces of the fin 52 and can have facets.

[0045] The epitaxial source / drain regions 82 and / or fins 52 may be implanted with dopants to form source / drain regions, similar to the process previously discussed for forming lightly doped source / drain regions, followed by annealing. The impurity concentration of the source / drain regions may be approximately 10 19 cm -3 and about 10 21 cm -3 The n-type and / or p-type impurities of the source / drain regions may be any of the impurities discussed above. In some embodiments, the epitaxial source / drain regions 82 may be in-situ doped during growth.

[0046] As a result of the epitaxial process used to form epitaxial source / drain regions 82 in regions 50N and 50P, the upper surfaces of the epitaxial source / drain regions have facets that extend laterally outward beyond the sidewalls of fin 52. In some embodiments, these facets cause adjacent source / drain regions 82 of the same FinFET to merge, e.g., Figure 10C In other embodiments, adjacent source / drain regions 82 remain separated after the epitaxial process is completed, as shown in FIG. Figure 10C As shown in the area 50P. Figure 10C In the embodiment shown, gate spacers 86 are formed to cover a portion of the sidewalls of fin 52, extending over STI regions 56 to block epitaxial growth. In some other embodiments, the spacer etch used to form gate spacers 86 can be tuned to remove spacer material, thereby allowing the epitaxial growth region to extend to the surface of STI regions 56.

[0047] exist Figure 11A 、 Figure 11B and Figure 11C In the first interlayer dielectric (ILD) 88 is deposited on Figure 10A 、 Figure 10B and Figure 10C88 is formed of a dielectric material and can be deposited by any suitable method, such as CVD, plasma-enhanced CVD (PECVD), or FCVD. The dielectric material can include phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG), etc. Other insulating materials formed by any acceptable process can be used. In some embodiments, a contact etch stop layer (CESL) 87 is disposed between the first ILD 88 and the epitaxial source / drain regions 82, the mask 74, and the gate spacers 86. The CESL 87 can include a dielectric material, such as silicon nitride, silicon oxide, silicon oxynitride, etc., which has a different etch rate than the material of the overlying first ILD 88.

[0048] exist Figure 12A and Figure 12B In the process, a planarization process such as CMP can be performed to make the top surface of the first ILD 88 flush with the top surface of the dummy gate 72 or the mask 74. The planarization process can also remove the mask 74 on the dummy gate 72, as well as portions of the gate sealing spacer 80 and the gate spacer 86 along the sidewalls of the mask 74. After the planarization process, the top surfaces of the dummy gate 72, the gate sealing spacer 80, the gate spacer 86, and the first ILD 88 are level. Therefore, the top surface of the dummy gate 72 is exposed through the first ILD 88. In some embodiments, the mask 74 can remain, in which case the planarization process makes the top surface of the first ILD 88 flush with the top surface of the mask 74.

[0049] exist Figure 13A and 13BIn the embodiment of the present invention, dummy gate 72 and mask 74 (if present) are removed in one or more etching steps, thereby forming recesses 90. Portions of dummy dielectric layer 60 within recesses 90 may also be removed. In some embodiments, only dummy gate 72 is removed, and dummy dielectric layer 60 remains and is exposed by recesses 90. In some embodiments, dummy dielectric layer 60 is removed from recesses 90 within a first region of the die (e.g., the core logic region) and remains within recesses 90 within a second region of the die (e.g., the input / output region). In some embodiments, dummy gate 72 is removed by an anisotropic dry etching process. For example, the etching process may include a dry etching process using a reactive gas that selectively etches dummy gate 72 without etching first ILD 88 or gate spacers 86. Each recess 90 exposes and / or covers a channel region 58 of a corresponding fin 52. Each channel region 58 is disposed between adjacent pairs of epitaxial source / drain regions 82. During removal, dummy dielectric layer 60 may serve as an etch stop layer as dummy gate 72 is etched. Dummy dielectric layer 60 may then optionally be removed after dummy gate 72 is removed.

[0050] exist Figure 14A and Figure 14B In the embodiment, a gate dielectric layer 92 and a gate electrode 94 are formed to replace the gate. Figure 14C Shown Figure 14B Detailed view of region 89 of FIG. A gate dielectric layer 92 is conformally deposited in recess 90 , for example, on the top surface and sidewalls of fin 52 and on the sidewalls of gate seal spacer 80 / gate spacer 86 . Gate dielectric layer 92 may also be formed on the top surface of first ILD 88 . According to some embodiments, gate dielectric layer 92 comprises silicon oxide, silicon nitride, or multilayers thereof. In some embodiments, gate dielectric layer 92 comprises a high-k dielectric material, and in these embodiments, gate dielectric layer 92 may have a k value greater than approximately 7.0 and may comprise a metal oxide or silicate of hafnium, aluminum, zirconium, lanthanum, manganese, barium, titanium, lead, and combinations thereof. Methods of forming gate dielectric layer 92 may include molecular beam deposition (MBD), ALD, PECVD, and the like. In embodiments where a portion of dummy dielectric layer 60 remains in recess 90 , gate dielectric layer 92 comprises the material of dummy dielectric layer 60 (e.g., SiO 2 ).

[0051] Gate electrodes 94 are deposited over gate dielectric layer 92 and fill the remainder of recess 90. Gate electrodes 94 may include a metal-containing material, such as titanium nitride, titanium oxide, tantalum nitride, tantalum carbide, cobalt, ruthenium, aluminum, tungsten, combinations thereof, or multiple layers thereof. For example, although Figure 14BA single-layer gate electrode 94 is shown in FIG, but the gate electrode 94 may include any number of liner layers 94A, any number of work function adjustment layers 94B and filler materials 94C, such as Figure 14C As shown. After filling recess 90, a planarization process such as CMP can be performed to remove excess portions of gate dielectric layer 92 and gate electrode 94 material that are located above the top surface of ILD 88. Thus, gate electrode 94 and the remaining portion of gate dielectric layer 92 material form a replacement gate for the resulting FinFET. Gate electrode 94 and gate dielectric layer 92 can be collectively referred to as a "gate stack." The gate and gate stack can extend along the sidewalls of channel region 58 of fin 52.

[0052] The formation of gate dielectric layer 92 in region 50N and region 50P can occur simultaneously, such that gate dielectric layer 92 in each region is formed of the same material, and the formation of gate electrode 94 can occur simultaneously, such that gate electrode 94 in each region is formed of the same material. In some embodiments, gate dielectric layer 92 in each region can be formed by a different process, such that gate dielectric layer 92 can be a different material, and / or gate electrode 94 in each region can be formed by a different process, such that gate electrode 94 can be a different material. When different processes are used, various masking steps can be used to mask and expose the appropriate regions.

[0053] exist Figure 15A and Figure 15B In the embodiment, the gate stack (including the gate dielectric layer 92 and the corresponding overlying gate electrode 94) is recessed so that a groove is formed directly above the gate stack and between opposing portions of the gate spacer 86, as shown in FIG. Figure 15A and Figure 15B As shown. A gate mask 96 comprising one or more layers of dielectric material (e.g., silicon nitride, silicon oxynitride, etc.) is filled in the recess, and a planarization process is then performed to remove excess portions of the dielectric material extending above the first ILD 88. The gate contact 233 ( Figure 21 ) penetrates the gate mask 96 to contact the top surface of the recessed gate electrode 94.

[0054] exist Figures 16A-16BIn the embodiment of the present invention, the second ILD 108 is deposited over the first ILD 88, wherein the etch stop 150 is formed between the second ILD 108 and the first ILD 88. In an embodiment, the etch stop 150 can be formed of a dielectric material such as silicon nitride deposited by a process such as plasma enhanced chemical vapor deposition (PECVD), physical vapor deposition (PVD), atomic layer deposition (ALD), low pressure chemical vapor deposition (LPCVD), spin-on coating, etc. However, any suitable material and method can be used.

[0055] Furthermore, the second ILD 108 may be a flowable film formed by a flowable CVD method. In some embodiments, the second ILD 108 is formed of a dielectric material such as PSG, BSG, BPSG, or USG, and may be deposited by any suitable method such as CVD and PECVD. However, any suitable material or manufacturing method may be used.

[0056] exist Figures 17A-17C 87, source / drain contact openings 93 are formed through second ILD 108, etch stop 150, first ILD 88, and CESL 87. In an embodiment, source / drain contact openings 93 may be formed by sequentially etching through each of second ILD 108, etch stop 150, first ILD 88, and CESL 87 using one or more etching processes. However, any suitable process may be used to form source / drain contact openings 93 and expose source / drain regions 82.

[0057] Once the source / drain contact openings 93 have been formed and the source / drain regions 82 have been exposed, an optional pre-silicide implant may be performed to form a partially amorphous region and help repair any surface damage that may have occurred. For example, in some embodiments, ions such as silicon or germanium may be implanted through the source / drain contact openings 93 and into the source / drain regions 82. However, any suitable ions may be used.

[0058] Figures 17A-17C Also shown are the deposition of a first dual-material silicide precursor layer 201 and the deposition of an oxidation barrier layer 203. In an embodiment, the first dual-material silicide precursor layer 201 includes at least a first silicide precursor material and a second silicide precursor material. However, the second silicide precursor material is insoluble (e.g., less than 5%) in a first phase of a silicide formed from the first silicide precursor material, but is soluble (e.g., greater than about 10%) in a second phase of a silicide formed from the first silicide precursor material.

[0059] For example, the first silicide precursor material can be a material that is tailored for the source / drain region 82 in which it is located. For example, in an embodiment, the first silicide precursor material has a relatively high Schottky barrier for placement within the region 50N, such as nickel, which has a first phase as a silicide of Ni2Si and a second phase as a silicide of NiSi. In such an embodiment, the second silicide precursor material is a material that has a low Schottky barrier to holes / electrons and is insoluble in the first phase (e.g., Ni2Si) while being soluble in the second phase (e.g., NiSi), such as platinum. In such an embodiment, the first bi-material silicide precursor layer 201 can be an alloy layer of nickel and platinum, or can be alternating nickel layers separated by alternating platinum layers. However, any suitable material can be used.

[0060] In an embodiment, the first bi-material silicide precursor layer 201 may be deposited using a deposition process such as physical vapor deposition, chemical vapor deposition, atomic layer deposition, or a combination thereof. Furthermore, the first bi-material silicide precursor layer 201 may be deposited to a thickness between about 0.5 nm and about 10 nm. However, any suitable thickness may be used.

[0061] In some embodiments, the deposition process can be performed at a temperature that is less than about 250° C., while still high enough to allow the deposited nickel to form a first phase of silicide (Ni2Si) during the deposition process. Thus, a first phase layer 205 of silicide is formed over source / drain regions 82 in both regions 50N and 50P. The first phase layer 205 of silicide can be formed to a thickness between about 1 nm and about 20 nm, for example, about 3 nm.

[0062] Additionally, in some embodiments, the first phase of the silicide (e.g., Ni2Si) is metal-rich. For example, in embodiments where the first phase of the silicide is Ni2Si, the nickel concentration may be from about 55% to about 85%, such as about 65%. However, any suitable metal-rich composition may be used.

[0063] In other embodiments, the deposition process for depositing the first bi-material silicide precursor layer 201 may be performed at a temperature that is too low to react the first silicide precursor material, such as a temperature below about 250° C. In such embodiments, an optional annealing process may be performed after deposition to form the first phase layer 205 of silicide. In an embodiment, the optional annealing process may be performed at a temperature between about 150° C. and about 250° C. (e.g., about 200° C.) for a time between about 1 second and about 100 seconds (e.g., about 30 seconds). However, any suitable temperature and time may be used.

[0064] However, because the second silicide precursor material is insoluble in the first phase of the silicide present in the first phase layer 205 of the silicide, the second silicide precursor material (e.g., platinum) will not diffuse into the first phase layer 205 of the silicide and will not react to form its own silicide. Thus, at this stage of manufacturing, the second silicide precursor material is effectively confined to only within the first bi-material silicide precursor layer 201.

[0065] Once the first bi-material silicide precursor layer 201 has been formed, an optional oxidation barrier layer 203 may be deposited over the first bi-material silicide precursor layer 201 to help protect the first bi-material silicide precursor layer 201 during subsequent processes. In an embodiment, the oxidation barrier layer 203 may be a material such as titanium, tungsten, tantalum, or ruthenium, which may be deposited to a thickness between about 2 nm and about 10 nm, for example, about 4 nm, using a deposition process such as physical vapor deposition, chemical vapor deposition, atomic layer deposition, or combinations thereof. However, any suitable material, thickness, or process may be used.

[0066] Figure 18 (which shows the Figure 1 ) illustrates patterning the first dual material silicide precursor layer 201 to remove the first dual material silicide precursor layer 201 from the region 50N while maintaining the first dual material silicide precursor layer 201 within the region 50P. In an embodiment, the first dual material silicide precursor layer 201 may be patterned by first applying a photoresist layer 207 (e.g., a three-layer photoresist) over the first dual material silicide precursor layer 201, exposing the photosensitive material within the photoresist layer 207 to a patterned light source, developing the photosensitive material to remove the portion of the photosensitive material located over the region 50N, and then using the photosensitive material as a mask to remove the other layers of the photoresist layer 207 and expose the oxidation barrier layer 203 and the material of the first dual material silicide precursor layer 201 located in the region 50N.

[0067] Once the photoresist layer 207 has been patterned, the photoresist layer 207 can be used as a mask to protect the portion of the first dual-material silicide precursor layer 201 located in the region 50P while removing the oxidation barrier layer 203 and the portion of the first dual-material silicide precursor layer 201 located in the region 50N. In an embodiment, the removal can be performed using, for example, one or more anisotropic etching processes (e.g., reactive ion etching) to remove the exposed portion of the oxidation barrier layer 203 and the first dual-material silicide precursor layer 201 located in the region 50N. However, any suitable method can be used.

[0068] However, although the oxidation barrier layer 203 and the first dual-material silicide precursor layer 201 are removed from the region 50N, the first phase layer 205 of the silicide in the region 50N is not removed. In addition, the oxidation barrier layer 203, the first dual-material silicide precursor layer 201, and the first phase layer 205 of the silicide in the region 50P also remain after the patterning process.

[0069] Figure 19A (which shows the Figure 1 ) shows that once the first bi-material silicide precursor layer 201 has been removed from the region 50N, an annealing process may be performed (at Figure 19A The annealing process 209 may be a rapid thermal annealing performed at a higher temperature (e.g., between about 400° C. and about 450° C.) than the deposition temperature of the first bi-material silicide precursor layer 201 for a time period between about <1 s and about 60 s (e.g., about 30 s), although any suitable temperature and time may be used. However, any suitable annealing process may be used, such as millisecond laser annealing, flash annealing, spike annealing, or conventional immersion annealing.

[0070] By utilizing such a temperature, the phase of the first phase layer 205 of the silicide located in the region 50N can be transferred to a second phase of the same material. For example, in an embodiment where the first phase layer 205 of the silicide is initially formed as Ni2Si, the annealing process 209 can transfer the phase of the material to NiSi. In this way, a second phase layer 211 of the silicide can be formed in the region 50N.

[0071] Additionally, in some embodiments, the second phase layer 211 of the silicide is semiconductor-rich, such as by being silicon-rich, germanium-rich, or III-V-rich. For example, in embodiments where the second phase of the silicide is NiSi, the concentration of silicon may be between about 35% and about 65%, such as about 50%. However, any suitable semiconductor-rich composition may be used.

[0072] Additionally, in region 50P, a similar phase transition occurs in the first phase layer 205 of the silicide due to the annealing process 209. Specifically, in embodiments where the first phase layer 205 of the silicide is deposited as Ni2Si, the Ni2Si will undergo a phase transition to NiSi. However, with the phase transition from the first phase of the material (e.g., Ni2Si) to the second phase of the material (NiSi), the second silicide precursor (e.g., platinum) is no longer prevented from diffusing and reacting because the second silicide precursor is now soluble in the material. Specifically, in embodiments where the first silicide precursor is nickel and the second silicide precursor is platinum, the annealing process 209 changes the phase of Ni2Si in the first phase layer 205 of the silicide (in which platinum is insoluble) to the second phase (e.g., NiSi, in which platinum is soluble).

[0073] Taking into account the change in solubility, the second silicide precursor (e.g., platinum) will begin to diffuse and react with the first silicide precursor (e.g., nickel) and the material of the source / drain regions 82 to form a third phase layer 213 of silicide. Thus, the third phase layer 213 of silicide includes not only the first silicide precursor and silicon from the source / drain regions 82, but also the material of the second silicide precursor. In an embodiment where the first silicide precursor is nickel and the second silicide precursor is platinum, the third phase layer 213 of silicide is NiPtSi. However, any suitable material may be formed.

[0074] Additionally, in some embodiments, the second silicide precursor (e.g., platinum) can migrate through the third phase layer 213 of the silicide, thereby reacting with previously unreacted material of the source / drain regions 82. Thus, the second silicide precursor can actually self-separate from the third phase layer 213 of the silicide to form a separate silicide layer 215 between the third phase layer 213 of the silicide and the remaining portion of the source / drain regions 82 located within the region 50P. In an embodiment, the separate silicide layer 215 can have a thickness between about 0.5 nm and about 4 nm, for example, about 2 nm. However, any suitable thickness can be used.

[0075] Figure 19B The relative intensities of the elements are shown for an embodiment in which the first precursor material is nickel, the second precursor material is platinum, and the source / drain regions 82 are silicon germanium. It can be seen that the nickel and platinum form a third phase layer 213 of silicide together with the silicon, with the platinum extending all the way through the third phase layer 213 of the silicide.

[0076] Figure 19AIt is also shown that once the third phase layer 213 of silicide has been formed, the oxidation barrier layer 203 can be selectively removed. In an embodiment, the oxidation barrier layer 203 can be removed using an etching process such as a wet etching process or a dry etching process that utilizes an etchant that is selective to the material (e.g., titanium) of the oxidation barrier layer 203. However, any suitable etching process can be used.

[0077] Once the oxidation barrier layer 205 has been removed, any unreacted material of the first bi-material silicide precursor layer 201 that has not been removed or reacted is removed. In an embodiment, the first bi-material silicide precursor layer 201 may be removed using an etching process such as a wet etching process or a dry etching process that utilizes an etchant that is selective to the materials (e.g., nickel and platinum) of the first bi-material silicide precursor layer 201. However, any suitable etching process may be used.

[0078] Figure 20 (which shows the Figure 1 ) shows that once the oxidation barrier layer 203 and the unreacted portion of the first bi-material silicide precursor layer 201 have been removed, a glue layer 217 can be deposited in preparation for forming the contact 233. In an embodiment, an optional cleaning process can be performed before forming the glue layer 217 to remove any oxides that may be present after the various etching processes are completed. In some embodiments, the cleaning process uses a hydrogen pre-cleaning treatment (e.g., a hydrogen (H2) plasma treatment, etc.) to remove waste and any oxides from the surface. However, any suitable cleaning process can be used.

[0079] Once cleaned, a glue layer 217 may be deposited to help the cover layer adhere to the underlying layers. In some embodiments, glue layer 217 may be a material such as titanium, tungsten, or tantalum, deposited to a thickness between about 1 nm and about 10 nm, for example, about 5 nm, using a deposition process such as chemical vapor deposition, physical vapor deposition, or atomic layer deposition. However, any suitable material, deposition process, and thickness may be used.

[0080] Additionally, in some embodiments, the deposition process of the glue layer can be performed at a temperature at which the material of glue layer 217 (e.g., titanium) will react with the underlying material during the deposition process to form a first glue silicide layer 219 over the second phase layer of silicide 211. In embodiments where glue layer 217 is titanium, the deposition process can be performed at a deposition temperature between about 400° C. and about 600° C., although any suitable temperature can be used.

[0081] At these temperatures, the material of glue layer 217 can react with the exposed material to form additional silicide. For example, in region 50N, the material of glue layer 217 reacts with the second phase layer 211 of the silicide to form a first glued silicide layer 219 above the second phase layer 211 of the silicide. In an embodiment where glue layer 217 is titanium and the second phase layer 211 of the silicide is NiSi, first glued silicide layer 219 can be formed as a TiNiSi alloy having a thickness between about 2 nm and about 20 nm, for example, about 8 nm. However, any suitable thickness can be used.

[0082] Similarly, in region 50P, the material of glue layer 217 (e.g., titanium) reacts with silicon from the material of the third phase layer 213 of the silicide to form a second glued silicide layer 221. In embodiments where glue layer 217 is titanium, second glued silicide layer 221 reacts to form a silicide, e.g., titanium silicide, over the third phase layer 213 of the silicide. In embodiments, second glued silicide layer 221 may be formed to have a thickness between approximately 1 nm and approximately 10 nm, e.g., approximately 5 nm. However, any suitable thickness may be used.

[0083] Figure 20 It is also shown that once the glue layer 217 has been formed, a barrier layer 223 can be deposited over the glue layer 217. In an embodiment, the barrier layer 223 can be formed of a metal material such as TiN, Ti, TiAlN, TaC, TaCN, TaSiN, Mn, Zr, TaN, Ru, Mo, WN, other metal oxides, metal nitrides, metal silicates, transition metal oxides, transition metal nitrides, transition metal silicates, metal oxynitrides, metal aluminates, zirconium silicate, zirconium aluminate, combinations thereof, etc. In addition, the barrier layer 223 can be deposited to a depth of about 1000 nm using a deposition process such as atomic layer deposition, chemical vapor deposition, sputtering, or the like. to about A thickness between , but any suitable deposition process or thickness may be used.

[0084] Once barrier layer 223 has been formed, and in embodiments where the deposition process for depositing glue layer 217 is performed at a temperature that is too low to react glue layer 217, an optional annealing process may be performed to form first glue silicide layer 219 and second glue silicide layer 221. In embodiments, the optional annealing process may be performed at a temperature between about 350° C. and about 600° C. (e.g., about 500° C.) for a time between about 1 millisecond and about 60 seconds (e.g., about 30 seconds). However, any suitable temperature and time may be used.

[0085] Figure 21 (which shows the Figure 1 The cutout of reference cross section CC shown in FIG2 illustrates the formation of first contact 233. In an embodiment, first contact 233 may be a conductive material, such as W, Al, Cu, Co, Ti, Ta, Ru, TiN, TiAl, TiAlN, TaN, TaC, NiSi, CoSi, combinations thereof, or the like, but any suitable material may be deposited using a deposition process such as sputtering, chemical vapor deposition, electroplating, or electroless plating to fill and / or overfill the opening. Once filled or overfilled, a planarization process such as chemical mechanical polishing (CMP) may be used to remove any deposited material outside the opening. However, any suitable material and formation process may be used.

[0086] By utilizing the embodiments described herein, the silicide material can be tailored to the device into which it is placed, rather than using a single Schottky barrier (which cannot satisfy both N+ and P+ contacts separately). For example, the silicide material for N-type devices (e.g., within the 50N region) is tailored for N-type devices, while the silicide material for P-type devices (e.g., within the 50P region) is tailored for P-type devices. In this way, the reduction in the P+ Schottky barrier for contact to the P+ device can be reduced by more than about 25%. In addition, due to the outward diffusion of the characteristic material, the effective silicide area is also increased, which reduces both the N+ and P+ contact resistances, as well as improving the dopant concentration from the faster diffusing metal due to snowplow and low solid solubility.

[0087] According to an embodiment, a method for manufacturing a semiconductor device includes: depositing a first silicide precursor and a second silicide precursor on a source / drain region, wherein the deposition further forms a first silicide having a first phase, and the second silicide precursor is insoluble in the first phase of the first silicide; changing the first phase of the first silicide to a second phase of the first silicide, and the second silicide precursor is soluble in the second phase of the first silicide; and forming a second silicide using the second silicide precursor and the second phase of the first silicide. In an embodiment, forming the second silicide further forms a separation region between the second silicide and the remaining portion of the source / drain region. In an embodiment, the first silicide precursor includes nickel. In an embodiment, the second silicide precursor includes platinum. In an embodiment, the method further includes: removing a portion of the first silicide precursor and the second silicide precursor before changing the first phase of the first silicide to the second phase of the first silicide. In an embodiment, before removing a portion of the first silicide precursor and the second silicide precursor, a portion of the first silicide precursor and the second silicide precursor is located above the N+ source / drain region. In an embodiment, the second silicide is located above the P+ source / drain region.

[0088] According to another embodiment, a method for manufacturing a semiconductor device includes forming a first source / drain region adjacent to a first gate stack; forming a second source / drain region adjacent to a second gate stack; depositing a first material layer on both the first source / drain region and the second source / drain region, the first material layer including a first silicide precursor and a second silicide precursor; forming a first silicide on both the first source / drain region and the second source / drain region, wherein the first silicide is formed using the first silicide precursor but not the second silicide precursor, and the first silicide has a first phase; removing the first silicide precursor and the second silicide precursor from the first source / drain region without removing the second silicide precursor from the second source / drain region; and changing the first phase of the first silicide to a second phase of the first silicide. In one embodiment, the second silicide precursor is insoluble in the first phase of the first silicide. In one embodiment, during the changing of the first phase of the first silicide, the second silicide precursor diffuses into the second phase to form a third silicide. In one embodiment, the method further comprises: forming a fourth silicide over the third silicide. In one embodiment, forming the fourth silicide comprises depositing titanium. In one embodiment, forming the fourth silicide further comprises performing an annealing process separate from depositing the titanium. In one embodiment, forming the first silicide comprises performing an annealing process separate from depositing the first material layer.

[0089] According to another embodiment, a semiconductor device includes: a first source / drain region separated from a second source / drain region; a first silicide located on the first source / drain region, the first silicide including a first group of elements; a second silicide located on the second source / drain region, the second silicide including the first group of elements and a first element, wherein the first element is insoluble in a first phase of the silicide including the first group of elements and is soluble in a second phase of the silicide including the first group of elements. In an embodiment, the first group of elements includes nickel and silicon. In an embodiment, the first element is platinum. In an embodiment, the semiconductor device further includes: a separating silicide located between the second silicide and the second source / drain region, the separating silicide including the first element. In an embodiment, the semiconductor device further includes: a third silicide located above the second silicide, the third silicide including a material different from the second silicide. In an embodiment, the third silicide includes titanium

[0090] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art will appreciate that they can easily use the present disclosure as a basis for designing or modifying other processes and structures to achieve the same purpose and / or the same advantages of the embodiments introduced herein. Those skilled in the art will also appreciate that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they can make various changes, substitutions, and modifications herein without departing from the spirit and scope of the present disclosure.

[0091] Example 1. A method for manufacturing a semiconductor device, the method comprising: depositing a first silicide precursor and a second silicide precursor on a source / drain region, wherein the deposition also forms a metal-rich silicide having a metal-rich phase, and the second silicide precursor is insoluble in the metal-rich phase of the metal-rich silicide; changing the metal-rich phase of the metal-rich silicide into a semiconductor-rich phase by thermal annealing, and the second silicide precursor is soluble in the semiconductor-rich phase due to the additional semiconductor material formed in the silicide; and forming a second silicide using the second silicide precursor and the semiconductor-rich phase.

[0092] Example 2. The method of Example 1, wherein forming the second silicide further forms a separation region between the second silicide and a remaining portion of the source / drain region.

[0093] Example 3. The method of Example 1, wherein the first silicide precursor comprises a silicide material comprising nickel, titanium, ruthenium, tungsten, and cobalt.

[0094] Example 4. The method of Example 3, wherein the second silicide precursor comprises a P-type metal or an N-type metal.

[0095] Example 5. The method of Example 1, further comprising removing a portion of the first silicide precursor and the second silicide precursor before changing the metal-rich phase of the metal-rich silicide.

[0096] Example 6. The method of Example 5, wherein, prior to removing the portion of the first silicide precursor and the second silicide precursor, the portion of the first silicide precursor and the second silicide precursor is located above an N+ source / drain region.

[0097] Example 7. The method of Example 6, wherein the second silicide is located above the P+ source / drain region.

[0098] Example 8. A method for manufacturing a semiconductor device, the method comprising: forming a first source / drain region adjacent to a first gate stack; forming a second source / drain region adjacent to a second gate stack; depositing a first material layer on both the first source / drain region and the second source / drain region, the first material layer comprising a first silicide precursor and a second silicide precursor; forming a first silicide on both the first source / drain region and the second source / drain region, wherein the first silicide is metal-rich and wherein the first silicide is formed using the first silicide precursor but not the second silicide precursor, and the first silicide has a first phase; removing the first silicide precursor and the second silicide precursor from the first source / drain region without removing the second silicide precursor from the second source / drain region; and changing the first phase of the first silicide to the second phase of the first silicide.

[0099] Example 9. The method of Example 8, wherein the second silicide precursor is insoluble in the first phase of the first silicide.

[0100] Example 10. The method of Example 9, wherein during the changing of the first phase of the first silicide, the second silicide precursor diffuses into the second phase to form a third silicide.

[0101] Example 11. The method of Example 10, further comprising: forming a fourth silicide over the third silicide.

[0102] Example 12. The method of Example 11, wherein forming the fourth silicide comprises depositing titanium.

[0103] Example 13. The method of Example 12, wherein forming the fourth silicide further comprises performing an annealing process separate from depositing the titanium.

[0104] Example 14. The method of Example 8, wherein forming the first silicide comprises performing an annealing process separate from depositing the first material layer.

[0105] Example 15. A semiconductor device comprising: a first source / drain region, the first source / drain region being separated from a second source / drain region; a first silicide, the first silicide being located on the first source / drain region, the first silicide comprising a first group of elements; and a second silicide being located on the second source / drain region, the second silicide comprising the first group of elements and a first element, wherein the first element is insoluble in a first phase of the silicide comprising the first group of elements, and the first element is soluble in a second phase of the silicide comprising the first group of elements.

[0106] Example 16. The semiconductor device of Example 15, wherein the first group of elements includes nickel and silicon.

[0107] Example 17. The semiconductor device of Example 16, wherein the first element is platinum.

[0108] Example 18. The semiconductor device of Example 15, further comprising: a separate silicide located between the second silicide and the second source / drain region, the separate silicide comprising the first element.

[0109] Example 19. The semiconductor device of Example 18, further comprising: a third silicide located above the second silicide, the third silicide comprising a different material from the second silicide.

[0110] Example 20. The semiconductor device of Example 19, wherein the third silicide comprises titanium.

Claims

1. A method for manufacturing a semiconductor device, the method include: Depositing a first silicide precursor and a second silicide precursor on the source / drain region, wherein the deposition further forms a metal-rich silicide having a metal-rich phase, and the second silicide precursor is insoluble in the metal-rich phase of the metal-rich silicide; changing the metal-rich phase of the metal-rich silicide into a semiconductor-rich phase by thermal annealing, the second silicide precursor being soluble in the semiconductor-rich phase due to the formation of the silicide with additional semiconductor material; and A second silicide is formed using the second silicide precursor and the semiconductor-rich phase.

2. The method according to claim 1, in, Forming the second silicide also forms a separation region between the second silicide and a remaining portion of the source / drain region.

3. The method according to claim 1, in, The first silicide precursor includes a silicide material including nickel, titanium, ruthenium, tungsten, and cobalt.

4. The method according to claim 3, in, The second silicide precursor includes a P-type metal or an N-type metal.

5. The method according to claim 1, further comprising: include: Prior to changing the metal-rich phase of the metal-rich silicide, a portion of the first silicide precursor and the second silicide precursor are removed.

6. The method according to claim 5, in, Prior to removing the portions of the first silicide precursor and the second silicide precursor, the portions of the first silicide precursor and the second silicide precursor are located over an N+ source / drain region.

7. The method according to claim 6, in, The second silicide is located above the P+ source / drain region.

8. A method for manufacturing a semiconductor device, the method include: forming a first source / drain region adjacent to the first gate stack; forming a second source / drain region adjacent to the second gate stack; Depositing a first material layer on both the first source / drain region and the second source / drain region, the first material layer comprising a first silicide precursor and a second silicide precursor; forming a first silicide on both the first source / drain region and the second source / drain region, wherein the first silicide is metal-rich, and wherein forming the first silicide utilizes the first silicide precursor but does not utilize the second silicide precursor to form the first silicide, and the first silicide has a first phase; removing the first silicide precursor and the second silicide precursor from the first source / drain region without removing the second silicide precursor from the second source / drain region; and The first phase of the first silicide is changed to a second phase of the first silicide.

9. The method according to claim 8, in, The second silicide precursor is insoluble in the first phase of the first silicide.

10. The method according to claim 9, in, During the changing of the first phase of the first silicide, the second silicide precursor diffuses into the second phase to form a third silicide.

11. The method according to claim 10, further comprising: include: A fourth silicide is formed over the third silicide.

12. The method according to claim 11, in, Forming the fourth silicide includes depositing titanium.

13. The method according to claim 12, in, Forming the fourth silicide further includes performing an annealing process separate from depositing the titanium.

14. The method according to claim 8, in, Forming the first silicide includes performing an annealing process separate from depositing the first material layer.

15. A semiconductor device, include: a first source / drain region, the first source / drain region being separated from the second source / drain region; a first silicide, the first silicide being located on the first source / drain region, the first silicide comprising a first group of elements; as well as A second silicide, the second silicide is located on the second source / drain region, the second silicide includes the first group of elements and a first element, wherein the first element is insoluble in a first phase of the silicide including the first group of elements, and the first element is soluble in a second phase of the silicide including the first group of elements.

16. The semiconductor device according to claim 15, in, The first group of elements includes nickel and silicon.

17. The semiconductor device according to claim 16, in, The first element is platinum.

18. The semiconductor device according to claim 15, further comprising: include: A separate silicide is located between the second silicide and the second source / drain region, and the separate silicide includes the first element.

19. The semiconductor device according to claim 18, further comprising: include: A third silicide is located above the second silicide, and the third silicide includes a material different from that of the second silicide.

20. The semiconductor device according to claim 19, in, The third silicide includes titanium.

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