Semiconductor structure and method for forming the same

Abstract

A semiconductor structure and a method for forming the same, the method comprising: providing a substrate; forming a first electrode layer on the substrate; forming a dielectric layer on the first electrode layer; forming a second electrode layer on the dielectric layer; forming an oxide layer on the second electrode layer; forming a first etch stop layer on the surface of the oxide layer; forming an insulating layer on the first etch stop layer; etching the insulating layer, the first etch stop layer and the oxide layer to form a first contact hole, wherein the bottom of the first contact hole exposes the top surface of the second electrode layer, and the first contact hole penetrates the insulating layer, the first etch stop layer and the oxide layer. The present invention helps to improve the adhesion strength between the second electrode plate and the first etch stop layer, and reduce the risk of delamination between the second electrode plate and the first etch stop layer, thereby improving the packaging quality.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing technology, and in particular to a semiconductor structure and a forming method thereof. Background Art

[0002] An integrated circuit is a miniature electronic device. Specifically, an integrated circuit integrates electronic components such as transistors, diodes, resistors, capacitors, and inductors through wiring interconnections and integrates them onto a semiconductor chip or dielectric substrate. Because the size of an integrated circuit is extremely small, the integrated circuit works extremely fast and has high reliability.

[0003] Integrated circuit packaging refers to dividing the processed wafer into multiple chips, and using wires to connect the contacts on the chip to the pins of the package shell. These pins are then connected to other devices through wires on the printed circuit board, ultimately forming a path connected to an external power source.

[0004] The quality of integrated circuit packaging has an important impact on the performance of integrated circuits. Integrated circuit packaging can play a role in fixing the pin system, physical protection, environmental protection and enhancing heat dissipation.

[0005] However, the semiconductor structure and the forming method thereof in the existing packaging process still need to be improved. Summary of the invention

[0006] The problem solved by the present invention is to provide a semiconductor structure and a method for forming the same, which helps to enhance the adhesion strength between the second electrode plate and the first etch stop layer, reduce the risk of delamination between the second electrode plate and the first etch stop layer, and improve the packaging quality.

[0007] To solve the above problems, the present invention provides a method for forming a semiconductor structure, comprising: providing a substrate; forming a first electrode layer on the substrate; forming a dielectric layer on the first electrode layer; forming a second electrode layer on the dielectric layer; forming an oxide layer on the second electrode layer; forming a first etch stop layer on the surface of the oxide layer; forming an insulating layer on the first etch stop layer; etching the insulating layer, the first etch stop layer and the oxide layer to form a first contact hole, the bottom of the first contact hole exposes the top surface of the second electrode layer, and the first contact hole penetrates the insulating layer, the first etch stop layer and the oxide layer.

[0008] Optionally, in the process of forming the dielectric layer, the dielectric layer exposes a portion of the surface of the first electrode layer, and the dielectric layer includes a plurality of discretely arranged sub-dielectric structures; in the process of forming the second electrode layer, the second electrode layer includes a plurality of second sub-electrode structures, and the second sub-electrode structures correspond one-to-one to the sub-dielectric structures.

[0009] Optionally, the method for forming the dielectric layer and the second electrode layer includes: forming a dielectric film covering the entire surface of the first electrode plate; forming a second electrode film covering the entire surface of the dielectric film; forming a patterned layer on a portion of the second electrode film; using the patterned layer as a mask, etching a portion of the second electrode film and a portion of the dielectric film until the surface of the first electrode layer is exposed, and the remaining second electrode film forms the second electrode layer, and the remaining dielectric film forms the dielectric layer.

[0010] Optionally, in the process of forming the oxide layer, the oxide layer covers the top of the first electrode layer, the sidewalls of the sub-dielectric structure, the sidewalls of the second sub-electrode structure and the top surface of the second sub-electrode structure.

[0011] Optionally, before forming the oxide layer, the method further includes: forming a thickening layer on the top surface of the second sub-electrode structure, wherein the thickening layer is made of the same material as the oxide layer.

[0012] Optionally, the method for forming the thickening layer includes: after forming the second electrode film and before forming the patterned layer, forming a thickening film covering the entire second electrode film, the patterned layer covering part of the surface of the thickening film; using the patterned layer as a mask to etch part of the second electrode film and part of the dielectric film, further including: etching part of the thickening film, and the remaining thickening film forms the thickening layer.

[0013] Optionally, in the process of forming the oxide layer, the oxide layer covers the top of the first electrode layer, the sidewalls of the sub-dielectric structure, the sidewalls of the second sub-electrode structure, the sidewalls of the thickening layer and the top surface of the thickening layer.

[0014] Optionally, in the process of forming the first contact holes, there are multiple first contact holes, and the first contact holes correspond to the second sub-electrode structures one by one.

[0015] Optionally, the process of forming the first contact hole also includes: etching the insulating layer, the first etch stop layer and the oxide layer located on one side of the second sub-electrode structure to form a second contact hole, wherein the second contact hole is located on the surface of the first electrode layer exposed by the dielectric layer, and the second contact hole penetrates the insulating layer, the first etch stop layer and the oxide layer.

[0016] Optionally, after providing the substrate and before forming the first electrode layer, it also includes: forming a dielectric layer on the surface of the substrate; etching the dielectric layer to form a plurality of through holes in the dielectric layer; forming a conductive layer filling the through holes; forming a second etch stop layer covering the top of the dielectric layer and the top surface of the conductive layer; forming an interface layer covering the top surface of the second etch stop layer, and the first electrode layer covers the top surface of the interface layer.

[0017] Optionally, in the process of providing the substrate, the substrate includes a first region and a second region; in the process of forming the first electrode layer, the first electrode layer covers the top of the substrate in the first region and the second region; in the process of forming the dielectric layer, the dielectric layer is located on the first electrode layer in the second region, and the dielectric layer exposes a portion of the surface of the first electrode layer in the second region.

[0018] Optionally, after forming the insulating layer and before forming the first contact hole, it also includes: etching and removing the insulating layer, the first etch stop layer, the oxide layer, the first electrode layer and the interface layer in the first region; forming an isolation layer on the surface of the second etch stop layer in the first region, and the isolation layer is flush with the top of the insulating layer.

[0019] Optionally, the process of forming the first contact hole and the second contact hole also includes: etching the isolation layer and the second etch stop layer to form a third contact hole, the third contact hole penetrates the isolation layer and the second etch stop layer, and the bottom of the third contact hole exposes one of the top surfaces of the conductive layers.

[0020] Optionally, after forming the first contact hole, the second contact hole and the third contact hole, the method further includes: forming a metal layer that fills the first contact hole, the second contact hole and the third contact hole, and the top surface of the metal layer is flush with the top surface of the insulating layer.

[0021] Optionally, the method for forming the metal layer includes: forming a metal film that fills the first contact hole, the second contact hole and the third contact hole, wherein the metal film covers the top surface of the insulating layer and the top surface of the isolation layer; flattening the metal film, removing the metal film located on the top surface of the insulating layer and the top surface of the isolation layer, and forming the metal layer.

[0022] Optionally, the material of the oxide layer is silicon oxide.

[0023] Correspondingly, the present invention also provides a semiconductor structure, including: a substrate; a first electrode layer, the first electrode layer is located on the substrate; a dielectric layer, the dielectric layer is located on the first electrode layer; a second electrode layer, the second electrode layer is located on the dielectric layer; an oxide layer, the oxide layer is located on the second electrode layer; a first etch stop layer, the first etch stop layer covers the surface of the oxide layer; an insulating layer, the insulating layer is located on the first etch stop layer; a first contact hole, the first contact hole passes through the insulating layer, the first etch stop layer and the oxide layer, and the bottom of the first contact hole exposes the top surface of the second electrode layer.

[0024] Optionally, the dielectric layer exposes a portion of the surface of the first electrode layer, the dielectric layer includes a plurality of discretely arranged sub-dielectric structures, and the second electrode layer includes a plurality of second sub-electrode structures, and the second sub-electrode structures correspond one-to-one to the sub-dielectric structures.

[0025] Optionally, the oxide layer covers the top of the first electrode layer, the sidewalls of the sub-dielectric structure, the sidewalls of the second sub-electrode structure and the top surface of the second sub-electrode structure.

[0026] Optionally, the semiconductor structure also includes: a thickening layer, the thickening layer covers the top surface of the second sub-electrode structure, the thickening layer is made of the same material as the oxide layer, and the oxide layer covers the top of the first electrode layer, the side walls of the sub-dielectric structure, the side walls of the second sub-electrode structure, the side walls of the thickening layer and the top surface of the thickening layer.

[0027] Compared with the prior art, the technical solution of the present invention has the following advantages:

[0028] After forming the second electrode layer and before forming the first etch stop layer, an oxide layer is formed on the second electrode layer, and the first etch stop layer covers the surface of the oxide layer. The oxide layer is located between the second electrode layer and the first etch stop layer, which can improve the bonding ability between the second electrode layer and the first etch stop layer, and enhance the adhesion strength between the second electrode plate and the first etch stop layer, thereby reducing the risk of delamination between the second electrode plate and the first etch stop layer, and preventing the second electrode plate and the first etch stop layer from forming a gap. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figures 1 to 9 is a schematic structural diagram corresponding to each step in the first embodiment of the semiconductor structure forming method of the present invention;

[0030] Figures 10 to 23 is a schematic structural diagram corresponding to each step in the second embodiment of the semiconductor structure forming method of the present invention;

[0031] Figure 24 to Figure 27 It is a schematic structural diagram corresponding to each step in the third embodiment of the semiconductor structure forming method of the present invention. DETAILED DESCRIPTION

[0032] Now, an analysis is conducted in combination with a method for forming a semiconductor structure. The process steps for forming the semiconductor structure mainly include: providing a substrate; forming a first electrode layer on the substrate; forming a dielectric layer on the first electrode layer; forming a second electrode layer on the dielectric layer; forming a first etch stop layer on the surface of the second electrode layer; forming an insulating layer on the first etch stop layer; etching the insulating layer and the first etch stop layer until the top surface of the second electrode layer is exposed to form a contact hole.

[0033] The lattice matching between the first etch stop layer material and the second electrode layer material is poor, resulting in poor adhesion between the first etch stop layer and the second electrode layer. Therefore, delamination is likely to occur between the first etch stop layer and the second electrode layer, affecting the packaging quality.

[0034] The inventors have studied the method for forming the above-mentioned semiconductor structure. Through creative work, the inventors noticed that by forming an oxide layer between the first etch stop layer and the second electrode layer, the first etch stop layer and the second electrode layer can be well bonded, thereby reducing the risk of stratification.

[0035] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0036] First embodiment

[0037] refer to Figure 1 , providing a substrate 100.

[0038] In this embodiment, the material of the substrate 100 is silicon. In other embodiments, the material of the substrate is germanium.

[0039] refer to Figure 2 , a first electrode layer 410 is formed on the substrate 100 .

[0040] In this embodiment, the material of the first electrode layer 410 is titanium nitride. In other embodiments, the material of the first electrode layer is tantalum nitride.

[0041] The first electrode layer 410 is formed by chemical vapor deposition or atomic layer deposition.

[0042] refer to Figure 3 , a dielectric layer 511 is formed on the first electrode layer 410 .

[0043] The material of the dielectric layer 511 is a high-K dielectric material. In this embodiment, the material of the dielectric layer 511 is HfO2; in other embodiments, the material of the dielectric layer may also be HfSiO, HfSiON, HfTaO, HfTiO, HfZrO or ZrO2.

[0044] refer to Figure 4 , a second electrode layer 421 is formed on the dielectric layer 511 .

[0045] The first electrode layer 410, the dielectric layer 511 and the second electrode layer 421 form a capacitor structure. The first electrode layer 410 serves as a lower plate of the capacitor structure, and the second electrode layer 421 serves as an upper plate of the capacitor structure.

[0046] The material of the second electrode layer 421 is the same as that of the first electrode layer 410. In this embodiment, the material of the second electrode layer 421 is titanium nitride. In other embodiments, the material of the second electrode layer is tantalum nitride.

[0047] refer to Figure 5 , an oxide layer 610 is formed on the second electrode layer 421 .

[0048] Subsequently, a first etch stop layer is formed on the surface of the oxide layer 610. The oxide layer 610 is located between the first etch stop layer and the second electrode layer 421. The oxide layer 610 can bond the first etch stop layer and the second electrode layer 421, thereby improving the bonding strength between the first etch stop layer and the second electrode layer 421, reducing the risk of stratification between the first etch stop layer and the second electrode layer 421, and improving the packaging quality.

[0049] refer to Figure 6 , forming a first etch stop layer 700 on the surface of the oxide layer 610 .

[0050] In this embodiment, the material of the first etch stop layer 700 is silicon carbonitride. In other embodiments, the material of the first etch stop layer is silicon carbon nitride oxide.

[0051] Subsequently, an insulating layer is formed on the first etch stop layer 700 , and an etching process is used to form a first contact hole. The first etch stop layer 700 serves as a stop layer for the etching process to reduce damage to the top surface of the second electrode layer 421 caused by the etching process.

[0052] refer to Figure 7 , an insulating layer 710 is formed on the first etch stop layer 700 .

[0053] The material of the insulating layer 710 is silicon oxide, silicon nitride, silicon carbonitride, silicon carbon nitride oxide, silicon nitride oxide, boron nitride or boron carbonitride. In this embodiment, the material of the insulating layer 710 is silicon oxide.

[0054] refer to Figure 8 , the insulating layer 710, the first etch stop layer 700 and the oxide layer 610 are etched to form a first contact hole 810, the bottom of the first contact hole 810 exposes the top surface of the second electrode layer 421, and the first contact hole 810 penetrates the insulating layer 710, the first etch stop layer 700 and the oxide layer 610.

[0055] In this embodiment, a wet etching process is used to form the first contact hole 810. In other embodiments, a dry etching process is used to form the first contact hole.

[0056] refer to Fig. 9 , a metal layer 900 is formed to fill the first contact hole 810 , and the top surface of the metal layer 900 is flush with the top surface of the insulating layer 710 .

[0057] The method for forming the metal layer 900 includes: forming a metal film (not shown in the figure) that fills the first contact hole 810, and the metal film covers the top surface of the insulating layer 710; using a chemical mechanical polishing process to remove the metal film located on the top surface of the insulating layer 710 to form the metal layer 900.

[0058] In this embodiment, the material of the metal film is copper. In other embodiments, the material of the metal film is aluminum.

[0059] Second embodiment

[0060] refer to Fig.10 , providing a substrate 100.

[0061] In this embodiment, the material of the substrate 100 is silicon. In other embodiments, the material of the substrate is germanium.

[0062] In this embodiment, the substrate 100 includes a first region I and a second region II.

[0063] refer to Fig.11 , forming a dielectric layer 200 on the surface of the substrate 100; etching the dielectric layer 200 to form a plurality of through holes in the dielectric layer 200; forming a conductive layer 210 filling the through holes, wherein the top of the conductive layer 210 is flush with the top of the dielectric layer 200.

[0064] The material of the dielectric layer 200 is an insulating material. In this embodiment, the material of the dielectric layer 200 is silicon oxide. In other embodiments, the material of the dielectric layer is silicon nitride, silicon carbonitride, silicon carbonitride oxide, silicon nitride oxide, boron nitride or boron carbonitride.

[0065] In this embodiment, the dielectric layer 200 is formed by a chemical vapor deposition process.

[0066] The method for forming the conductive layer 210 includes: forming a conductive film (not shown in the figure) that fills the through hole, and the conductive film covers the top of the dielectric layer 200; flattening the conductive film, removing the conductive film located on the top of the dielectric layer 200, and forming the conductive layer 210.

[0067] The conductive film is made of copper or aluminum. In this embodiment, the conductive film is made of copper.

[0068] In this embodiment, there are multiple through holes, some of which are located in the dielectric layer 200 in the first region I, and the rest of the through holes are located in the dielectric layer 200 in the second region II. Accordingly, there are multiple conductive layers 210.

[0069] refer to Fig.12 , forming a second etch stop layer 300 covering the top surface of the dielectric layer 200 and the top surface of the conductive layer 210 .

[0070] In this embodiment, the material of the second etch stop layer 300 is silicon carbonitride. In other embodiments, the material of the second etch stop layer is silicon carbon nitride oxide or silicon nitride oxide.

[0071] In this embodiment, an atomic layer deposition process is used to form the second etch stop layer 300. In other embodiments, a chemical vapor deposition process may also be used to form the second etch stop layer.

[0072] refer to Fig.13 , forming an interface layer 310 covering the top surface of the second etch stop layer 300 .

[0073] The first electrode layer formed subsequently covers the top surface of the interface layer 310 . The interface layer 310 can improve the bonding ability between the first electrode layer and the second etch stop layer 300 , and enhance the adhesion strength between the first electrode layer and the second etch stop layer 300 .

[0074] In this embodiment, the material of the interface layer 310 is silicon oxide. The silicon content of the interface layer 310 material is higher than that of the dielectric layer 200 material. The higher silicon content of the interface layer 310 material helps to improve the adhesion performance of the interface layer 310.

[0075] refer to Fig.14 , forming the first electrode layer 410 on the surface of the interface layer 310 .

[0076] In this embodiment, the first electrode layer 410 covers the top of the substrate 100 in the first region I and the second region II. Specifically, the first electrode layer 410 covers the surface of the interface layer 310 in the first region I and the second region II.

[0077] In this embodiment, the material of the first electrode layer 410 is titanium nitride. In other embodiments, the material of the first electrode layer is tantalum nitride.

[0078] The first electrode layer 410 is formed by a physical vapor deposition process or an atomic layer deposition process.

[0079] refer to Fig.15 and Fig.16 , a dielectric layer 511 is formed on the first electrode layer 410 ; a second electrode layer 421 is formed on the dielectric layer 511 ; and a thickening layer 600 is formed on the top surface of the second electrode layer 421 .

[0080] The dielectric layer 511 material is a high-K dielectric material. The dielectric layer 511 material is a ternary compound or a binary compound. In addition, the dielectric layer 511 material can also be a mixture of a ternary compound and a binary compound. The ternary compound is HfSiO, HfSiON, HfTaO, HfTiO or HfZrO. The binary compound is ZrO2, La2O3 or Al2O3.

[0081] The material of the dielectric layer 511 is a high-K dielectric material. In this embodiment, the material of the dielectric layer 511 is HfO2; in other embodiments, the material of the dielectric layer may also be HfSiO, HfSiON, HfTaO, HfTiO, HfZrO or ZrO2.

[0082] In this embodiment, the dielectric layer 511 exposes a portion of the surface of the first electrode layer 410 , and the dielectric layer 511 includes a plurality of discretely arranged sub-dielectric structures 510 .

[0083] In this embodiment, the dielectric layer 511 is located on the first electrode layer 410 in the second region II, and the dielectric layer 511 exposes a portion of the surface of the first electrode layer 410 in the second region II.

[0084] The material of the second electrode layer 421 is the same as that of the first electrode layer 410. In this embodiment, the material of the second electrode layer 421 is titanium nitride. In other embodiments, the material of the second electrode layer is tantalum nitride.

[0085] In this embodiment, the second electrode layer 421 includes a plurality of second sub-electrode structures 420 , and the second sub-electrode structures 420 correspond to the sub-dielectric structures 510 one by one.

[0086] The first electrode layer 410, the sub-dielectric structure 510 and the second sub-electrode structure 420 form a capacitor structure. The first electrode layer 410 serves as a lower plate of the capacitor structure, and the second sub-electrode structure 420 serves as an upper plate of the capacitor structure.

[0087] In this embodiment, the method of forming the dielectric layer 511, the second electrode layer 421 and the thickening layer 600 includes: referring to Fig.15 , forming a dielectric film 500 covering the entire surface of the first electrode layer 410; forming a second electrode film 400 covering the entire surface of the dielectric film 500; forming a thickened film 601 covering the entire second electrode film 400; forming a patterned layer (not shown in the figure) on part of the thickened film 601; referring to Fig.16 , using the patterned layer as a mask, etching part of the thickened film 601 (reference Fig.15 ), part of the second electrode film 400 (reference Fig.15 ) and part of the dielectric film 500 (reference Fig.15 ) until the surface of the first electrode layer 410 is exposed, the remaining second electrode film 400 forms the second electrode layer 421, and the remaining dielectric film 500 forms the dielectric layer 511.

[0088] The thickening layer 600 is used to increase the thickness of the adhesive material located on the top of the second sub-electrode structure 420 .

[0089] In this embodiment, the material of the thickening layer 600 is silicon oxide.

[0090] refer to Fig.17 , forming an oxide layer 610, the oxide layer 610 covers the top of the first electrode layer 410, the sidewalls of the sub-dielectric structure 510, the sidewalls of the second sub-electrode structure 420, the sidewalls of the thickening layer 600 and the top surface of the thickening layer 600.

[0091] The material of the oxide layer 610 is the same as that of the thickened layer 600. In this embodiment, the material of the oxide layer 610 is silicon oxide.

[0092] The function of the oxide layer 610 is described in detail below:

[0093] On the one hand, since the material of the thickening layer 600 is the same as that of the oxide layer 610, the thickening layer 600 also has good adhesion performance. The thickening layer 600 and the oxide layer 610 located on the top of the thickening layer 600 can play a role in bonding the second sub-electrode structure 420 and the first etch stop layer formed subsequently, thereby enhancing the adhesion strength between the second sub-electrode structure 420 and the first etch stop layer.

[0094] On the other hand, the oxide layer 610 covers the surface of the first electrode layer 410 exposed by the dielectric layer 511, and the first etch stop layer formed subsequently covers the entire surface of the oxide layer 610. Therefore, the oxide layer 610 can also improve the adhesion strength between the first electrode layer 410 and the first etch stop layer, and reduce the risk of stratification between the first electrode layer 410 and the first etch stop layer.

[0095] In addition, the oxide layer 610 covers the corners between the side walls of the second sub-electrode structure 420, the side walls of the sub-dielectric structure 510 and the top surface of the first electrode layer 410. Since the oxide layer 610 has good stress adjustment performance, the oxide layer 610 can offset the stress of the first etch stop layer at the corner, thereby avoiding the first etch stop layer from breaking at the corner due to excessive stress.

[0096] refer to Fig.18 , forming a first etch stop layer 700 on the surface of the oxide layer 610 .

[0097] In this embodiment, the material of the first etch stop layer 700 is silicon carbonitride. In other embodiments, the material of the first etch stop layer is silicon carbon nitride oxide.

[0098] In this embodiment, a chemical vapor deposition process is used to form the first etch stop layer 700. In other embodiments, an atomic layer deposition process or a physical vapor deposition process may also be used to form the first etch stop layer.

[0099] Due to the presence of the oxide layer 610, the first etch stop layer 700 can be firmly bonded to the top of the first electrode layer 410 and the top of the second sub-electrode structure 420, thereby reducing the risk of delamination between the first etch stop layer 700 and the top of the second sub-electrode structure 420, and also reducing the risk of delamination between the first etch stop layer 700 and the top of the first electrode layer 410, thereby improving packaging reliability. Furthermore, at the corner position between the side wall of the second sub-electrode structure 420, the side wall of the sub-dielectric structure 510 and the top surface of the first electrode layer 410, the stress generated in the first etch stop layer 700 can be offset by the stress generated by the oxide layer 610, thereby avoiding excessive concentration of stress in the first etch stop layer 700 at the corner position, so as to prevent the first etch stop layer 700 from cracking.

[0100] refer to Fig.19 , an insulating layer 710 is formed on the first etch stop layer 700 .

[0101] The material of the insulating layer 710 is silicon oxide, silicon nitride, silicon carbonitride, silicon carbon nitride oxide, silicon nitride oxide, boron nitride or boron carbonitride. In this embodiment, the material of the insulating layer 710 is silicon oxide.

[0102] In this embodiment, the top of the insulating layer 710 is flush.

[0103] The insulating layer 710 is formed by a chemical vapor deposition process, a physical vapor deposition process or an atomic layer deposition process. In this embodiment, the insulating layer 710 is formed by a chemical vapor deposition process.

[0104] refer to Fig. 20 , the insulating layer 710 , the first etch stop layer 700 , the oxide layer 610 , the first electrode layer 410 and the interface layer 310 in the first region I are etched away to expose the surface of the second etch stop layer 300 in the first region I.

[0105] refer to Fig.21 , an isolation layer 720 is formed on the surface of the second etch stop layer 300 in the first region I, and the isolation layer 720 is flush with the top of the insulating layer 710.

[0106] refer to Fig. 22 , the insulating layer 710, the first etch stop layer 700, the oxide layer 610 and the thickened layer 600 are etched to form a first contact hole 810, the bottom of the first contact hole 810 exposes the top surface of the second sub-electrode structure 420, and the first contact hole 810 penetrates the insulating layer 710, the first etch stop layer 700, the oxide layer 610 and the thickened layer 600.

[0107] In this embodiment, there are multiple first contact holes 810 , and the first contact holes 810 correspond to the second sub-electrode structures 420 one by one.

[0108] In this embodiment, the process of forming the first contact hole 810 also includes: etching the insulating layer 710, the first etch stop layer 700 and the oxide layer 610 located on one side of the second sub-electrode structure 420 to form a second contact hole 820, and the second contact hole 820 is located on the surface of the first electrode layer 410 exposed by the dielectric layer 511, and the second contact hole 820 penetrates the insulating layer 710, the etch stop layer and the oxide layer 610.

[0109] In this embodiment, the process of forming the first contact hole 810 and the second contact hole 820 also includes: etching the isolation layer 720 and the second etch stop layer 300 to form a third contact hole 830, the third contact hole 830 penetrates the isolation layer 720 and the second etch stop layer 300, and the bottom of the third contact hole 830 exposes one of the top surfaces of the conductive layer 210.

[0110] In this embodiment, the first contact hole 810 , the second contact hole 820 and the third contact hole 830 are formed in the same process step.

[0111] The material of the thickening layer 600 and the material of the oxide layer 610 are both adhesive materials. Since the top of the second sub-electrode structure 420 is covered with the thickening layer 600, the adhesive material located on the top surface of the second sub-electrode structure 420 is thicker than the adhesive material located on the top surface of the first electrode layer 410. By increasing the thickness of the adhesive material located on the top surface of the second sub-electrode structure 420 through the thickening layer 600, the time consumption of the formation process of the first contact hole 810 and the second contact hole 820 can be consistent, which facilitates the control of the process progress of the first contact hole 810 and the second contact hole 820.

[0112] In other embodiments, the first contact hole, the second contact hole and the third contact hole may be formed in steps. For example, the second contact hole is formed after the first contact hole, and the third contact hole is formed after the second contact hole.

[0113] refer to Fig.23 , a metal layer 900 is formed to fill the first contact hole 810 , the second contact hole 820 and the third contact hole 830 , and the top surface of the metal layer 900 is flush with the top surface of the insulating layer 710 .

[0114] The method for forming the metal layer 900 includes: forming a metal film (not shown in the figure) that fills the first contact hole 810, the second contact hole 820 and the third contact hole 830, and the metal film covers the top of the insulating layer 710 and the top surface of the isolation layer 720; flattening the metal film, removing the metal film located on the top of the insulating layer 710 and the top surface of the isolation layer 720, and forming the metal layer 900.

[0115] In this embodiment, the material of the metal film is copper. In other embodiments, the material of the metal film is aluminum.

[0116] In this embodiment, the metal layer 900 in the third contact hole 830 is electrically connected to the conductive layer 210 in the first region I.

[0117] Third embodiment

[0118] The differences between this embodiment and the second embodiment are described in detail below: The process steps of forming the first electrode layer 410 and before can refer to the second embodiment and will not be described in detail.

[0119] refer to Fig.24 and Fig.25 , a dielectric layer 511 is formed on the first electrode layer 410 ; and a second electrode layer 421 is formed on the dielectric layer 511 .

[0120] In this embodiment, the dielectric layer 511 exposes a portion of the surface of the first electrode layer 410 , and the dielectric layer 511 includes a plurality of discretely arranged sub-dielectric structures 510 .

[0121] In this embodiment, the second electrode layer 421 includes a plurality of second sub-electrode structures 420 , and the second sub-electrode structures 420 correspond to the sub-dielectric structures 510 one by one.

[0122] The method for forming the dielectric layer 511 and the second electrode layer 421 includes: referring to Fig.24 , forming a dielectric film 500 covering the entire surface of the first electrode plate; forming a second electrode film 400 covering the entire surface of the dielectric film 500; forming a patterned layer (not shown in the figure) on a portion of the second electrode film 400; referring to Fig.25 , using the patterned layer as a mask, etching a portion of the second electrode film 400 (reference Fig.24 ) and part of the dielectric film 500 (reference Fig.24 ) until the surface of the first electrode layer 410 is exposed, the remaining second electrode film 400 forms the second electrode layer 421, and the remaining dielectric film 500 forms the dielectric layer 511.

[0123] refer to Fig.26 , forming an oxide layer 610 , wherein the oxide layer 610 covers the top of the first electrode layer 410 , the sidewalls of the sub-dielectric structure 510 , the sidewalls of the second sub-electrode structure 420 , and the top surface of the second sub-electrode structure 420 .

[0124] refer to Fig. 27 After the oxide layer 610 is formed, the first etch stop layer 700, the insulating layer 710, the isolation layer 720, the first contact hole 810, the second contact hole 820, the third contact hole 830 and the metal layer 900 are formed in sequence.

[0125] In the process of forming the first contact hole 810 , the first contact hole 810 penetrates the oxide layer 610 , the first etch stop layer 700 , and the insulating layer 710 located on the top of the second sub-electrode structure 420 .

[0126] The formation process of the first etch stop layer 700 , the insulating layer 710 , the second contact hole 820 , the third contact hole 830 and the metal layer 900 may refer to the second embodiment and will not be described in detail.

[0127] The present invention also provides a semiconductor structure obtained by the above-mentioned forming method. Fig. 9 The semiconductor structure is obtained by the first embodiment of the formation method of the present invention.

[0128] Reference Fig. 9 In this embodiment, the semiconductor structure includes: a substrate 100; a first electrode layer 410, wherein the first electrode layer 410 is located on the substrate 100; a dielectric layer 511, wherein the dielectric layer 511 is located on the first electrode layer 410; a second electrode layer 421, wherein the second electrode layer 421 is located on the dielectric layer 511; an oxide layer 610, wherein the oxide layer 610 is located on the second electrode layer 421; a first etch stop layer 700, wherein the first etch stop layer 700 covers the surface of the oxide layer 610; an insulating layer 710, wherein the insulating layer 710 is located on the first etch stop layer 700; a first contact hole, wherein the first contact hole penetrates the insulating layer 710, the etch stop layer and the oxide layer 610, wherein the bottom of the first contact hole exposes the top surface of the second electrode layer 421; and a metal layer 900, wherein the metal layer 900 fills the first contact hole, and the top surface of the metal layer 900 is flush with the top surface of the insulating layer 710.

[0129] With the help of the oxide layer 610 , the first etch stop layer 700 and the second electrode layer 421 are firmly bonded together, preventing a gap from appearing between the first etch stop layer 700 and the second electrode layer 421 due to delamination, thereby improving packaging quality.

[0130] Fig.23 The semiconductor structure is obtained by the second embodiment of the formation method of the present invention.

[0131] refer to Fig.23 In this embodiment, the substrate 100 includes a first region I and a second region II.

[0132] In this embodiment, the first electrode layer 410 covers the top of the substrate 100 in the second region II.

[0133] In this embodiment, the dielectric layer exposes a portion of the surface of the first electrode layer 410 , and the dielectric layer includes a plurality of discretely arranged sub-dielectric structures 510 .

[0134] In this embodiment, the second electrode layer includes a plurality of second sub-electrode structures 420 , and the second sub-electrode structures 420 correspond to the sub-dielectric structures 510 one by one.

[0135] In this embodiment, the semiconductor structure further includes: a thickening layer 600, the thickening layer 600 covers the top surface of the second sub-electrode structure 420, and the thickening layer 600 is made of the same material as the oxide layer 610. The oxide layer 610 covers the top of the first electrode layer 410, the sidewalls of the sub-dielectric structure 510, the sidewalls of the second sub-electrode structure 420, the sidewalls of the thickening layer 600, and the top surface of the thickening layer 600.

[0136] In this embodiment, the material of the oxide layer 610 is silicon oxide.

[0137] On the one hand, the thickening layer 600 and the oxide layer 610 located on the top of the thickening layer 600 can play a role in bonding the second sub-electrode structure 420 and the first etch stop layer 700, thereby reducing the occurrence of delamination between the second sub-electrode structure 420 and the first etch stop layer 700.

[0138] On the other hand, the oxide layer 610 can also play a role in bonding the first electrode layer 410 and the first etch stop layer 700 to prevent a gap from appearing between the first electrode layer 410 and the first etch stop layer 700 due to delamination.

[0139] In addition, at the corners between the side walls of the second sub-electrode structure 420, the side walls of the sub-dielectric structure 510 and the top surface of the first electrode layer 410, the stress generated in the material of the first etch stop layer 700 can be offset by the oxide layer 610, which helps to improve the formation quality of the first etch stop layer 700 and reduce the risk of cracking of the first etch stop layer 700.

[0140] In this embodiment, the semiconductor structure further includes: a second contact hole 820 , which is located on the surface of the first electrode layer 410 exposed by the dielectric layer 511 , and the second contact hole 820 penetrates the insulating layer 710 , the first etch stop layer and the oxide layer 610 .

[0141] In this embodiment, the semiconductor structure further includes: a dielectric layer 200, wherein the dielectric layer 200 covers the surface of the substrate 100; a through hole, wherein the through hole penetrates the dielectric layer 200; a conductive layer 210, wherein the conductive layer 210 fills the through hole, and the top of the conductive layer 210 is flush with the top of the dielectric layer 200; a second etch stop layer 300, wherein the second etch stop layer 300 covers the top of the dielectric layer 200 and the top surface of the conductive layer 210; an interface layer 310, wherein the interface layer 310 covers the top surface of the second etch stop layer 300, and the first electrode layer 410 covers the top surface of the interface layer 310; and an isolation layer 720, wherein the isolation layer 720 covers the top surface of the interface layer 310 in the first region I, and the top of the isolation layer 720 is flush with the top of the insulating layer 710.

[0142] In this embodiment, the semiconductor structure further includes: a third contact hole 830 , wherein the third contact hole 830 penetrates the isolation layer 720 and the second etch stop layer 300 , and the bottom of the third contact hole 830 exposes the top surface of one of the conductive layers 210 .

[0143] In this embodiment, the semiconductor structure further includes: a metal layer 900 , the metal layer 900 completely fills the first contact hole 810 , the second contact hole 820 and the third contact hole 830 , and the top surface of the metal layer 900 is flush with the top surface of the insulating layer 710 .

[0144] Fig. 27 The semiconductor structure is obtained by the third embodiment of the forming method of the present invention.

[0145] The difference between the semiconductor structure obtained in this embodiment and the second embodiment is that the oxide layer 610 covers the top of the first electrode layer 410, the sidewalls of the sub-dielectric structure 510, the sidewalls of the second sub-electrode structure 420 and the top surface of the second sub-electrode structure 420. That is, the oxide layer 610 directly covers the top surface of the second sub-electrode structure 420.

[0146] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that: include: providing a substrate; forming a first electrode layer on the substrate; forming a dielectric layer on the first electrode layer; forming a second electrode layer on the dielectric layer; forming an oxide layer on the second electrode layer; forming a first etch stop layer on the surface of the oxide layer; forming an insulating layer on the first etch stop layer; The insulating layer, the first etch stop layer and the oxide layer are etched to form a first contact hole on the top of the second electrode layer, wherein the bottom of the first contact hole exposes the top surface of the second electrode layer, and the first contact hole penetrates the insulating layer, the first etch stop layer and the oxide layer.

2. The forming method according to claim 1, characterized in that: In the process of forming the dielectric layer, the dielectric layer exposes a portion of the surface of the first electrode layer, and the dielectric layer includes a plurality of discretely arranged sub-dielectric structures; in the process of forming the second electrode layer, the second electrode layer includes a plurality of second sub-electrode structures, and the second sub-electrode structures correspond one-to-one to the sub-dielectric structures.

3. The forming method according to claim 2, characterized in that: The method for forming the dielectric layer and the second electrode layer includes: forming a dielectric film covering the entire surface of the first electrode plate; forming a second electrode film covering the entire surface of the dielectric film; forming a patterned layer on a portion of the second electrode film; using the patterned layer as a mask, etching a portion of the second electrode film and a portion of the dielectric film until the surface of the first electrode layer is exposed, and the remaining second electrode film forms the second electrode layer, and the remaining dielectric film forms the dielectric layer.

4. The forming method according to claim 3, characterized in that: In the process of forming the oxide layer, the oxide layer covers the top of the first electrode layer, the sidewalls of the sub-dielectric structure, the sidewalls of the second sub-electrode structure and the top surface of the second sub-electrode structure.

5. The forming method according to claim 3, characterized in that: Before forming the oxide layer, the method further comprises: A thickening layer is formed on the top surface of the second sub-electrode structure, and the material of the thickening layer is the same as that of the oxide layer.

6. The forming method according to claim 5, characterized in that: The method for forming the thickening layer comprises: after forming the second electrode film and before forming the patterned layer, forming a thickening film covering the entire second electrode film, wherein the patterned layer covers a portion of the surface of the thickening film; in the process of etching a portion of the second electrode film and a portion of the dielectric film using the patterned layer as a mask, further comprising: A portion of the thickened film is etched, and the remaining thickened film forms the thickened layer.

7. The forming method according to claim 5, characterized in that: In the process of forming the oxide layer, the oxide layer covers the top of the first electrode layer, the sidewalls of the sub-dielectric structure, the sidewalls of the second sub-electrode structure, the sidewalls of the thickening layer and the top surface of the thickening layer.

8. The forming method according to claim 2, characterized in that: In the process of forming the first contact holes, there are multiple first contact holes, and the first contact holes correspond to the second sub-electrode structures one by one.

9. The forming method according to claim 2, characterized in that: The process of forming the first contact hole also includes: etching the insulating layer, the first etch stop layer and the oxide layer located on one side of the second sub-electrode structure to form a second contact hole, wherein the second contact hole is located on the surface of the first electrode layer exposed by the dielectric layer, and the second contact hole penetrates the insulating layer, the first etch stop layer and the oxide layer.

10. The forming method according to claim 9, characterized in that: After providing the substrate and before forming the first electrode layer, it also includes: forming a dielectric layer on the surface of the substrate; etching the dielectric layer to form a plurality of through holes in the dielectric layer; forming a conductive layer filling the through holes; forming a second etch stop layer covering the top of the dielectric layer and the top surface of the conductive layer; forming an interface layer covering the top surface of the second etch stop layer, and the first electrode layer covers the top surface of the interface layer.

11. The forming method according to claim 10, characterized in that: In the process of providing the substrate, the substrate includes a first region and a second region; in the process of forming the first electrode layer, the first electrode layer covers the top of the substrate in the first region and the second region; in the process of forming the dielectric layer, the dielectric layer is located on the first electrode layer in the second region, and the dielectric layer exposes a portion of the surface of the first electrode layer in the second region.

12. The forming method according to claim 11, characterized in that: After forming the insulating layer and before forming the first contact hole, it also includes: etching and removing the insulating layer, the first etch stop layer, the oxide layer, the first electrode layer and the interface layer in the first area; forming an isolation layer on the surface of the second etch stop layer in the first area, and the isolation layer is flush with the top of the insulating layer.

13. The forming method according to claim 12, characterized in that: The process of forming the first contact hole and the second contact hole also includes: etching the isolation layer and the second etch stop layer to form a third contact hole, wherein the third contact hole penetrates the isolation layer and the second etch stop layer, and the bottom of the third contact hole exposes one of the top surfaces of the conductive layers.

14. The forming method according to claim 13, characterized in that: After forming the first contact hole, the second contact hole and the third contact hole, the method further includes: forming a metal layer that fills the first contact hole, the second contact hole and the third contact hole, wherein the top surface of the metal layer is flush with the top surface of the insulating layer.

15. The forming method according to claim 14, characterized in that: The method for forming the metal layer includes: forming a metal film that fills the first contact hole, the second contact hole and the third contact hole, and the metal film covers the top surface of the insulating layer and the top surface of the isolation layer; flattening the metal film, removing the metal film located on the top surface of the insulating layer and the top surface of the isolation layer, and forming the metal layer.

16. The forming method according to claim 1, characterized in that: The material of the oxide layer is silicon oxide.

17. A semiconductor structure, characterized in that: include: substrate; a first electrode layer, wherein the first electrode layer is located on the substrate; a dielectric layer, wherein the dielectric layer is located on the first electrode layer; a second electrode layer, the second electrode layer being located on the dielectric layer; an oxide layer, wherein the oxide layer is located on the second electrode layer; A first etch stop layer, wherein the first etch stop layer covers a surface of the oxide layer; an insulating layer, wherein the insulating layer is located on the first etch stop layer; A first contact hole penetrates the insulating layer, the first etch stop layer and the oxide layer and is located on the top of the second electrode layer. The bottom of the first contact hole exposes the top surface of the second electrode layer.

18. The semiconductor structure according to claim 17, wherein: The dielectric layer exposes a portion of the surface of the first electrode layer. The dielectric layer includes a plurality of discretely arranged sub-dielectric structures. The second electrode layer includes a plurality of second sub-electrode structures. The second sub-electrode structures correspond one-to-one to the sub-dielectric structures.

19. The semiconductor structure according to claim 18, wherein: The oxide layer covers the top of the first electrode layer, the sidewalls of the sub-dielectric structure, the sidewalls of the second sub-electrode structure, and the top surface of the second sub-electrode structure.

20. The semiconductor structure according to claim 18, wherein: Also includes: A thickening layer, wherein the thickening layer covers the top surface of the second sub-electrode structure, the thickening layer is made of the same material as the oxide layer, and the oxide layer covers the top of the first electrode layer, the sidewalls of the sub-dielectric structure, the sidewalls of the second sub-electrode structure, the sidewalls of the thickening layer and the top surface of the thickening layer.

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