Method for manufacturing a semiconductor device

Abstract

A semiconductor device having good electrical characteristics is provided. A semiconductor device having stable electrical characteristics is provided. A semiconductor device having high reliability is provided. A semiconductor layer is formed, a gate insulating layer is formed over the semiconductor layer, a metal oxide layer is formed over the gate insulating layer, and a gate electrode is formed to overlap with a part of the semiconductor layer. Then, a first element is supplied to a region of the semiconductor layer which does not overlap with the gate electrode through the metal oxide layer and the gate insulating layer. As the first element, phosphorus, boron, magnesium, aluminum, silicon, and the like can be given. If the metal oxide layer is processed, this step is performed after the first element is supplied to the semiconductor layer.

Description

TECHNICAL FIELD

[0001] One embodiment of the present application relates to a semiconductor device and a manufacturing method thereof. One embodiment of the present application relates to a display device and a manufacturing method thereof.

[0002] Furthermore, one embodiment of the present application is not limited to the above technical field. Examples of a technical field to which one embodiment of the present application pertains are a semiconductor device, a display device, a light-emitting device, a power storage device, a memory device, an electronic device, a lighting device, an input device (e.g., a touch sensor), an input-output device (e.g., a touch panel), a driving method thereof, or a manufacturing method thereof. A semiconductor device refers to any device that can function by utilizing semiconductor characteristics. BACKGROUND

[0003] As a semiconductor material applicable to a transistor, an oxide semiconductor using a metal oxide has attracted attention. For example, Patent Document 1 discloses a semiconductor device in which a plurality of oxide semiconductor layers are stacked, an oxide semiconductor layer serving as a channel in the plurality of oxide semiconductor layers contains indium and gallium, and the proportion of indium is higher than that of gallium, so that the field-effect mobility (sometimes simply referred to as mobility or μFE) is increased.

[0004] Since a metal oxide that can be used for a semiconductor layer can be formed by a sputtering method or the like, it can be used for a semiconductor layer of a transistor included in a large display device. Furthermore, since the production equipment of a transistor using polycrystalline silicon or amorphous silicon can be partly modified and utilized, equipment investment can be suppressed. Furthermore, since a transistor using a metal oxide has high field-effect mobility as compared with a transistor using amorphous silicon, a high-performance display device provided with a driver circuit can be realized.

[0005] Furthermore, Patent Document 2 discloses a thin film transistor using an oxide semiconductor film including a low-resistance region containing at least one of aluminum, boron, gallium, indium, titanium, silicon, germanium, tin, and lead as a dopant in a source region and a drain region.

[0006] [Patent Document]

[0007] [Patent Document]

[0008] [Patent Document 1] Japanese Published Patent Application No. 2014-7399

[0009] [Patent Document 2] Japanese Published Patent Application No. 2011-228622 SUMMARY

[0010] PROBLEMS TO BE SOLVED BY THE INVENTION

[0011] One of objects of one embodiment of the present application is to provide a semiconductor device with good electric characteristics. One of objects of one embodiment of the present application is to provide a semiconductor device with stable electric characteristics. One of objects of one embodiment of the present application is to provide a semiconductor device with high reliability.

[0012] Note that the description of the above object does not preclude the existence of other objects. One embodiment of the present application does not necessarily achieve all of the above objects. An object other than those described above can be extracted from the description, drawings, or claims.

[0013] Means for solving the technical problem

[0014] One embodiment of the present application is a method for manufacturing a semiconductor device, including the steps of forming a semiconductor layer; forming a gate insulating layer over the semiconductor layer; forming a metal oxide layer over the gate insulating layer; forming a gate electrode overlapping with part of the semiconductor layer over the metal oxide layer; and supplying a first element to a region in the semiconductor layer which does not overlap with the gate electrode through the metal oxide layer and the gate insulating layer.

[0015] One embodiment of the present application is a method for manufacturing a semiconductor device, including the steps of forming a semiconductor layer; forming a gate insulating layer over the semiconductor layer; forming a metal oxide layer over the gate insulating layer; forming a gate electrode overlapping with part of the semiconductor layer over the metal oxide layer; supplying a first element to a region in the semiconductor layer which does not overlap with the gate electrode through the metal oxide layer and the gate insulating layer; and processing the metal oxide layer into an island shape after the first element is supplied to the semiconductor layer.

[0016] One embodiment of the present application is a method for manufacturing a semiconductor device, including the steps of forming a semiconductor layer; forming a gate insulating layer over the semiconductor layer; forming a metal oxide layer over the gate insulating layer; forming a gate electrode overlapping with part of the semiconductor layer over the metal oxide layer; supplying a first element to a region in the semiconductor layer which does not overlap with the gate electrode through the metal oxide layer and the gate insulating layer; supplying a second element to a region in the metal oxide layer which does not overlap with the gate electrode through the gate insulating layer; and processing the metal oxide layer into an island shape after the second element is supplied to the metal oxide layer. The second element can be supplied to the metal oxide layer after the first element is supplied to the semiconductor layer, or the first element can be supplied to the semiconductor layer after the second element is supplied to the metal oxide layer.

[0017] The first element is, for example, phosphorus, boron, magnesium, aluminum, or silicon. The second element is, for example, silicon, phosphorus, argon, krypton, xenon, arsenic, gallium, or germanium.

[0018] The metal oxide layer is preferably processed into an island shape by wet etching.

[0019] The metal oxide layer preferably comprises an aluminum oxide film. Alternatively, both the metal oxide layer and the semiconductor layer comprise the same metal oxide.

[0020] Preferably, the first heat treatment is performed after the metal oxide layer is formed and before the gate electrode is formed, and the second heat treatment is performed after the first element is supplied to the semiconductor layer. Preferably, the second heat treatment is performed at a temperature lower than that of the first heat treatment.

[0021] The semiconductor layer preferably comprises a metal oxide.

[0022] Invention Effects

[0023] According to one aspect of the present invention, a semiconductor device with good electrical characteristics can be provided. According to one aspect of the present invention, a semiconductor device with stable electrical characteristics can be provided. According to one aspect of the present invention, a semiconductor device with high reliability can be provided.

[0024] Note that the above description of effects does not preclude the existence of other effects. An embodiment of the invention does not necessarily need to have all the above-described effects. Effects other than those described above can be extracted from the description in the specification, drawings, and claims.

[0025] Brief description of the attached figures

[0026] [Figure 1] FIG. 1A This is a top view showing an example of a transistor. FIG. 1B , FIG. 1C This is a cross-sectional view showing an example of a transistor.

[0027] [Figure 2] FIG. 2A , FIG. 2B This is a cross-sectional view showing an example of a transistor.

[0028] [Figure 3] FIG. 3A This is a top view showing an example of a transistor. FIG. 3B , FIG. 3C This is a cross-sectional view showing an example of a transistor.

[0029] [Figure 4] FIG. 4A to FIG. 4C This is a cross-sectional view showing an example of a transistor.

[0030] [Figure 5] FIG. 5A to FIG. 5E This is a cross-sectional view illustrating an example of a transistor manufacturing method.

[0031] [Figure 6] FIG. 6A , FIG. 6B This is a cross-sectional view illustrating an example of a transistor manufacturing method.

[0032] [Figure 7] FIG. 7A , FIG. 7BFIG. 1 is a cross-sectional view showing one example of a manufacturing method of a transistor.

[0033] [FIG. 8] FIG. 8A to FIG. 8C FIG. 8 is a cross-sectional view showing one example of a manufacturing method of a transistor.

[0034] [FIG. 9] FIG. 9A to FIG. 9C FIG. 9 is a cross-sectional view showing one example of a manufacturing method of a transistor.

[0035] [FIG. 10] FIG. 10A to FIG. 10C FIG. 10 is a top view showing one example of a display device.

[0036] [ FIG. 11 ] FIG. 11 FIG. 11 is a cross-sectional view showing one example of a display device.

[0037] [ FIG. 12 ] FIG. 12 FIG. 12 is a cross-sectional view showing one example of a display device.

[0038] [ FIG. 13 ] FIG. 13 FIG. 13 is a cross-sectional view showing one example of a display device.

[0039] [ FIG. 14 ] FIG. 14 FIG. 14 is a cross-sectional view showing one example of a display device.

[0040] [FIG. 15] FIG. 15A FIG. 15 is a block diagram showing one example of a display device. FIG. 15B 、 FIG. 15C FIG. 16 is a circuit diagram showing one example of a display device.

[0041] [FIG. 16] FIG. 16A 、 FIG. 16C 、 FIG. 16D FIG. 16 is a circuit diagram showing one example of a display device. FIG. 16B FIG. 17 is a timing chart of a display device.

[0042] [FIG. 17] FIG. 17A 、 FIG. 17B FIG. 18 is a diagram showing one example of a display module.

[0043] [FIG. 18] FIG. 18A 、 FIG. 18B FIG. 19 is a diagram showing one example of an electronic device.

[0044] [FIG. 19] FIG. 19A to FIG. 19D FIG. 20 is a diagram showing one example of an electronic device.

[0045] [FIG. 20] FIG. 20A to FIG. 20E FIG. 21 is a diagram showing one example of an electronic device.

[0046] [Fig. 21] FIG. 21A to FIG. 21F is a diagram showing one example of an electronic device.

[0047] [ FIG. 22 ] FIG. 22 is a graph showing etching rates of metal oxide films according to Embodiment 1.

[0048] [Fig. 23] FIG. 23A , FIG. 23B is a cross-sectional observation photograph of a sample according to Embodiment 1.

[0049] [ FIG. 24 ] FIG. 24 is a graph showing electrical characteristics of a transistor according to Embodiment 1.

[0050] [ FIG. 25 ] FIG. 25 is a graph showing reliability evaluation results of a transistor according to Embodiment 1.

[0051] [Fig. 26] FIG. 26A to FIG. 26D is a graph showing electrical characteristics of a transistor according to Embodiment 2.

[0052] [ FIG. 27 ] FIG. 27 is a graph showing reliability evaluation results of a transistor according to Embodiment 2.

[0053] [ FIG. 28 ] FIG. 28 is a cross-sectional observation photograph of a sample according to Embodiment 2.

[0054] [Fig. 29] FIG. 29A , FIG. 29B is a graph showing structure analysis results and film densities of a sample according to Embodiment 3.

[0055] [ FIG. 30 ] FIG. 30 is a cross-sectional observation photograph of a sample according to Embodiment 3.

[0056] [ FIG. 31 ] FIG. 31 is a cross-sectional observation photograph of a sample according to Embodiment 3.

[0057] Embodiment

[0058] Embodiments are described in detail with reference to the accompanying drawings. Note that the present application is not limited to the following description, and it is easily possible for a person skilled in the art to understand that the mode and details thereof can be changed in various ways without departing from the spirit and scope of the present application. Therefore, the present application should not be interpreted as being limited to the contents described in the following embodiments.

[0059] Note that, in the drawings illustrating the inventive structures described below, the same symbols are used to show the same parts or parts having the same function in different drawings, and repeated description is omitted. Further, the same hatching is used when showing parts having the same function, and a symbol is not particularly added.

[0060] Further, for convenience of understanding, the position, size, range, and the like of each constituent element shown in the drawings are not necessarily shown as the actual position, size, range, and the like. Therefore, the disclosed application is not necessarily limited to the position, size, range, and the like disclosed in the drawings.

[0061] Further, depending on the case or state, the words "film" and "layer" can be interchanged. For example, a "conductive layer" can be changed to a "conductive film". Further, an "insulating film" can be changed to an "insulating layer".

[0062] Note that, in this specification and the like, the channel length direction of a transistor is one of directions parallel to a straight line connecting the source region and the drain region in the shortest distance. That is, the channel length direction corresponds to one of directions of current flowing through a semiconductor in the on state of the transistor. Further, the channel width direction is a direction orthogonal to the channel length direction. In addition, depending on the structure and shape of the transistor, the channel length direction and the channel width direction are not necessarily limited to one value.

[0063] Further, in this specification and the like, an off-state current refers to a drain current in the off state (also referred to as a non-conducting state, a blocking state) of a transistor, in the case where no particular description is given. In the case where no particular description is given, in an n-channel transistor, the off state refers to a state where the voltage V gs is lower than the threshold voltage V th( in a p-channel transistor. gs is higher than V th) .

[0064] (Embodiment 1)

[0065] In this embodiment, a semiconductor device of one embodiment of the present application and a manufacturing method thereof are described with reference to FIGS. 1 to 9. In this embodiment, a transistor is specifically described as a semiconductor device.

[0066] A semiconductor device of one embodiment of the present application is formed by the following steps: forming a semiconductor layer; forming a gate insulating layer over the semiconductor layer; forming a metal oxide layer over the gate insulating layer; forming a gate electrode overlapping with part of the semiconductor layer over the metal oxide layer; and supplying (also referred to as adding or injecting) a first element to a region of the semiconductor layer which does not overlap with the gate electrode through the metal oxide layer and the gate insulating layer.

[0067] In one embodiment of the invention, a first element is supplied to the semiconductor layer by sequentially passing through a metal oxide layer and a gate insulating layer. The layer into which the first element enters is most susceptible to damage. Therefore, by providing a metal oxide layer on the gate insulating layer and allowing the first element to enter the metal oxide layer first, damage to both the gate insulating layer and the semiconductor layer can be reduced. This, in turn, improves the reliability of the transistor.

[0068] The semiconductor layer preferably comprises a metal oxide. The following mainly describes the case where the semiconductor layer comprises a metal oxide.

[0069] Preferably, the first heat treatment is performed after the metal oxide layer is formed and before the gate electrode is formed. In the first heat treatment, oxygen is preferably supplied to the semiconductor layer from the gate insulating layer.

[0070] The gate insulating layer preferably comprises an oxide. The metal oxide layer preferably does not readily allow oxygen to permeate. This suppresses the release of oxygen contained in the gate insulating layer to the metal oxide layer side and promotes the supply of oxygen to the semiconductor layer. Therefore, oxygen vacancies in the semiconductor layer can be filled, and the reliability of the transistor can be improved.

[0071] Then, a gate electrode is formed and used as a mask to supply the first element to the semiconductor layer, thereby forming a pair of low-resistance regions in the semiconductor layer. That is, the semiconductor layer is formed in such a way that it includes a channel formation region overlapping the gate electrode and a pair of low-resistance regions sandwiching the channel formation region.

[0072] The first element is, for example, phosphorus, boron, magnesium, aluminum, or silicon.

[0073] The metal oxide layer is preferably designed to prevent hydrogen and water from permeating. This suppresses the release of hydrogen and water contained in the gate electrode to the metal oxide layer and inhibits their diffusion into the semiconductor layer. Consequently, it suppresses the increase in carrier density in the channel formation region of the semiconductor layer. When there are few oxygen vacancies and a low carrier density in the channel formation region of the semiconductor layer, the off-state current of the transistor can be significantly reduced, and the reliability of the transistor can be improved.

[0074] When processing the metal oxide layer into an island shape using the gate electrode as a mask, it is preferable to process the metal oxide layer after supplying the first element to the semiconductor layer. As described above, by supplying the first element to the semiconductor layer through the metal oxide layer, damage to the semiconductor layer and the gate insulating layer can be reduced. Furthermore, the first element can be supplied to the metal oxide layer at the same time as the first element is supplied to the semiconductor layer. This increases the etching rate of the metal oxide layer, resulting in different etching rates for the portions of the metal oxide layer overlapping with and not overlapping with the gate electrode. Therefore, shape defects in the metal oxide layer caused by etching can be suppressed.

[0075] Further, depending on the material and the forming conditions, it is sometimes difficult to process the metal oxide layer. In this case, it is preferable to supply the second element to the metal oxide layer and then process it. By supplying the second element, the crystallinity of the metal oxide layer is reduced, and thus the metal oxide layer is easily processed.

[0076] The second element is, for example, silicon, phosphorus, argon, krypton, xenon, arsenic, gallium, or germanium.

[0077] The order of the supply process of the first element and the supply process of the second element is not limited. Further, when both purposes (low resistance of the semiconductor layer and reduction of the crystallinity of the metal oxide layer) are achieved by supplying the same element, the element supply process can be performed only once.

[0078] For example, an aluminum oxide film can be used as the metal oxide layer. For example, by adding argon to the aluminum oxide film, etching of the aluminum oxide film can be easily performed.

[0079] Alternatively, the metal oxide layer and the semiconductor layer preferably contain the same metal oxide.

[0080] It is preferable to process the metal oxide layer by wet etching. By using wet etching, the gate insulating layer and the metal oxide layer can be prevented from being etched at the same time. Thus, the thickness of the gate insulating layer can be prevented from being reduced to make the thickness of the gate insulating layer uniform.

[0081] Further, the second heat treatment can be performed after the supply of the first element to the semiconductor layer. It is preferable to perform the first heat treatment at a high temperature (for example, 350°C) to supply sufficient oxygen from the gate insulating layer to the semiconductor layer. On the other hand, if the second heat treatment after the formation of the gate electrode and the supply of the first element to the semiconductor layer is performed at a high temperature, there is a concern that oxygen contained in the channel formation region of the semiconductor layer or the gate insulating layer diffuses to the low resistance region or the gate electrode. Therefore, it is preferable to perform the second heat treatment at a temperature lower than that of the first heat treatment.

[0082] Further, in one embodiment of the present application, the first element can also be supplied to the gate insulating layer. Specifically, when the gate electrode is used as a mask, the portion of the main semiconductor layer in the gate insulating layer that overlaps the low-resistance region is supplied with the first element, and the portion of the semiconductor layer that overlaps the channel formation region is not easily supplied with the first element. Therefore, oxygen is supplied from the gate insulating layer to the channel formation region in the second heat treatment, and this oxygen fills the oxygen vacancies of the channel formation region. On the other hand, since oxygen is not easily supplied from the gate insulating layer to the low-resistance region, the resistance of the low-resistance region does not easily increase. Thus, a semiconductor layer in which the channel formation region in which oxygen vacancies are sufficiently reduced and the carrier density is extremely low and the source region and the drain region in which the resistance is extremely low coexist can be formed, and a semiconductor device with excellent electrical characteristics and high reliability can also be achieved.

[0083] [Structural Example 1]

[0084] FIG. 1A A plan view of the transistor 100 is shown. FIG. 1B A cross-sectional view along the dot-dash line A1-A2 of FIG. 1A the transistor 100 is shown. FIG. 1C A cross-sectional view along the dot-dash line B1-B2 of FIG. 1A the transistor 100 is shown. The dot-dash line A1-A2 direction corresponds to the channel length direction, and the dot-dash line B1-B2 direction corresponds to the channel width direction. Note that FIG. 1A part of the transistor 100 (the gate insulating layer and the like) is omitted in the plan view of the transistor 100. The plan view of the transistor below also has part of the transistor omitted. FIG. 1A

[0085] The transistor 100 includes an insulating layer 103, an island-shaped semiconductor layer 108, a gate insulating layer 110, a metal oxide layer 114, a gate electrode 112, and an insulating layer 118.

[0086] The insulating layer 103 is provided over a substrate 102. The semiconductor layer 108 is provided over the insulating layer 103. The gate insulating layer 110 is in contact with the top surface of the insulating layer 103 and the top surface and side surface of the semiconductor layer 108. The metal oxide layer 114 is provided over the gate insulating layer 110. The metal oxide layer 114 has a portion overlapping with the semiconductor layer 108 with the gate insulating layer 110 interposed therebetween. The gate electrode 112 is provided over the metal oxide layer 114. The gate electrode 112 has a portion overlapping with the semiconductor layer 108 with the gate insulating layer 110 and the metal oxide layer 114 interposed therebetween. The insulating layer 118 is provided so as to cover the top surface of the gate insulating layer 110, the side surface of the metal oxide layer 114, and the top surface of the gate electrode 112.

[0087] The transistor 100 is a top-gate transistor including the gate electrode 112 over the semiconductor layer 108.

[0088] ​Further, as shown in FIG. 1A , FIG. 1B , the transistor 100 can include a conductive layer 120a and a conductive layer 120b over the insulating layer 118. One of the conductive layer 120a and the conductive layer 120b is used as a source electrode, and the other is used as a drain electrode. The conductive layer 120a and the conductive layer 120b are electrically connected to the subsequent low-resistance region 108n through an opening portion 141a and an opening portion 141b provided in the insulating layer 118 and the insulating layer 110, respectively.

[0089] The semiconductor layer 108 preferably contains a metal oxide having semiconductor properties (hereinafter also referred to as an oxide semiconductor).

[0090] The semiconductor layer 108 includes a region overlapping with the gate electrode 112 and a pair of low-resistance regions 108n sandwiching the region. The region of the semiconductor layer 108 overlapping with the gate electrode 112 is used as a channel formation region in which a channel of the transistor 100 is formed. The pair of low-resistance regions 108n is used as a source region and a drain region of the transistor 100.

[0091] Further, the low-resistance region 108n can be referred to as a region having lower resistance, a region having higher carrier concentration, a region having higher oxygen defect density, a region having higher impurity concentration, or a region exhibiting n-type than the channel formation region.

[0092] The low-resistance region 108n is a region containing one or plural kinds of impurity elements. As the impurity elements, for example, hydrogen, boron, carbon, nitrogen, fluorine, phosphorus, sulfur, arsenic, aluminum, magnesium, silicon, and a rare gas (helium, neon, argon, krypton, xenon, and the like) can be given. The pair of low-resistance regions 108n preferably contains boron, phosphorus, aluminum, magnesium, or silicon, and more preferably contains boron or phosphorus.

[0093] Further, part of the above impurity elements contained in the low-resistance region 108n sometimes diffuses into the channel formation region due to the influence of heat applied in a manufacturing process or the like. The impurity element concentration in the channel formation region is preferably lower than one-tenth, and more preferably lower than one percent, of the impurity element concentration in the low-resistance region 108n.

[0094] The gate insulating layer 110 includes a region in contact with the channel formation region of the semiconductor layer 108 and overlapping with the gate electrode 112. The gate insulating layer 110 also includes a region in contact with the pair of low-resistance regions 108n of the semiconductor layer 108 and not overlapping with the gate electrode 112.

[0095] When the semiconductor layer 108 contains a metal oxide, the gate insulating layer 110 preferably contains an oxide. The gate insulating layer 110 is particularly preferably an oxide film from which oxygen is released by heating.

[0096] In a state where the gate insulating layer 110 containing an oxide is provided in contact with the top surface of the semiconductor layer 108, heat treatment is performed, whereby oxygen released from the gate insulating layer 110 can be supplied to the semiconductor layer 108. Thus, oxygen vacancies in the semiconductor layer 108 can be filled, and a transistor with high reliability can be implemented.

[0097] In one embodiment of the present application, heat treatment is performed before the gate electrode 112 is formed and impurity elements are supplied to the semiconductor layer 108, and oxygen is supplied to the semiconductor layer 108 from the gate insulating layer 110. On the other hand, depending on the structure of a transistor or a semiconductor device or a display device including the transistor, or the like, heat treatment is sometimes performed after the gate electrode 112 is formed and impurity elements are supplied to the semiconductor layer 108. In this case, there is a concern that oxygen contained in the channel formation region of the semiconductor layer 108 diffuses to the low-resistance regions 108n or the gate electrode 112. Further, oxygen can be supplied to the low-resistance regions 108n from the gate insulating layer 110. When oxygen is supplied to the low-resistance regions 108n, the carrier density is sometimes reduced and the resistance is increased.

[0098] Thus, the region of the gate insulating layer 110 which is in contact with the pair of low-resistance regions 108n, i.e., the region which does not overlap with the gate electrode 112, preferably contains the impurity element described above. The region of the gate insulating layer 110 which does not overlap with the gate electrode 112 preferably includes a region with a higher impurity concentration than the region of the gate insulating layer 110 which overlaps with the gate electrode 112 and a lower impurity concentration than the low-resistance regions 108n. By supplying the impurity element described above to the oxide film from which oxygen is released by heat, the amount of released oxygen can be reduced. Thus, when the region of the gate insulating layer 110 which is in contact with the low-resistance regions 108n contains the impurity element described above, oxygen is less likely to be supplied to the low-resistance regions 108n from the gate insulating layer 110, and thus the low-resistance regions 108n can maintain a low-resistance state.

[0099] With such a structure, a semiconductor device including a channel formation region in which oxygen vacancies are sufficiently reduced and the carrier density is extremely low, and source and drain regions whose resistance is extremely low, and which have good electrical characteristics and high reliability can be implemented.

[0100] Further, the insulating layer 103 and the gate insulating layer 110 which are in contact with the channel formation region of the semiconductor layer 108 preferably contain an oxide. For example, the insulating layer 103 and the gate insulating layer 110 can use a silicon oxide film, a silicon oxynitride film, an aluminum oxide film, or the like. Thus, oxygen released from the insulating layer 103 or the gate insulating layer 110 by heat treatment or the like in the manufacturing process of the transistor 100 is supplied to the channel formation region of the semiconductor layer 108, whereby oxygen vacancies in the semiconductor layer 108 can be reduced.

[0101] FIG. 2A is amplifiedFIG. 1B a cross-sectional view of the region P surrounded by the dotted line in FIG. 10.

[0102] The gate insulating layer 110 has a region 110d containing the impurity element described above. The region 110d is at least located at or near the interface with the low-resistance region 108n. The region 110d is also at least located at or near the interface with the insulating layer 103 in a region where the semiconductor layer 108 and the gate electrode 112 are not provided. Further, as shown in FIG. 10, the region 110d is preferably not provided in a portion that contacts the channel formation region of the semiconductor layer 108. FIG. 1B FIG. 1C FIG. 2A As shown in FIG. 10, the region 110d is preferably not provided in a portion that contacts the channel formation region of the semiconductor layer 108.

[0103] Further, the insulating layer 103 includes a region 103d containing the impurity element described above at or near the interface with the gate insulating layer 110. As shown in FIG. 10, the region 103d is also provided at or near the interface with the low-resistance region 108n. At this time, the impurity concentration of the portion overlapping with the low-resistance region 108n is lower than that of the portion in contact with the gate insulating layer 110. FIG. 2A

[0104] Here, the impurity concentration of the low-resistance region 108n preferably has a concentration gradient that is higher near the gate insulating layer 110. Thus, the resistance is lower as the upper portion of the low-resistance region 108n is approached, so that the contact resistance between the low-resistance region 108n and the conductive layer 120a (or the conductive layer 120b) can be reduced more effectively. Further, compared with the case where the concentration is uniform throughout the low-resistance region 108n, the total amount of the impurity element in the low-resistance region 108n can be further reduced, so that the amount of the impurity element which can possibly diffuse into the channel formation region due to the influence of heating in a manufacturing process or the like can be kept at a low level.

[0105] Further, the impurity concentration of the region 110d preferably has a concentration gradient that is higher near the low-resistance region 108n. In the gate insulating layer 110 using an oxide film capable of releasing oxygen by heating, the region 110d containing the impurity element can suppress the release of oxygen as compared with other regions. Thus, the region 110d located at or near the interface with the low-resistance region 108n of the gate insulating layer 110 is used as an oxygen barrier layer, so that the supply of oxygen to the low-resistance region 108n can be reduced effectively.

[0106] The gate electrode 112 is used as a mask to supply the impurity element to at least the semiconductor layer 108. Further, it is preferable that the gate insulating layer 110 is also supplied with the impurity element. Thus, the region 110d can be formed self-alignedly at the same time when the low-resistance region 108n is formed.

[0107] In the case where the low-resistance region 108n is formed by implantation of an impurity element, the region 110d can be formed at the same time when the low-resistance region 108n is formed. FIG. 2A ​​​In the drawings, in order to exaggerate the fact that the high impurity concentration portion of the gate insulating layer 110 is located at or near the interface with the semiconductor layer 108, the region 110d is shown by hatching only in the vicinity of the semiconductor layer 108 in the gate insulating layer 110, but in fact the above-mentioned impurity element is contained in the entire thickness direction of the gate insulating layer 110.

[0108] The supply of the impurity element is preferably performed by a plasma ion doping method or an ion implantation method. Since the depth of the added ions is easily adjusted in these methods, the added ions can be easily aimed at the region including the gate insulating layer 110 and the semiconductor layer 108.

[0109] The supply conditions of the impurity element are preferably set in such a manner that the impurity concentration is highest in the region of the semiconductor layer 108 on the side of the gate insulating layer 110 or at or near the interface of the semiconductor layer 108 and the gate insulating layer 110. Thereby, the impurity element of an appropriate concentration can be supplied to both the semiconductor layer 108 and the gate insulating layer 110 in one process. Further, by supplying the impurity element of a high concentration to the upper portion of the low-resistance region 108n to lower the resistance thereof, the contact resistance of the low-resistance region 108n to the source electrode or the drain electrode can be further reduced. In addition, by forming a region of a high impurity element concentration in the portion adjacent to the low-resistance region 108n of the gate insulating layer 110, the oxygen diffusivity of the portion is effectively reduced, and the diffusion of oxygen in the gate insulating layer 110 to the side of the low-resistance region 108n can be more effectively suppressed.

[0110] The low-resistance region 108n and the region 110d preferably respectively include a region in which the impurity concentration is 1 x 10 19 atoms / cm 3 or more and 1 x 10 23 atoms / cm 3 or less. Hereinafter, a region in which the impurity concentration is preferably 5 x 10 19 atoms / cm 3 or more and 5 x 10 22 atoms / cm 3 or less is more preferable. Further, a region in which the impurity concentration is more preferably 1 x 10 20 atoms / cm 3 or more and 1 x 10 22 atoms / cm 3 or less is further preferable. Furthermore, the low-resistance region 108n preferably has a portion in which the impurity concentration is higher than that of the region 110d of the gate insulating layer 110, and thereby the resistance of the low-resistance region 108n can be further reduced.

[0111] For example, the concentration of impurities included in the low-resistance region 108n and the region 110d can be analyzed by analysis methods such as secondary ion mass spectrometry (SIMS), X-ray photoelectron spectroscopy (XPS), and the like. In the case of analysis by XPS, by combining ion sputtering from the surface side or the back surface side and XPS analysis, the concentration distribution in the depth direction can be known.

[0112] In the case where an element that easily bonds with oxygen is used as the impurity element, the impurity element exists in a state of bonding with oxygen in the semiconductor layer 108. That is, because the impurity element takes oxygen in the semiconductor layer 108, an oxygen vacancy is generated in the semiconductor layer 108, which bonds with hydrogen in the film to generate a carrier. Further, the impurity element in the semiconductor layer 108 stably exists in an oxidized state, and thus is not easily detached due to heat or the like applied in a process, and thus a low-resistance region 108n that is stable in a low-resistance state can be achieved.

[0113] In the case where an element that easily bonds with oxygen is used as the impurity element, as in the semiconductor layer 108, the impurity element also exists in a state of bonding with oxygen in the gate insulating layer 110. Because the oxygen and the impurity element are bonded and thus stabilized, even if heating is performed, the region including the impurity element becomes a state in which oxygen is hardly detached, that is, a state in which oxygen is not easily diffused to other layers. Thus, oxygen can be supplied to the channel formation region while suppressing the supply of oxygen from the gate insulating layer 110 to the low-resistance region 108n. Therefore, the oxygen vacancy in the channel formation region can be reduced while preventing the increase in the resistance of the low-resistance region 108n. As a result, a transistor that is excellent in electric characteristics and high in reliability can be achieved.

[0114] As the impurity element, an element that is stabilized by bonding with oxygen in the semiconductor layer 108 and the gate insulating layer 110 is preferably used. For example, an element that exists as a solid in the case where the oxide is in a standard state is preferably used. As particularly preferable elements, noble gas, typical non-metal elements other than hydrogen, typical metal elements, and transition metal elements can be given. Boron, phosphorus, aluminum, magnesium, and silicon are particularly preferably used.

[0115] For example, in the case where boron is used as the impurity element, the boron included in the low-resistance region 108n and the region 110d can exist in a state of bonding with oxygen. This can be confirmed by observing a spectral peak due to B2O3 bonding in XPS analysis. Further, in XPS analysis, a peak due to the state in which boron exists alone is not observed or the peak intensity thereof is extremely small to the extent of being buried in the background noise of the detection lower limit.

[0116] The metal oxide layer 114 is formed of a material that is not easily permeable to oxygen and hydrogen. The metal oxide layer 114 has a function of suppressing diffusion of oxygen contained in the gate insulating layer 110 to the side of the gate electrode 112. The metal oxide layer 114 has a function of suppressing diffusion of hydrogen and water contained in the gate electrode 112 to the side of the gate insulating layer 110. The metal oxide layer 114 preferably uses a material that is not easily permeable to oxygen and hydrogen at least compared with the gate insulating layer 110.

[0117] By providing the metal oxide layer 114, even if a material that easily sucks oxygen such as aluminum or copper is used for the gate electrode 112, diffusion of oxygen from the gate insulating layer 110 to the gate electrode 112 can be suppressed. Further, even if the gate electrode 112 contains hydrogen, diffusion of hydrogen from the gate electrode 112 to the semiconductor layer 108 through the gate insulating layer 110 can be suppressed. As a result, the carrier density in the channel formation region of the semiconductor layer 108 can be made extremely low.

[0118] The metal oxide layer 114 can be an insulating layer or a conductive layer. In the case where the metal oxide layer 114 is an insulating layer, the metal oxide layer 114 can be said to be part of the gate insulating layer 110. In the case where the metal oxide layer 114 is a conductive layer, the metal oxide layer 114 can be said to be part of the gate electrode 112.

[0119] As the metal oxide layer 114, an insulating material whose dielectric constant is higher than that of silicon oxide is preferably used. In particular, an aluminum oxide film, a hafnium oxide film, or a hafnium aluminate film, or the like is preferably used because the driving voltage can be reduced.

[0120] As the metal oxide layer 114, for example, an electrically conductive oxide such as indium oxide, indium tin oxide (ITO), or indium tin oxide containing silicon (ITSO) can be used. In particular, an electrically conductive oxide containing indium is preferably used because the conductivity is high.

[0121] Further, as the metal oxide layer 114, an oxide material containing one or more elements that are the same as those of the semiconductor layer 108 is preferably used. In particular, an oxide semiconductor material that can be applied to the semiconductor layer 108 is preferably used. At this time, by using a metal oxide film formed using the same sputtering target as that of the semiconductor layer 108 as the metal oxide layer 114, equipment can be shared, which is preferable.

[0122] Further, in the case where a metal oxide material containing indium and gallium is used for both the semiconductor layer 108 and the metal oxide layer 114, by using a material whose gallium composition (content ratio) is higher than that of the semiconductor layer 108, the barrier property against oxygen can be improved, which is preferable. At this time, by using a material whose indium composition is higher than that of the metal oxide layer 114 for the semiconductor layer 108, the field-effect mobility of the transistor 100 can be improved.

[0123] Further, the metal oxide layer 114 is preferably formed using a sputtering apparatus. For example, when an oxide film is formed using a sputtering apparatus, oxygen can be supplied to the gate insulating layer 110 or the semiconductor layer 108 by forming the oxide film in an atmosphere containing oxygen gas.

[0124] When the metal oxide layer 114 is a conductive layer, the manufacturing process of the transistor 100 includes a step of processing the metal oxide layer 114 into an island shape. Further, the metal oxide layer 114 can be processed into an island shape even when the metal oxide layer 114 is an insulating layer. At this time, depending on the material and the processing method, it is sometimes difficult to perform the processing.

[0125] For example, FIG. 2B The region Q in FIG. 1A shows an example in which a part (lower part) of the portion of the metal oxide layer 114 overlapping with the gate electrode 112 is etched. In this manner, a shape defect occurs in the metal oxide layer 114, which leads to a decrease in coverage of the insulating layer 118.

[0126] In this embodiment, in one embodiment of the present application, the semiconductor layer 108 is supplied with an impurity element by the metal oxide layer 114. Thus, the metal oxide layer 114 is also supplied with the impurity element, so that the etching rate of the metal oxide layer 114 can be increased. Accordingly, the etching rate of the portion of the metal oxide layer 114 overlapping with the gate electrode 112 and the portion thereof not overlapping with the gate electrode 112 can be made different. Thus, the portion of the metal oxide layer 114 overlapping with the gate electrode 112 is less likely to be etched, so that a shape defect of the metal oxide layer 114 can be suppressed. Further, the coverage of the insulating layer 118 can be increased and a coverage defect can be suppressed.

[0127] The gate electrode 112 and the metal oxide layer 114 are processed so that the top surface shapes thereof are substantially the same. The gate electrode 112 can be used as a mask to be processed to form the metal oxide layer 114 in an island shape.

[0128] In this specification and the like, "the top surface shapes are substantially the same" means that at least a part of the profile of each of the layers in the stack is overlapped. For example, a case where an upper layer is processed using a lower layer as a mask, a case where one or both of an upper layer and a lower layer are processed by the same mask pattern, or the like is included. However, there is a case where the profiles are not overlapped, for example, a case where an upper layer is positioned inside a lower layer or a case where an upper layer is positioned outside a lower layer, which can also be said "the top surface shapes are substantially the same".

[0129] The insulating layer 118 is used as a protective layer for protecting the transistor 100. The insulating layer 118 preferably has a function of preventing oxygen which might be released from the gate insulating layer 110 from diffusing to the outside. For example, an inorganic insulating material such as an oxide or a nitride can be used. Specifically, an inorganic insulating material such as silicon nitride, silicon oxynitride, silicon oxy-nitride, aluminum oxide, aluminum oxynitride, aluminum nitride, hafnium oxide, hafnium aluminate, or the like can be used.

[0130] [Structure Example 2]

[0131] FIG. 3A A top view of transistor 100A is shown. FIG. 3B Show along FIG. 3A The cross-sectional view of the dotted-dash line A1-A2. FIG. 3C Show along FIG. 3A The cross-sectional view of the dashed-dot line B1-B2. The direction of the dashed-dot line A1-A2 corresponds to the length direction of the channel, and the direction of the dashed-dot line B1-B2 corresponds to the width direction of the channel.

[0132] The difference between transistor 100A and transistor 100 is that a conductive layer 106 is included between the substrate 102 and the insulating layer 103. The conductive layer 106 has a region that overlaps with the semiconductor layer 108 and the gate electrode 112.

[0133] In transistor 100A, conductive layer 106 functions as a first gate electrode (also known as a bottom gate electrode), and gate electrode 112 functions as a second gate electrode (also known as a top gate electrode). Furthermore, a portion of insulating layer 103 is used as a first gate insulating layer, and a portion of gate insulating layer 110 is used as a second gate insulating layer.

[0134] The portion of the semiconductor layer 108 that overlaps with at least one of the gate electrode 112 and the conductive layer 106 is used as a channel formation region. Hereinafter, for ease of explanation, the portion of the semiconductor layer 108 that overlaps with the gate electrode 112 is sometimes referred to as the channel formation region, but in practice, the channel is sometimes also formed in the portion that does not overlap with the gate electrode 112 but overlaps with the conductive layer 106 (including the portion of the low-resistance region 108n).

[0135] In addition, such as FIG. 3C As shown, the conductive layer 106 can be electrically connected to the gate electrode 112 through openings 142 provided in the metal oxide layer 114, the gate insulating layer 110, and the insulating layer 103. Therefore, the conductive layer 106 and the gate electrode 112 can be supplied with the same potential.

[0136] As the conductive layer 106, the same material as the gate electrode 112, conductive layer 120a, or conductive layer 120b can be used. In particular, it is preferred to use a material containing copper for the conductive layer 106, as this can reduce wiring resistance.

[0137] In addition, such as FIG. 3A , FIG. 3C As shown, preferably, the gate electrode 112 and the conductive layer 106 protrude to the outer side of the end of the semiconductor layer 108 in the channel width direction. At this time, as... FIG. 3CAs shown, the gate electrode 112 and the conductive layer 106 cover the entire channel width direction of the semiconductor layer 108 through the gate insulating layer 110 and the insulating layer 103.

[0138] By employing the above structure, an electric field generated by a pair of gate electrodes can be used to surround the semiconductor layer 108. In this case, it is particularly preferable to supply the conductive layer 106 and the gate electrode 112 with the same potential. This allows an electric field to be effectively applied to the semiconductor layer 108 to induce a channel, thereby increasing the on-state current of the transistor 100A. Therefore, miniaturization of the transistor 100A can be achieved.

[0139] Furthermore, the gate electrode 112 may not be connected to the conductive layer 106. In this case, a fixed potential can be supplied to one of the pair of gate electrodes, and a signal for driving the transistor 100A can be supplied to the other. In this case, the threshold voltage when driving the transistor 100A with the other electrode can be controlled by utilizing the potential supplied to one electrode.

[0140] [Application Examples]

[0141] Next, as an application example, a semiconductor device of one aspect of the present invention, including a transistor and a capacitor, will be described with reference to FIG4. Specifically, an example will be described in which a semiconductor layer 108c containing impurities is used as one electrode of the capacitor and the transistor and capacitor are formed on the same surface.

[0142] With transistor 100 ( FIG. 1A to FIG. 1C Arranged in a specific pattern FIG. 4A The capacitor shown is 130A.

[0143] With transistor 100A ( FIG. 3A to FIG. 3C Arranged in a specific pattern FIG. 4B The capacitor shown is 130A.

[0144] The capacitor 130A has a structure in which a gate insulating layer 110 and an insulating layer 118, which serve as dielectrics, are disposed between the semiconductor layer 108c and the conductive layer 120b.

[0145] Semiconductor layer 108c is disposed on the same surface as semiconductor layer 108. For example, semiconductor layer 108c can be formed by supplying the same impurity elements as the low-resistance region 108n after processing the same metal oxide film as semiconductor layer 108.

[0146] By adopting such a structure, transistors and capacitors 130A can be manufactured simultaneously without adding manufacturing steps.

[0147] FIG. 4C The capacitor 130B and transistor 100A shown are FIG. 3A to FIG. 3C Arranged in a specific order.

[0148] The capacitor 130B has a structure in which an insulating layer 103 used as a dielectric is provided between the conductive layer 106c and the semiconductor layer 108c.

[0149] The conductive layer 106c is provided on the same face as the conductive layer 106. The conductive layer 106c can be formed by processing the same conductive film as the conductive layer 106.

[0150] The thickness of the dielectric in the capacitor 130B can be smaller than that of the capacitor 130A, and thus a capacitor with a larger capacitance can be realized.

[0151] [Components of Semiconductor Device]

[0152] Components included in the semiconductor device according to the present embodiment will be described in detail below. Note that the description of the components already described will be omitted in some cases.

[0153] Although there is no particular limitation on the material of the substrate 102, at least heat resistance capable of withstanding a subsequent heat treatment is required. For example, a single-crystal semiconductor substrate or a polycrystal semiconductor substrate using silicon or silicon carbide as a material, a compound semiconductor substrate such as silicon germanium, an SOI substrate, a glass substrate, a ceramic substrate, a quartz substrate, a sapphire substrate, or the like can be used as the substrate 102. Further, the above-described substrate provided with a semiconductor element can be used as the substrate 102.

[0154] Further, a flexible substrate can be used as the substrate 102, and a transistor 100 or the like can be formed directly over the flexible substrate. Alternatively, a separation layer can be provided between the substrate 102 and the transistor 100 or the like. The separation layer can be used when part or all of a semiconductor device is manufactured over the separation layer, and then separated from the substrate 102 and transferred to another substrate. At this time, the transistor 100 or the like can be transferred to a substrate with low heat resistance or a flexible substrate.

[0155] The insulating layer 103 can be formed using a single layer or a stack of an oxide insulating film or a nitride insulating film, for example. Note that in order to improve the interface characteristics of the insulating layer 103 and the semiconductor layer 108, at least a region of the insulating layer 103 in contact with the semiconductor layer 108 is preferably formed using an oxide insulating film. Further, the insulating layer 103 is preferably formed using a film that releases oxygen by heating.

[0156] The insulating layer 103 can be formed using silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, hafnium oxide, gallium oxide, Ga-Zn oxide, or the like, and be provided in a stack or a single layer.

[0157] Further, when a film other than an oxide film such as a silicon nitride film is used on the side of the insulating layer 103 in contact with the semiconductor layer 108, it is preferable that the surface in contact with the semiconductor layer 108 be subjected to pretreatment such as oxygen plasma treatment to oxidize the surface or the vicinity of the surface.

[0158] The gate electrode 112, the conductive layer 106 serving as a gate electrode, and the conductive layers 120a and 120b serving as source and drain electrodes can each be formed using a metal element selected from chromium, copper, aluminum, gold, silver, zinc, molybdenum, tantalum, titanium, tungsten, manganese, nickel, iron, cobalt, an alloy containing the above metal element, or an alloy containing a combination of the above metal elements.

[0159] Further, the gate electrode 112, the conductive layer 106, the conductive layer 120a, and the conductive layer 120b can use an oxide conductor (OC: Oxide Conductor) such as an In-Sn oxide, an In-W oxide, an In-W-Zn oxide, an In-Ti oxide, an In-Ti-Sn oxide, an In-Zn oxide, an In-Sn-Si oxide, or an In-Ga-Zn oxide, or a metal oxide film.

[0160] Further, by forming an oxygen vacancy in a metal oxide having a semiconductor property and adding hydrogen to the oxygen vacancy, a donor level is formed in the vicinity of a conduction band. Thus, the metal oxide becomes a conductor by increasing the conductivity, and the metal oxide that has become a conductor can be referred to as an oxide conductor (OC).

[0161] Further, the gate electrode 112 and the conductive layer 106 can each have a stacked structure of a conductive film containing the above oxide conductor (metal oxide) and a conductive film containing a metal or an alloy. By using a conductive film containing a metal or an alloy, the wiring resistance can be reduced. Note that it is preferable that the conductive film containing the oxide conductor be used on the side of the gate electrode 112 in contact with the gate insulating layer 110 or on the side of the conductive layer 106 in contact with the insulating layer 103.

[0162] Further, the gate electrode 112, the conductive layer 106, the conductive layer 120a, and the conductive layer 120b each preferably contain any one or a plurality of elements selected from titanium, tungsten, tantalum, and molybdenum among the above metal elements. In particular, a tantalum nitride film is preferably used. The tantalum nitride film has conductivity and has high barrier properties against copper, oxygen, or hydrogen, and releases less hydrogen from the tantalum nitride film itself, and thus the tantalum nitride film can be suitably used as a conductive film in contact with the semiconductor layer 108 or a conductive film in the vicinity of the semiconductor layer 108.

[0163] As the insulating layer 110, an insulating layer containing one or more of a silicon oxide film, a silicon oxynitride film, a silicon nitride oxide film, a silicon nitride film, an aluminum oxide film, a hafnium oxide film, a yttrium oxide film, a zirconium oxide film, a gallium oxide film, a tantalum oxide film, a magnesium oxide film, a lanthanum oxide film, a cerium oxide film, and a neodymium oxide film can be used. The gate insulating layer 110 is not limited to a single layer, and a stacked structure of two or more layers can be employed.

[0164] At least a region of the gate insulating layer 110 in contact with the semiconductor layer 108 is preferably an oxide insulating film, more preferably a region having an oxygen content exceeding the stoichiometric composition. In other words, the gate insulating layer 110 is an insulating film capable of releasing oxygen. For example, oxygen can be supplied into the gate insulating layer 110 by forming the gate insulating layer 110 in an oxygen atmosphere, performing heat treatment, plasma treatment, or the like on the formed gate insulating layer 110 in an oxygen atmosphere, or forming an oxide film on the gate insulating layer 110 in an oxygen atmosphere.

[0165] As the gate insulating layer 110, a material such as hafnium oxide having a higher relative dielectric constant than silicon oxide or silicon oxynitride can also be used. By this means, the thickness of the gate insulating layer 110 can be increased to suppress leakage current due to tunnel current. In particular, it is preferable to use hafnium oxide having crystallinity, because it has a higher relative dielectric constant than amorphous hafnium oxide.

[0166] The semiconductor layer 108 preferably contains an oxide semiconductor. Alternatively, the semiconductor layer 108 can contain silicon. As silicon, amorphous silicon, crystalline silicon (low-temperature polysilicon, single crystal silicon, or the like), or the like can be given.

[0167] For example, the semiconductor layer 108 preferably contains indium, M (M is one or more selected from gallium, aluminum, silicon, boron, yttrium, tin, copper, vanadium, beryllium, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, and magnesium), and zinc. In particular, M is preferably one or more selected from aluminum, gallium, yttrium, and tin.

[0168] In particular, as the semiconductor layer 108, an oxide containing indium (In), gallium (Ga), and zinc (Zn) (also referred to as IGZO) is preferably used.

[0169] When the semiconductor layer 108 is an In-M-Zn oxide, the atomic ratio of In in a sputtering target used to form the In-M-Zn oxide is preferably higher than or equal to the atomic ratio of M. As the atomic ratio of metal elements in such a sputtering target, In:M:Zn = 1:1:1, In:M:Zn = 1:1:1.2, In:M:Zn = 2:1:3, In:M:Zn = 3:1:2, In:M:Zn = 4:2:4.1, In:M:Zn = 5:1:6, In:M:Zn = 5:1:7, In:M:Zn = 5:1:8, In:M:Zn = 6:1:6, In:M:Zn = 5:2:5, or the like can be given.

[0170] As the sputtering target, a target including a polycrystalline oxide is preferably used, whereby the semiconductor layer 108 having crystallinity can be easily formed. Note that the atomic ratio of the semiconductor layer 108 formed is varied within a range of ±40 % of the atomic ratio of the metal elements in the above-described sputtering target. For example, when the composition of the sputtering target used for the semiconductor layer 108 is In:Ga:Zn = 4:2:4.1 [atomic ratio], the composition of the semiconductor layer 108 formed is In:Ga:Zn = 4:2:3 [atomic ratio] or the vicinity thereof in some cases.

[0171] When it is stated that the atomic ratio is In:Ga:Zn = 4:2:3 or the vicinity thereof, the following cases are included: when the atomic ratio of In is 4, the atomic ratio of Ga is higher than or equal to 1 and lower than or equal to 3, and the atomic ratio of Zn is higher than or equal to 2 and lower than or equal to 4. Further, when it is stated that the atomic ratio is In:Ga:Zn = 5:1:6 or the vicinity thereof, the following cases are included: when the atomic ratio of In is 5, the atomic ratio of Ga is higher than 0.1 and lower than or equal to 2, and the atomic ratio of Zn is higher than or equal to 5 and lower than or equal to 7. Further, when it is stated that the atomic ratio is In:Ga:Zn = 1:1:1 or the vicinity thereof, the following cases are included: when the atomic ratio of In is 1, the atomic ratio of Ga is higher than 0.1 and lower than or equal to 2, and the atomic ratio of Zn is higher than 0.1 and lower than or equal to 2.

[0172] Here, an oxygen vacancy which can be formed in the semiconductor layer 108 is described.

[0173] An oxygen vacancy formed in the semiconductor layer 108 causes a problem in that it affects the transistor characteristics. For example, when an oxygen vacancy is formed in the semiconductor layer 108, the oxygen vacancy is sometimes bonded to hydrogen to become a carrier supply source. When a carrier supply source is generated in the semiconductor layer 108, the electrical characteristics of the transistor 100 fluctuate, typically the shift of the threshold voltage. Thus, it is preferable that as few oxygen vacancies as possible be included in the semiconductor layer 108.

[0174] Thus, in one embodiment of the present application, the insulating film in the vicinity of the semiconductor layer 108, specifically, the gate insulating layer 110 positioned over the semiconductor layer 108 and the insulating layer 103 positioned below the semiconductor layer 108, includes an oxide film. By moving oxygen from the insulating layer 103 and the gate insulating layer 110 to the semiconductor layer 108 by heating or the like in a manufacturing process, oxygen vacancies in the semiconductor layer 108 can be reduced.

[0175] Next, a metal oxide that can be used for a semiconductor layer will be described below.

[0176] In this specification and the like, a metal oxide including nitrogen is also referred to as a metal oxide (metal oxide). Further, the metal oxide including nitrogen can be referred to as a metal oxynitride. For example, a metal oxide containing nitrogen such as zinc oxynitride (ZnON) can be used for a semiconductor layer.

[0177] In this specification and the like, CAAC (c-axis aligned crystal) or CAC (Cloud-Aligned Composite) is sometimes described. CAAC refers to one example of a crystal structure, and CAC refers to one example of a function or a material composition.

[0178] For example, as a semiconductor layer, a CAC (Cloud-Aligned Composite)-OS can be used.

[0179] The CAC-OS or the CAC-metal oxide has a function of conductivity in part of a material, a function of insulating property in another part of the material, and a function of a semiconductor as a whole of the material. Further, in the case where the CAC-OS or the CAC-metal oxide is used for a light-emitting layer of a transistor, the function of conductivity is a function of causing an electron (or a hole) used as a carrier to flow, and the function of insulating property is a function of not causing an electron used as a carrier to flow. By complementary action of the function of conductivity and the function of insulating property, the CAC-OS or the CAC-metal oxide can have a switching function (a function of being turned on / off). By separating each function in the CAC-OS or the CAC-metal oxide, each function can be maximally improved.

[0180] Further, the CAC-OS or the CAC-metal oxide includes a conductive region and an insulating region. The conductive region has the above-described conductivity function, and the insulating region has the above-described insulating function. Further, in the material, the conductive region and the insulating region are sometimes separated at the nanometer level. Further, the conductive region and the insulating region are sometimes unevenly distributed in the material. Further, a conductive region whose edge is blurred and connected in a cloud shape is sometimes observed.

[0181] Further, in the CAC-OS or the CAC-metal oxide, the conductive region and the insulating region are sometimes dispersed in the material at a size of greater than or equal to 0.5 nm and less than or equal to 10 nm, preferably greater than or equal to 0.5 nm and less than or equal to 3 nm.

[0182] Further, the CAC-OS or the CAC-metal oxide is composed of components having different band gaps. For example, the CAC-OS or the CAC-metal oxide is composed of a component having a wide gap due to the insulating region and a component having a narrow gap due to the conductive region. In this composition, when a carrier is caused to flow, the carrier mainly flows in the component having the narrow gap. Further, the component having the narrow gap causes the carrier to flow in the component having the wide gap in conjunction with the component having the narrow gap through a complementary action with the component having the wide gap. Thus, when the above-described CAC-OS or CAC-metal oxide is used for a channel formation region of a transistor, a high current driving force, i.e., a large on-state current and a high field-effect mobility can be obtained in the on state of the transistor.

[0183] That is, the CAC-OS or the CAC-metal oxide can also be referred to as a matrix composite or a metal matrix composite.

[0184] An oxide semiconductor (metal oxide) is classified into a single crystal oxide semiconductor and a non-single-crystal oxide semiconductor. As the non-single-crystal oxide semiconductor, for example, a CAAC-OS (c-axis aligned crystalline oxide semiconductor), a polycrystalline oxide semiconductor, an nc-OS (nanocrystalline oxide semiconductor), an a-like OS (amorphous-like oxide semiconductor), and an amorphous oxide semiconductor are known.

[0185] The CAAC-OS has c-axis alignment, a plurality of nanocrystals each having a crystal axis (c-axis) aligned in a direction parallel to the normal line of the formation surface, and a region approximately parallel to the formation surface. Note that the c-axis alignment refers to the case where crystal locations of the plurality of nanocrystals approximately match the normal line of the formation surface. Further, the plurality of nanocrystals are connected in the a-b plane direction, and the crystal structure has distortion.

[0186] Although the nanocrystal is basically hexagonal, it is not limited to a regular hexagon, and there is a case of a distorted hexagon. Further, in the distortion, there is a case of a pentagon, a heptagon, or the like. Further, in the CAAC-OS, a clear grain boundary cannot be observed even in the vicinity of a distortion. That is, it is said that the formation of a grain boundary is suppressed due to the distortion of the crystal arrangement. This is because the CAAC-OS can tolerate the distortion due to a low density of oxygen atom arrangement in the a-b plane direction or a change in the bond length between atoms due to substitution of a metal element.

[0187] The CAAC-OS has a tendency to have a layered crystal structure (also referred to as a layered structure) in which a layer containing indium and oxygen (hereinafter referred to as an In layer) and a layer containing an element M, zinc, and oxygen (hereinafter referred to as an (M, Zn) layer) are stacked. Further, indium and the element M can be substituted with each other, and in the case where indium is substituted with the element M in the (M, Zn) layer, the layer can be referred to as an (In, M, Zn) layer. Further, in the case where indium is substituted with the element M in the In layer, the layer can be referred to as an (In, M) layer.

[0188] The CAAC-OS is a metal oxide having high crystallinity. On the other hand, in the CAAC-OS, a clear grain boundary cannot be observed, and thus a reduction in electron mobility due to the grain boundary is less likely to occur than in the polycrystalline oxide semiconductor. Further, the CAAC-OS has low density of defects and impurities in the bulk, and is also called a single crystal-like semiconductor or a single crystal semiconductor. O ( The CAAC-OS is a metal oxide having high crystallinity. On the other hand, in the CAAC-OS, a clear grain boundary cannot be observed, and thus a reduction in electron mobility due to the grain boundary is less likely to occur than in the polycrystalline oxide semiconductor. Further, the CAAC-OS has low density of defects and impurities in the bulk, and is also called a single crystal-like semiconductor or a single crystal semiconductor.

[0189] In the nc-OS, the arrangement of atoms is periodic in a region (e.g., a region with a size greater than or equal to 1 nm and less than or equal to 10 nm, in particular, a region with a size greater than or equal to 1 nm and less than or equal to 3 nm) that is smaller than the volume of a nanocrystal. Further, the nc-OS has no regularity of crystal orientation between different nanocrystals. Thus, the nc-OS has no orientation in the whole film.

[0190] Further, indium-gallium-zinc oxide (hereinafter referred to as IGZO), which is one of metal oxides containing indium, gallium, and zinc, has a stable structure when it is formed of the above-described nanocrystal. In particular, IGZO has a tendency that crystal growth is less likely to proceed in the air, and thus IGZO is sometimes more stable in structure when it is formed of a small crystal (e.g., the above-described nanocrystal) than when it is formed of a large crystal (here, a crystal of several mm or a crystal of several cm).

[0191] An a-like OS is a metal oxide having a structure between that of an nc-OS and that of an amorphous oxide semiconductor. The a-like OS includes a void or a low-density region. That is, the a-like OS has lower crystallinity than the nc-OS and the CAAC-OS.

[0192] An oxide semiconductor (metal oxide) has various structures and various characteristics. The oxide semiconductor of one embodiment of the present application can include two or more of an amorphous oxide semiconductor, a polycrystalline oxide semiconductor, an a-like OS, an nc-OS, and a CAAC-OS.

[0193] A metal oxide film used as a semiconductor layer can be formed using either or both of an inert gas and an oxygen gas. Note that there is no particular limitation on the oxygen flow ratio (oxygen partial pressure) at the time of forming the metal oxide film. However, in the case where a transistor with high field-effect mobility is to be obtained, the oxygen flow ratio (oxygen partial pressure) at the time of forming the metal oxide film is preferably higher than or equal to 0 % and lower than or equal to 30 %, more preferably higher than or equal to 5 % and lower than or equal to 30 %, and still more preferably higher than or equal to 7 % and lower than or equal to 15 %.

[0194] The energy gap of the metal oxide is preferably higher than or equal to 2 eV, more preferably higher than or equal to 2.5 eV, and still more preferably higher than or equal to 3 eV. With the use of a metal oxide with a wide energy gap, the off-state current of a transistor can be reduced.

[0195] [Manufacturing Method Example 1]

[0196] Next, a manufacturing method of a transistor of one embodiment of the present application is described with reference to FIGS. 5 to 9. FIGS. 5 to 9 each show a cross section in the channel length direction and a cross section in the channel width direction of each stage of the manufacturing process of a transistor.

[0197] The thin films (insulating films, semiconductor films, conductive films, etc.) that constitute the semiconductor device can be formed by sputtering, chemical vapor deposition (CVD), vacuum evaporation, pulsed laser deposition (PLD), atomic layer deposition (ALD), or the like. As the CVD method, there are plasma-enhanced CVD (PECVD), thermal CVD, and the like. Further, as one of the thermal CVD methods, there is metal organic CVD (MOCVD).

[0198] Further, the thin films (insulating films, semiconductor films, conductive films, etc.) that constitute the semiconductor device can be formed by a spin coating method, an immersion method, a spray coating method, an inkjet method, a dispenser method, a screen printing method, an offset printing method, a doctor knife method, a slit coating method, a roll coating method, a curtain coating method, a blade coating method, or the like.

[0199] Further, when the thin films that constitute the semiconductor device are processed, the processing can be performed by photolithography or the like. Alternatively, the thin films can be processed by nanoimprint, sandblasting, peeling, or the like. Further, the thin films can be formed directly in island shapes by a film formation method in which a metal mask or the like is used as a mask.

[0200] The photolithography typically has two methods. One is a method in which a resist mask is formed on a thin film to be processed, the thin film is processed by etching or the like, and the resist mask is removed. The other is a method in which a photosensitive thin film is formed, and then the thin film is processed into a desired shape by exposure and development.

[0201] In the photolithography, as light for exposure, i-line (wavelength: 365 nm), g-line (wavelength: 436 nm), h-line (wavelength: 405 nm), or light in which these lights are mixed can be used, for example. Further, ultraviolet light, KrF laser light, ArF laser light, or the like can be used. Further, exposure can be performed by liquid immersion exposure technology. As light for exposure, extreme ultraviolet light (EUV) or X-rays can be used. Further, an electron beam can be used instead of light for exposure. When extreme ultraviolet light, X-rays, or an electron beam is used, extremely fine processing can be performed, and thus is preferable. Further, when exposure is performed by scanning of a light beam such as an electron beam, a photomask is not needed.

[0202] As the etching method of the thin film, dry etching, wet etching, sandblasting, or the like can be used.

[0203] In the manufacturing method example 1, a manufacturing method of the transistor 100A illustrated in the structure example 2 is described with reference to FIGS. 5 to 7.

[0204] First, as FIG. 5A indicated in FIG. 1, a conductive film is formed over a substrate 102, and is processed by etching to form a conductive layer 106 which is used as a gate electrode.

[0205] Next, an insulating layer 103 FIG. 5A ) covering the substrate 102 and the conductive layer 106 is formed.

[0206] Further, the insulating layer 103 can be subjected to an oxygen supply treatment after the insulating layer 103 is formed. As the oxygen supply treatment, for example, a plasma treatment in an oxygen atmosphere, a heat treatment in an oxygen atmosphere, a treatment by a plasma ion doping method, and a treatment by an ion implantation method can be given.

[0207] Next, a metal oxide film is formed over the insulating layer 103, and is processed to form an island-shaped semiconductor layer 108 FIG. 5B ).

[0208] The metal oxide film is preferably formed by a sputtering method using a metal oxide target.

[0209] At the time of formation of the metal oxide film, an oxygen gas is preferably used. Further, when the metal oxide film is formed, an inert gas (e.g., a helium gas, an argon gas, a xenon gas, or the like) can be mixed in addition to the oxygen gas. The higher the proportion of the oxygen gas in the entire deposition gas at the time of formation of the metal oxide film (hereinafter also referred to as an oxygen flow ratio), the higher the crystallinity of the metal oxide film can be, and thus a highly reliable transistor can be achieved. On the other hand, the lower the oxygen flow ratio, the lower the crystallinity of the metal oxide film is, and thus a transistor with a large on-state current can be obtained.

[0210] As the deposition conditions of the metal oxide film, the substrate temperature can be higher than or equal to room temperature and lower than or equal to 200 °C, preferably higher than or equal to room temperature and lower than or equal to 140 °C. For example, the substrate temperature is preferably higher than or equal to room temperature and lower than 140 °C, because the productivity can be improved. Further, by forming the metal oxide film at a substrate temperature of room temperature or in a state where no intentional heating is performed, the crystallinity can be reduced.

[0211] Further, it is preferable to perform a treatment for removing water, hydrogen, an organic substance, or the like attached to the surface of the insulating layer 103 or to perform a treatment for supplying oxygen to the insulating layer 103 before forming the metal oxide film. For example, heat treatment can be performed at a temperature of 70 °C or higher and 200 °C or lower in a reduced pressure atmosphere. Alternatively, plasma treatment in an atmosphere containing oxygen can be performed. Further, by performing plasma treatment in an atmosphere containing nitric oxide gas, an organic substance on the surface of the insulating layer 103 can be appropriately removed. After such a treatment, it is preferable to continuously form the metal oxide film in a state where the surface of the insulating layer 103 is not exposed to the atmosphere.

[0212] When the metal oxide film is processed, one or both of a wet etching method and a dry etching method can be used. At this time, a part of the insulating layer 103 which does not overlap with the semiconductor layer 108 is sometimes etched and thinned.

[0213] Further, heat treatment for removing hydrogen or water in the metal oxide film or the semiconductor layer 108 can be performed after the metal oxide film is formed or after the metal oxide film is processed into the semiconductor layer 108. Typically, the temperature of the heat treatment can be 150 °C or higher and lower than the strain point of the substrate, 250 °C or higher and 450 °C or lower, or 300 °C or higher and 450 °C or lower.

[0214] The heat treatment can be performed in an atmosphere containing a rare gas or nitrogen. Alternatively, heat can be performed in this atmosphere and then heat can be performed in an atmosphere containing oxygen. Further, the atmosphere of the above heat treatment preferably does not contain hydrogen, water, or the like. The heat treatment can use an electric furnace, an RTA device, or the like. By using an RTA device, the heat treatment time can be shortened.

[0215] Next, a gate insulating layer 110 and a metal oxide layer 114f are formed to be stacked in a manner of covering the insulating layer 103 and the semiconductor layer 108. FIG. 5C ).

[0216] As the gate insulating layer 110, for example, an oxide film such as a silicon oxide film or a silicon oxynitride film is preferably formed by using a PECVD method. Further, the gate insulating layer 110 can be formed by a PECVD method using microwaves.

[0217] The metal oxide layer 114f is preferably formed in an atmosphere containing oxygen, for example. In particular, it is preferable to be formed by a sputtering method in an atmosphere containing oxygen. By this, oxygen can be supplied to the gate insulating layer 110 at the time of forming the metal oxide layer 114f.

[0218] In the case where the metal oxide layer 114f is formed by a sputtering method using an oxide target containing a metal oxide as with the semiconductor layer 108, the above method can be employed.

[0219] For example, oxygen can also be used as the deposition gas, and a metal oxide film layer 114f is formed by a reactive sputtering method using a metal target. For example, in the case where aluminum is used as the metal target, an aluminum oxide film can be formed.

[0220] When the metal oxide layer 114f is formed, the higher the ratio of the oxygen flow rate to the total flow rate of the deposition gas introduced into the deposition chamber of the deposition apparatus (oxygen flow rate ratio) or the oxygen partial pressure in the deposition chamber, the more the amount of oxygen supplied to the gate insulating layer 110 can be increased. The oxygen flow rate ratio or the oxygen partial pressure is, for example, 50% or more and 100% or less, preferably 65% or more and 100% or less, more preferably 80% or more and 100% or less, and further preferably 90% or more and 100% or less. In particular, it is preferable to set the oxygen flow rate ratio to 100% so as to make the oxygen partial pressure as close to 100% as possible.

[0221] Thus, by forming the metal oxide layer 114f using a sputtering method in an atmosphere containing oxygen, oxygen can be prevented from escaping from the gate insulating layer 110 while oxygen is supplied to the gate insulating layer 110 when the metal oxide layer 114f is formed. As a result, a large amount of oxygen can be enclosed in the gate insulating layer 110. Furthermore, a large amount of oxygen can be supplied to the semiconductor layer 108 by a subsequent heat treatment. As a result, oxygen vacancies in the semiconductor layer 108 can be reduced, and a transistor with high reliability can be achieved.

[0222] Next, it is preferable to supply oxygen from the gate insulating layer 110 to the semiconductor layer 108 by performing a heat treatment. For example, the heat treatment can be performed at a temperature of 200°C or higher and 400°C or lower in an atmosphere containing one or more of nitrogen, oxygen, and a rare gas.

[0223] After the metal oxide layer 114f is formed, oxygen can be effectively supplied from the gate insulating layer 110 to the semiconductor layer 108 by performing a heat treatment before the gate electrode 112 is formed.

[0224] After the metal oxide layer 114f is formed, an opening portion 142 reaching the conductive layer 106 is formed by etching a part of the metal oxide layer 114f, the gate insulating layer 110, and the insulating layer 103. Thus, the gate electrode 112 formed later and the conductive layer 106 can be electrically connected in the opening portion 142.

[0225] Next, a conductive film 112f (to be a gate electrode 112) is formed over the metal oxide layer 114f. FIG. 5D The conductive film 112f is preferably formed by a sputtering method using a sputtering target of a metal or an alloy. Here, the conductive film 112f and the conductive layer 106 are connected in the opening portion 142.

[0226] Next, a part of the conductive film 112f is etched to form the gate electrode 112 FIG. 5E

[0227] In this way, by covering the top surface and side surface of the semiconductor layer 108 and the insulating layer 103 with the metal oxide layer 114f and the gate insulating layer 110, it is possible to prevent a part of the semiconductor layer 108 or the insulating layer 103 from being thinned by etching when the gate electrode 112 is etched.

[0228] Next, the gate electrode 112 is used as a mask to perform a process of supplying an impurity element 140 to the metal oxide layer 114f, the gate insulating layer 110, and the semiconductor layer 108 to form a low-resistance region 108n, a region 110d, and a region 103d FIG. 6A

[0229] The supply of the impurity element 140 can be appropriately performed using a plasma ion doping method or an ion implantation method. By using these methods, it is possible to control the concentration distribution in the depth direction with high accuracy according to the ion acceleration voltage and the dose, and the like. By using the plasma ion doping method, it is possible to improve the productivity. Further, by using an ion implantation method using mass separation, it is possible to improve the purity of the supplied impurity element.

[0230] In the supply process of the impurity element 140, it is preferable to control the process conditions in such a manner that the interface between the semiconductor layer 108 and the gate insulating layer 110, a part of the semiconductor layer 108 adjacent to the interface, or a part of the gate insulating layer 110 adjacent to the interface becomes the highest concentration. Thereby, it is possible to supply the impurity element 140 having the most appropriate concentration to both the semiconductor layer 108 and the gate insulating layer 110 by one process.

[0231] As the impurity element 140, hydrogen, boron, carbon, nitrogen, fluorine, phosphorus, sulfur, arsenic, aluminum, magnesium, silicon, and rare gas, and the like can be given. As the impurity element 140, it is preferable to use boron, phosphorus, aluminum, magnesium, or silicon, and it is more preferable to use boron or phosphorus.

[0232] As the source gas of the impurity element 140, a gas containing the above-described impurity element can be used. When boron is supplied, B2H6gas or BF3gas, or the like can be typically used. Further, when phosphorus is supplied, PH3gas, or the like can be typically used. Further, a mixed gas in which these source gases are diluted with a rare gas can also be used.

[0233] ​​In addition to the above, as the source gas, CH4, N2, NH3, AlH3, AlCl3, SiH4, Si2H6, F2, HF, H2, (C5H5)2Mg, and a rare gas, or the like can be used. Further, the ion source is not limited to a gas, and a solid or liquid that is vaporized by being heated can also be used.

[0234] By setting the conditions of the acceleration voltage or the dose, or the like in consideration of the composition, density, thickness, or the like of the metal oxide layer 114f, the gate insulating layer 110, and the semiconductor layer 108, the supply of the impurity element 140 can be controlled.

[0235] Note that there is no limitation on the method of supplying the impurity element 140, and for example, plasma treatment or treatment using thermal diffusion caused by heating can be performed. In the case of using a plasma treatment method, the impurity element can be supplied by first generating plasma in a gas atmosphere containing the supplied impurity element, and then performing plasma treatment. As a device for generating the above plasma, a dry etching device, an ashing device, a plasma CVD device, a high-density plasma CVD device, or the like can be used.

[0236] In one embodiment of the present application, the impurity element 140 can be supplied to the semiconductor layer 108 through the metal oxide layer 114f and the gate insulating layer 110. Thus, the crystallinity of the semiconductor layer 108 can be inhibited from being reduced at the time of supply of the impurity element 140. Thus, this is particularly suitable for a case where the resistance is increased due to reduction in crystallinity.

[0237] In the supply process of the impurity element 140, the portion of the gate insulating layer 110 which does not overlap with the gate electrode 112 is also supplied with the impurity element 140. Thus, in the portion of the gate insulating layer 110 which overlaps with the gate electrode 112 and the portion which does not overlap with the gate electrode 112, there is a difference in the ease of release of oxygen due to heating. Thus, even in the case where heat treatment is performed after the supply process of the impurity element 140, the supply of oxygen from the gate insulating layer 110 to the low-resistance region 108n can be inhibited, and thus the increase in resistance of the low-resistance region 108n can be inhibited.

[0238] Next, a portion of the metal oxide layer 114f is etched using the gate electrode 112 as a hard mask to form a metal oxide layer 114f2 FIG. 6B Thus, the gate electrode 112 and the metal oxide layer 114f2 whose top surface shape is substantially uniform can be formed.

[0239] In the supply process of the impurity element 140, the portion of the metal oxide layer 114f which does not overlap with the gate electrode 112 is supplied with the impurity element 140. Thereby, the etching rate of the portion of the metal oxide layer 114f which does not overlap with the gate electrode 112 and the portion which does not overlap therewith is made to differ. Thus, the shape defect of the metal oxide layer due to etching can be suppressed.

[0240] Although the processing method of the metal oxide layer 114f is not particularly limited, when wet etching is used, the metal oxide layer 114f and the gate insulating layer 110 can be simultaneously etched. Thereby, the thickness of the gate insulating layer 110 can be suppressed from being reduced, and the thickness of the gate insulating layer 110 can be made uniform.

[0241] Next, the insulating layer 118 which covers the gate insulating layer 110, the metal oxide layer 114, and the gate electrode 112 is formed. FIG. 7A ).

[0242] In the case where the insulating layer 118 is formed using the plasma CVD method, when the deposition temperature is too high, the impurities contained in the low-resistance region 108n and the like can diffuse to the surrounding portion of the channel formation region including the semiconductor layer 108 or cause the resistance of the low-resistance region 108n to rise. The film formation temperature of the insulating layer 118 is, for example, preferably 150°C or higher and 400°C or lower, more preferably 180°C or higher and 360°C or lower, and further preferably 200°C or higher and 250°C or lower. By forming the insulating layer 118 at a low temperature, even in the case of a transistor having a short channel length, good electrical characteristics can be obtained.

[0243] Next, a mask is formed at a desired position of the insulating layer 118 using a photolithography method, and then, the insulating layer 118 and a portion of the insulating layer 110 are etched to form an opening portion 141a and an opening portion 141b which reach the low-resistance region 108n.

[0244] Next, a conductive film is formed on the insulating layer 118 so as to cover the opening portion 141a and the opening portion 141b, and the conductive film is processed into a desired shape to form a conductive layer 120a and a conductive layer 120b FIG. 7B ).

[0245] By the above process, the transistor 100A can be manufactured. For example, in the case where the transistor 100A is applied to a pixel of a display device, one or more of a process of forming a protective insulating layer, a planarization layer, a display element, and a wiring can be added later.

[0246] [Manufacturing Method Example 2]

[0247] In one aspect of the invention, depending on the materials and formation conditions, it can sometimes be difficult to process the metal oxide layer 114f. In this case, by adding a step to reduce the crystallinity of the metal oxide layer 114f, the processing of the metal oxide layer 114f can be made easier.

[0248] In manufacturing method example 2, the processes up to the manufacturing of the gate electrode 112 are the same as in manufacturing method example 1. FIG. 5A to FIG. 5E ).

[0249] Then, the supply process of impurity element 140 is carried out. FIG. 8A The supply process of impurity element 143. FIG. 8B Example 1 of the supply process and manufacturing method for impurity element 140 (). FIG. 6A Similarly, this process forms a low-resistance region 108n in the semiconductor layer 108. Impurity element 143 is supplied at least to the metal oxide layer 114f. This allows the metal oxide layer 114f to become a metal oxide layer 114g with low crystallinity. Either impurity element 140 or impurity element 143 can be supplied first.

[0250] Examples of impurity element 143 include silicon, phosphorus, argon, krypton, xenon, arsenic, gallium, and germanium. A gas containing the aforementioned impurity element can be used as the source gas for impurity element 143.

[0251] By taking into account the composition, density, thickness, and other conditions of the metal oxide layer 114f, such as the acceleration voltage or dosage, the supply of impurity element 143 can be controlled.

[0252] Then, using the gate electrode 112 as a hard mask, a portion of the low-crystallinity metal oxide layer 114g is etched to form the metal oxide layer 114. FIG. 8C Therefore, it is easy to form a metal oxide layer 114 whose top surface shape is approximately the same as that of the gate electrode 112.

[0253] [Example 3 of manufacturing method]

[0254] When the metal oxide layer 114f is an insulating film, the process of processing the metal oxide layer 114f into an island shape can be omitted.

[0255] In manufacturing method example 3, the processes up to the supply of impurity element 140 are the same as in manufacturing method example 1. FIG. 5A to FIG. 5E , FIG. 6A ).

[0256] In the supply process of impurity element 140 ( FIG. 9A) after that, the insulating layer 118 is formed to cover the gate insulating layer 110, the metal oxide layer 114f, and the gate electrode 112 without processing the metal oxide layer 114f FIG. 9B

[0257] Next, a mask is formed at a desired position in the insulating layer 118 by photolithography, and then, the insulating layer 118, the metal oxide layer 114f, and a part of the gate insulating layer 110 are etched to form an opening portion 141a and an opening portion 141b reaching the low-resistance region 108n.

[0258] Next, a conductive film is formed on the insulating layer 118 so as to cover the opening portion 141a and the opening portion 141b, and the conductive film is processed into a desired shape to form a conductive layer 120a and a conductive layer 120b FIG. 9C

[0259] By the above process, a transistor including the metal oxide layer 114f can be manufactured.

[0260] In the method for manufacturing the semiconductor device of this embodiment, the metal oxide layer which is not easily permeated by oxygen, hydrogen, water, or the like is provided between the gate insulating layer and the gate electrode, so that oxygen can be efficiently supplied from the gate insulating layer to the semiconductor layer. Thus, the oxygen vacancy in the channel formation region of the semiconductor layer is reduced, and the reliability of the transistor is improved. Further, the processing of the metal oxide layer is performed after the low-resistance region of the semiconductor layer is formed by supplying an impurity element. Since the metal oxide layer also contains the impurity element at the time of processing of the metal oxide layer, the shape defect of the metal oxide layer due to etching can be suppressed.

[0261] This embodiment can be combined with other embodiments as appropriate. In addition, in this specification, in the case where a plurality of structures are expressed in one embodiment, the structures can be combined as appropriate.

[0262] (Embodiment 2)

[0263] In this embodiment, with reference to FIGS. 10 to FIG. 14 A display device including a semiconductor device of one embodiment of the present application is described.

[0264] The semiconductor device of one embodiment of the present application has a good electrical characteristic, and by using the semiconductor device for a display device, the reliability of the display device can be improved. For example, the transistor of one embodiment of the present application can be applied to a transistor included in one or both of a pixel and a driver circuit of the display device.

[0265] ​​The semiconductor device of one embodiment of the present application can be used for a display device or a module including the display device. As the module including the display device, a module to which a flexible printed circuit (FPC) or a tape carrier package (TCP) is attached, a module having a TCP to which a printed circuit board is attached by a COG (Chip On Glass) method or a COF (Chip On Film) method, and the like can be given.

[0266] [Top surface structure of display device]

[0267] FIG. 10A A plan view of a display device 700 is shown. The display device 700 includes a first substrate 701 and a second substrate 705 which are attached together with a sealant 712. In a region which is sealed with the first substrate 701, the second substrate 705, and the sealant 712, a pixel portion 702, a source driver 704, and a gate driver 706 are provided over the first substrate 701. The pixel portion 702 includes a plurality of display elements.

[0268] A FPC 716 is attached to a FPC terminal portion 708 included in a portion of the first substrate 701 which does not overlap with the second substrate 705. Various signals are supplied to the pixel portion 702, the source driver 704, and the gate driver 706 through the FPC 716, the FPC terminal portion 708, and a signal line 710.

[0269] A plurality of gate drivers 706 can be provided. Alternatively, the gate driver 706 and the source driver 704 can each be formed separately over a semiconductor substrate or the like, and mounted to the first substrate 701 or the FPC 716 as an IC chip.

[0270] The display elements included in the pixel portion 702, the source driver 704, and the gate driver 706 can be the transistor of one embodiment of the present application.

[0271] As the display element provided in the pixel portion 702, a liquid crystal element, a light-emitting element, or the like can be given. As the liquid crystal element, a transmissive liquid crystal element, a reflective liquid crystal element, a semi-transmissive liquid crystal element, or the like can be used. Further, as the light-emitting element, an LED (Light Emitting Diode), an OLED (Organic LED), a QLED (Quantum-dot LED), a semiconductor laser, or the like can be given. Further, a MEMS (Micro Electro Mechanical Systems) element of a shutter type or an optical interference type, or a display element of a microcapsule type, an electrophoretic type, an electro wetting type, an electronic ink (registered trademark) type, or the like can be used.

[0272] FIG. 10B The display device 700A illustrated is an example of a display device that can be used as a flexible display device using a flexible resin layer 743 instead of the first substrate 701.

[0273] The pixel portion 702 of the display device 700A is not rectangular but has a shape in which the corners have a circular arc shape. As illustrated in a region P1 in FIG. 8A, the display device 700A includes a notch portion in which a part of the pixel portion 702 and the resin layer 743 are cut. A pair of gate drivers 706 is provided on both sides sandwiching the pixel portion 702. The gate drivers 706 are provided inside the outline of the circular arc shape at the corners of the pixel portion 702. FIG. 10B

[0274] A part of the resin layer 743 in which the FPC terminal portion 708 is provided protrudes. A part of the resin layer 743 including the FPC terminal portion 708 can be folded to the back surface along the region P2 in FIG. 8B. By folding a part of the resin layer 743 to the back surface, the display device 700A can be mounted to an electronic device in a state where the FPC 716 is arranged overlapping the back surface of the pixel portion 702, and thus the space of the electronic device can be saved. FIG. 10B

[0275] The FPC 716 connected to the display device 700A is provided with an IC 717. The IC 717 has a function of a source driver, for example. Here, the source driver 704 in the display device 700A can have a structure including at least one of a protection circuit, a buffer circuit, a demultiplexer circuit, or the like.

[0276] FIG. 10C The display device 700B illustrated is a display device suitable for an electronic device having a large screen. For example, the display device 700B can be applied to a television device, a monitor device, a personal computer (including a notebook or a desktop), a tablet terminal, a digital signage, or the like. ​​

[0277] The display device 700B includes multiple source driver ICs 721 and a pair of gate drivers 722.

[0278] Multiple source driver ICs 721 are mounted on FPC 723. One terminal of each FPC 723 is connected to a first substrate 701, and another terminal is connected to a printed circuit board 724. By bending the FPC 723, the printed circuit board 724 can be positioned on the back of the pixel section 702 and mounted in the electronic device, thereby reducing the space required to mount the electronic device.

[0279] On the other hand, a gate driver 722 is formed on the first substrate 701. Thus, a narrow-bezel electronic device can be realized.

[0280] By adopting the above structure, large and high-resolution display devices can be realized. For example, it can be applied to display devices with a screen size of 30 inches or more, 40 inches or more, 50 inches or more, or 60 inches or more diagonal. In addition, it can realize extremely high-resolution display devices such as 4K2K and 8K4K.

[0281] [Cross-sectional structure of the display device]

[0282] FIG. 11 and FIG. 12 A display device is shown, which includes a liquid crystal element as a display element. FIG. 13 and FIG. 14 A display device is shown, which includes an EL element as a display element. FIG. 11 , FIG. 12 and FIG. 13 They are all along FIG. 10A The cross-sectional view of the dotted-dash line QR is shown. FIG. 14 It is along FIG. 10B The cross-sectional view of the dotted line ST is shown.

[0283] FIG. 11 to FIG. 13 The display device 700 shown and FIG. 14 The display device 700A shown includes a lead-wound wiring section 711, a pixel section 702, a source driver 704, and an FPC terminal section 708. The lead-wound wiring section 711 includes signal lines 710. The pixel section 702 includes transistors 750 and capacitors 790. FIG. 12 The diagram shows the case where capacitor 790 is not present. Source driver 704 includes transistor 752.

[0284] The transistor 750 and the transistor 752 are transistors to which an oxide semiconductor is applied to a semiconductor layer in which a channel is formed. For example, each of the transistor 750 and the transistor 752 can be a transistor illustrated in Embodiment 1. Further, a display device can include a transistor in which silicon (amorphous silicon, polycrystalline silicon, or single crystal silicon) is used for a semiconductor layer.

[0285] The transistor used in this embodiment includes an oxide semiconductor film which is highly purified and in which formation of oxygen vacancies is suppressed. The transistor can have a small off-state current. Thus, the retention time of an electrical signal such as an image signal can be lengthened, and the writing interval of an image signal or the like can be lengthened. Thus, the frequency of refresh operation can be reduced, which can reduce power consumption.

[0286] Further, the transistor used in this embodiment can have high field-effect mobility, and thus high-speed driving can be performed. For example, by using such a transistor capable of high-speed driving for a display device, a switching transistor of a pixel portion and a driver transistor used for a driver circuit portion can be formed over the same substrate. That is, a semiconductor device formed using a silicon wafer or the like is not used as a driver circuit, which can reduce the number of components of a display device. Further, by using a transistor capable of high-speed driving also in a pixel portion, a high-quality image can be provided.

[0287] FIG. 11 FIG. 13 The capacitor 790 illustrated in FIG. 8A is formed by processing the same film as the semiconductor layer included in the transistor 750, and includes a lower electrode which is low-resistance and an upper electrode which is formed by processing the same conductive film as the source electrode or the drain electrode. Further, between the lower electrode and the upper electrode, two insulating films which cover the transistor 750 are provided. That is, the capacitor 790 has a stacked-layer structure in which the insulating films serving as dielectric films are interposed between a pair of electrodes.

[0288] FIG. 14 The capacitor 790 illustrated in FIG. 8A includes a lower electrode which is formed by processing the same film as the first gate electrode included in the transistor 750 and an upper electrode which is formed by processing the same metal oxide film as the semiconductor layer. Like the low-resistance region of the transistor 750, the upper electrode is low-resistance. Further, between the lower electrode and the upper electrode, a part of the insulating film serving as the first gate insulating layer of the transistor 750 is provided. That is, the capacitor 790 has a stacked-layer structure in which the insulating films serving as dielectric films are interposed between a pair of electrodes. Further, the upper electrode is connected to a wiring obtained by processing the same film as the source electrode and the drain electrode of the transistor.

[0289] The transistor 750, the transistor 752, and the capacitor 790 are provided with a planarization insulating film 770. ​

[0290] The transistor 750 included in the pixel portion 702 and the transistor 752 included in the source driver 704 can have different structures from each other. For example, one of them can be a top-gate transistor and the other can be a bottom-gate transistor. Note that the gate driver 706 is similar to the source driver 704.

[0291] The signal line 710, the source and drain electrodes of the transistors 750 and 752, and the like are formed of the same conductive film. Here, a low-resistance material such as a material containing a copper element is preferably used, so that signal delay and the like due to wiring resistance can be reduced, and thus a large-screen display can be achieved.

[0292] The FPC terminal portion 708 includes a wiring 760 of which a part serves as a connection electrode, an anisotropic conductive film 780, and an FPC 716. The wiring 760 is electrically connected to a terminal of the FPC 716 through the anisotropic conductive film 780. Here, the wiring 760 is formed of the same film as the source and drain electrodes of the transistors 750 and 752.

[0293] As the first substrate 701 and the second substrate 705, a flexible substrate such as a glass substrate or a plastic substrate can be used, for example. By using a flexible substrate, a flexible display can be achieved. When a flexible substrate is used as the first substrate 701, an insulating layer having a barrier property against water or hydrogen is preferably provided between the first substrate 701 and the transistor 750.

[0294] The second substrate 705 side is provided with a light-blocking film 738, a coloring film 736, and an insulating film 734 in contact with them.

[0295] In the display device 700, FIG. 11 , FIG. 12 and FIG. 13 a spacer 778 for adjusting the gap between the first substrate 701 and the second substrate 705 is provided. Further, the first substrate 701 and the second substrate 705 are attached with a sealant 712.

[0296] FIG. 11 The display device 700 illustrated in FIG. 8A includes a liquid crystal element 775 of a vertical electric field mode. The liquid crystal element 775 includes a conductive layer 772, a conductive layer 774, and a liquid crystal layer 776 between the conductive layer 772 and the conductive layer 774. The conductive layer 774 is provided on the second substrate 705 side and serves as a common electrode. The conductive layer 772 is electrically connected to the source or drain electrode of the transistor 750. The conductive layer 772 is formed over the planarization insulating film 770 and serves as a pixel electrode.

[0297] The conductive layer 772 can use a material that is transmissive to visible light or a material that is reflective to visible light. As a material that is transmissive to visible light, for example, an oxide material containing indium, zinc, tin, or the like can be used. As a material that is reflective to visible light, for example, a material containing aluminum, silver, or the like can be used.

[0298] When a material that is reflective to visible light is used as the conductive layer 772, the display device 700 is a reflective liquid crystal display device. On the other hand, when a material that is transmissive to visible light is used as the conductive layer 772, the display device 700 is a transmissive liquid crystal display device. When it is a reflective liquid crystal display device, a polarizing plate is provided on the viewing side. When it is a transmissive liquid crystal display device, a pair of polarizing plates is provided in a manner of sandwiching the liquid crystal element.

[0299] FIG. 12 The display device 700 illustrated is an example in which a liquid crystal element 775 using a lateral electric field mode (e.g., an FFS (Fringe Field Switching) mode) is used. The conductive layer 772 has a conductive layer 774 serving as a common electrode provided thereover with an insulating layer 773 interposed therebetween. The alignment state of a liquid crystal layer 776 can be controlled by an electric field generated between the conductive layer 772 and the conductive layer 774.

[0300] In the display device 700 illustrated in FIG. 8A, the conductive layer 772, the insulating layer 773, and the conductive layer 774 can be stacked to form a storage capacitor. FIG. 12

[0301] FIG. 11 FIG. 12 In the display device 700 illustrated in FIG. 8A, the conductive layer 772, the insulating layer 773, and the conductive layer 774 can be stacked to form a storage capacitor.

[0302] The liquid crystal layer 776 can use a thermotropic liquid crystal, a low-molecular liquid crystal, a high-molecular liquid crystal, a high-molecular dispersion type liquid crystal, a high-molecular network type liquid crystal, a ferroelectric liquid crystal, an anti-ferroelectric liquid crystal, or the like. Further, in the case of using a lateral electric field mode, a liquid crystal exhibiting a blue phase can be used, which does not require an alignment film.

[0303] ​​​As a mode of the liquid crystal element, a TN (Twisted Nematic) mode, a VA (Vertical Alignment) mode, an IPS (In-Plane-Switching) mode, an FFS mode, an ASM (Axially Symmetric aligned Micro-cell) mode, an OCB (Optical Compensated Birefringence) mode, an ECB (Electrically Controlled Birefringence) mode, a VA-IPS mode, a guest-host mode, or the like can be used.

[0304] Further, as a driving method of the liquid crystal element, a time-division display method (also referred to as a field sequential driving method) in which color display is performed by a chronological addition color mixing method can be used. In this case, a structure in which the coloring film 736 is not provided can be used. When the time-division display method is used, for example, subpixels each of which exhibits red (R), green (G), and blue (B) colors do not need to be provided, and thus the aperture ratio of a pixel or the resolution of a display device can be improved.

[0305] FIG. 13 The display device 700 and the display device 700A illustrated in FIG. 8A each include a light emitting element 782. The light emitting element 782 includes a conductive layer 772, an EL layer 786, and a conductive film 788. The EL layer 786 includes a light emitting substance. FIG. 14 As the light emitting substance, a substance (fluorescent material) that emits fluorescent light, a substance (phosphorescent material) that emits phosphorescent light, a substance (Thermally activated delayed fluorescence (TADF) material) that exhibits thermally activated delayed fluorescence, an inorganic compound (quantum dot material, etc.), or the like can be given.

[0306] In the display device 700 and the display device 700A illustrated in FIG. 8A,

[0307] The display device 700 and the display device 700A illustrated in FIG. 8A each include a light emitting element 782. The light emitting element 782 includes a conductive layer 772, an EL layer 786, and a conductive film 788. The EL layer 786 includes a light emitting substance. FIG. 13 The display device 700 and the display device 700A illustrated in FIG. 8A each include a light emitting element 782. The light emitting element 782 includes a conductive layer 772, an EL layer 786, and a conductive film 788. The EL layer 786 includes a light emitting substance. FIG. 14 In the display device 700 and the display device 700A illustrated in FIG. 8A,

[0308] FIG. 13 ​In this case, the coloring film 736 is provided at a position overlapping with the light-emitting element 782, and the light-blocking film 738 is provided at a position overlapping with the insulating film 730, in the wire-lead portion 711 and the source driver 704. Further, the coloring film 736 and the light-blocking film 738 are covered with the insulating film 734. Further, the light-emitting element 782 and the insulating film 734 are filled with the sealing film 732. Further, as shown in FIG. 8B, when a Side-By-Side method (also referred to as a separate coating method) in which different EL layers 786 are formed in each color of sub-pixel is employed, the coloring film 736 can not be provided. FIG. 14

[0309] In this case, the EL layer 786 included in the light-emitting element 782 is provided in an island shape over the insulating film 730 and the conductive layer 772. By forming the EL layer 786 separately in such a manner that the emission color of the EL layer 786 in each sub-pixel is different, color display can be achieved without using the coloring film 736. Further, a protective layer 741 is provided so as to cover the light-emitting element 782. The protective layer 741 can prevent impurities such as water from diffusing into the light-emitting element 782. The protective layer 741 is preferably formed using an inorganic insulating film. Further, it is more preferable to employ a stacked-layer structure in which the inorganic insulating film and the organic insulating film are each one or more. FIG. 14

[0310] FIG. 14 As shown in FIG. 8A, the display device 700A employs a stacked-layer structure in which a support substrate 745, a bonding layer 742, a resin layer 743, and an insulating layer 744 support the first substrate 745, the adhesive layer 742, the resin layer 743, and the insulating layer 744, instead of the substrate 701 shown in FIG. 8B. The transistor 750, the capacitor 790, and the like are provided over the insulating layer 744. FIG. 13

[0311] The support substrate 745 is a thin substrate having flexibility, which includes an organic resin, glass, or the like. The resin layer 743 is a layer of an organic resin including a polyimide resin, an acrylic resin, or the like. The insulating layer 744 includes an inorganic insulating film such as silicon oxide, silicon oxynitride, silicon nitride, or the like. The resin layer 743 and the support substrate 745 are attached to each other with the bonding layer 742. The resin layer 743 is preferably thinner than the support substrate 745.

[0312] Further, as shown in FIG. 8A, the display device 700A includes a protective layer 740 instead of the second substrate 705 shown in FIG. 8B. The protective layer 740 is attached to the sealing film 732. The protective layer 740 can be formed using a glass substrate, a resin film, or the like. Further, the protective layer 740 can be formed using a polarizing plate, a scattering plate, or the like optical member, an input device such as a touch sensor, or a stacked-layer structure of two or more of the above. FIG. 14 FIG. 13

[0313] Further, as shown in FIG. 8A, the display device 700A includes a protective layer 740 instead of the second substrate 705 shown in FIG. 8B. The protective layer 740 is attached to the sealing film 732. The protective layer 740 can be formed using a glass substrate, a resin film, or the like. Further, the protective layer 740 can be formed using a polarizing plate, a scattering plate, or the like optical member, an input device such as a touch sensor, or a stacked-layer structure of two or more of the above. FIG. 14 ​​​​​A foldable region P2 is indicated in the center. The region P2 includes a portion where no inorganic insulating film such as the support substrate 745, the adhesive layer 742, and the insulating layer 744 is provided. Further, in the region P2, the wiring 760 is provided with the resin layer 746. By employing a structure in which only a conductive layer containing metal or alloy and a layer containing organic material are stacked without providing an inorganic insulating film in the foldable region P2 as much as possible, a crack can be prevented from being generated when it is bent. Further, by not providing the support substrate 745 in the region P2, a portion of the display device 700A can be bent with a small radius of curvature.

[0314] The display device of this embodiment also includes an input device such as a touch sensor. That is, the display device of this embodiment can also have a function of a touch panel.

[0315] As a mode of the sensor, various modes such as an electrostatic capacity type, a resistance film type, a surface acoustic wave type, an infrared type, an optical type, and a pressure sensitive type can be used. Further, two or more of the above modes can be used in combination.

[0316] As the touch panel, there are a so-called In-Cell type touch panel in which an input device is formed on the inner side of a pair of substrates, a so-called On-Cell type touch panel in which an input device is formed on a display device, a so-called Out-Cell type touch panel in which an input device is attached to a display device, and the like.

[0317] This embodiment can be combined with other embodiments as appropriate.

[0318] (Embodiment 3)

[0319] A display device including a semiconductor device of one embodiment of the present application is described with reference to FIG. 15 in this embodiment.

[0320] Since the semiconductor device of one embodiment of the present application has a good electrical characteristic, the reliability of a display device can be improved by using the semiconductor device for the display device. For example, the transistor of one embodiment of the present application can be applied to a transistor included in one or both of a pixel and a driver circuit of the display device.

[0321] FIG. 15A The display device illustrated includes a pixel portion 502, a driver circuit portion 504, a protection circuit 506, and a terminal portion 507. Note that a structure in which the protection circuit 506 is not provided can be employed.

[0322] A transistor included in the pixel portion 502 or the driver circuit portion 504 can be a transistor of one embodiment of the present application. Further, a transistor of one embodiment of the present application can be used for the protection circuit 506.

[0323] The pixel section 502 includes a plurality of pixel circuits 501 configured to drive a plurality of display elements arranged in X rows and Y columns (X and Y are each an integer of two or more).

[0324] The drive circuit section 504 includes a drive circuit such as a gate driver 504a that outputs a scan signal to the gate lines GL_1 to GL_X, a source driver 504b that supplies a data signal to the data lines DL_1 to DL_Y, and the like. The gate driver 504a includes at least a shift register. Further, the source driver 504b is configured, for example, by a plurality of analog switches and the like. Further, the source driver 504b can also be configured by a shift register and the like.

[0325] The terminal section 507 refers to a section in which a terminal for inputting a power supply, a control signal, an image signal, and the like from an external circuit to the display device is provided.

[0326] The protection circuit 506 is a circuit that brings a wiring to which the protection circuit 506 is connected and another wiring into a conduction state when a potential outside a certain range is supplied to the wiring. FIG. 15A The protection circuit 506 is connected to various wirings such as the scan lines GL between the gate driver 504a and the pixel circuit 501, or the data lines DL between the source driver 504b and the pixel circuit 501, for example.

[0327] The gate driver 504a and the source driver 504b can be configured to be directly formed on the same substrate as the pixel section 502, or can be configured to be formed on another substrate and mounted on a substrate on which the pixel section is formed in COG or TAB (Tape Automated Bonding).

[0328] FIG. 15A The plurality of pixel circuits 501 can be configured, for example, in the structure illustrated in FIG. 6. FIG. 15B and FIG. 15C

[0329] FIG. 15B The pixel circuit 501 includes a liquid crystal element 570, a transistor 550, and a capacitor 560. The pixel circuit 501 is connected to a data line DL_n, a scan line GL_m, a potential supply line VL, and the like.

[0330] ​The potential of one of the pair of electrodes of the liquid crystal element 570 is set in accordance with the specifications of the pixel circuit 501. The alignment state of the liquid crystal element 570 is set in accordance with the data that is written. Further, a common potential can be supplied to one of the pair of electrodes of the liquid crystal element 570 of each of the plurality of pixel circuits 501. Further, different potentials can be supplied to one of the pair of electrodes of the liquid crystal element 570 of each of the pixel circuits 501 of each row.

[0331] FIG. 15C The pixel circuit 501 illustrated includes a transistor 552, a transistor 554, a capacitor 562, and a light emitting element 572. The pixel circuit 501 is connected to a data line DL_n, a scan line GL_m, a potential supply line VL_a, and a power supply line VL_b, and the like.

[0332] One of the potential supply line VL_a and the potential supply line VL_b is applied with a high power supply potential VDD, and the other is applied with a low power supply potential VSS. The current flowing through the light emitting element 572 is controlled in accordance with the potential applied to the gate of the transistor 554, and thus the luminance of light from the light emitting element 572 is controlled.

[0333] The present embodiment can be appropriately combined with other embodiments.

[0334] (Embodiment 4)

[0335] A display device including a semiconductor device of one embodiment of the present application is described with reference to FIG. 16 in this embodiment.

[0336] The pixel of the display device of this embodiment includes a memory for correcting the gray scale displayed in the pixel. The transistor of one embodiment of the present application can be applied to the transistor included in the pixel.

[0337] [Pixel Circuit]

[0338] FIG. 16A A circuit diagram of a pixel circuit 400 is shown. The pixel circuit 400 includes a transistor M1, a transistor M2, a capacitor C1, and a circuit 401. The pixel circuit 400 is connected to a wiring S1, a wiring S2, a wiring G1, and a wiring G2.

[0339] The gate of the transistor M1 is connected to the wiring G1, one of a source and a drain is connected to the wiring S1, and the other is connected to one electrode of the capacitor C1. The gate of the transistor M2 is connected to the wiring G2, one of a source and a drain is connected to the wiring S2, and the other is connected to the other electrode of the capacitor C1 and the circuit 401.

[0340] The circuit 401 includes at least one display element. The display element can use a variety of elements, and typically can use a light-emitting element such as an organic EL element or an LED element, a liquid crystal element, or a MEMS element.

[0341] The node connecting the transistor M1 and the capacitor C1 is denoted as N1, and the node connecting the transistor M2 and the circuit 401 is denoted as N2.

[0342] The pixel circuit 400 can hold the potential of the node N1 by making the transistor M1 into an off state. In addition, the potential of the node N2 can be held by making the transistor M2 into an off state. In addition, when a predetermined potential is written to the node N1 through the transistor M1 in a state where the transistor M2 is in an off state, the potential of the node N2 can be changed in correspondence with the change in the potential of the node N1 due to capacitive coupling through the capacitor C1.

[0343] Here, one or both of the transistor M1 and the transistor M2 can use the transistor using an oxide semiconductor illustrated in Embodiment 1. Since the transistor has a very small off-state current, the potentials of the nodes N1 and N2 can be held for a long time. In addition, when the potential holding period of each node is short (particularly, when the frame frequency is 30 Hz or higher, or the like), a transistor using a semiconductor such as silicon can be employed.

[0344] [Driving method]

[0345] Reference Signs FIG. 16B An example of the operation method of the pixel circuit 400 will be described. FIG. 16B is a timing chart of the operation of the pixel circuit 400. Note that here, for convenience of explanation, the effects of various resistances such as wiring resistances, parasitic capacitances of transistors or wirings, and threshold voltages of transistors are not taken into account.

[0346] In FIG. 16B the operation shown in FIG. 8, one frame period is divided into a period T1 and a period T2. The period T1 is a period in which a potential is written to the node N2, and the period T2 is a period in which a potential is written to the node N1.

[0347] In the period T1, both the wiring G1 and the wiring G2 are supplied with a potential which makes the transistors into an on state. In addition, the wiring S1 is supplied with a potential V ref , which is a fixed potential. The wiring S2 is supplied with a first data potential V w .

[0348] The node N1 is supplied with a potential V ref from the wiring S1 through the transistor M1. In addition, the node N2 is supplied with the first data potential V w through the transistor M2. Thus, the capacitor C1 becomes to hold a potential difference Vw -V ref The state.

[0349] During period T2, wiring G1 is supplied with a potential that turns transistor M1 on, and wiring G2 is supplied with a potential that turns transistor M2 off. Wiring S1 is supplied with the second data potential V. data Additionally, a predetermined constant potential is provided to wiring S2 or it is made to float.

[0350] Node N1 is supplied with a second data potential V through transistor M1. data At this time, due to capacitive coupling through capacitor C1, the corresponding second data potential V... data The potential of node N2 changes by a value of dV. In other words, circuit 401 is input with the first data potential V. w The potential added together with the potential dV. Note that, although... FIG. 16B The diagram shows dV as a positive value, but it can also be negative. That is, the potential V... data It can also be compared to the potential V ref Low.

[0351] Here, the potential dV is primarily determined by the capacitance of capacitor C1 and the capacitance of circuit 401. When the capacitance of capacitor C1 is sufficiently greater than the capacitance of circuit 401, the potential dV becomes close to the second data potential V. data The potential.

[0352] As described above, since the pixel circuit 400 can combine two data signals to generate a potential supplied to the circuit 401 including the display element, grayscale correction can be performed within the pixel circuit 400.

[0353] Furthermore, the pixel circuit 400 can generate a potential exceeding the maximum potential that can be supplied to wiring S1 and wiring S2. For example, when using a light-emitting element, high dynamic range (HDR) display can be achieved. Additionally, when using a liquid crystal element, overdrive can be implemented.

[0354] [Including pixel circuitry for liquid crystal elements]

[0355] FIG. 16C The pixel circuit 400LC shown includes circuit 401LC. Circuit 401LC includes a liquid crystal element LC and a capacitor C2.

[0356] One electrode of the liquid crystal element LC is connected to node N2 and one electrode of capacitor C2, and the other electrode is connected to the supplied potential V. com2 The wiring connection. The other electrode of capacitor C2 is connected to the supplied potential V. com1 Wiring connections.

[0357] The capacitor C2 functions as a storage capacitor. The capacitor C2 can be omitted when not needed.

[0358] Since the pixel circuit 400LC can supply a high voltage to the liquid crystal element LC, high-speed display can be achieved by overdrive, for example, and a liquid crystal material with a high driving voltage can be used. In addition, by supplying a correction signal to the wiring S1 or the wiring S2, gradation correction can be performed in accordance with the use temperature or the deterioration state of the liquid crystal element LC, or the like.

[0359] [Pixel circuit including light emitting element]

[0360] FIG. 16D The pixel circuit 400EL illustrated includes a circuit 401EL. The circuit 401EL includes a light emitting element EL, a transistor M3, and a capacitor C2.

[0361] The gate of the transistor M3 is connected to the node N2 and one electrode of the capacitor C2, one of a source and a drain is connected to a wiring to which a potential V H is supplied, and the other of the source and the drain is connected to one electrode of the light emitting element EL. The other electrode of the capacitor C2 is connected to a wiring to which a potential V com is supplied. The other electrode of the light emitting element EL is connected to a wiring to which a potential V L is supplied.

[0362] The transistor M3 has a function of controlling a current supplied to the light emitting element EL. The capacitor C2 functions as a storage capacitor. The capacitor C2 can be omitted when not needed.

[0363] In addition, although a structure in which the anode side of the light emitting element EL is connected to the transistor M3 is illustrated here, a structure in which the cathode side is connected to the transistor M3 can be employed. When the structure in which the cathode side is connected to the transistor M3 is employed, the values of the potential V H and the potential V L can be changed as appropriate.

[0364] In the pixel circuit 400EL, a large current can flow through the light emitting element EL by applying a high potential to the gate of the transistor M3, and thus HDR display or the like can be achieved. Furthermore, by supplying a correction signal to the wiring S1 or the wiring S2, the electrical characteristics of the transistor M3 and the light emitting element EL can be corrected.

[0365] In addition, the circuit illustrated in FIG. 16C , FIG. 16D is not limited thereto, and a structure in which a transistor or a capacitor or the like is additionally provided can be employed.

[0366] The present embodiment can be combined with other embodiments as appropriate.

[0367] (Embodiment 5)

[0368] A display module of one embodiment of the present application is described with reference to FIG. 17.

[0369] FIG. 17A The display module 6000 illustrated includes a display device 6006 connected to an FPC 6005, a frame 6009, a printed circuit board 6010, and a battery 6011 between a top cover 6001 and a bottom cover 6002.

[0370] The display device manufactured using the transistor of one embodiment of the present application can be used as the display device 6006. With the use of the display device 6006, a display module with high reliability can be achieved.

[0371] The top cover 6001 and the bottom cover 6002 can be appropriately changed in shape or size depending on the size of the display device 6006.

[0372] The display device 6006 can have a function as a touch panel.

[0373] The frame 6009 has a function of protecting the display device 6006, a function of blocking electromagnetic waves generated due to the operation of the printed circuit board 6010, a function of a heat dissipation plate, and the like.

[0374] The printed circuit board 6010 has a power supply circuit and a signal processing circuit for outputting a video signal and a clock signal, a battery control circuit, and the like. Further, the battery 6011 can be used as a power supply.

[0375] FIG. 17B FIG. 17 is a cross-sectional view of a display module 6000 provided with an optical touch sensor.

[0376] The display module 6000 includes a light emitting portion 6015 and a light receiving portion 6016 provided over the printed circuit board 6010. Further, a pair of light guide portions (light guide portion 6017a and light guide portion 6017b) is provided in a region surrounded by the top cover 6001 and the bottom cover 6002.

[0377] The display device 6006 overlaps with the printed circuit board 6010 and the battery 6011 with the frame 6009 therebetween. The display device 6006 and the frame 6009 are fixed to the light guide portion 6017a and the light guide portion 6017b.

[0378] Light 6018 emitted from the light emitting portion 6015 passes through the light guide portion 6017a, the top of the display device 6006, and the light guide portion 6017b to reach the light receiving portion 6016. For example, when the light 6018 is blocked by a detected object such as a finger or a stylus, a touch operation can be detected.

[0379] For example, a plurality of light emitting portions 6015 are provided along two adjacent sides of the display device 6006. A plurality of light receiving portions 6016 are arranged at positions opposite to the light emitting portions 6015. Thus, information of a position of a touch operation can be obtained.

[0380] As the light emitting portion 6015, a light source such as an LED element can be used, and particularly, a light source that emits infrared light is preferably used. As the light receiving portion 6016, a photoelectric element that receives light emitted from the light emitting portion 6015 and converts the light into an electric signal can be used. A photodiode that can receive infrared light is preferably used.

[0381] By using the light guide portions 6017a and 6017b that transmit light 6018, the light emitting portion 6015 and the light receiving portion 6016 can be arranged on the lower side in the display device 6006, and the erroneous operation of the touch sensor due to external light reaching the light receiving portion 6016 can be suppressed. Particularly, when a resin that absorbs visible light and transmits infrared light is used, the erroneous operation of the touch sensor can be more effectively suppressed.

[0382] The present embodiment can be combined with other embodiments as appropriate.

[0383] (Embodiment 6)

[0384] In this embodiment, an electronic device of one embodiment of the present application will be described with reference to FIGS. 18 to 21.

[0385] The electronic device of this embodiment includes a semiconductor device of one embodiment of the present application. For example, a transistor of one embodiment of the present application can be applied to a transistor of a display device used for a display portion of an electronic device. The transistor of one embodiment of the present application has stable and good electrical characteristics and high reliability, and thus the reliability of the display device and the electronic device can be improved. Thus, the transistor of one embodiment of the present application can be used for various electronic devices.

[0386] An image with a resolution of full high vision, 4K2K, 8K4K, 16K8K, or higher can be displayed on the display portion of the electronic device of this embodiment, for example.

[0387] As the electronic device, for example, a digital camera, a digital video camera, a digital photo frame, a mobile phone, a portable game console, a portable information terminal, a sound reproduction device, or the like can be given in addition to a television device, a desktop or a notebook personal computer, a display for a computer or the like, a digital signage, a large game machine such as a pinball machine, and the like having a large screen.

[0388] The electronic device of this embodiment can be assembled along a curved surface of an inner wall or an outer wall of a house or a high-rise building, an interior or an exterior of a car, or the like.

[0389] The electronic device of this embodiment can also include an antenna. By receiving a signal with the antenna, an image or information or the like can be displayed on the display portion. In addition, when the electronic device includes an antenna and a secondary battery, the antenna can be used for noncontact power transfer.

[0390] The electronic device of this embodiment can also include a sensor having a function of measuring a factor of force, displacement, position, velocity, acceleration, angular velocity, rotational frequency, distance, light, liquid, magnetism, temperature, chemical substance, sound, time, hardness, electric field, electric current, voltage, electric power, radiation, flow rate, humidity, inclination, vibration, odor, or infrared rays.

[0391] The electronic device of this embodiment can have various functions. For example, it can have a function of displaying various information (still images, moving images, character images, and the like) on the display portion; a function of a touch panel; a function of displaying a calendar, date, time, or the like; a function of executing various software (programs); a function of performing wireless communication; a function of reading out a program or data stored in a storage medium; and the like.

[0392] FIG. 18A The electronic device 6500 shown is a portable information terminal device that can be used as a smartphone.

[0393] The electronic device 6500 includes a housing 6501, a display portion 6502, a power button 6503, a button 6504, a speaker 6505, a microphone 6506, a camera 6507, a light source 6508, and the like. The display portion 6502 has a touch panel function.

[0394] The display portion 6502 can use a display device including a transistor of one embodiment of the present application.

[0395] FIG. 18B FIG. 19B is a cross-sectional view of an end portion of the microphone 6506 on the side of the housing 6501.

[0396] The display surface side of the housing 6501 is provided with a protective member 6510 having light-transmitting properties. A display panel 6511, an optical member 6512, a touch sensor panel 6513, a printed board 6517, a battery 6518, and the like are provided in a space surrounded by the housing 6501 and the protective member 6510.

[0397] The display panel 6511, the optical member 6512, and the touch sensor panel 6513 are fixed to the protective member 6510 with an adhesive layer (not shown).

[0398] In a region outside the display portion 6502, part of the display panel 6511 is folded back, and an FPC 6515 is connected to the folded-back portion. The FPC 6515 is provided with an IC 6516. The FPC 6515 is connected to a terminal included in a printed circuit board 6517.

[0399] The display panel 6511 can be formed using a flexible display of one embodiment of the present application. With this structure, an electronic device with a small thickness can be achieved. Furthermore, since the display panel 6511 is thin, a large-capacity battery 6518 can be mounted without increasing the thickness of the electronic device. Furthermore, by folding back part of the display panel 6511 to provide a connection portion to the FPC 6515 on the back surface of the pixel portion, an electronic device with narrow bezels can be achieved.

[0400] FIG. 19A An example of a television device is shown. In the television device 7100, a display portion 7000 is incorporated in a housing 7101. Here, a structure in which the housing 7101 is supported by a stand 7103 is shown.

[0401] A display device including a transistor of one embodiment of the present application can be used for the display portion 7000.

[0402] The operation of the television device 7100 shown in FIG. 8 can be performed by operating switches included in the housing 7101 or a remote control 7111 provided separately. FIG. 19A In addition, a touch sensor can be provided in the display portion 7000, and the operation of the television device 7100 can be performed by touching the display portion 7000 with a finger or the like. Furthermore, a display portion which displays data output from the remote control 7111 can be provided in the remote control 7111. The channel and volume can be operated by operating keys or a touch panel included in the remote control 7111, and an image displayed on the display portion 7000 can be operated.

[0403] In addition, the television device 7100 includes a receiver and a modem, or the like. General television broadcasting can be received by means of the receiver. Furthermore, connection to a communication network is possible by means of the modem, so that unidirectional (from transmitter to receiver) or bidirectional (between transmitter and receiver, between receivers, etc.) information communication is possible.

[0404] FIG. 19B An example of a notebook personal computer is shown. The notebook personal computer 7200 includes a housing 7211, a keyboard 7212, a pointing device 7213, an external connection port 7214, and the like. The display portion 7000 is incorporated in the housing 7211.

[0405] A display device including a transistor of one embodiment of the present application can be used for the display portion 7000.

[0406] FIG. 19C and FIG. 19D An example of a digital sign is shown.

[0407] FIG. 19C The digital sign 7300 shown includes a frame 7301, a display portion 7000, and a speaker 7303, and the like. Further, an LED lamp, an operation key (including a power switch or an operation switch), a connection terminal, various sensors, a microphone, and the like can be included.

[0408] FIG. 19D A digital sign 7400 provided on a cylindrical column 7401 is shown. The digital sign 7400 includes a display portion 7000 provided along the curved surface of the column 7401.

[0409] In FIG. 19C and FIG. 19D , a display device including a transistor of one embodiment of the present application can be applied to the display portion 7000.

[0410] The larger the display portion 7000 is, the more information can be provided at one time. The larger the display portion 7000 is, the more likely it is to attract attention, and for example, the effect of advertisement can be improved.

[0411] By using a touch panel for the display portion 7000, not only a still image or a moving image can be displayed on the display portion 7000, but also a user can intuitively operate, which is preferable. Further, in the use for providing information such as route information or traffic information, the ease of use can be improved by intuitive operation.

[0412] As shown in FIG. 19C and FIG. 19D , the digital sign 7300 or the digital sign 7400 can be preferably linked to an information terminal device 7311 or an information terminal device 7411 carried by a user through wireless communication. For example, advertisement information displayed on the display portion 7000 can be displayed on the screen of the information terminal device 7311 or the information terminal device 7411. Further, by operating the information terminal device 7311 or the information terminal device 7411, the display of the display portion 7000 can be switched.

[0413] Further, a game can be executed on the digital sign 7300 or the digital sign 7400 with the screen of the information terminal device 7311 or the information terminal device 7411 as an operation unit (controller). Thus, a plurality of users can participate in the game at the same time, and enjoy the game.

[0414] FIG. 20A is an external view of a camera 8000 in which a viewfinder 8100 is mounted.

[0415] The camera 8000 includes a housing 8001, a display portion 8002, an operation button 8003, a shutter button 8004, and the like. Further, the camera 8000 is provided with a detachable lens 8006. In the camera 8000, the lens 8006 and the housing can be formed integrally.

[0416] The camera 8000 can perform imaging by pressing the shutter button 8004 or touching the display portion 8002 serving as a touch panel.

[0417] The housing 8001 includes an embedder having an electrode, and can be connected to a viewfinder 8100, a flash device, or the like, in addition to the lens 8006.

[0418] The viewfinder 8100 includes a housing 8101, a display portion 8102, a button 8103, and the like.

[0419] The housing 8101 is attached to the camera 8000 by fitting to the embedder of the camera 8000. The viewfinder 8100 can display an image or the like received from the camera 8000 on the display portion 8102.

[0420] The button 8103 is used as a power button or the like.

[0421] A display device including a transistor of one embodiment of the present application can be used for the display portion 8002 of the camera 8000 and the display portion 8102 of the viewfinder 8100. Further, the viewfinder can be built in the camera 8000.

[0422] FIG. 20B FIG. 20A is an external view of a head-mounted display 8200.

[0423] The head-mounted display 8200 includes a mounting portion 8201, a lens 8202, a main body 8203, a display portion 8204, a cable 8205, and the like. Further, a battery 8206 is built in the mounting portion 8201.

[0424] Power is supplied from the battery 8206 to the main body 8203 through the cable 8205. The main body 8203 has a wireless receiver or the like and can display received image information or the like on the display portion 8204. Further, the main body 8203 has a camera, and thus the user's eye movement and eyelid movement can be used as input methods.

[0425] Further, a plurality of electrodes can be provided at a position of the mounting portion 8201 which is touched by the user, so that a current flowing through the electrodes in accordance with movement of the eyeball of the user is detected, whereby a function of recognizing the line of sight of the user is realized. Further, a function of monitoring the pulse of the user in accordance with the current flowing through the electrodes can be provided. The mounting portion 8201 can have various sensors such as a temperature sensor, a pressure sensor, an acceleration sensor, and the like, and can have a function of displaying biological information of the user on the display portion 8204 or a function of changing an image displayed on the display portion 8204 in synchronization with movement of the head of the user.

[0426] A display device including a transistor of one embodiment of the present application can be used for the display portion 8204.

[0427] FIG. 20C to FIG. 20E FIG. 17A is a view of the appearance of a head-mounted display 8300. The head-mounted display 8300 includes a housing 8301, a display portion 8302, a band-shaped fixing tool 8304, and a pair of lenses 8305.

[0428] The user can see display on the display portion 8302 through the lenses 8305. It is preferable that the display portion 8302 be curved. Since the user can feel high reality. Further, images displayed on different regions of the display portion 8302 are seen through the lenses 8305, respectively, so that three-dimensional display using parallax or the like can be performed. Further, one embodiment of the present application is not limited to a structure provided with one display portion 8302, and two display portions 8302 can be provided to be arranged for one pair of eyes of the user.

[0429] The display portion 8302 can apply a display device including a transistor of one embodiment of the present application. Further, a display device with extremely high definition can be manufactured using a transistor of one embodiment of the present application. For example, as illustrated in FIG. 17B, even when display is enlarged and viewed using the lenses 8305, pixels are not easily viewed by the user. That is, the user can view an image with higher reality using the display portion 8302. FIG. 20E

[0430] FIG. 21A to FIG. 21F The electronic device illustrated in FIG. 18 includes a housing 9000, a display portion 9001, a speaker 9003, an operation key 9005 (including a power source switch or an operation switch), a connection terminal 9006, a sensor 9007 (which has a function of measuring a force, a displacement, a position, a speed, an acceleration, an angular velocity, an angular acceleration, a distance, light, a liquid, a magnetism, a temperature, a chemical substance, a sound, a time, a hardness, an electric field, an electric current, a voltage, an electric power, a radiation, a flow rate, a humidity, an inclination, a vibration, a smell, or an infrared ray), a microphone 9008, and the like.

[0431] FIG. 21A to FIG. 21F ​The electronic device shown has various functions. For example, it may have the following functions: displaying various information (still images, moving images, and text images, etc.) on a display unit; a touch panel function; displaying a calendar, date, or time; controlling processing using various software (programs); wireless communication function; reading and processing programs or data stored in a storage medium; etc. Note that the electronic device may have functions beyond those listed above, and may possess a variety of functions. The electronic device may include multiple display units. Furthermore, a camera or similar device may be incorporated into the electronic device to enable it to: capture still or moving images and store the captured images in a storage medium (external storage medium or storage medium built into the camera); display the captured images on a display unit; etc.

[0432] The following is a detailed explanation. FIG. 21A to FIG. 21F The electronic device shown.

[0433] FIG. 21A This is a perspective view showing a portable information terminal 9101. The portable information terminal 9101 can be used, for example, as a smartphone. Note that a speaker 9003, a connection terminal 9006, a sensor 9007, etc., may also be included in the portable information terminal 9101. Furthermore, as a portable information terminal 9101, text or image information can be displayed on multiple surfaces. FIG. 21A Examples of three icons 9050 are shown. Furthermore, information 9051, indicated by a dashed rectangle, can be displayed on other surfaces of the display unit 9001. Examples of information 9051 include notifications of received emails, SNS messages, or phone calls; the subject of the email or SNS message; the sender's name; the date; the time; remaining battery level; and displays of antenna signal strength. Alternatively, icons 9050 can be displayed in the same locations where information 9051 is displayed.

[0434] FIG. 21B This is a perspective view showing a portable information terminal 9102. The portable information terminal 9102 has the function of displaying information on three or more surfaces of the display unit 9001. Here, examples are shown where information 9052, information 9053, and information 9054 are displayed on different surfaces. For example, when the portable information terminal 9102 is placed in a jacket pocket, the user can check information 9053 displayed in a position seen from above the portable information terminal 9102. The user can check this display without taking the portable information terminal 9102 out of their pocket, thereby determining whether to answer a phone call.

[0435] FIG. 21Cis a perspective view illustrating a wristwatch-type portable information terminal 9200. The portable information terminal 9200 can be used as, for example, a smart watch. Further, a display surface of a display portion 9001 is curved, and display can be performed along the curved display surface. Further, the portable information terminal 9200 can perform hands-free calling by communicating with a headset capable of wireless communication, for example. Further, the portable information terminal 9200 can perform data transmission with or charging from another information terminal by using a connection terminal 9006. Charging can also be performed by wireless power feeding.

[0436] FIG. 21D to FIG. 21F is a perspective view illustrating a portable information terminal 9201 which can be folded. Further, FIG. 21D is a perspective view of a state in which the portable information terminal 9201 is unfolded, FIG. 21F is a perspective view of a state in which the portable information terminal 9201 is folded, FIG. 21E is a perspective view of a state in which the portable information terminal 9201 is folded, FIG. 21D is a perspective view of a state in which the portable information terminal 9201 is unfolded, FIG. 21F is a perspective view of a state in which the portable information terminal 9201 is folded. The portable information terminal 9201 is easy to carry in the folded state, and display is easy to view in the unfolded state because a large display region is seamlessly connected. A display portion 9001 included in the portable information terminal 9201 is supported by three housing bodies 9000 which are connected by a hinge 9055. The display portion 9001 can be curved, for example, in a range of a radius of curvature of 0.1 mm or more and 150 mm or less.

[0437] This embodiment mode can be combined as appropriate with other embodiment modes and examples.

[0438] [Example 1]

[0439] In this example, a transistor of one embodiment of the present application is manufactured and evaluated, and the results are described. In particular, in this example, a case where a metal oxide layer 114 includes the same metal oxide (IGZO) as a semiconductor layer 108 is described.

[0440] [Etching rate of metal oxide layer 114f]

[0441] First, the etching rate of the metal oxide layer 114f is evaluated. Here, six samples are manufactured, and the etching rate of the metal oxide layer 114f in each sample is evaluated.

[0442] In each of the samples, an IGZO film having a thickness of approximately 20 nm was formed as the metal oxide layer 114f. The IGZO film was formed by a sputtering method using a metal oxide target having an atomic ratio of In:Ga:Zn = 4:2:4.1 under conditions of an oxygen flow ratio of 100% and a substrate temperature of 200°C. After the formation of the IGZO film, heat treatment was performed at 350°C for 1 hour in a mixed atmosphere of oxygen and nitrogen.

[0443] Further, in three of the samples, boron (B) was supplied to the metal oxide layer 114f using a plasma ion doping apparatus that does not have a mass separation mechanism. As the gas used to supply boron, B2H6 gas was used, the acceleration voltage was 40 kV, and the dose was 2 x 1014ions / cm2. 15 2 In the other three samples, boron was not supplied to the metal oxide layer 114f.

[0444] Next, wet etching was performed on the metal oxide layer 114f. As the etchant, three types of etchant were used, namely, oxalic acid (5% or less, liquid temperature of 60°C, spin treatment), mixed acid (phosphoric acid of less than 80%, nitric acid of less than 5%, acetic acid of less than 10%, water of 5% or more, liquid temperature of 30°C, spray treatment), and a 30-fold diluted aqueous solution of phosphoric acid (liquid temperature of room temperature, spin treatment). Wet etching was performed on each of the metal oxide layers 114f in the samples to which boron was supplied and the samples to which boron was not supplied using each of the etchants.

[0445] FIG. 22 The results of the etching rate (unit: nm / min.) of each of the samples are shown. In addition, the etching rate was found by optical interferometric film thickness measurement.

[0446] It was found that the etching rate of the sample to which boron was supplied (B-doped) was higher than that of the sample to which boron was not supplied (not B-doped) in each case in which any of the etchants was used. In particular, when oxalic acid was used, the etching rate of the metal oxide layer 114f was approximately 2.5 times higher when boron was supplied to the metal oxide layer 114f than when boron was not supplied.

[0447] It was found that the etching rate can be increased by supplying boron to the metal oxide layer 114f. It is considered that the supply of boron to the metal oxide layer 114f reduces the crystallinity of the metal oxide layer 114f, and thus the etching rate is increased.

[0448] [Cross-sectional observation of the metal oxide layer 114]

[0449] Next, the metal oxide layer 114 was formed by wet etching of the metal oxide layer 114f, and cross-sectional observation was performed. Two samples were manufactured, and cross-sectional observation was performed. ​

[0450] As a sample, forming a corresponding FIG. 1A to FIG. 1C The transistor 100 shown is a stacked structure. Specifically, an insulating layer 103, a semiconductor layer 108, a gate insulating layer 110, a metal oxide layer 114, a gate electrode 112, and an insulating layer 118 are formed on a substrate 102.

[0451] The formation conditions for the metal oxide layer 114f are the same as described above. After the metal oxide layer 114f is formed on the gate insulating layer 110, a molybdenum film is formed as the gate electrode 112. In one of the two samples, the gate electrode 112 is used as a mask, and boron is supplied to the metal oxide layer 114f. In the other sample, boron is not supplied to the metal oxide layer 114f.

[0452] Then, using the gate electrode 112 as a mask, the metal oxide layer 114f is processed to form the metal oxide layer 114. Here, wet etching is used to process the metal oxide layer 114f.

[0453] The wet etching of the metal oxide layer 114f was performed using oxalic acid (5% or less, liquid temperature 60°C, spin etching). The processing time for samples with no boron supplied to the metal oxide layer 114f was 30 seconds, and the processing time for samples with boron supplied to the metal oxide layer 114f was 10 seconds. Furthermore, the processing time depends on the etching rate of the metal oxide layer 114f described above. FIG. 22 Specifically, when boron is supplied to the metal oxide layer 114f, the etching rate of the metal oxide layer 114f increases, thus making the processing time of the sample with boron supplied shorter than that of the sample without boron supplied.

[0454] FIG. 23A A cross-sectional photograph of a sample in which the metal oxide layer 114f was not supplied with boron is shown. FIG. 23B A cross-sectional photograph of a sample supplied with boron is shown.

[0455] like FIG. 23A As shown in the section surrounded by dashed lines, in the sample where no boron is supplied to the metal oxide layer 114f, a portion (the lower part) of the metal oxide layer 114f that overlaps with the gate electrode 112 is etched.

[0456] On the other hand, such as FIG. 23B As shown in the section surrounded by the dashed line, in the sample supplied with boron, it can be confirmed that the etching of the metal oxide layer 114 overlapping with the gate electrode 112 is suppressed, thereby improving the coverage of the insulating layer 118.

[0457] Therefore, by using the gate electrode 112 as a mask to supply boron to the metal oxide layer 114f, a difference in etching rates can be achieved between the boron-supplied portion (the portion not overlapping with the gate electrode 112) and the non-boron-supplied portion (the portion overlapping with the gate electrode 112). Consequently, the portion of the metal oxide layer 114 overlapping with the gate electrode 112 is less likely to be etched, thereby suppressing shape defects in the metal oxide layer 114. This, in turn, improves the coverage of the insulating layer 118, thus suppressing poor coverage.

[0458] [Electrical characteristics and reliability evaluation of transistors]

[0459] Next, transistors were manufactured, and their electrical characteristics and reliability were evaluated. Six samples were manufactured in this process.

[0460] As each sample, a corresponding FIG. 3A to FIG. 3C The transistor 100A shown is a stacked structure. Specifically, a conductive layer 106, an insulating layer 103, a semiconductor layer 108, a gate insulating layer 110, a metal oxide layer 114, a gate electrode 112, an insulating layer 118, a conductive layer 120a, and a conductive layer 120b are formed on a substrate 102. Furthermore, a planarization film (not shown) is formed on the insulating layer 118, the conductive layer 120a, and the conductive layer 120b.

[0461] In samples A to C, which apply one aspect of the present invention, as shown in Embodiment 1, the metal oxide layer 114f is etched after the impurity element 140 is supplied to form the metal oxide layer 114. In comparative samples A to C, the metal oxide layer 114f is etched to form the metal oxide layer 114, and then the impurity element 140 is supplied.

[0462] As sample A and control sample A, a transistor with a channel length of 2 μm and a channel width of 50 μm was manufactured. As sample B and control sample B, a transistor with a channel length of 3 μm and a channel width of 50 μm was manufactured. As sample C and control sample C, a transistor with a channel length of 6 μm and a channel width of 50 μm was manufactured.

[0463] The following figures 5 to 7 illustrate the specific manufacturing method of transistors.

[0464] First, a tungsten film with a thickness of approximately 100 nm is formed on a glass substrate (equivalent to substrate 102) by sputtering. This tungsten film is then processed to form a conductive layer 106. FIG. 5A ).

[0465] Next, as the insulating layer 103, a silicon nitride film having a thickness of about 240 nm, a silicon nitride film having a thickness of about 60 nm, and a silicon oxynitride film having a thickness of about 5 nm were sequentially formed over the substrate 102 and the conductive layer 106 by a plasma CVD method. FIG. 5A

[0466] Next, an IGZO film having a thickness of about 50 nm was formed over the insulating layer 103, and the IGZO film was processed to form a semiconductor layer 108. FIG. 5B The IGZO film was formed by a sputtering method using a metal oxide target having an atomic ratio of In:Ga:Zn = 4:2:4.1 at an oxygen flow ratio of 10% and a substrate temperature of room temperature. After the formation of the IGZO film, heat treatment was performed at 350 °C for 1 hour in a nitrogen atmosphere, and then heat treatment was performed at 350 °C for 1 hour in a mixed atmosphere of oxygen and nitrogen.

[0467] Next, as the gate insulating layer 110, a silicon oxynitride film having a thickness of about 150 nm was formed over the insulating layer 103 and the semiconductor layer 108 by a plasma CVD method. FIG. 5C

[0468] Next, as the metal oxide layer 114f, an IGZO film having a thickness of about 20 nm was formed over the gate insulating layer 110 by a sputtering method in an atmosphere containing oxygen. FIG. 5C By forming the metal oxide layer 114f in an atmosphere containing oxygen, oxygen can be supplied to the gate insulating layer 110. The IGZO film was formed by a sputtering method using a metal oxide target having an atomic ratio of In:Ga:Zn = 4:2:4.1 at an oxygen flow ratio of 100% and a substrate temperature of 200 °C. After the formation of the IGZO film, heat treatment was performed at 350 °C for 1 hour in a mixed atmosphere of oxygen and nitrogen.

[0469] Next, as the conductive film 112f, a molybdenum film having a thickness of about 100 nm was formed over the metal oxide layer 114f by a sputtering method FIG. 5D ), and the molybdenum film was processed to form a gate electrode 112 FIG. 5E ).

[0470] Next, for Samples A to C each of which is a sample to which one embodiment of the present application is applied, boron (B) was supplied using a plasma ion doping apparatus FIG. 6A In this step, the gate electrode 112 was used as a mask to supply boron to the semiconductor layer 108, the gate insulating layer 110, and the metal oxide layer 114f. As a gas for supplying boron, B2H6 gas was used, the acceleration voltage was 40 kV, and the dose was 2 x 1015 ions / cm 15 2 ​​​The metal oxide layer 114f is then processed by wet etching to form a metal oxide layer 114f FIG. 6B When the metal oxide layer 114f is wet-etched, oxalic acid (5% or less, liquid temperature 60°C, spin treatment) is used, and the treatment time is 10 sec.

[0471] On the other hand, for the comparative samples A to C, the metal oxide layer 114f is first processed by wet etching to form a metal oxide layer 114. When the metal oxide layer 114f is wet-etched, oxalic acid (5% or less, liquid temperature 60°C, spin treatment) is used, and the treatment time is 30 sec. Then, boron (B) is supplied using a plasma ion doping device. In this process, the gate electrode 112 is used as a mask to supply boron to the semiconductor layer 108 and the gate insulating layer 110.

[0472] The subsequent processes are common to the samples and the comparative samples. As the insulating layer 118, a silicon oxynitride film 118a having a thickness of about 300 nm is formed by a plasma CVD method on the gate insulating layer 110, the metal oxide layer 114, and the gate electrode 112. FIG. 7A

[0473] Next, openings are partially formed in the gate insulating layer 110 and the insulating layer 118. Then, a molybdenum film having a thickness of about 100 nm is formed by a sputtering method and processed to form a conductive layer 120a and a conductive layer 120b. FIG. 7B

[0474] Subsequently, as a planarization film (not shown), an acrylic resin film having a thickness of about 1.5 μm is formed, and heat treatment is performed at 250°C for 1 hour in a nitrogen atmosphere.

[0475] Each sample is manufactured by the above-described steps.

[0476] Next, in each sample, the Id-Vg characteristics of the transistor are measured. FIG. 24 The results of the Id-Vg characteristics of the transistor of each sample are shown.

[0477] As the measurement conditions of the Id-Vg characteristics of the transistor, the voltage applied to the gate electrode 112 (gate voltage (Vg)) and the voltage applied to the conductive layer 106 (back gate voltage (Vbg)) are changed from -15 V to +20 V at intervals of 0.25 V. In addition, the voltage applied to the source electrode (source voltage (Vs)) is 0 V (comm), and the voltage applied to the drain electrode (drain voltage (Vd)) is 0.1 V and 20 V.

[0478] As FIG. 24 ​​As shown, no significant differences were observed in the Id-Vg characteristics between sample A and control sample A. Similarly, no significant differences were observed in the Id-Vg characteristics between sample B and control sample B, or between sample C and control sample C.

[0479] This confirms that the order of processing the metal oxide layer 114f and supplying boron does not significantly affect the Id-Vg characteristics of the transistor. In other words, even if the metal oxide layer 114f is processed after the boron supply to suppress the etching of a portion (the lower part) of the metal oxide layer 114 overlapping with the gate electrode 112, a transistor with good electrical characteristics can still be manufactured.

[0480] Next, stress tests were performed on the transistors of sample B and control sample B.

[0481] As a stress test, a gate bias thermal stress test (GBT test) is used. The GBT test is an accelerated test that can evaluate changes in transistor characteristics due to prolonged use in a short time. In this GBT test, the substrate with the transistor is held at 60°C, and a voltage of 0V is applied to the source and drain of the transistor, while a voltage of 20V or -20V is applied to the gate, and this state is maintained for 3600 seconds. The test with a positive voltage applied to the gate is denoted as PBTS (Positive Bias Temperature Stress), and the test with a negative voltage applied to the gate is denoted as NBTS (Negative Bias Temperature Stress). Furthermore, the substrate with the transistor is held at 60°C, and under illumination of 10000lx white LED light, a voltage of 0V is applied to the source and drain of the transistor, while a voltage of 20V or -20V is applied to the gate, and this state is maintained for 3600 seconds. At this point, the test that applies a positive voltage to the gate is denoted as PBTIS (Positive Bias Temperature Illumination Stress), and the test that applies a negative voltage to the gate is denoted as NBTIS (Negative Bias Temperature Illumination Stress).

[0482] FIG. 25 The results of PBTS and NBTIS for sample B and control sample B are shown.

[0483] like FIG. 25 As shown, no significant difference was observed in the threshold fluctuation (ΔVth) between sample B and control sample B in PBTS and NBTIS.

[0484] It is thus confirmed that the order of the process of processing the metal oxide layer 114f and the process of supplying boron does not greatly affect the GBT test results of the transistor. That is, even if the metal oxide layer 114f is processed after the boron is supplied to suppress the portion (lower portion) of the metal oxide layer 114 overlapping with the gate electrode 112 from being etched, a transistor with high reliability can be manufactured.

[0485] [Embodiment 2]

[0486] In this embodiment, a transistor of one embodiment of the present application is manufactured and evaluated, and the results are described. In particular, in this embodiment, a case in which an aluminum oxide (AlO x ) film is used as the metal oxide layer 114 is described.

[0487] In this embodiment, a transistor is manufactured, and then the electrical characteristics and reliability thereof are evaluated. Here, four samples are manufactured. In this embodiment, a transistor with a channel length of 2 μm and a channel width of 50 μm is manufactured.

[0488] For the sample D and the sample E of one embodiment of the present application, a transistor including the metal oxide layer 114f is formed without performing a process of processing the metal oxide layer 114f using the gate electrode 112 as a mask. On the other hand, for the comparative sample F and the comparative sample G, a transistor including the metal oxide layer 114 is formed by etching the metal oxide layer 114f.

[0489] Next, a specific manufacturing method of a transistor is described with reference to FIGS. 5 and 9.

[0490] First, a tungsten film with a thickness of about 100 nm is formed over a glass substrate (corresponding to the substrate 102) by a sputtering method, and the tungsten film is processed to form the conductive layer 106 FIG. 5A ).

[0491] Next, as the insulating layer 103, a silicon nitride film with a thickness of about 240 nm, a silicon nitride film with a thickness of about 60 nm, and a silicon oxynitride film with a thickness of about 5 nm are sequentially formed over the substrate 102 and the conductive layer 106 by a plasma CVD method FIG. 5A ).

[0492] Next, an IGZO film is formed over the insulating layer 103, and the IGZO film is processed to form the semiconductor layer 108 FIG. 5B ).

[0493] In Sample D and Sample E, an IGZO film of approximately 30 nm in thickness was formed by a sputtering method using a metal oxide target having an atomic ratio of In:Ga:Zn = 4:2:4.1, at an oxygen flow ratio of 10% and a substrate temperature of room temperature. After the formation of the IGZO film, heat treatment was performed at 350°C for 1 hour in a nitrogen atmosphere, and then heat treatment was performed at 350°C for 1 hour in a mixed atmosphere of oxygen and nitrogen.

[0494] In Comparative Sample F and Comparative Sample G, an IGZO film of approximately 40 nm in thickness was formed by a sputtering method using a metal oxide target having an atomic ratio of In:Ga:Zn = 4:2:4.1, at an oxygen flow ratio of 30% and a substrate temperature of 200°C. After the formation of the IGZO film, heat treatment was performed at 400°C for 1 hour in a nitrogen atmosphere, and then heat treatment was performed at 400°C for 1 hour in a mixed atmosphere of oxygen and nitrogen.

[0495] Next, as the gate insulating layer 110, a silicon oxynitride film (SiOxNy) of approximately 150 nm in thickness was formed over the insulating layer 103 and the semiconductor layer 108 by a plasma CVD method in an atmosphere containing oxygen. FIG. 5C ) In this case, in Comparative Sample F and Comparative Sample G, heat treatment was performed at 400°C for 1 hour in a nitrogen atmosphere.

[0496] Next, as the metal oxide layer 114f, an aluminum oxide film (AlOx) was formed over the gate insulating layer 110 by a sputtering method in an atmosphere containing oxygen. FIG. 5C ) In Sample D and Sample E, an aluminum oxide film of approximately 10 nm in thickness was formed, and in Comparative Sample F and Comparative Sample G, an aluminum oxide film of approximately 5 nm in thickness was formed. After the formation of the aluminum oxide film, heat treatment was performed at 350°C for 1 hour in a mixed atmosphere of oxygen and nitrogen.

[0497] Next, as the conductive film 112f, a molybdenum film (Mo) was formed over the metal oxide layer 114f by a sputtering method FIG. 5D ), which was processed to form a gate electrode 112 FIG. 5E ). In Sample D and Sample E, a molybdenum film of approximately 300 nm in thickness was formed, and in Comparative Sample F and Comparative Sample G, a molybdenum film of approximately 200 nm in thickness was formed.

[0498] Next, Sample D and Sample E, to which one embodiment of the present application is applied, were supplied with boron (B) or phosphorus (P) FIG. 9A ) In this step, the gate electrode 112 was used as a mask to supply the semiconductor layer 108, the gate insulating layer 110, and the metal oxide layer 114f with boron or phosphorus. Sample D was supplied with boron, and Sample E was supplied with phosphorus.

[0499] On the other hand, in Comparative Sample F and Comparative Sample G, the metal oxide layer 114f was processed by wet etching to form the metal oxide layer 114. Then, boron or phosphorus was supplied using an ion implantation device. In this process, the gate electrode 112 was used as a mask to supply boron or phosphorus to the semiconductor layer 108 and the gate insulating layer 110. Boron was supplied to Comparative Sample F, and phosphorus was supplied to Comparative Sample G.

[0500] The beam energy was 30 keV when boron was supplied, and the beam energy was 80 keV when phosphorus was supplied. The dose of boron or phosphorus was 3 x 1014 / cm2in the samples other than Comparative Sample F. 15 / cm 2 The dose of boron or phosphorus was 1 x 1014 / cm2in Comparative Sample F. 16 / cm 2 .

[0501] The subsequent processes are processes common to the samples and the comparative samples. As the insulating layer 118, a silicon oxynitride film (SiON) having a thickness of about 300 nm was formed by a plasma CVD method on the gate insulating layer 110, the metal oxide layer 114f (or the metal oxide layer 114), and the gate electrode 112. FIG. 9B

[0502] Next, openings were partially formed in the metal oxide layer 114f, the gate insulating layer 110, and the insulating layer 118. Then, a molybdenum film having a thickness of about 100 nm was formed by a sputtering method and processed to form the conductive layer 120a and the conductive layer 120b. FIG. 9C

[0503] Subsequently, as a planarization film (not shown), an acrylic resin film having a thickness of about 1.5 μm was formed, and heat treatment was performed at 250°C for 1 hour in a nitrogen atmosphere.

[0504] Each sample was manufactured by the above-described steps.

[0505] Next, in each sample, the Id-Vg characteristics of the transistor were measured. FIG. 26 shows the results of the Id-Vg characteristics of the transistor of each sample.

[0506] As the measurement conditions of the Id-Vg characteristics of the transistor, the voltage applied to the gate electrode 112 (gate voltage (Vg)) and the voltage applied to the conductive layer 106 (back gate voltage (Vbg)) were changed from -15 V to +20 V at intervals of 0.25 V. In addition, the voltage applied to the source electrode (source voltage (Vs)) was 0 V (comm), and the voltage applied to the drain electrode (drain voltage (Vd)) was 0.1 V and 10 V in Sample D and Sample E, respectively, and was 0.1 V and 5.1 V in Comparative Sample F and Comparative Sample G, respectively.

[0507] As​​FIG. 26A to FIG. 26D As shown, all four samples manufactured in this embodiment exhibited good Id-Vg characteristics.

[0508] This confirms that even if boron or phosphorus is supplied through the metal oxide layer 114f without processing it, and the transistor includes the metal oxide layer 114f, it does not significantly affect the Id-Vg characteristics of the transistor.

[0509] Next, stress tests were performed on transistors in samples D and E.

[0510] The stress test conditions were the same as in Example 1.

[0511] FIG. 27 The results of PBTS, NBTS, PBTIS, and NBTIS for samples D and E are shown.

[0512] like FIG. 27 As shown, samples D and E all achieved good results in PBTS, NBTS, PBTIS and NBTIS, with the threshold fluctuation (ΔVth) being less than ±1V.

[0513] This confirms that even if boron or phosphorus is supplied through the metal oxide layer 114f without processing it, and the transistor includes the metal oxide layer 114f, it does not significantly affect the stress test results of the transistor.

[0514] also, FIG. 28 A cross-sectional photograph of a sample in which one aspect of the present invention is applied is shown. For example... FIG. 28 As shown, a metal oxide layer 114f is formed on the gate insulating layer 110. The process of using the gate electrode 112 as a mask to process the metal oxide layer 114f is not performed on the sample applying one aspect of the present invention. This confirms that the metal oxide layer 114f includes a region contacting the gate electrode 112 and a region contacting the insulating layer 118.

[0515] [Example 3]

[0516] In this embodiment, the aluminum oxide film forming the metal oxide layer 114 of a transistor that can be used in one aspect of the present invention is described and the results of its evaluation are presented.

[0517] [Etching of aluminum oxide film]

[0518] This embodiment illustrates the results of forming an alumina film and wet etching it.

[0519] First, an aluminum oxide (Al₂O₃) layer with a thickness of approximately 50 nm is formed on a glass substrate by sputtering in an oxygen-containing atmosphere. x )membrane.

[0520] FIG. 29A The results of structural analysis using an XRD apparatus are shown. FIG. 29A As indicated by the arrow, a peak value originating from Al2O3 crystallization was observed. Furthermore, the film density of the alumina film was 3.98 g / cm³ when measured by X-ray reflectionometry (XRR). 3 .

[0521] Next, the alumina film was wet-etched. Wet etching was performed using diluted hydrofluoric acid (DHF).

[0522] FIG. 30 The upper section shows cross-sectional photographs of samples that have not undergone wet etching (no etching) and samples that have undergone the process (etching).

[0523] like FIG. 30 As shown in the upper paragraph, wet etching did not progress in the alumina film. This is believed to be due to the high crystallinity of the alumina film. Furthermore, in FIG. 30 In each of the photographs, a protective (Coat) layer is formed on the alumina film.

[0524] Next, an alumina film with a thickness of approximately 50 nm was formed on the glass substrate by sputtering in an oxygen-containing atmosphere. Argon (Ar) was then supplied to the alumina film using a plasma ion doping device. The accelerating voltage was 30 kV, and the dose was 1 × 10⁻⁶. 16 ions / cm 2 .

[0525] FIG. 29B The results of structural analysis using an XRD apparatus are shown. FIG. 29B As indicated by the arrow, nothing was observed. FIG. 29A The peak value observed was derived from Al₂O₃ crystallization. Furthermore, when the film density was determined by XRR, the film density of the argon-supplied alumina film was 2.45 g / cm³. 3 Therefore, it can be concluded that by supplying argon, the crystallization of Al2O3 can be disrupted, thereby reducing the film density of the alumina film.

[0526] Next, the alumina film supplied with argon is wet-etched. Wet etching is performed using diluted hydrofluoric acid.

[0527] FIG. 30 The lower section shows cross-sectional photographs of a sample supplied with argon but not wet-etched (without etching) and a sample supplied with argon and treated (etched).

[0528] like FIG. 30As shown in the lower section, wet etching proceeds in an alumina film supplied with argon, causing the alumina film on the glass to be removed. Therefore, it can be seen that wet etching of the alumina film can be achieved by reducing its crystallinity through the supply of argon.

[0529] [Etching of alumina film in a laminated structure]

[0530] Next, the result obtained by forming a stacked structure equivalent to a gate insulating layer 110, a metal oxide layer 114f (alumina film), and a gate electrode 112 on a glass substrate and then wet etching the alumina film will be described. Two samples were fabricated here.

[0531] First, a silicon oxynitride (SiON) film (equivalent to gate insulating layer 110) is formed on a glass substrate. Then, an aluminum oxide (AlO) layer with a thickness of approximately 50 nm is formed on the SiON film by sputtering in an oxygen-containing atmosphere. x ) film (equivalent to metal oxide layer 114f).

[0532] Next, in AlO x A molybdenum (Mo) film (equivalent to gate electrode 112) is formed on the film.

[0533] In one of the two samples, a Mo film was used as a mask against AlO. x The membrane supplies argon (Ar). In another case, AlO is not supplied. x Argon is supplied through the membrane.

[0534] Next, the Mo film was used as a mask for AlO. x The film was wet etched. Wet etching was performed using diluted hydrofluoric acid (DHF). The processing time was 30 seconds for samples with argon supply and 60 seconds for samples without argon supply.

[0535] FIG. 31 The upper section is a cross-sectional photograph of a sample without argon supply, and the lower section is a cross-sectional photograph of a sample without argon supply. FIG. 31 The sample on the left is the one that has not undergone wet etching (no etching process), and the sample on the right is the one that has undergone the etching process.

[0536] like FIG. 31 As shown in the upper paragraph, AlO is not supplied with argon. x AlO was confirmed in the membrane. x Both the portions overlapping with and not overlapping with the Mo film remain in the film. That is, it can be seen that wet etching did not progress. On the other hand, as... FIG. 31 As shown in the lower section, AlO is supplied with argon. x AlO was confirmed in the membrane. x The portions of the membrane that do not overlap with the Mo membrane are removed, leaving only AlO.x The portion of the film that overlaps with the Mo film remains. That is, it is known that in the AlO x In the portion of the film that is supplied with argon (the portion that does not overlap with the Mo film), wet etching progresses so that the AlO x film is removed. Furthermore, it is also known that the AlO x In the portion of the film that is not supplied with argon (the portion that overlaps with the Mo film), wet etching does not progress.

[0537] Thus, it is known that by using the Mo film as a mask, the etching rate of the portion of the AlO x film that is supplied with argon can be made to differ between the portion supplied with argon (the portion that does not overlap with the Mo film) and the portion not supplied with argon (the portion that overlaps with the Mo film). Furthermore, it is also known that in the AlO x film that is supplied with argon (the portion that does not overlap with the Mo film), wet etching progresses so that the AlO x film is removed.

[0538] [Explanation of Symbols]

[0539] 100: transistor, 100A: transistor, 102: substrate, 103: insulating layer, 103d: region, 106: conductive layer, 106c: conductive layer, 108: semiconductor layer, 108c: semiconductor layer, 108n: low-resistance region, 110: gate insulating layer, 110d: region, 112: gate electrode, 112f: conductive film, 114: metal oxide layer, 114f: metal oxide layer, 114g: metal oxide layer, 118: insulating layer, 120a: conductive layer, 120b: conductive layer, 130A: capacitor, 130B: capacitor, 140: impurity element, 141a: opening portion, 141b: opening portion, 142: opening portion, 143: impurity element, 400: pixel circuit, 400EL: pixel circuit, 400LC: pixel circuit, 401: circuit, 401EL: circuit, 401LC: circuit, 501: pixel circuit, 502: pixel portion, 504: driver circuit portion, 504a: gate driver, 504b: source driver, 506: protection circuit, 507: terminal portion, 550: transistor, 552: transistor, 554: transistor, 560: capacitor, 562: capacitor, 570: liquid crystal element, 572: light-emitting element, 700: display device, 700A: display device, 700B: display device, 701: first substrate, 702: pixel portion, 704: source driver, 705: second substrate, 706: gate driver, 708: FPC terminal portion, 710: signal line, 711: wiring portion, 712: sealing agent, 716: FPC, 717: IC, 721: source driver IC, 722: gate driver, 723: FPC, 724: printed circuit board, 730: insulating film, 732: sealing film, 734: insulating film, 736: colored film, 738: light-blocking film, 740: protective layer, 741: protective layer, 742: adhesive layer, 743: resin layer, 744: insulating layer, 745: support substrate, 746: resin layer, 750: transistor, 752: transistor, 760: wiring, 770: planarization insulating film, 772: conductive layer, 773: insulating layer, 774: conductive layer, 775: liquid crystal element, 776: liquid crystal layer, 778: spacer, 780: anisotropic conductive film, 782: light-emitting element, 786: EL layer, 788: conductive film, 790: capacitor, 6000: display module, 6001: upper cover, 6002: lower cover, 6005: FPC, 6006: display device, 6009: frame, 6010: printed circuit board, 6011: battery, 6015: light-emitting portion, 6016: light-receiving portion, 6017a: light-guiding portion, 6017b: light-guiding portion, 6018: light, 6500: electronic device, 6501: housing, 6502: display portion, 6503: power button, 6504: button, 6505: speaker, 6506: microphone,6507: camera, 6508: light source, 6510: protection member, 6511: display panel, 6512: optical member, 6513: touch sensor panel, 6515: FPC, 6516: IC, 6517: printed circuit board, 6518: battery, 7000: display unit, 7100: television device, 7101: frame, 7103: stand, 7111: remote control, 7200: notebook personal computer, 7211: frame, 7212: keyboard, 7213: pointing device, 7214: external connection port, 7300: digital sign, 7301: frame, 7303: speaker, 7311: information terminal device, 7400: digital sign, 7401: column, 7411: information terminal device, 8000: camera, 8001: frame, 8002: display unit, 8003: operation button, 8004: shutter button, 8006: lens, 8100: viewfinder, 8101: frame, 8102: display unit, 8103: button, 8200: head-mounted display, 8201: mounting portion, 8202: lens, 8203: main body, 8204: display unit, 8205: cable, 8206: battery, 8300: head-mounted display, 8301: frame, 8302: display unit, 8304: fixing tool, 8305: lens, 9000: frame, 9001: display unit, 9003: speaker, 9005: operation key, 9006: connection terminal, 9007: sensor, 9008: microphone, 9050: icon, 9051: information, 9052: information, 9053: information, 9054: information, 9055: hinge, 9101: portable information terminal, 9102: portable information terminal, 9200: portable information terminal, 9201: portable information terminal,

Claims

1. A method for manufacturing a semiconductor device, comprising the following steps: Forming an oxide semiconductor layer; A gate insulating layer is formed on the oxide semiconductor layer; A metal oxide layer is formed on the gate insulating layer; A gate electrode is formed on the metal oxide layer that overlaps with a portion of the oxide semiconductor layer; as well as The first element is supplied through the metal oxide layer and the gate insulating layer to the region of the oxide semiconductor layer that does not overlap with the gate electrode. Both the oxide semiconductor layer and the metal oxide layer contain indium, gallium, and zinc. The first element is phosphorus, boron, magnesium, aluminum, or silicon.

2. A method for manufacturing a semiconductor device, comprising the following steps: Forming an oxide semiconductor layer; A gate insulating layer is formed on the oxide semiconductor layer; A metal oxide layer is formed on the gate insulating layer; A gate electrode is formed on the metal oxide layer that overlaps with a portion of the oxide semiconductor layer; The first element is supplied through the metal oxide layer and the gate insulating layer to the region of the oxide semiconductor layer that does not overlap with the gate electrode; as well as After supplying the first element to the oxide semiconductor layer, the metal oxide layer is processed into an island shape. Both the oxide semiconductor layer and the metal oxide layer contain indium, gallium, and zinc. The first element is phosphorus, boron, magnesium, aluminum, or silicon.

3. A method for manufacturing a semiconductor device, comprising the following steps: Forming a semiconductor layer; A gate insulating layer is formed on the semiconductor layer; A metal oxide layer is formed on the gate insulating layer; A gate electrode is formed on the metal oxide layer that overlaps with a portion of the semiconductor layer; The first element is supplied to the region of the semiconductor layer that does not overlap with the gate electrode through the metal oxide layer and the gate insulating layer; A second element is supplied to the region of the metal oxide layer that does not overlap with the gate electrode; as well as After supplying the second element to the metal oxide layer, the metal oxide layer is processed into an island shape. Wherein, the first element is phosphorus, boron, magnesium, aluminum, or silicon. Furthermore, the second element is silicon, phosphorus, argon, krypton, xenon, arsenic, gallium, or germanium.

4. The method for manufacturing a semiconductor device according to claim 3, The second element is supplied to the metal oxide layer after the first element is supplied to the semiconductor layer.

5. The method for manufacturing a semiconductor device according to claim 3, The first element is supplied to the semiconductor layer after the second element is supplied to the metal oxide layer.

6. The method for manufacturing a semiconductor device according to any one of claims 2 to 5, The metal oxide layer is processed into island-like structures through wet etching.

7. A method for manufacturing a semiconductor device according to any one of claims 1 to 5, The metal oxide layer mentioned above includes an aluminum oxide film.

8. The method for manufacturing a semiconductor device according to claim 1 or 2, A first heat treatment is performed after the metal oxide layer is formed and before the gate electrode is formed. A second heat treatment is performed after the first element is supplied to the oxide semiconductor layer. The second heat treatment is performed at a temperature lower than that of the first heat treatment.

Images