Substrate and substrate processing method

Abstract

This invention provides a substrate and a substrate processing method. The substrate includes: an etchable film to be etched; and a first film. The first film is formed on the etchable film and is made of a material with a lower etch rate than the etchable film. In the first film, a plurality of first openings are formed at first intervals in one direction on its surface. In the first film, outside the plurality of first openings in one direction, second openings with a width wider than the first openings and at a second interval equal to the distance from the outermost first opening and the first interval are formed, are shallower than the first openings. This invention can suppress differences in the shape of the openings formed in the etchable film.

Description

Technical Field

[0001] The following invention relates to substrates and substrate processing methods. Background Technology

[0002] Patent document 1 discloses a technique for etching openings such as holes and grooves with high aspect ratios.

[0003] Existing technical documents

[0004] Patent documents

[0005] Patent Document 1: Japanese Patent Application Publication No. 2016-122774 Summary of the Invention

[0006] The technical problem that the invention aims to solve

[0007] The present invention provides a technique for suppressing differences in the shape of the openings formed in the etched film.

[0008] Technical means for solving technical problems

[0009] According to one aspect of the present invention, a substrate includes: an etchable film to be etched; and a first film. The first film is formed on the etchable film and is made of a material with a lower etch rate than the etchable film. In the first film, a plurality of first openings are formed at first intervals in one direction on its surface. In the first film, outside the plurality of first openings in one direction, second openings are formed with a width wider than the first openings and at a second interval equal to the first interval from the outermost first opening. These second openings are shallower than the first openings.

[0010] Invention Effects

[0011] According to the present invention, it is possible to suppress differences in the shape of the openings formed in the etched film. Attached Figure Description

[0012] Figure 1 This is a cross-sectional view that schematically illustrates an example of the structure of the substrate in an embodiment.

[0013] Figure 2 This is a plan view that schematically illustrates an example of the structure of the substrate in an embodiment.

[0014] Figure 3 This is a diagram illustrating an example of the changes caused by etching of the substrate in an embodiment.

[0015] Figure 4 This is a diagram illustrating an example of the flow of a substrate processing method according to an implementation method.

[0016] Figure 5AThis is a diagram illustrating an example of the flow of wafer changes in each step of a substrate processing method based on an implementation method.

[0017] Figure 5B This is a diagram illustrating an example of the flow of wafer changes in each step of a substrate processing method based on an implementation method.

[0018] Figure 6 This is a longitudinal cross-sectional view showing an example of a substrate processing apparatus according to an embodiment.

[0019] Figure 7 This is a cross-sectional view that schematically represents an example of the structure of an existing substrate.

[0020] Figure 8 This is a diagram showing the result of etching the laminated film on an existing substrate.

[0021] Figure 9 This is a diagram showing the angle of incidence of ions relative to the target membrane.

[0022] Figure 10 This is a graph illustrating an example of the relationship between the incident angle of ions and the etching amount of the target film.

[0023] Figure 11 This is a diagram illustrating an example of changes in ACL caused by plasma etching.

[0024] Explanation of reference numerals in the attached figures

[0025] 10. Substrate processing device

[0026] 50 Control Department

[0027] 60-layer film

[0028] 61 ACL

[0029] 62 SiON membrane

[0030] 70 Opening

[0031] 71 Opening

[0032] 80 partition wall

[0033] 81. Spacer

[0034] d1 interval

[0035] d2 interval

[0036] W chip. Detailed Implementation

[0037] Hereinafter, with reference to the accompanying drawings, embodiments of the substrate and substrate processing method disclosed in this invention will be described in detail. Furthermore, the substrate and substrate processing method disclosed in this invention are not limited to these embodiments.

[0038] In substrate processing, sometimes holes, trenches, and other openings are densely formed on the film to be etched on the substrate. For example, in the manufacture of three-dimensional stacked semiconductor memories such as 3D-NAND flash memory, there is a process in which holes with high aspect ratios are densely formed on a stacked film on which a large number of insulating films are stacked. In this process, for example, firstly, a mask film is formed on the film to be etched on the substrate. On the mask film, openings are formed at positions corresponding to the locations where openings are to be formed on the film to be etched. Then, the mask film is used as a mask to etch the film to be etched. As a result of the etching, multiple openings are formed on the film to be etched at positions corresponding to the positions of the openings on the mask film. However, sometimes differences arise between the shapes of the openings formed on the film to be etched. For example, the openings are shallower in the peripheral portion compared to the central portion of the area where multiple openings are formed.

[0039] Therefore, it is desirable to develop a technique that can suppress the differences in the shape of the openings formed in the etched film.

[0040] [Primary Technology]

[0041] First, let's illustrate an example of the structure of an existing substrate. Figure 7 This is a cross-sectional view that schematically represents an example of the structure of an existing substrate. The substrate is a silicon wafer (hereinafter referred to as "wafer").

[0042] Figure 7 An example of the layer structure of a wafer W in the fabrication of a three-dimensional stacked semiconductor memory is shown. Wafer W has a stacked film 60. The stacked film 60 is a film formed by alternating layers of two insulating films with different dielectric constants. For example, the stacked film 60 is a structure formed by alternating layers of silicon oxide film 60a (SiO) and silicon nitride film 60b (SiN). In wafer W, an amorphous carbon layer (ACL) 61 of organic material is formed on the stacked film 60. In ACL 61, openings 70 are formed at positions corresponding to where openings are to be formed in the stacked film 60. Furthermore, the ACL 61 with the openings 70 forms spacers 80 between the multiple openings 70, and spacers 82 between regions with multiple openings 70 and other regions with multiple openings 70. Moreover, the width of spacers 82 is much larger than the width of spacers 80.

[0043] In the process of manufacturing a three-dimensional stacked semiconductor memory, ACL61 is used as a mask to etch the stacked film 60. For example, while supplying a mixture of fluorocarbon gases such as C4F8 and rare gases such as Ar, a high-frequency electrical power of a predetermined frequency is applied to generate plasma to perform plasma etching on the stacked film 60. Figure 8 This diagram shows the result of etching the laminated film 60 on the existing substrate. An opening 70 extends through the laminated film 60, allowing etching of the bottom laminated film 60. Therefore, an opening 70 is also formed on the laminated film 60. However, the shape of the openings 70 differs between the central and peripheral portions of the region where multiple openings 70 are formed. For example, the openings 70 are shallower in the peripheral portions compared to the central portions. Furthermore, ACL61 is etched from the upper surface side by plasma etching, but the central portion of the region where multiple openings 70 are formed is etched more extensively. As a result, the height of the spacer wall 80 is lower than the height of the spacer wall 82.

[0044] The inventor believes that the difference in shape between the central portion and the peripheral portion of the opening 70 is due to the following reasons.

[0045] In plasma etching, free radicals and ions generated in the plasma are incident on the target film, thereby etching the target film. Plasma etching is angle-dependent on the etching amount. Figure 9 This is a diagram showing the incident angle of ions relative to the target film at 90°. Figure 9 The image shows the incident angle θ of the ions in the direction perpendicular to the target film 90. Figure 10 This is a graph illustrating an example of the relationship between the incident angle of ions and the etching amount of the target film at 90°. Figure 10 The example illustrates the relationship between the incident angle θ and the etching amount when a Si3N4 film is used as the target film at 90°. The etching amount in the graph is represented by a value normalized to 1 when the etching amount at an incident angle θ = 0°. In plasma etching, the etching amount increases from an incident angle θ to 60°, and decreases sharply beyond 60°.

[0046] Regarding ACL61, since free radicals and ions are incident from various angles onto the corner portion of the upper end of the opening 70 that forms the upper surface, the etching amount at the corner portion is greater than that at the flat portion of the upper surface, making it easier to change from a rectangular shape to a circular or conical shape. Moreover, when it becomes a circular or conical shape, the incident angle θ of the ions from the plasma becomes from vertical (0°) to inclined (~60°), resulting in even greater etching. Figure 11 This is a diagram schematically illustrating an example of changes in ACL61 caused by plasma etching. Figure 11In the diagram, the changes in the upper surface of ACL61 over time due to plasma etching are represented as L1 to L5. L1 represents the state before etching, and L5 represents the state at the end of etching. Regarding ACL61, due to the formation of multiple openings 70, and the rapid etching near the corners of the openings 70 on the upper surface, a conical shape is formed. The spacer walls 80 between the openings 70 are etched from both sides, thus, during the middle of the plasma etching process (in... Figure 11 After L3, the flat portion of the upper surface of spacer 80 disappears, accelerating the etching of spacer 80. In contrast, the flat portion of the upper surface of spacer 82 is maintained even midway through etching, thus the etching of spacer 82 is not accelerated. Therefore, from the midway point of plasma etching (at... Figure 11 From L3 onwards until the end of etching, the height of spacer wall 82 becomes higher than the height of spacer wall 80. Furthermore, in the region where multiple openings 70 are formed, the height of ACL61 differs at the left and right positions of the openings 70 in the peripheral portion. This results in varying degrees to which free radicals and ions can easily penetrate the openings 70. Consequently, compared to the central portion of the region with multiple openings 70, fewer free radicals and ions reach the bottom of the openings 70 in the peripheral portion, leading to a lower etching rate. As a result, the openings 70 are formed shallower in the peripheral portion compared to the central portion.

[0047] [Implementation Method]

[0048] [Substrate Structure]

[0049] Therefore, in this embodiment, the substrate is configured as described below. Figure 1 This is a cross-sectional view that schematically illustrates an example of the structure of the substrate in an embodiment. Figure 2 This is a plan view illustrating an example of the structure of a substrate according to an embodiment. Here, the wafer W is used as the substrate.

[0050] Figure 1 This is an example of the layer structure of a wafer W in the fabrication of a three-dimensional stacked semiconductor memory. A stacked film 60 is formed on the wafer W, and an ACL 61 is formed on the stacked film 60. The stacked film 60 is an example of an etched film. ACL 61 is an example of a first film. The stacked film 60 is a film formed by alternately stacking multiple layers of two insulating films with different dielectric constants. For example, the stacked film 60 is a structure formed by alternately stacking multiple layers of silicon oxide film 60a (such as SiO) and silicon nitride film 60b (such as SiN).

[0051] Regarding ACL61, an opening 70 is formed at a position corresponding to the location where an opening is to be formed in the laminated film 60. Furthermore, regarding ACL61, an opening 71 is formed on the outer side of the plurality of openings 70.

[0052] Here is an example of the configuration of openings 70 and 71 on the chip W. Figure 2 This illustrates an example of the configuration of openings 70 and 71 in an embodiment. Figure 2 This is a diagram showing the configuration of openings 70 and 71 formed in the ACL61, viewed from above on the wafer W. Furthermore, in the aforementioned... Figure 1 In, with Figure 2 The representation is simplified compared to reducing the number of openings 70.

[0053] On the surface of ACL61, a plurality of openings 70 are arranged at intervals d1 in the orthogonal X and Y directions. Each opening 70 is a circular hole with a width (diameter) of h1. Furthermore, openings 71 are formed on the outer side of the plurality of openings 70 on the surface of ACL61. Figure 2 In this configuration, an opening 71 is arranged on the outer side of the plurality of openings 70 in the X direction, spaced d2 apart from the outermost opening 70a. The opening 71 is a rectangular trench with a width h2 in the X direction wider than the width h1 of the opening 70a, and is longer in the Y direction on the outer side of the opening 70a. Furthermore, the opening 71 can be a circular or elliptical hole. The spacing d2 between the openings 70a and 71 can be the same as the spacing d1, for example, it can be in the range of 0.5 to 2 times the spacing d1. For example, in the case of a three-dimensional stacked semiconductor memory, the width h1 of the opening 70 is 50 to 200 nm. The spacing d1 of the openings 70 is 30 to 200 nm. The spacing d2 between the openings 70a and 71 is 30 to 300 nm. The width h2 of the opening 71 is 100 to 400 nm. Furthermore, in... Figure 2 The diagram shows a case where an opening 71 is formed on the outer side of the plurality of openings 70 in the X direction; however, the opening 71 can also be formed on the outer side of the plurality of openings 70 in the Y direction. Furthermore, in... Figure 2 Multiple openings 70 are configured in a grid (quadrilateral) shape, for example, multiple openings 70 can also be arranged in a triangular or honeycomb shape.

[0054] like Figure 1 As shown, opening 71 is formed to a shallower depth than opening 70. For example, opening 70 extends to the laminated film 60. Opening 71 is formed not to extend to the laminated film 60, and the thickness from the bottom surface to the position of the laminated film 60 is t1.

[0055] In the process of manufacturing a three-dimensional stacked semiconductor memory, as in this embodiment, for a wafer W with openings 70 and 71, the stacked film 60 is etched using ACL61 as a mask. For example, while supplying a mixed gas containing a fluorocarbon gas such as C4F8 gas and a rare gas such as Ar gas, a high-frequency electrical power of a predetermined frequency is applied to generate plasma, and plasma etching is performed on the stacked film 60.

[0056] Figure 3 This is a diagram illustrating an example of the changes caused by etching of the substrate in an embodiment. Figure 3 (A) represents the initial state of the wafer W before etching. Figure 3 (B) indicates the state of the wafer W during etching. Figure 3 (C) indicates the state of the wafer W after etching is complete. The opening 70 extends to the laminate 60, thus the bottom laminate 60 is etched due to etching. Therefore, the opening 70 is also formed in the laminate 60. Furthermore, an opening 71 is provided outside the opening 70 at a distance d2 equal to the distance d1, so that the spacer walls 80 between the openings 70 and the spacer walls 81 between the openings 70 and 71 are etched from both sides at the same rate, decreasing in depth accordingly. Thus, the etching of each opening 70 progresses equally in both the central and peripheral portions, suppressing differences in the shape of each opening 70.

[0057] On the other hand, since the opening 71 does not penetrate into the laminated film 60, the bottom ACL 61 is etched due to etching. The ACL 61 has a lower etching rate than the laminated film 60, and the etching progresses slowly. Therefore, regarding the opening 71, by making the thickness t1 up to the initial state of the laminated film 60 an appropriate thickness, even after etching is complete, the opening 71 can be prevented from reaching the laminated film 60. The opening 71 is formed at a depth that does not penetrate into the laminated film 60 at the end of the etching of the laminated film 60. That is, in this embodiment, during the etching of the laminated film 60, the opening 71 is formed at a depth where the laminated film 60 is not etched, at a location on the laminated film 60 where etching is not required. For example, regarding the opening 71, its thickness t1 up to the initial state of the laminated film 60 is formed to a depth greater than the amount of ACL 61 etched during the etching of the laminated film 60. Thus, it is possible to prevent the formation of the opening 71 in the laminated film 60 at the end of the etching of the laminated film 60.

[0058] Furthermore, ACL61 is also etched during the etching of the laminate 60. The etching rate of ACL61 is generally higher in wider areas, and higher on the upper surface of ACL61 compared to the bottom of the opening 71. For example, if the etching rate of the upper surface of ACL61 is set to X and the etching rate of the bottom of the opening 70 is set to Y, the etching rate is X > Y. Therefore, for example, if the opening 71 is too shallow, the etching of the upper surface of ACL61 catches up with the bottom surface of the opening 70 during etching, and the opening 70 disappears. Therefore, the depth of the opening 71 is formed such that the depth from the upper surface of ACL61 becomes a predetermined depth or greater at the end of the etching of the laminate 60. For example, if the etching processing time is set to T and the minimum required depth of the opening 71 at the end of the etching is set to α, the depth D of the opening 71 becomes deeper than the following formula (1). α can be the same as the interval d2 between the opening 70a and the opening 71.

[0059] D=(X-Y)×T+α (1)

[0060] Thus, the depth of the opening 71 is formed such that it does not penetrate into the stacked film 60 at the end of etching, and the depth from the upper surface of ACL 61 is a depth within a predetermined range. Therefore, since the opening 71 does not reach the stacked film 60 at the end of etching, the formation of the opening 71 in the stacked film 60 can be prevented. Furthermore, since the opening 71 remains in ACL 61 at the end of etching, differences in the shape of the openings 70 can be suppressed.

[0061] [Substrate manufacturing method]

[0062] Hereinafter, an example of the process for manufacturing a substrate processing method for a wafer W having such a structure as in this embodiment will be described. Figure 4 This is a diagram illustrating an example of the flow of a substrate processing method according to an implementation method. Figure 5A , Figure 5B This is a diagram illustrating an example of the flow of wafer W changes in each step of the substrate processing method based on the implementation method.

[0063] First, prepare as follows Figure 5AThe wafer W shown in (A) has a laminated film 60 formed on it, and an ACL 61 formed on the laminated film 60. Furthermore, a SiON film 62 is formed on the ACL 61 in the wafer W, and an anti-reflective film 63 using organic materials, such as BARC (Bottom Anti-Reflective Coating), is formed on the SiON film 62. The SiON film 62 is an example of a second film. Additionally, a photoresist film 64 is formed on the anti-reflective film 63 in the wafer W. On the photoresist film 64, by photolithography, an opening 70b is formed on the laminated film 60 and the ACL 61 at the location where an opening 70 is to be formed, and an opening 71b is formed on the ACL 61 at the location where an opening 71 is to be formed. The width of the opening 71 in the ACL 61 is made wider than the width of the opening 70, and the opening 71b is wider than the opening 70b.

[0064] Using the photoresist film 64 as a mask, the antireflective film 63 and the SiON film 62 are etched (step S10). For example, plasma etching of the antireflective film 63 and the SiON film 62 is performed by applying a high-frequency electrical power of a predetermined frequency while supplying CF4 gas to generate plasma. Then, the photoresist film 64 and the antireflective film 63 are removed. Thus, as... Figure 5A As shown in (B), in the SiON film 62, an opening 70 is formed at the position of opening 70b of the photoresist film 64, and an opening 71 is formed at the position of opening 71b. Furthermore, the photoresist film 64 and the antireflective film 63 are made of the same organic material as ACL61, and can also be removed in the etching of ACL61 in the next step, therefore, it can also be... Figure 5A As shown in (B), the photoresist film 64 and the antireflective film 63 are not removed.

[0065] Next, using the SiON film 62 as a mask, ACL61 is etched (step S11). Figure 5A (C)). For example, plasma is generated by supplying O2 gas while applying high-frequency electrical power at a predetermined frequency to etch ACL61. Openings 70 and 71 extend into ACL61, thus the bottom of ACL61 is etched due to etching. Therefore, openings 70 and 71 are also formed in ACL61.

[0066] Here, opening 71 is wider than opening 70, therefore the etching rate is higher and it is etched deeper than opening 70. With this etching process, opening 71 will be formed more deeply than opening 70.

[0067] Therefore, a protective film is formed at the bottom of the opening 71 of the ACL61 formed on the wafer W (step S12). Figure 5A(D) For example, a SiO2 film 65 as a protective film is formed on wafer W using chemical vapor deposition (CVD) with SiCl4 gas, TEOS (tetraethyl orthosilicate) gas, and O2 gas. In CVD, step coverage is generally degraded, and conformal film formation is not possible. Therefore, more film is formed in wider exposed areas, while film formation is difficult in narrower openings. Therefore, the SiO2 film 65 is formed thicker on the upper surface of the SiON film 62 and at the bottom of the opening 71, and thinner at the bottom of the opening 70. The SiO2 film 65 is then etched onto wafer W. At this time, isotropic etching or atomic layer etching (ALE) is desired to achieve good overall uniformity. For example, as an isotropic etching process, CF4 gas is supplied, and a high-frequency electrical power of a specified frequency is applied under high pressure to generate plasma, thereby etching a relatively thin SiO2 film 65 on ACL61. The SiO2 film 65 at the bottom of the opening 70 is removed. A SiO2 film 65 is formed on the upper surface of the SiON film 62 and at the bottom of the opening 71, which is thicker than the bottom of the opening 70. Therefore, if the etching is stopped when the SiO2 film 65 at the bottom of the opening 70 is removed, a SiO2 film 65 remains on the upper surface of the SiON film 62 and at the bottom of the opening 71. Furthermore, by adjusting the CVD processing conditions to use conditions with poorer step coverage, although the SiO2 film 65 is formed relatively thickly on the upper surface of the SiON film 62 and at the bottom of the opening 71, if a film cannot be formed at the bottom of the opening 70, then it is unnecessary to perform etching of the SiO2 film 65 after film formation.

[0068] Next, using the SiON film 62 as a mask, ACL61 is etched (step S13). For example, plasma etching is performed on ACL61 by applying a high-frequency electrical power at a predetermined frequency while supplying O2 gas. The opening 70 deepens as etching progresses. On the other hand, since the opening 71 is the SiO2 film 65, etching is difficult to proceed. Thus, as... Figure 5B As shown in (A), opening 71 can be formed at a shallower depth compared to opening 70. Furthermore, it can be determined whether the depths of openings 71 and 70 meet the necessary conditions (step S14). If the necessary conditions are not met, steps S12 and S13 are repeated. For example, if the SiO2 film 65 at the bottom of opening 71 disappears due to etching, and the bottom of opening 71 is etched beyond the required degree, the process proceeds to step S12. After the SiO2 film 65 is re-formed at the bottom of opening 71, ACL61 is etched. This process is repeated as needed. Figure 5A (D) Figure 5B(A) allows for the individual adjustment of the depths of openings 70 and 71.

[0069] Next, as Figure 5B As shown in (B), the SiON film 62 is removed. On the ACL 61 of the wafer W, outside the plurality of openings 70, an opening 71 is formed with a depth shallower than the opening 70, at a distance d2 equal to the distance from the outermost opening 70 and the distance d1, and with a width wider than the opening 70. Furthermore, the SiON film 62 can also be removed by the next step, namely, etching of the laminated film 60.

[0070] For a wafer W with this structure, using ACL61 as a mask, the stacked film 60 is etched, thereby... Figure 5B As shown in (C) and (D), it is possible to form each opening 70 at the same depth in the laminated film 60.

[0071] [Device Structure]

[0072] The following describes a substrate processing apparatus 10 for etching a substrate having a structure according to an embodiment and for etching a substrate according to an embodiment. Figure 6 This is a longitudinal cross-sectional view showing an example of a substrate processing apparatus 10 according to an embodiment. The substrate processing apparatus 10 is a capacitively coupled plasma processing apparatus. The substrate processing apparatus 10 includes a chamber 1, an exhaust device 2, and a gate valve 3. The chamber 1 is formed of aluminum and is cylindrical in shape, with its surface treated with aluminum oxide (anodizing). The chamber 1 is electrically grounded. Inside the chamber 1, a processing space 5 is formed. The chamber 1 isolates the processing space 5 from the external atmosphere. An exhaust port 6 and an opening 7 are also formed in the chamber 1. The exhaust port 6 is formed on the bottom surface of the chamber 1. The opening 7 is formed on the side wall of the chamber 1. The exhaust device 2 is connected to the processing space 5 of the chamber 1 via the exhaust port 6. The exhaust device 2 discharges gas from the processing space 5 via the exhaust port 6. The gate valve 3 is capable of opening or closing the opening 7.

[0073] The substrate processing apparatus 10 also includes a mounting stage 8. The mounting stage 8 is disposed in the processing space 5, located at the bottom of the chamber 1. The mounting stage 8 includes a support stage 11 and an electrostatic chuck 12. The support stage 11 is formed of a conductor, exemplified by aluminum (Al), titanium (Ti), or silicon carbide (SiC). The support stage 11 is supported on the chamber 1. A refrigerant flow path 14 is formed inside the support stage 11. The electrostatic chuck 12 is disposed above the support stage 11 and supported on it. The electrostatic chuck 12 has an electrostatic chuck body 15 and a chuck electrode 16. The electrostatic chuck body 15 is formed of an insulator. The electrostatic chuck 12 is formed by embedding the chuck electrode 16 inside the electrostatic chuck body 15. The substrate processing apparatus 10 also includes a DC voltage source 17. The DC voltage source 17 is electrically connected to the chuck electrode 16 and supplies DC current to the chuck electrode 16.

[0074] The substrate processing apparatus 10 also includes a cooler 21, a refrigerant inlet pipe 22, and a refrigerant outlet pipe 23. The cooler 21 is connected to the refrigerant flow path 14 via the refrigerant inlet pipe 22 and the refrigerant outlet pipe 23. The cooler 21 cools a cooling medium, exemplified as cooling water or brine, and the cooled cooling medium circulates in the refrigerant flow path 14 via the refrigerant inlet pipe 22 and the refrigerant outlet pipe 23 to cool the electrostatic chuck 12 of the mounting stage 8.

[0075] The substrate processing apparatus 10 also includes a thermally conductive gas supply source 25 and a thermally conductive gas supply passage 26. The thermally conductive gas supply passage 26 is formed such that one end is formed on the upper surface of the electrostatic chuck 12. The thermally conductive gas supply source 25 supplies a thermally conductive gas, for example, helium (He) or argon (Ar), to the thermally conductive gas supply passage 26, supplying thermally conductive gas between the wafer 27 placed on the mounting stage 8 and the electrostatic chuck 12.

[0076] The substrate processing apparatus 10 also includes a gas spray head 31 and a shielding ring 32. The gas spray head 31 is formed of a conductor and is in the shape of a circular plate. The gas spray head 31 is opposite to the mounting stage 8 and is configured such that the plane along the lower surface of the gas spray head 31 is parallel to the plane along the upper surface of the mounting stage 8. The gas spray head 31 is also configured to close an opening formed at the top of the chamber 1. The shielding ring 32 is formed of an insulator and is in the shape of a ring. The shielding ring 32 covers the periphery of the gas spray head 31. The gas spray head 31 is supported in the chamber 1 via the shielding ring 32 in a manner that insulates the gas spray head 31 from the chamber 1. The gas spray head 31 is electrically grounded. Alternatively, the gas spray head 31 can be connected to a variable DC power supply, allowing a specified DC voltage to be applied.

[0077] The gas spray head 31 includes a gas diffusion chamber 33, a gas inlet 35, and multiple gas supply holes 36. The gas diffusion chamber 33 is formed inside the gas spray head 31. The gas inlet 35 is formed on the upper side of the gas diffusion chamber 33 and communicates with it. The multiple gas supply holes 36 are formed on the lower side of the gas diffusion chamber 33, with their upper ends communicating with the gas diffusion chamber 33 and their lower ends communicating with the processing space 5.

[0078] The substrate processing apparatus 10 also includes a processing gas supply source 37. The processing gas supply source 37 is connected to a gas inlet 35. The processing gas supply source 37 supplies various processing gases to the gas inlet 35. For example, the processing gas supply source 37 supplies various gases used for etching the antireflective film 63 and the SiON film 62, etching the ACL 61, and etching the laminated film 60. Furthermore, the processing gas supply source 37 supplies various gases used for film formation of the SiO2 film 65. In addition, multiple processing gas supply sources 37 may be provided. For example, one processing gas supply source 37 may be provided for each type of processing gas used in etching, film formation, and atomic layer etching.

[0079] The support platform 11 of the mounting stage 8 is used as the lower electrode, and the gas spray head 31 is used as the upper electrode. The substrate processing apparatus 10 also has an electrical power supply device 41. The electrical power supply device 41 includes a first high-frequency power supply 42, a first matching device 43, a second high-frequency power supply 44, and a second matching device 45. The first high-frequency power supply 42 is connected to the mounting stage 8 via the first matching device 43. The first high-frequency power supply 42 supplies a first high frequency (e.g., 40 MHz) to the support platform 11 of the mounting stage 8 at a specified electrical power. The first matching device 43 matches the internal (or output) impedance of the first high-frequency power supply 42 with the load impedance. The first matching device 43 enables the internal impedance of the first high-frequency power supply 42 to appear to match the load impedance when plasma is generated in the processing space 5.

[0080] The second high-frequency power supply 44 is connected to the stage 8 via the second matching unit 45. The second high-frequency power supply 44 supplies a second high frequency (e.g., 0.3 MHz) lower than the first frequency to the stage 8 at a specified power. The second matching unit 45 matches the internal (or output) impedance of the second high-frequency power supply 44 to the load impedance. The second matching unit 45 makes the internal impedance of the second high-frequency power supply 44 appear to match the load impedance when plasma is generated in the processing space 5. Furthermore, in this embodiment, the first and second high frequencies are applied to the stage 8, but they could also be applied to the gas spray head 31.

[0081] The substrate processing apparatus 10 also includes a control unit 50. The control unit 50 controls each component of the substrate processing apparatus 10. The control unit 50 is, for example, a computer, including a CPU (Central Processing Unit), RAM (Random Access Memory), ROM (Read Only Memory), and auxiliary storage devices. The CPU operates based on computer programs and processing conditions stored in the ROM or auxiliary storage devices, controlling the overall operation of the apparatus. Furthermore, the computer-readable program required for control can also be stored on a storage medium. The storage medium may be, for example, a floppy disk, CD (Compact Disc), CD-ROM, hard disk, flash memory, or DVD. Moreover, the control unit 50 can be located inside or outside the substrate processing apparatus 10. When the control unit 50 is located externally, it can control the substrate processing apparatus 10 via wired or wireless communication methods.

[0082] In each step of the substrate processing method of the embodiment, the control unit 50 operates according to a computer program (a program based on an input scheme) for controlling each part of the substrate processing apparatus 10, and sends out control signals. Each part of the substrate processing apparatus 10 is controlled by the control signals from the control unit 50. For example, the control unit 50 uses control signals in the substrate processing apparatus 10 to control the selection and flow rate of the gas supplied from the processing gas supply source 37, and the exhaust of the exhaust device 2. In addition, the control unit 50 controls the electrical power supply from the first high-frequency power supply 42 and the second high-frequency power supply 44, the voltage application from the DC voltage source 17, and the refrigerant flow rate and refrigerant temperature from the cooler 21. Each step of the substrate processing method disclosed in this specification is implemented by operating each part of the substrate processing apparatus 10 based on the control of the control unit 50. The storage unit of the control unit 50 stores in a readable manner the computer program for implementing the substrate processing method of the embodiment and various data for implementing the method.

[0083] [Effects of the Implementation Method]

[0084] The wafer W of the above embodiment has a laminated film 60 and an ACL 61, which are to be etched. The ACL 61 is formed on the laminated film 60 and is made of a material with a lower etch rate than the laminated film 60. The ACL 61 has a plurality of openings 70 (first openings) at intervals d1 (first intervals) in one direction on its surface. Outside the plurality of openings 70 in one direction, the ACL 61 has openings 71 (second openings) with a width wider than the openings 70, at an interval d2 (second interval) that is the same distance from the outermost opening 70a and the interval d1. Therefore, when the wafer W is etched on the laminated film 60 using the ACL 61 as a mask, it is possible to suppress differences in the shape of the openings 70 formed on the laminated film 60.

[0085] Furthermore, in the wafer W of this embodiment, the opening 70 extends through the laminated film 60, while the opening 71 does not extend through the laminated film 60. Therefore, in this embodiment, when the laminated film 60 is etched using ACL61 as a mask, the formation of the opening 71 in the laminated film 60 can be suppressed.

[0086] Furthermore, in the wafer W of this embodiment, openings 70 are formed in the portions of the laminated film 60 where openings are to be formed, and openings 71 are formed in the portions of the laminated film 60 where openings are not formed. In the wafer W of this embodiment, by forming openings 71 in the portions of the laminated film 60 where openings are not formed, differences in the shapes of the openings 70 formed in the laminated film 60 can be suppressed.

[0087] Furthermore, in the wafer W of this embodiment, the opening 71 is formed such that, at the end of the etching of the laminated film 60, which uses ACL61 as a mask, it does not penetrate into the laminated film 60, and its depth from the upper surface of ACL61 is a depth within a predetermined range. Thus, at the end of etching, an opening 71 can be formed in the wafer W that does not penetrate into the laminated film 60, and a spacer 81 is formed between it and the opening 70.

[0088] In addition, in the wafer W of this embodiment, an ACL 61 is formed on the laminated film 60 using a material with a lower etching rate than the laminated film 60, and a SiON film 62 is formed on the ACL 61. In the substrate processing method of this embodiment, a plurality of openings 70 are formed in one direction on the surface of the SiON film 62 of the wafer W at intervals d1. Furthermore, in the substrate processing method of this embodiment, an opening 71 wider than the opening 70 is formed on the outer side of the plurality of openings 70 in one direction at an interval d2 equal to the distance from the outermost opening 70a and the interval d1. In the substrate processing method of this embodiment, the SiON film 62 is used as a mask to etch the ACL 61, forming a plurality of openings 70 and openings 71 in the ACL 61. In the substrate processing method of this embodiment, a SiO2 film 65 is formed at the bottom of the openings 71 formed in the ACL 61. In the substrate processing method of this embodiment, the laminated film 60 is etched using the ACL 61, on which the SiO2 film 65 is formed at the bottom of the openings 71, as a mask. In the substrate processing method of this embodiment, a wafer W can be manufactured such that a plurality of openings 70 are formed at intervals d1 in one direction of ACL61, and openings 71 with a depth shallower than the openings 70 are formed at a distance d2 from the outermost opening 70a and with a width wider than the openings 70.

[0089] The embodiments have been described above; however, it should be considered that the embodiments disclosed in this invention are illustrative in all respects and not restrictive. In fact, the above-described embodiments can be implemented in various ways. Furthermore, the above-described embodiments can be omitted, substituted, or modified in various ways without departing from the scope and spirit of the claims.

[0090] For example, in the above embodiment, taking the fabrication of a three-dimensional stacked semiconductor memory as an example, the case where the film to be etched is the stacked film 60, the first film is the ACL 61, the second film is the SiON film 62, and the protective film is the SiO2 film 65 has been described. However, it is not limited to this. For example, it can also be applied to the wiring formation process (the so-called BEOL (Back End of Line)). The film to be etched can also be a SiCOH film or a low-k film. The first film can also be a spin-coated hard mask (SOH). The second film can also be an anti-reflective film such as a Si-ARC film. The protective film can also be a SiO2 film. Furthermore, it can also be applied to the HARC (High Aspect Ratio Contact) process. The film to be etched can also be a SiO2 film. The first film can also be a polycrystalline silicon (Poly-Si) film. The second film can also be a SiO2 film. The protective film can also be a SiO2 film. The SiO2 film as a protective film can be formed, for example, by CVD using SiCl4 gas or TEOS gas and O2 gas. Furthermore, it can also be applied to silicon processing steps. The etched film can also be polycrystalline silicon. The first film can also be an organic film. The second film can also be a SiO2 film. The protective film can also be an organic film. Organic films as protective films can, for example, be formed using CVD with CH4 gas.

[0091] Furthermore, the optimal values ​​for various dimensions (h1, d1, h2, d2) can be selected through the process. Moreover, it is foreseeable that even smaller values ​​can be selected as semiconductor devices become miniaturized. In any case, as in the above embodiment, as long as the relationship between the various dimensions in the mask (first film) is maintained, the differences in the shape of the openings formed in the etched film can be suppressed.

[0092] Furthermore, the above embodiments describe the use of a silicon wafer as the substrate. However, this is not a limitation. For example, the substrate can be any substrate such as a compound semiconductor, a glass substrate, or a ceramic substrate.

Claims

1. A substrate, characterized in that, include: The film being etched is the object being etched. and A first film formed on the etched film, the first film being made of a material with a lower etching rate than the etched film, has a plurality of first openings formed at first intervals in one direction on its surface. Outside the plurality of first openings in one direction, a second opening is formed with a width wider than the first opening and at a second interval equal to the first interval from the outermost first opening, and shallower in depth than the first opening. A second opening, wider than the first opening, is provided on the outside of the first opening, spaced apart by a second interval of the same degree as the first interval, such that the etching of the spacer wall between the first openings and the spacer wall between the first opening and the second opening progresses from both sides to the same degree.

2. The substrate as described in claim 1, characterized in that: The first opening extends through the etched film, while the second opening does not extend through the etched film.

3. The substrate as described in claim 1 or 2, characterized in that: The first opening is formed in the portion of the etched film where an opening is to be formed, and the second opening is formed in the portion of the etched film where no opening is to be formed.

4. The substrate as described in any one of claims 1 to 3, characterized in that: The second opening is formed such that, at the end of the etching of the etched film using the first film as a mask, it does not penetrate to the etched film, and its depth D from the upper surface of the first film is greater than that of the following formula (1). D=(X-Y)×T+α (1), Where X is the etching rate of the upper surface of the first film, Y is the etching rate of the bottom of the first opening, X > Y, T is the etching processing time, and α is the minimum depth of the second opening required to finish etching.

5. A substrate processing method, characterized in that, On the substrate, a first film is formed on the etchable film, which is the object to be etched. A first film is formed from a material with a lower etch rate compared to the etchable film. A second film is then formed on the first film. The substrate processing method includes: On the second film of the substrate, a plurality of first openings are formed at a first interval in one direction on the surface of the first film, and a second opening with a width wider than the first opening is formed at a second interval at the same distance from the outermost first opening and the first interval on the outside of the plurality of first openings in one direction. The process of etching the first film using the second film as a mask to form the plurality of first openings and the second openings on the first film; The process of forming a protective film at the bottom of the second opening formed in the first film; as well as The process of etching the film to be etched using the first film, on which the protective film is formed at the bottom of the second opening, as a mask. A second opening, wider than the first opening, is provided on the outside of the first opening, spaced apart by a second interval of the same degree as the first interval, such that the etching of the spacer wall between the first openings and the spacer wall between the first opening and the second opening progresses from both sides to the same degree.

6. The substrate processing method as described in claim 5, characterized in that: Repeat the following steps: The process of etching the first film until the depth of the first opening and the second opening meets the specified condition that the depth of the second opening is shallower than that of the first opening, in order to form the plurality of first openings and the second openings in the first film; as well as The process of forming the protective film.

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