Semiconductor wafer and method of dicing a semiconductor wafer

Abstract

A semiconductor wafer and a method of dicing a semiconductor wafer are provided. The method of dicing a semiconductor wafer includes providing a semiconductor substrate having a plurality of integrated circuit regions on an active surface of the semiconductor substrate, a dicing region provided between adjacent integrated circuit regions of the plurality of integrated circuit regions, and a metal shielding layer provided on the active surface across at least a portion of the adjacent integrated circuit regions and the dicing region; forming a modified layer by irradiating a laser inside the semiconductor substrate along the dicing region; causing a crack to propagate from the modified layer in a direction perpendicular to a long axis direction of the metal shielding layer by polishing a non-active surface of the semiconductor substrate opposite the active surface; and forming semiconductor chips by separating the adjacent integrated circuit regions based on the crack propagated from the modified layer, respectively.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to a semiconductor wafer and a method of cutting the same, and more particularly, to a method of cutting a semiconductor substrate by using a laser. BACKGROUND

[0002] In a chip manufacturing process, after integrated circuits are formed on an active surface of a semiconductor substrate, a passive surface of the semiconductor substrate is polished, and the polished semiconductor substrate is cut to divide the integrated circuits into individual semiconductor chips. Generally, the polished semiconductor substrate is mechanically cut using a sawing blade. When mechanical cutting is performed in this way, the cut surface of the semiconductor chip can be cracked, thereby causing many failures in the semiconductor chip. Therefore, a method of cutting a semiconductor substrate using a laser has been studied. SUMMARY

[0003] The present disclosure provides a semiconductor substrate and a method of cutting the semiconductor substrate, which suppresses the generation of failures in a process of cutting a semiconductor substrate into semiconductor chips by using a laser.

[0004] Aspects of the present disclosure are not limited to the foregoing, and other unmentioned aspects will be apparent to those of ordinary skill in the art in light of the following description.

[0005] According to an aspect of the present disclosure, there is provided a method of cutting a semiconductor wafer, the method including: providing a semiconductor substrate having a plurality of integrated circuit regions on an active surface of the semiconductor substrate, a cut region provided between adjacent integrated circuit regions of the plurality of integrated circuit regions, and a metal shielding layer provided on the active surface across at least a portion of the adjacent integrated circuit regions and the cut region; forming a modified layer by irradiating a laser into an inside of the semiconductor substrate along the cut region; causing a crack to propagate from the modified layer in a direction perpendicular to a long axis direction of the metal shielding layer by polishing a passive surface of the semiconductor substrate opposite the active surface; and forming semiconductor chips by separating the adjacent integrated circuit regions based on the crack propagated from the modified layer, respectively.

[0006] According to another aspect of the disclosure, there is provided a method of cutting a semiconductor wafer, the method including: providing a semiconductor substrate having a plurality of integrated circuit regions on an active surface of the semiconductor substrate, a cut region provided between adjacent integrated circuit regions among the plurality of integrated circuit regions, and a metal shielding layer formed on the active surface across at least a portion of the integrated circuit regions and the cut region; forming a modified layer by irradiating a laser inside the semiconductor substrate along the cut region; causing a crack to propagate from the modified layer in a direction perpendicular to a long axis direction of the metal shielding layer by polishing a non-active surface of the semiconductor substrate opposite the active surface; and forming semiconductor chips by separating the adjacent integrated circuit regions based on the crack propagated from the modified layer, respectively, wherein, in a cross-sectional view, the metal shielding layer includes a first metal shielding layer and a second metal shielding layer, a space region is between the first metal shielding layer and the second metal shielding layer and in a position where the crack propagates, in the cross-sectional view, each of the first metal shielding layer and the second metal shielding layer includes a long axis parallel to the active surface and a short axis perpendicular to the active surface, and a length of the long axis is about 50 µm to about 100 µm, and a length of the short axis is about 0.5 µm to about 1 µm.

[0007] According to an aspect of the disclosure, there is provided a semiconductor wafer including: a semiconductor substrate including a plurality of integrated circuit regions on an active surface; a cut region provided between adjacent integrated circuit regions among the plurality of integrated circuit regions; and a metal shielding layer provided on the active surface across a portion of the adjacent integrated circuit regions and the cut region, wherein, in a cross-sectional view, the metal shielding layer includes a long axis parallel to the active surface and a short axis perpendicular to the active surface, and, in a plan view, the metal shielding layer is arranged along a perimeter of a respective integrated circuit region among the adjacent integrated circuit regions.

[0008] According to an aspect of the disclosure, there is provided a semiconductor device including: a semiconductor substrate including an integrated circuit region and a cut region on an active surface of the semiconductor substrate, the cut region being provided adjacent to the integrated circuit region; a metal shielding layer provided on the active surface across the integrated circuit region and the cut region; a device layer including one or more semiconductor devices provided on the active surface of the semiconductor substrate; one or more wirings provided in a wiring layer formed on the device layer; and one or more vertical metal structures formed on the metal shielding layer, wherein, in a cross-sectional view, the metal shielding layer includes a long axis parallel to the active surface and a short axis perpendicular to the active surface, wherein, in the cross-sectional view, the one or more vertical metal structures are perpendicular to the long axis of the metal shielding layer. BRIEF DESCRIPTION OF DRAWINGS

[0009] Embodiments of the present disclosure will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0010] Figure 1 is a perspective view of a semiconductor substrate according to an example embodiment of the present disclosure;

[0011] Figure 2A is Figure 1 is an enlarged plan view of region A shown in

[0012] Figure 2B is a side sectional view corresponding to a surface taken by cutting the center of Figure 2A in the X direction;

[0013] Figure 2C is an enlarged plan view of region C shown in Figure 1

[0014] Figure 3 is a perspective view showing a state in which a protective sheet is attached to a semiconductor substrate according to an embodiment of the present disclosure;

[0015] Figure 4 is a side sectional view corresponding to line IV-IV' shown in Figure 3 in which attachment of the protective sheet to the semiconductor substrate is completed;

[0016] Figure 5A is a perspective view showing a state in which laser irradiation into a semiconductor substrate according to an embodiment of the present disclosure;

[0017] Figure 5B is a side sectional view showing a direction of travel of laser;

[0018] Figure 6 is a side sectional view showing a state in which irradiation of laser is completed according to an embodiment of the present disclosure;

[0019] Figure 7A is an enlarged plan view of region A shown in Figure 2A corresponding to Figure 6

[0020] is a side sectional view corresponding to a surface taken by cutting the center of Figure 7B in the X direction; Figure 7A

[0021] is a side sectional view showing a state in which a semiconductor substrate according to an embodiment of the present disclosure is polished; Figure 8

[0022] is an enlarged plan view of region C shown in Figure 9A corresponding to Figure 2A Figure 8 ​​is an enlarged plan view of the area A shown in

[0023] Figure 9B is a side sectional view of a surface taken through the center of the Figure 9A ;

[0024] Figure 10 is a side sectional view showing a state in which a semiconductor substrate according to an embodiment of the present disclosure is cut into semiconductor chips;

[0025] Figure 11A is an enlarged plan view of the area A shown in Figure 2A ; Figure 10 is an enlarged plan view of the area A shown in

[0026] Figure 11B is a side sectional view of a surface taken through the center of the Figure 11A ;

[0027] Figure 12A and Figure 12B shows a semiconductor substrate according to another embodiment of the present disclosure, in which Figure 12A is an enlarged side sectional view of the area A shown in Figure 1 ; and Figure 12B is an enlarged plan view of the area C shown in Figure 1 ;

[0028] Figure 13 shows a semiconductor substrate according to another embodiment of the present disclosure, in which Figure 13 is an enlarged side sectional view of the area A shown in Figure 1 ;

[0029] Figure 14 is a side sectional view showing a semiconductor package including semiconductor chips cut from a semiconductor substrate according to an embodiment of the present disclosure;

[0030] Figure 15A is an enlarged side sectional view of the portion D shown in Figure 14 according to an embodiment of the present disclosure;

[0031] Figure 15B is an enlarged side sectional view of the portion D shown in Figure 14 according to an embodiment of the present disclosure;

[0032] Figure 16 is a structural diagram of a system showing a semiconductor package including semiconductor chips cut from a semiconductor substrate according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0033] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0034] Figure 1 is a perspective view of a semiconductor substrate according to an exemplary embodiment of the present disclosure, Figure 2A is Figure 1 is an enlarged plan view of the region A shown in Figure 2B is a side sectional view corresponding to a surface taken by cutting Figure 2A at the center in the X direction, and Figure 2C is Figure 1 is an enlarged plan view of the region C shown in

[0035] Referring to Figure 1 , Figure 2A , Figure 2B and Figure 2C , the semiconductor substrate 100 includes an integrated circuit region 102 and a dicing region 104.

[0036] According to an exemplary embodiment, the semiconductor substrate 100 can include a wafer and can have a circular shape having a constant first thickness T1. The semiconductor substrate 100 can have a notch 100N serving as a reference point for wafer alignment.

[0037] The semiconductor substrate 100 can include, for example, silicon. Alternatively, the semiconductor substrate 100 can include a semiconductor element such as germanium or a compound semiconductor such as silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs), and indium phosphide (InP). The semiconductor substrate 100 can have a silicon-on-insulator (SOI) structure. In some embodiments of the present disclosure, the semiconductor substrate 100 can include a well or a structure doped with impurities, which is a conductive region. The semiconductor substrate 100 can have a variety of element isolation structures such as a shallow trench isolation (STI) structure.

[0038] Here, it is assumed that the semiconductor substrate 100 has a diameter of about 12 inches, and a case where a silicon wafer is used will be described. However, it will be understood by those of ordinary skill in the art that a semiconductor substrate 100 having a diameter greater than or less than the above diameter can be used, and a semiconductor substrate 100 formed of other materials can also be used. The semiconductor substrate 100 can have a first thickness T1 of about 0.1 mm to about 1 mm. When the first thickness T1 of the semiconductor substrate 100 is too small, the mechanical strength can not be satisfactory; when the first thickness T1 is too large, the time taken for subsequent polishing increases, thereby reducing the productivity of semiconductor chips.

[0039] The semiconductor substrate 100 can include an active surface 100F (which is a front surface) and an inactive surface 100B (which is a back surface). According to an exemplary embodiment, a plurality of integrated circuit regions 102 can be formed on the active surface 100F, and the plurality of integrated circuit regions 102 will be divided into semiconductor chips (10) of 10). Figure 10

[0040] According to an exemplary embodiment, a semiconductor device SD can be formed on the active surface 100F of the semiconductor substrate. According to an exemplary embodiment, the semiconductor substrate can be classified into a memory device and a logic device.

[0041] The memory device can include a volatile memory device or a non-volatile memory device. The volatile memory device can include existing volatile memory devices and currently developed volatile memory devices, for example, a dynamic random access memory (DRAM), a static RAM (SRAM), a thyristor RAM (TRAM), a zero capacitor RAM (ZRAM), or a dual transistor RAM (TTRAM). The non-volatile memory device can include existing non-volatile memory devices and currently developed non-volatile memory devices, for example, a flash memory, a magnetic RAM (MRAM), a spin transfer torque (STT)-MRAM, a ferroelectric RAM (FRAM), a phase change RAM (PRAM), a resistive RAM (RRAM), a nanotube RRAM, a polymer RAM, a nano floating gate memory, a holographic memory, a molecular electronic memory, or an insulator resistance change memory.

[0042] The logic device can be implemented with a microprocessor, a graphics processor, a signal processor, a network processor, an audio codec, a video codec, an application processor, a system on chip, etc., but is not limited thereto. The microprocessor can include, for example, a single core or a multi-core.

[0043] The integrated circuit regions 102 can be arranged to be isolated from each other by the dicing regions 104. The dicing regions 104 can be referred to as scribe lanes. The dicing regions 104 can extend in a cross shape in a first direction X and a second direction Y perpendicular to the first direction X. The dicing regions 104 can have a form of linear lanes having a constant width 104W.

[0044] That is, the integrated circuit regions 102 can be arranged to be separated from each other by being surrounded by the dicing regions 104 in the first direction X and the second direction Y. As will be described below, as the semiconductor substrate 100 and various types of material layers formed on the semiconductor substrate 100 are cut by a cutting process performed along the dicing regions 104, the integrated circuit regions 102 can be separated from each other into semiconductor chips (10) of 10). Figure 10

[0045] ​​A semiconductor device layer 110 can be formed on an active surface 100F of the semiconductor substrate 100. The semiconductor device layer 110 can correspond to a plurality of semiconductor devices (SDs) in the integrated circuit region 102, and can correspond to a region including a plurality of semiconductor dummy devices in the dicing region 104.

[0046] A multilayer wiring 120 can be formed from a top surface of the semiconductor device layer 110 to a bottom surface of the upper material film 130. The multilayer wiring 120 can include interlayer insulating films 124 and metal wirings 126 arranged alternately. The multilayer wiring 120 can include a plurality of metal vertical structures 122 arranged in a third direction Z perpendicular to the active surface 100F of the semiconductor substrate 100.

[0047] The metal wirings 126 can include an electrically conductive material including at least one of aluminum (Al), copper (Cu), nickel (Ni), tungsten (W), platinum (Pt), and gold (Au), and the plurality of metal vertical structures 122 can include substantially the same material as the metal wirings 126.

[0048] The interlayer insulating films 124 can include a low dielectric material. When a low dielectric material having a lower dielectric constant than that of silicon oxide is used as the interlayer insulating film 124 in the semiconductor devices SD, the low dielectric material can be useful for high integration and high speed of the semiconductor devices SD.

[0049] In some example embodiments of the disclosure, the interlayer insulating film 124 can be formed to have a structure in which a first interlayer insulating film, a second interlayer insulating film, and a third interlayer insulating film are sequentially stacked on the metal wiring 126. However, the number of films of the interlayer insulating film 124 is not limited to the above example. The interlayer insulating film 124 can be formed to fill the periphery of the plurality of metal vertical structures 122 and the metal wiring 126 formed of an electrically conductive material.

[0050] According to an example embodiment, mutually opposite sidewalls of each of the plurality of metal vertical structures 122 can be formed to be flat. Each of the plurality of metal vertical structures 122 can be formed of a single metal, can have flat sidewalls, and can have a bar shape having a long axis in the third direction Z and a short axis in the first direction X. Accordingly, the plurality of metal vertical structures 122 do not include a bonding interface between heterogeneous materials and a crack generation portion, thereby properly blocking propagation of a crack (CR) in the first direction X and the second direction Y, and thus effectively guiding propagation of the crack (CR) in the third direction Z. Figure 9B Figure 9B

[0051] ​​In the cutting region 104, the multilayer wiring 120 can be formed as a multilayer dummy wiring structure corresponding to the metal wiring formed in the integrated circuit region 102.

[0052] Although the multilayer wiring 120 is illustrated as three layers, they are not limited thereto. For example, the multilayer wiring 120 can be formed as two layers or four or more layers.

[0053] The upper material film 130 can be formed on the multilayer wiring 120. That is, the level of the lowermost surface of the upper material film 130 can be the same as or higher than the level of the uppermost surface of the multilayer wiring 120.

[0054] The upper material film 130 can be formed in a form in which the first material film 132, the second material film 134, and the third material film 136 are sequentially stacked. Each of the first material film 132, the second material film 134, and the third material film 136 can include an insulating film and can be formed of different materials. In some exemplary embodiments of the disclosure, the first material film 132 can include silicon oxide, the second material film 134 can include silicon carbon nitride (SiCN), and the third material film 136 can include silicon nitride. Although the upper material film 130 is illustrated as three films, it is not limited thereto. For example, unlike the illustrated, the upper material film 130 can be formed as two films or four or more films.

[0055] In further exemplary embodiments of the disclosure, the upper material film 130 can be formed to have a structure in which silicon oxide such as phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), undoped silicate glass (USG), tetraethyl orthosilicate (TEOS), plasma enhanced TEOS (PE-TEOS), or high-density plasma chemical vapor deposition (HDP-CVD) oxide and silicon nitride are alternately stacked.

[0056] According to another exemplary embodiment, the upper material film 130 of the cutting region 104 can include a test pattern for testing electrical characteristics of the semiconductor device SD present in the integrated circuit region 102, a redistribution layer for testing electrical connection between the test patterns, or an alignment key for aligning a mask.

[0057] According to an example embodiment of the disclosure, the protective film 140 can be formed to expose the upper material film 130 located in the cutting region 104W and cover the upper material film 130 located in the integrated circuit region 102. The sidewall of the protective film 140 can be an inclined plane. The protective film 140 can include a material film formed of, for example, an organic compound. In some example embodiments of the disclosure, the protective film 140 can include a material film formed of an organic high molecular material. In further example embodiments of the disclosure, the protective film 140 can include a photosensitive polyimide (PSPI) resin. The width 104W of the cutting region 104 exposed from the protective film 140 can be about 5 μm to about 100 μm. However, the value of the width 104W is not limited to the above example.

[0058] The metal shielding layer MS can be formed on the active surface 100F of the semiconductor substrate 100 across the integrated circuit region 102 and the cutting region 104. The metal shielding layer MS can prevent a spot generated due to leakage or scattering of a laser in a cutting process from spreading to the integrated circuit region 102.

[0059] The bottom surface of the metal shielding layer MS can be arranged to directly contact the active surface 100F. In other words, the metal shielding layer MS can be formed in a middle-of-line (MEOL) process. Accordingly, in the integrated circuit region 102 of the semiconductor substrate 100, the semiconductor device SD can not be arranged at a position in which the metal shielding layer MS is formed.

[0060] In a side sectional view, the metal shielding layer MS can include a first metal shielding layer MS1 and a second metal shielding layer MS2, and a first spaced space region SS between the first metal shielding layer MS1 and the second metal shielding layer MS2 and in the cutting region 104. In terms of position, the first metal shielding layer MS1 can be referred to as a left metal shielding layer, and the second metal shielding layer MS2 can be referred to as a right metal shielding layer. The first spacing of the space region SS can be narrower than the width 104W of the cutting region 104.

[0061] The first metal shielding layer MS1 can have a long axis MS1R in a first direction X parallel to the active surface 100F and a short axis MS1S in a third direction Z perpendicular to the active surface 100F. The second metal shielding layer MS2 can have a long axis MS2R in the first direction X parallel to the active surface 100F and a short axis MS2S in the third direction Z perpendicular to the active surface 100F.

[0062] The lengths of the major axes MS1R and MS2R can be from about 50 μm to about 100 μm, and the lengths of the minor axes MS1S and MS2S can be from about 0.5 μm to about 1 μm. Describing the above examples as ratios, the ratio of the lengths of the major axes MS1R and MS2R to the lengths of the minor axes MS1S and MS2S can be from about 50:1 to about 200:1.

[0063] That is, each of the first metal shielding layer MS1 and the second metal shielding layer MS2 can be formed as a thin, flat plate structure to cover the semiconductor substrate 100. The first metal shielding layer MS1 and the second metal shielding layer MS2 can have substantially the same shape as each other, but this disclosure is not limited thereto.

[0064] In the side sectional view, the crack ( Figure 9B The propagation direction of the crack (CR) and the long axis direction of the metal shielding layer MS can be perpendicular to each other. That is, the crack (CR) Figure 9B The propagation direction of CR can be the third direction Z, and the long axis direction of the metal shielding layer MS can be the first direction X.

[0065] In the plan view, the metal shielding layer MS can be a single metal in each of the adjacent integrated circuit regions 102, forming a hollow rectangle or a hollow square, and the cut area 104 is between the adjacent integrated circuit regions 102. This is to allow for cracking (…). Figure 9B The CR (conductor optics) passes through the spatial region SS, and the metal shielding layers MS can be arranged to be spaced apart from each other. In other words, the metal shielding layers MS can be arranged to surround the semiconductor chip (the semiconductor chip). Figure 10 (10). In the plan view, the area of ​​at least one contact metal shielding layer MS in adjacent integrated circuit regions 102 is larger than the area of ​​the contact metal shielding layer MS in the cut region 104.

[0066] The metal shielding layer MS can be made of a metal having a melting point of about 600°C or higher. To prevent the metal shielding layer MS from melting, it can include a metal having a melting point higher than the temperature of the laser-heated portion of the semiconductor substrate 100. In some exemplary embodiments of this disclosure, the metal shielding layer MS can include aluminum (melting point of about 660°C).

[0067] Recently, due to the need for large size and high integration of semiconductor devices, the area occupied by the diced regions in semiconductor substrates has been reduced. Typically, semiconductor substrates are mechanically cut using a dicing blade. However, this mechanical cutting process can increase the risk of damage to integrated circuit areas due to the stress applied to the semiconductor substrate during the cutting process.

[0068] Accordingly, a process of cutting a semiconductor substrate by using a laser has been performed. However, due to a difference between a density of a modified layer of the semiconductor substrate and a density around the modified layer, a portion of the laser that must be focused on the inside of the semiconductor substrate leaks or is scattered, and penetrates a semiconductor device of an integrated circuit region, thereby causing a malfunction.

[0069] Accordingly, the semiconductor substrate 100 according to the disclosure can prevent the leakage or scattering of the laser into a region where the semiconductor device SD is located by forming the metal shielding layer MS across the integrated circuit region 102 and the cutting region 104 of the semiconductor substrate 100. In this way, a malfunction such as a functional failure that occurs in the semiconductor device SD due to the leakage or scattering of the laser can be prevented.

[0070] In this way, the semiconductor chip cut from the semiconductor substrate 100 according to the disclosure has fewer malfunctions in a cutting process, thereby improving the electrical characteristics and production efficiency of the semiconductor chip.

[0071] Hereinafter, a method of cutting the semiconductor substrate 100 including the metal shielding layer MS will be described in detail.

[0072] Figure 3 is a perspective view showing a state in which a protective sheet is attached to a semiconductor substrate according to an exemplary embodiment of the disclosure, and Figure 4 is a side sectional view corresponding to line IV-IV' shown in Figure 3 in which attachment of the protective sheet to the semiconductor substrate is completed.

[0073] Referring to Figure 3 and Figure 4 , the protective sheet 200 can be attached to the active surface 100F of the semiconductor substrate 100.

[0074] The protective sheet 200 can protect the integrated circuit region 102 during a cutting process of the semiconductor substrate 100.

[0075] The protective sheet 200 can include a polyvinyl chloride (PVC)-based polymer sheet, and can be attached to the active surface 100F using an acrylic resin-based adhesive. The acrylic resin-based adhesive can have a thickness of about 2 μm to about 10 μm, and the protective sheet 200 can have a thickness of about 60 μm to about 200 μm. The protective sheet 200 can have a circular shape having a diameter substantially the same as a diameter of the semiconductor substrate 100.

[0076] Figure 5A is a perspective view showing a state in which a laser is irradiated into a semiconductor substrate according to an exemplary embodiment of the disclosure, and Figure 5B is a side sectional view showing a traveling direction of the laser.

[0077] Referring to Figure 5A and Figure 5B After the protective sheet 200 is attached to the active surface 100F of the semiconductor substrate 100, the laser RA having a wavelength that is penetrative with respect to the semiconductor substrate 100 can be controlled to have a convergence point 150P inside the semiconductor substrate 100, and thus can be irradiated along the dicing region 104.

[0078] When the laser RA is irradiated inside the semiconductor substrate 100, a modified layer 150 of the semiconductor substrate 100 can be formed along the dicing region 104 inside the semiconductor substrate 100. Figure 6 The modified layer 150 of the semiconductor substrate 100 can be formed using the laser irradiation apparatus 300. Figure 6

[0079] The laser irradiation apparatus 300 can include a chuck table 310 that supports the semiconductor substrate 100, a laser irradiation device 320 that irradiates the laser RA to the semiconductor substrate 100 disposed on the chuck table 310, and an imaging device 330 that images the semiconductor substrate 100 disposed on the chuck table 310. The chuck table 310 can support the semiconductor substrate 100 by suction using vacuum pressure, and can move in a first direction X and a second direction Y.

[0080] The laser irradiation device 320 can be configured to irradiate a pulse laser from a condenser 324 mounted on a front end of a cylindrical-shaped housing 322 disposed horizontally. While the condenser 324 irradiates a pulse laser having a wavelength that is penetrative with respect to the semiconductor substrate 100, the chuck table 310 and the condenser 324 can perform relative movement at an appropriate speed.

[0081] The imaging device 330 mounted on the other front end of the housing 322 constituting the laser irradiation device 320 can be a normal charge-coupled device (CCD) imaging device that performs imaging by using visible light. In another exemplary embodiment of the disclosure, the imaging device 330 can include an infrared irradiation device that irradiates infrared rays to the semiconductor substrate 100, an optical system that captures the infrared rays irradiated by the infrared irradiation device, and an infrared CCD imaging device that outputs an electrical signal corresponding to the infrared rays captured by the optical system.

[0082] The laser irradiation device 320 can irradiate the laser RA after aligning a laser irradiation position. The convergence point 150P of the laser RA can be controlled to be closer to the active surface 100F of the semiconductor substrate 100 than to the non-active surface 100B of the semiconductor substrate 100. That is, the modified layer 150 of the semiconductor substrate 100 can be disposed closer to the active surface 100F. Figure 6

[0083] ​​The laser light RA emitted from the laser light irradiation device 320 can be strongly irradiated such that a portion of the semiconductor substrate 100 is heated to a temperature of about 600°C. That is, a portion of the semiconductor substrate 100 located in the convergence point 150P of the laser light RA can be melted by the laser light RA.

[0084] As such, when the portion of the semiconductor substrate 100 is melted, a crystalline state of the portion is changed, thereby causing an unexpected leakage or scattering RB of the laser light RA. The leakage or scattering RB of the laser light RA can cause a spot in a portion of the semiconductor substrate 100 other than the convergence point 150P, and the spot can cause a malfunction of the semiconductor device.

[0085] Figure 6 is a side sectional view showing a state in which irradiation of laser light is completed according to an exemplary embodiment of the present disclosure, Figure 7A which corresponds to Figure 2A is Figure 6 is a plan view of the region A shown in Figure 7B is a side sectional view of a surface corresponding to a surface taken by cutting Figure 7A in the X direction.

[0086] Referring to Figure 6 , Figure 7A and Figure 7B , the modification layer 150 can be disposed apart from the non-active surface 100B of the semiconductor substrate 100 by a first distance D1, and the modification layer 150 can be disposed closer to the active surface 100F.

[0087] By light amplification by stimulated emission of radiation, laser light can be easily irradiated to a target location. By utilizing a characteristic of laser light, the modification layer 150 can be formed at a target location inside the semiconductor substrate 100. The modification layer 150 can include a crack site at which a crack (CR) is induced by an external physical impact. Figure 9B

[0088] Due to an unexpected leakage or scattering of laser light, a first spot 151 and a second spot 153 can be formed. The first spot 151 can indicate a spot formed inside the semiconductor substrate 100, and the second spot 153 can indicate a spot formed inside the metal shielding layer MS. The second spot 153 is formed at a location that can substantially affect the semiconductor device SD, but the semiconductor substrate 100 according to the present disclosure can solve such a problem by including the metal shielding layer MS.

[0089] The modification layer 150 can be located below the semiconductor device layer 110. The modification layer 150 has a constant width in a first direction X, and a virtual line connecting the modification layer 150 in a second direction Y can have the form of a linear lane. ​

[0090] Figure 8 is a side sectional view showing a state in which the semiconductor substrate according to an exemplary embodiment of the present disclosure is polished, Figure 9A (corresponding to Figure 2A ) is Figure 8 is a plan view of the region A shown in Figure 9B is a side sectional view of a surface taken by cutting Figure 9A at the center in the X direction.

[0091] Referring to Figure 8 , Figure 9A and Figure 9B , a crack CR can be induced in the dicing region 104 by polishing the passive surface 100B of the semiconductor substrate 100.

[0092] By polishing the passive surface 100B of the semiconductor substrate 100 using the polishing apparatus 400, the thickness of the semiconductor substrate 100 can be reduced, and the crack CR can propagate from the modification layer 150.

[0093] The polishing apparatus 400 can include a chuck table 410 supporting the semiconductor substrate 100 and a grinder 420 polishing the semiconductor substrate 100 disposed on the chuck table 410. The grinder 420 can move while rotating, and a polishing pad can be attached under the grinder 420.

[0094] The polished semiconductor substrate 100 can have a second thickness T2 that is substantially smaller than the initial first thickness (T1) of the semiconductor substrate 100. The second thickness T2 can be about 20 µm to about 50 µm. Figure 2B

[0095] By polishing the semiconductor substrate 100 using the polishing apparatus 400, a polished semiconductor substrate 100 having a final thickness can be formed. At the same time, in the dicing region 104, the crack CR can pass through the active surface 100F of the polished semiconductor substrate 100 from the modification layer 150 and propagate away from the active surface 100F in the third direction Z.

[0096] According to an exemplary embodiment of the present disclosure, a laser can be irradiated inside the semiconductor substrate 100 to form a modification layer 150 along the dicing region 104 of the semiconductor substrate 100, and then the passive surface 100B of the semiconductor substrate 100 can be polished. The polishing process can be a grinding process in a state in which physical pressure is applied to the semiconductor substrate 100.

[0097] ​When a polishing process is performed under physical pressure on a semiconductor substrate 100, the polished semiconductor substrate 100 can become brittle and fracture. Brittle fracture indicates that when a force greater than or equal to the elastic limit is applied to an object, the object fractures rather than undergoes permanent deformation. Therefore, during the polishing of the passive surface 100B of the semiconductor substrate 100, the gradually thinning semiconductor substrate 100 may brittle fracture due to cracks CR propagating from the modified layer 150. As cracks CR propagating from the modified layer 150 are initiated along the dicing region 104 that isolates the integrated circuit region 102, the integrated circuit region 102 can be separated into semiconductor chips through the brittle fracture of the semiconductor substrate 100. Figure 10 10). Semiconductor chips ( Figure 10 10) can be fixed in the original position by the protective sheet 200 without leaving the original position.

[0098] In another exemplary embodiment of this disclosure, the modified layer 150 can be completely removed by continuing to polish the passive surface 100B of the semiconductor substrate 100. The semiconductor chip separated by completely removing the modified layer 150 ( Figure 10 The cut surface of 10) can be smoother than that of mechanical cutting using a dicing blade. In addition, by completely removing the modified layer 150 in the polishing process, the cracked areas in the modified layer 150 can be completely removed without causing another crack CR.

[0099] Cracks CR propagating from the modified layer 150 can propagate in the third direction Z. Even when cracks CR partially propagate in the first direction X and / or the second direction Y, they can be prevented from propagating to the integrated circuit region 102 by being blocked by the multiple metal vertical structures 122.

[0100] Furthermore, by using a laser, the cutting width of the semiconductor substrate 100 can be reduced. Therefore, compared with mechanical cutting using a dicing blade, the width of the cutting region 104 can be reduced, thereby forming more integrated circuit regions 102 on the semiconductor substrate 100.

[0101] Figure 10 This is a side sectional view showing a semiconductor substrate, according to an exemplary embodiment of the present disclosure, being diced into a semiconductor chip. Figure 11A (which corresponds to) Figure 2A )yes Figure 10 An enlarged plan view of region A shown, and Figure 11B This corresponds to cutting in the X direction. Figure 11A A side sectional view of the surface taken from the center.

[0102] Refer to together Figure 10 , Figure 11A and Figure 11BThe semiconductor substrate 100 can be separated into semiconductor chips 10 by a dicing process.

[0103] More specifically, in the semiconductor substrate 100, the integrated circuit region 102 can be separated into semiconductor chips 10 by a crack (CR) in the dicing region 104. Figure 9B The separated semiconductor chips (10) can be fixed in the original position without leaving the original position by the protection sheet 200. Figure 10

[0104] The method of dicing the semiconductor substrate 100 according to the present disclosure can form a metal shielding layer MS across the integrated circuit region 102 and the dicing region 104 of the semiconductor substrate 100, thereby preventing the leaked or scattered laser light from affecting the semiconductor device and reducing the width of the dicing region 104.

[0105] In other words, in the method of dicing the semiconductor substrate 100 using a laser, the effect of the leaked or scattered laser light can be removed by the metal shielding layer MS, thereby preventing a malfunction such as a functional failure of the semiconductor device.

[0106] Finally, the malfunction of the semiconductor chips 10 diced by the method of dicing the semiconductor substrate 100 can be reduced, and the electrical characteristics and productivity of the semiconductor chips 10 can be improved.

[0107] Figure 12A and Figure 12B shows a semiconductor substrate according to another exemplary embodiment of the present disclosure, wherein Figure 12A is a magnified side sectional view corresponding to the region A shown in FIG. 1A, and Figure 1 is a magnified plan view corresponding to the region C shown in FIG. 1A. Figure 12B Figure 1 Hereinafter, many components of the semiconductor substrate 100-1 and materials of the components are substantially the same as or similar to the descriptions made with reference to the semiconductor substrate (100) described above.

[0108] Figure 1 Figure 2A Figure 2B and Figure 2C , the description will be described based on the differences from the semiconductor substrate (100) described above for convenience. Figure 1 Referring to

[0109] and Figure 12A , the semiconductor substrate 100-1 can include a metal shielding layer MS that continuously across adjacent integrated circuit regions 102 having a dicing region 104 therebetween. Figure 12B

[0110] ​​​​​​A metal shielding layer MS can be formed on the active surface 100F of the semiconductor substrate 100 across the adjacent integrated circuit regions 102 and the cutting region 104. The metal shielding layer MS can prevent a spot generated due to leakage or scattering of a laser in a cutting process from spreading to the integrated circuit regions 102.

[0111] A bottom surface of the metal shielding layer MS can be arranged to directly contact the active surface 100F. In other words, the metal shielding layer MS can be formed in an MEOL process. Accordingly, in the integrated circuit regions 102 of the semiconductor substrate 100, the semiconductor device SD can not be arranged at a position where the metal shielding layer MS is formed.

[0112] In a side sectional view, the metal shielding layer MS can have a long axis MSR in a first direction X parallel to the active surface 100F and a short axis MSS in a third direction Z perpendicular to the active surface 100F.

[0113] The length of the long axis MSR can be about 100 μm to about 200 μm, and the length of the short axis MSS can be about 0.5 μm to about 1 μm. Describing the above examples as a ratio, the ratio of the length of the long axis MSR to the length of the short axis MSS can be about 100:1 to about 400:1.

[0114] That is, the metal shielding layer MS can be formed as a thin flat plate type structure to cover the semiconductor substrate 100.

[0115] In a side sectional view, the propagation direction of the crack (CR) can be perpendicular to the long axis direction of the metal shielding layer MS. That is, the propagation direction of the crack (CR) can be the third direction Z, and the long axis direction of the metal shielding layer MS can be the first direction X. In the cutting process, the crack (CR) can penetrate a central portion of the metal shielding layer MS located in the cutting region 104. Figure 9B Figure 9B In a side sectional view, the propagation direction of the crack (CR) and the long axis direction of the metal shielding layer MS can be perpendicular to each other. That is, the propagation direction of the crack (CR) can be the third direction Z, and the long axis direction of the metal shielding layer MS can be the first direction X. In the cutting process, the crack (CR) can penetrate a central portion of the metal shielding layer MS located in the cutting region 104. Figure 9B In a side sectional view, the propagation direction of the crack (CR) and the long axis direction of the metal shielding layer MS can be perpendicular to each other. That is, the propagation direction of the crack (CR) can be the third direction Z, and the long axis direction of the metal shielding layer MS can be the first direction X. In the cutting process, the crack (CR) can penetrate a central portion of the metal shielding layer MS located in the cutting region 104.

[0116] Figure 9B In a plan view, the metal shielding layer MS can include a one-piece metal in a hollow lattice shape in each of the adjacent integrated circuit regions 102, covering the active surface 100F corresponding to the cutting region 104. The metal shielding layer MS can be arranged to allow the crack (CR) to pass through the metal shielding layer MS. In other words, the metal shielding layer MS can be arranged to surround the semiconductor chip (10). Figure 10

[0117] ​​​The metal shielding layer MS can be made of a metal having a melting point of about 600°C or higher. To prevent the metal shielding layer MS from melting, it can include a metal having a melting point higher than the temperature of the laser-heated portion of the semiconductor substrate 100. In some exemplary embodiments of this disclosure, the metal shielding layer MS can include aluminum (melting point of about 660°C).

[0118] Figure 13 A semiconductor substrate according to another exemplary embodiment of the present disclosure is shown, wherein Figure 13 It corresponds to Figure 1 An enlarged side sectional view of region A shown.

[0119] In the following text, many components of the semiconductor substrate 100-2, as well as the materials of the components, are compared with reference to [reference material]. Figures 1 to 2C The descriptions are essentially the same or similar. Therefore, for convenience, the description will be based on the semiconductor substrate described above ( Figure 1 The differences between 100 and 100 are described.

[0120] Reference Figure 13 The semiconductor substrate 100-2 may include an integrated circuit region 102 and a diced region 104, but does not include multiple metal vertical structures.

[0121] Multilayer wiring 120 can be formed from the top surface of semiconductor device layer 110 to the bottom surface of upper material film 130. Multilayer wiring 120 may include alternating interlayer insulating films 124 and metal wiring 126.

[0122] The metal wiring 126 may include a conductive material, which includes at least one of aluminum (Al), copper (Cu), nickel (Ni), tungsten (W), platinum (Pt), and gold (Au).

[0123] The interlayer insulating film 124 may include a low-dielectric material. When a low-dielectric material having a dielectric constant lower than that of silicon oxide is used as the interlayer insulating film 124 in a semiconductor device SD, the low-dielectric material can be useful for the high integration and high speed of the semiconductor device SD.

[0124] In some exemplary embodiments of this disclosure, the interlayer insulating film 124 may be formed having a structure in which a first interlayer insulating film, a second interlayer insulating film, and a third interlayer insulating film are sequentially stacked and the metal wiring 126 is therein. However, the number of films in the interlayer insulating film 124 is not limited to the examples described above. The interlayer insulating film 124 may be formed to fill the area around the plurality of metal vertical structures 122 and the metal wiring 126.

[0125] A metal shielding layer MS can be formed on the active surface 100F of the semiconductor substrate 100 across the integrated circuit region 102 and the cutting region 104. The metal shielding layer MS can prevent a spot generated due to leakage or scattering of a laser in a cutting process from spreading to the integrated circuit region 102.

[0126] In a side sectional view, the metal shielding layer MS can include a first metal shielding layer MS1 and a second metal shielding layer MS2, and a first spaced apart space region SS between the first metal shielding layer MS1 and the second metal shielding layer MS2 and in the cutting region 104. In terms of position, the first metal shielding layer MS1 can be referred to as a left metal shielding layer, and the second metal shielding layer MS2 can be referred to as a right metal shielding layer. The first spacing of the space region SS can be narrower than the width 104W of the cutting region 104.

[0127] Figure 14 FIG. 1 is a side sectional view illustrating a semiconductor package including semiconductor chips cut from a semiconductor substrate, according to an exemplary embodiment of the present disclosure, Figure 15A FIG. 2 is a side sectional view illustrating a semiconductor package including semiconductor chips cut from a semiconductor substrate, according to an exemplary embodiment of the present disclosure, Figure 14 FIG. 3 is an enlarged side sectional view of a portion D shown in FIG. 2, and Figure 15B FIG. 4 is an enlarged side sectional view of a portion D shown in FIG. 2, according to an exemplary embodiment of the present disclosure. Figure 14 FIG. 5 is an enlarged side sectional view of a portion D shown in FIG. 2.

[0128] Referring to Figure 14 , the semiconductor package 1000 can include a package substrate 1010, a plurality of semiconductor chips 10, a connection member 1020, and a molding member 1030.

[0129] The package substrate 1010, which is a support substrate, can include a main body 1011. According to an exemplary embodiment, the package substrate 1010 can further include a lower protection layer and an upper protection layer. The package substrate 1010 can be formed based on a printed circuit board (PCB), a wafer substrate, a ceramic substrate, a glass substrate, an interposer substrate, or the like. In an exemplary embodiment of the present disclosure, the package substrate 1010 can be a PCB. The package substrate 1010 is not limited to a PCB.

[0130] According to an embodiment, a wiring 1016 can be formed on the package substrate 1010, and the wiring 1016 can be electrically connected to the semiconductor chip 10 through the connection member 1020 connected to the upper electrode pad 1012 on the top surface of the package substrate 1010. An external connection terminal 1040 can be disposed on the lower electrode pad 1014 on the bottom surface of the package substrate 1010. The package substrate 1010 can be mounted to be electrically connected to a module substrate or a system board of an electronic product through the external connection terminal 1040.

[0131] A multi-layer wiring or a single-layer wiring (e.g., the wiring 1016) can be formed in the main body 1011, and the semiconductor chip 10 can be electrically connected with the external connection terminal 1040 through the wiring 1016. A lower protective layer and an upper protective layer can function to protect the main body 1011, and can be formed, for example, as a solder resist.

[0132] When the package substrate 1010 is a PCB, the main body 1011 can be generally implemented by compressing a high molecular material such as a thermosetting resin, an epoxy-based resin such as flame retardant 4 (FR-4), a bismaleimide triazine (BT), an Ajinomoto build up film (ABF), etc., a phenol resin, etc., to form a thin film, applying a copper foil on opposite sides of each other, and forming the wiring 1016 as a transmission path of an electrical signal by patterning. Except for a portion connected with a terminal, for example, the upper electrode pad 1012 and the lower electrode pad 1014, a solder resist can be coated on a bottom surface and a top surface of the main body 1011, thereby implementing a lower protective layer and an upper protective layer.

[0133] Meanwhile, the PCB can be classified into a single-layer PCB in which the wiring 1016 is formed only on a single side and a double-layer PCB in which the wiring 1016 is formed on opposite sides of each other. By using an insulator called a prepreg, the number of layers of the copper foil can be three or more, and three or more wirings 1016 can be formed based on the number of formed copper foils, thereby implementing a PCB having a multi-layer structure. However, the package substrate 1010 is not limited to the above-described structure or material of the PCB.

[0134] A plurality of semiconductor chips 10 can be electrically connected to the package substrate 1010 through a connection member 1020. The connection member 1020 can electrically connect the package substrate 1010 and the plurality of semiconductor chips 10 by electrically connecting the upper electrode pad 1012 of the package substrate 1010 with the connection pad 12 of the semiconductor chip 10. In some exemplary embodiments of the disclosure, the connection member 1020 can be a bonding wire.

[0135] The connection member 1020 can be used to electrically connect the semiconductor chip 10 with the package substrate 1010. Through the connection member 1020, at least one of a control signal, a power signal, and a ground signal for the operation of the semiconductor chip 10 can be provided from the outside, a data signal to be stored in the semiconductor chip 10 can be provided from the outside, or data stored in the semiconductor chip 10 can be provided to the outside.

[0136] The molding member 1030 can protect the plurality of semiconductor chips 10 from an external environment by surrounding the plurality of semiconductor chips 10. The molding member 1030 can be used to form an appearance of the semiconductor package 1000 by an injection process of injecting an appropriate amount of molding resin onto the package substrate 1010 and a hardening process. As necessary, in a press process, the appearance of the semiconductor package 1000 can be formed by applying pressure to the molding resin. Here, process conditions such as a delay time between injection of the molding resin and pressing, an amount of injection molding resin, and a pressing temperature / pressure, etc. can be set based on physical properties such as viscosity of the molding resin.

[0137] The side surface and the top surface of the molding member 1030 can have a right angle shape. In a process of manufacturing the semiconductor package 1000 by cutting the package substrate 1010 along the cutting line, the side surface and the top surface of the molding member 1030 can generally have a right angle shape. Although not shown, a marking pattern including information of the semiconductor chip 10, such as a bar code, a number, a character, a symbol, etc. can be formed in a portion of the side surface of the semiconductor package 1000.

[0138] In some example embodiments of the disclosure, the molding resin can include an epoxy-based molding resin, a polyimide-based molding resin, etc. The molding member 1030 can include, for example, an epoxy resin molding compound (EMC).

[0139] The connection pad 12 can be disposed on the semiconductor device layer and can be electrically connected with a wiring layer inside the semiconductor device layer. The wiring layer can be electrically connected with the connection member 1020 through the connection pad 12. The connection pad 12 can include at least one of aluminum (Al), copper (Cu), nickel (Ni), tungsten (W), platinum (Pt), and gold (Au).

[0140] A passivation layer can be formed on the semiconductor device layer for protecting the semiconductor device layer, the wiring layer, and other structures from external impact or moisture. The passivation layer can expose at least a portion of a top surface of the connection pad 12.

[0141] The plurality of semiconductor chips 10 constituting the semiconductor package 1000 can have a stacked structure. When eight semiconductor chips 10 are stacked as shown, four semiconductor chips 10 can form a group, and the semiconductor package 1000 can include two groups.

[0142] When the four semiconductor chips 10 of the first group are stacked one by one from a bottom layer to a top layer, the semiconductor chips 10 can be moved step by step to be arranged in the first direction X, thereby exposing the connection pad 12 disposed in each semiconductor chip 10.

[0143] The four semiconductor chips 10 of the second group can be stacked on the first group. The four semiconductor chips 10 of the second group can be moved step by step in a first direction X opposite to the direction in which the first group is moved to be arranged.

[0144] Each semiconductor chip 10 constituting the semiconductor package 1000 can include a semiconductor chip cut from a semiconductor substrate according to the present disclosure. In some exemplary embodiments of the present disclosure, the semiconductor chip can include a semiconductor chip cut from the semiconductor substrate 100 as shown in Figure 15A In further exemplary embodiments of the present disclosure, the semiconductor chip can include a semiconductor chip cut from the semiconductor substrate 100-1 as shown in Figure 15B In further exemplary embodiments of the present disclosure, the semiconductor chip can include a semiconductor chip cut from the semiconductor substrate 100-1 as shown in

[0145] Figure 16 is a structural diagram showing a system including a semiconductor package including a semiconductor chip cut from a semiconductor substrate according to an exemplary embodiment of the present disclosure.

[0146] Referring to Figure 16 , the system 1100 can include a controller 1110, an input / output device 1120, a memory 1130, an interface 1140, and a bus 1150.

[0147] The system 1100 can be a mobile system or a system that transmits or receives information. In some exemplary embodiments of the present disclosure, the mobile system can be a portable computer, a web tablet, a mobile phone, a digital music player, or a memory card.

[0148] The controller 1110 is intended to control an execution program in the system 1100, and can include a microprocessor, a digital signal processor, a microcontroller, or a similar device.

[0149] The input / output device 1120 can be used to input or output data of the system 1100. The system 1100 can be connected with an external device (e.g., a personal computer (PC) or a network), or exchange data with the external device by using the input / output device 1120. The input / output device 1120 can be, for example, a touchpad, a keyboard, or a display device.

[0150] The memory 1130 can store data for operation of the controller 1110 or data processed in the controller 1110. The memory 1130 can include a semiconductor chip cut from a semiconductor substrate according to the present disclosure.

[0151] The interface 1140 can be a data transmission path between the system 1100 and an external device. The controller 1110, the input / output device 1120, the memory 1130, the interface 1140 can communicate with each other through the bus 1150.

[0152] While one or more aspects of the disclosure have been particularly shown and described with reference to exemplary implementations thereof, it will be understood that various changes in form and details can be made therein without departing from the spirit and scope of the appended claims.

[0153] This application is based on and claims priority under 35 U.S.C. 119 to Korean Patent Application No. 10-2019-0100527, filed on August 16, 2019, in the Korean Intellectual Property Office, the disclosure of which is incorporated by reference herein in its entirety.

Claims

1. A method of cutting a semiconductor wafer, the method comprising: providing a semiconductor substrate having a plurality of integrated circuit regions on an active surface of the semiconductor substrate, a cut region provided between adjacent integrated circuit regions of the plurality of integrated circuit regions, and a metal shield layer provided on the active surface across at least a portion of the adjacent integrated circuit regions and the cut region; forming a modified layer by irradiating a laser inside the semiconductor substrate along the cut region; propagating a crack from the modified layer in a direction perpendicular to a long axis direction of the metal shield layer by polishing a passive surface of the semiconductor substrate opposite the active surface; and forming semiconductor chips by separating the adjacent integrated circuit regions based on the crack propagated from the modified layer, respectively, the method further comprising forming a plurality of metal vertical structures contacting the metal shield layer, the plurality of metal vertical structures extending continuously through a plurality of interlayer insulating films and a plurality of metal wirings in a direction perpendicular to the active surface.

2. The method according to claim 1, wherein, forming the modified layer by irradiating a laser includes preventing a spot generated due to leakage or scattering of a laser from spreading to the adjacent integrated circuit regions using the metal shield layer.

3. The method according to claim 1, wherein, at the time of providing the semiconductor substrate, a bottom surface of the metal shield layer is arranged to directly contact the active surface.

4. The method according to claim 1, wherein the adjacent integrated circuit regions include a first integrated circuit region and a second integrated circuit region adjacent to each other, the metal shield layer includes a first metal shield layer corresponding to the first integrated circuit region and a second metal shield layer corresponding to the second integrated circuit region, the first metal shield layer and the second metal shield layer are spaced apart from each other by a first interval, and the first interval is smaller than a width of the cut region.

5. The method according to claim 4, wherein, each of the first metal shield layer and the second metal shield layer includes a long axis parallel to the active surface and a short axis perpendicular to the active surface, and a ratio of a length of the long axis to a length of the short axis is 50: 1 to 200:

1.

6. The method according to claim 1, wherein, in a plan view, the metal shield layer is continuous across the adjacent integrated circuit regions having the cut region therebetween, and the crack penetrates the metal shield layer located in the cut region.

7. The method according to claim 6, wherein, the metal shield layer covers the active surface corresponding to the cut region.

8. The method according to claim 1, wherein, at the time of providing the semiconductor substrate, the metal shield layer includes a single metal, and a melting point of a material forming the metal shield layer is higher than 600°C.

9. The method according to claim 1, wherein, the plurality of metal vertical structures are configured to guide propagation of the crack.

10. The method according to claim 9, wherein in a plan view, a direction of the crack and a long axis direction of each of the plurality of metal vertical structures are parallel to each other.

11. A method of cutting a semiconductor wafer, the method comprising: providing a semiconductor substrate having a plurality of integrated circuit regions on an active surface of the semiconductor substrate, a cut region provided between adjacent integrated circuit regions of the plurality of integrated circuit regions, and a metal shield layer formed on the active surface across at least a portion of the integrated circuit regions and the cut region; forming a modified layer by irradiating a laser into the semiconductor substrate along the cut region; causing a crack to propagate from the modified layer in a direction perpendicular to a long axis direction of the metal shield layer by polishing a non-active surface of the semiconductor substrate opposite the active surface; and forming semiconductor chips by separating the adjacent integrated circuit regions based on the crack propagated from the modified layer, respectively, wherein, in a cross-sectional view, the metal shield layer includes a first metal shield layer and a second metal shield layer, a space region is between the first metal shield layer and the second metal shield layer and in a position where the crack propagates, in the cross-sectional view, each of the first metal shield layer and the second metal shield layer includes a long axis parallel to the active surface and a short axis perpendicular to the active surface, and a length of the long axis is 50 μm to 100 μm and a length of the short axis is 0.5 μm to 1 μm, the method further includes forming a plurality of metal vertical structures contacting the metal shield layer, the plurality of metal vertical structures continuously extending through a plurality of interlayer insulating films and a plurality of metal wirings in a direction perpendicular to the active surface.

12. The method according to claim 11, wherein forming the modified layer by irradiating a laser includes preventing a spot generated due to leakage or scattering of the laser from spreading to the adjacent integrated circuit regions using the first metal shield layer and the second metal shield layer.

13. The method according to claim 11, wherein the adjacent integrated circuit regions include a first integrated circuit region and a second integrated circuit region adjacent to each other, and in forming the semiconductor chips, in a plan view, the first metal shield layer has a rectangular shape arranged along a perimeter of the first integrated circuit region and the second metal shield layer has a rectangular shape arranged along a perimeter of the second integrated circuit region adjacent to the first integrated circuit region.

14. The method according to claim 11, wherein in providing the semiconductor substrate, the first metal shield layer and the second metal shield layer have substantially the same shape to each other and the same material to each other.

15. The method according to claim 14, wherein the first metal shield layer and the second metal shield layer include aluminum.

16. A semiconductor wafer comprising: a semiconductor substrate including a plurality of integrated circuit regions on an active surface; a cut region provided between adjacent integrated circuit regions among the plurality of integrated circuit regions; and a metal shielding layer provided on the active surface across a portion of the adjacent integrated circuit regions and the cut region, wherein, in a cross-sectional view, the metal shielding layer includes a long axis parallel to the active surface and a short axis perpendicular to the active surface, and in a plan view, the metal shielding layer is arranged along a perimeter of a respective integrated circuit region among the adjacent integrated circuit regions, the semiconductor wafer further includes a plurality of metal vertical structures contacting the metal shielding layer, the plurality of metal vertical structures continuously extending through a plurality of interlayer insulating films and a plurality of metal wirings in a direction perpendicular to the active surface.

17. The semiconductor wafer according to claim 16, wherein a bottom surface of the metal shielding layer is arranged to directly contact the active surface.

18. The semiconductor wafer according to claim 16, wherein in the plan view, the metal shielding layer includes a first metal shielding layer and a second metal shielding layer, and a first spaced-apart space region is between the first metal shielding layer and the second metal shielding layer, and the first spacing is smaller than a width of the cut region.

19. The semiconductor wafer according to claim 18, wherein in each of the first metal shielding layer and the second metal shielding layer, a ratio of a length of the long axis to a length of the short axis is 50: 1 to 200:

1.

20. The semiconductor wafer according to claim 16, wherein in the plan view, an area of at least one of the adjacent integrated circuit regions contacting the metal shielding layer is larger than an area of the cut region contacting the metal shielding layer.

21. The semiconductor wafer according to claim 16, wherein in a plan view, the metal shielding layer is continuous across the adjacent integrated circuit regions with the cut region therebetween.

22. The semiconductor wafer according to claim 21, wherein the metal shielding layer covers the active surface corresponding to the cut region.

23. The semiconductor wafer according to claim 16, wherein the metal shielding layer includes a single metal, and a melting point of a material forming the metal shielding layer is higher than 600°C.

24. The semiconductor wafer according to claim 16, wherein in the plan view, a long axis direction of each of the plurality of metal vertical structures is perpendicular to the active surface.

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