Image Sensor

Abstract

An image sensor is provided. The image sensor includes: a first substrate; a plurality of photoelectric conversion units located in the first substrate; a first connection layer disposed on the first substrate; a plurality of first pixel pads disposed on the first connection layer; a plurality of first peripheral pads disposed on the first substrate; a plurality of second pixel pads respectively disposed on the plurality of first pixel pads; a plurality of second peripheral pads respectively disposed on the plurality of first peripheral pads; a second connection layer disposed on the plurality of second pixel pads and the plurality of second peripheral pads; a device disposed on the second connection layer; and a second substrate disposed on the second connection layer and the device, wherein the spacing between the plurality of first pixel pads is substantially the same as the spacing between the plurality of pixel regions of the first substrate.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the priority benefit of Korean Patent Application No. 10-2019-0098327 filed on August 12, 2019, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The present inventive concept relates to an image sensor and more particularly to a stacked image sensor including a stacked structure. Background Art

[0004] An image sensor is a device for converting an optical image into an electrical signal. Examples of image sensors include a charge coupled device (CCD) and an active pixel sensor (CMOS sensor). Image sensors can be used in cameras of portable electronic devices such as smartphones or tablet computers. However, due to the size of the image sensor, it may be difficult to reduce the size of the portable electronic device.

[0005] Stacked image sensors have been developed to reduce the size of portable electronic devices and improve camera performance. Stacked image sensors can achieve reduction in planar area, improvement in resolution, and improvement in signal processing speed. Summary of the invention

[0006] At least one embodiment of the inventive concept provides a stacked image sensor.

[0007] According to an exemplary embodiment of the inventive concept, there is provided an image sensor, comprising: a first substrate including a pixel array region including a plurality of pixel regions and a peripheral region around the pixel array region; a plurality of photoelectric conversion units respectively located in the plurality of pixel regions of the first substrate; a first connection layer disposed on the pixel array region and the peripheral region of the first substrate; a plurality of first pixel pads disposed on a portion of the first connection layer on the pixel array region of the first substrate; a plurality of first peripheral pads disposed on a portion of the first connection layer on the peripheral region of the first substrate; a plurality of second pixel pads respectively located on the plurality of first pixel pads; a plurality of second peripheral pads respectively located on the plurality of first peripheral pads; a second connection layer disposed on the plurality of second pixel pads and the plurality of second peripheral pads; a device disposed on the second connection layer; and a second substrate disposed on the second connection layer and the device, wherein a spacing of the plurality of first pixel pads in a first horizontal direction is substantially the same as a spacing of the plurality of pixel regions of the first substrate in the first horizontal direction, and wherein a center of each of the plurality of first pixel pads is spaced a predetermined distance from a center of each of the plurality of pixel regions of the first substrate in the second horizontal direction.

[0008] According to an exemplary embodiment of the present invention, an image sensor is provided, including a first structure and a second structure, wherein the first structure includes: a first substrate including a plurality of pixel regions; a plurality of photoelectric conversion units respectively located in the plurality of pixel regions of the first substrate; a first connection layer disposed on the first substrate; and a plurality of first pixel pads disposed on the first connection layer; the second structure includes: a second substrate; a device disposed on the second substrate; a second connection layer disposed on the second substrate and the device; and a plurality of second pixel pads disposed on the second connection layer, wherein the plurality of first pixel pads respectively contact the plurality of second pixel pads, wherein the first connection layer includes an insulating layer disposed on the first substrate and a device disposed on the second substrate. A conductive pattern disposed in an insulating layer, wherein the portion of the first connecting layer located on the plurality of pixel regions of the first substrate comprises: a plurality of overlapping portions, respectively overlapping with the plurality of first pixel pads in a plan view; and a plurality of non-overlapping portions, not overlapping with the plurality of first pixel pads in a plan view, and wherein a ratio of a total volume of the plurality of portions of the conductive pattern respectively located in the plurality of overlapping portions of the first connecting layer to a total volume of the plurality of portions of the insulating layer respectively located in the plurality of overlapping portions of the first connecting layer is smaller than a ratio of a total volume of the plurality of portions of the conductive pattern respectively located in the plurality of non-overlapping portions of the first connecting layer to a total volume of the plurality of portions of the insulating layer in the plurality of non-overlapping portions of the first connecting layer.

[0009] According to an exemplary embodiment of the present invention, an image sensor is provided, including a first structure and a second structure, wherein the first structure includes: a first substrate including a plurality of shared pixel regions, each of which includes a first pixel region and a second pixel region; a plurality of first photoelectric conversion units, each of which is located in a first pixel region of each of the plurality of shared pixel regions of the first substrate; a plurality of second photoelectric conversion units, each of which is located in a second pixel region of each of the plurality of shared pixel regions of the first substrate; a plurality of shared floating diffusion regions, located on the first pixel region and the second pixel region of each of the plurality of shared pixel regions; a first connection layer, disposed on the first substrate; and a plurality of first pixel pads and a plurality of second pixel pads, disposed on the first connection layer, wherein the second structure includes: a second substrate; a device a device, arranged on a second substrate; a second connection layer, on the second substrate and the device; and a plurality of third pixel pads and a plurality of fourth pixel pads, on the second connection layer, wherein the first structure contacts the second structure so that the plurality of first pixel pads respectively contact the plurality of third pixel pads, and the plurality of second pixel pads respectively contact the plurality of fourth pixel pads, wherein the spacing of the plurality of first pixel pads in the first horizontal direction and the spacing of the plurality of second pixel pads in the first horizontal direction are substantially the same as the spacing of the plurality of shared pixel areas in the first horizontal direction, and wherein the distance between the plurality of first pixel pads and the plurality of second pixel pads in the shared pixel area in the second horizontal direction is substantially different from the distance between the plurality of first pixel pads and the plurality of second pixel pads in the shared pixel area in the second horizontal direction.

[0010] According to an exemplary embodiment of the present invention, there is provided an image sensor, including: a first substrate having a pixel area including a photoelectric conversion unit; a first connection layer disposed on the pixel area; a first pixel pad including a conductive and reflective material, disposed on the first connection layer in the pixel area, and not overlapping with the photoelectric conversion unit in a plan view; a second pixel pad located on the first pixel pad; a second connection layer disposed on the second pixel pad; a device disposed on the second connection layer to control the photoelectric conversion unit; and a second substrate disposed on the second connection layer and the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Exemplary embodiments of the inventive concept will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0012] Figure 1 is a block diagram of an image sensor according to an exemplary embodiment of the inventive concept;

[0013] Figure 2 is a circuit diagram of a pixel circuit included in an image sensor according to an exemplary embodiment of the inventive concept;

[0014] Figure 3 is a plan view of a first structure included in an image sensor according to an exemplary embodiment of the inventive concept;

[0015] Figure 4 It is along Figure 3 A cross-sectional view of an image sensor according to an exemplary embodiment of the inventive concept, taken along line BB′;

[0016] Figure 5 It is along Figure 3 A cross-sectional view of an image sensor according to an exemplary embodiment of the inventive concept, taken along line BB′;

[0017] Figure 6 is a plan view of a first structure included in an image sensor according to an exemplary embodiment of the inventive concept;

[0018] Figure 7 It is along Figure 6 A cross-sectional view of an image sensor according to an exemplary embodiment of the inventive concept, taken along line BB′;

[0019] Figure 8 is a circuit diagram of a shared pixel circuit included in an image sensor according to an exemplary embodiment of the inventive concept;

[0020] Fig. 9 is a plan view of a first structure included in an image sensor according to an exemplary embodiment of the inventive concept;

[0021] Fig.10 It is along Fig. 9 A cross-sectional view of an image sensor according to an exemplary embodiment of the inventive concept, taken along line BB′;

[0022] Fig.11 is a circuit diagram of a shared pixel circuit included in an image sensor according to an exemplary embodiment of the inventive concept; and

[0023] Fig.12 is a plan view of a first structure included in an image sensor according to an exemplary embodiment of the inventive concept. DETAILED DESCRIPTION

[0024] In this specification, the Z direction shown in the drawings may be referred to as a vertical direction, and any direction perpendicular to the Z direction, for example, the X direction or the Y direction, may be referred to as a horizontal direction. In addition, in a plan view, objects that overlap each other in the Z direction may be referred to as overlapping each other. In an exemplary embodiment, the X direction is substantially perpendicular to the Y direction or completely perpendicular to the Y direction.

[0025] In this specification, the overlap of the first object and the second object in the Z direction means that the projection of the first object on a plane perpendicular to the Z direction (eg, XY plane) overlaps with the projection of the second object on the same plane.

[0026] In this specification, two values ​​described as being substantially the same means that the difference between the two values ​​is within the difference between the two values ​​that is designed or intended to be the same, but that may occur due to errors in the manufacturing process. For example, two values ​​being substantially the same means that the difference between the two values ​​is within 10% of each of the two values, such as within 5%. When used herein, two values ​​being substantially different means that the difference between the two values ​​is greater than the difference between the two values ​​that is designed or intended to be the same, but that may occur due to errors in the manufacturing process. For example, two values ​​being substantially different means that the difference between the two values ​​is greater than 10%.

[0027] In this specification, the distance between the first object and the second object may be defined as the distance between the center of the first object and the center of the second object.

[0028] Hereinafter, exemplary embodiments of the inventive concept will be described in detail with reference to the accompanying drawings.Throughout the application, like reference numerals refer to like elements.

[0029] Figure 1 is a block diagram of an image sensor 1000 according to an exemplary embodiment of the inventive concept.

[0030] refer to Figure 1 , the image sensor 1000 includes a control register block 1100 (e.g., a control circuit), a timing generator 1200 (e.g., a timing controller or a control circuit), a ramp generator 1300 (e.g., a voltage generator), a buffer unit 1400 (e.g., a buffer or a buffer circuit), an active pixel sensor array 1500, a row driver 1600 (e.g., a driver circuit), a correlated double sampler 1700, a comparator 1800 (e.g., a comparison circuit), and an analog-to-digital converter 1900.

[0031] The control register block 1100 may generally control the operation of the image sensor 1000. For example, the control register block 1100 may send an operation signal to the timing generator 1200, the ramp generator 1300, and the buffer unit 1400. The timing generator 1200 may generate an operation timing reference signal and send the operation timing reference signal to the row driver 1600, the correlated double sampler 1700, the comparator 1800, and / or the analog-to-digital converter 1900. The ramp generator 1300 may generate a ramp signal (or a ramp voltage) and send the ramp signal (or a ramp voltage) to the correlated double sampler 1700 and / or the comparator 1800. The buffer unit 1400 may temporarily store an image signal to be sent to the outside of the image sensor 1000, and send the image data to an external device. The active pixel sensor array 1500 may sense an external image. The active pixel sensor array 1500 may include a plurality of pixels (e.g., Figure 2 The pixel P shown Figure 8 The shared pixel 2SP shown or Fig.11 The shared pixel 4SP shown in FIG. 4A ). The row driver 1600 can selectively activate the rows of the active pixel sensor array 1500. The correlated double sampler 1700 can sample and output the analog signal generated from the active pixel sensor array 1500. The comparator 1800 can generate various reference signals by comparing the data sent from the correlated double sampler 1700 and the slope of the ramp signal fed back according to the analog reference voltage. The analog-to-digital converter 1900 can convert the analog image data into digital image data.

[0032] The active pixel sensor array 1500 may be located at Figure 4 The first structure 100 (e.g., pixel wafer) is shown in or on the pixel array area PXA of the first substrate 110. In addition, each of the control register block 1100, the timing generator 1200, the ramp generator 1300, the buffer unit 1400, the row driver 1600, the correlated double sampler 1700, the comparator 1800, and the analog-to-digital converter 1900 may be located Figure 4 The first structure 100 is shown on a peripheral region PR of a first substrate 110 or on a second substrate 210 of a second structure 200 (eg, a logic wafer).

[0033] Figure 2 is a circuit diagram of a pixel circuit P included in an image sensor according to an exemplary embodiment of the inventive concept.

[0034] refer to Figure 2 , each pixel circuit P may include a photoelectric conversion unit PD (eg, a photodiode), a floating diffusion region FD, and a plurality of transistors (such as a transfer transistor TX, a drive transistor DX, a selection transistor SX, and a reset transistor RX).

[0035] The photoelectric conversion unit PD can absorb light to generate and accumulate charges corresponding to the amount or intensity of the light. The transfer transistor TX may include a transfer gate TG. The transfer gate TG may transfer the charges accumulated in the photoelectric conversion unit PD to the floating diffusion region FD. The floating diffusion region FD may gradually accumulate the charges received from the photoelectric conversion unit PD. The drive transistor DX may be controlled according to the amount of charge accumulated in the floating diffusion region FD. In some embodiments, the pixel circuit P does not include a transfer gate TG. That is, the photoelectric conversion unit PD of the pixel circuit P may be directly connected to the floating diffusion region FD.

[0036] The source of the drive transistor DX may be connected to the power supply voltage VDD, and the drain of the drive transistor DX may be connected to the source of the selection transistor SX. The drive transistor DX may function as a source follower buffer amplifier that generates a source-drain current in proportion to the charge input to the gate. The drive transistor DX may amplify a potential change in the floating diffusion region FD and transmit the amplified signal to the selection transistor SX.

[0037] The select transistor SX may include a select gate SG and may be driven by a slave row driver (eg, Figure 1 Specifically, the selection transistor SX can output the signal output to the drain of the driving transistor DX to the output line Vout according to the row selection signal.

[0038] The reset transistor RX may reset the charge accumulated in the floating diffusion region FD. For example, the reset transistor RX may include a reset gate RG, a drain of the reset transistor RX may be connected to the floating diffusion region FD, and a source of the reset transistor RX may be connected to a power supply voltage VDD. The reset transistor RX may be controlled by a reset signal. Specifically, the reset transistor RX may transfer the power supply voltage VDD connected to the source of the reset transistor RX to the floating diffusion region FD according to the reset signal. Therefore, the charge accumulated in the floating diffusion region FD may be released by the reset transistor RX, and therefore, the floating diffusion region FD may be reset.

[0039] Figure 3 is a plan view of a first structure 100 included in an image sensor 1000 according to an exemplary embodiment of the inventive concept. Figure 4 It is along Figure 3 BB′ is a cross-sectional view of the image sensor 1000 according to an exemplary embodiment of the inventive concept.

[0040] refer to Figure 3 and Figure 4, the image sensor 1000 includes a first structure 100 and a second structure 200. The first structure 100 includes a first substrate 110, a plurality of photoelectric conversion units PD in the first substrate 110, a first connection layer 150 disposed on the first substrate 110, and a plurality of first pixel pads 130 disposed on the first connection layer 150. The second structure 200 includes a second substrate 210, a device 220 disposed on the second substrate 210, a second connection layer 250 disposed on the second substrate 210 and the device 220, and a plurality of second pixel pads 230 disposed on the second connection layer 250. In an exemplary embodiment, since the plurality of first pixel pads 130 respectively contact the plurality of second pixel pads 230, the first structure 100 is in contact with the second structure 200 (e.g., in direct contact). The first structure 100 and the second structure 200 may be combined by direct bonding between the first pixel pads 130 and the second pixel pads 230.

[0041] In an exemplary embodiment, the first structure 100 further includes a plurality of first peripheral pads 140 disposed on the first connection layer 150, and the second structure 200 further includes a plurality of second peripheral pads 240 disposed on the second connection layer 250. In an exemplary embodiment, the plurality of first peripheral pads 140 respectively contact (e.g., directly contact) the plurality of second peripheral pads 240. The first structure 100 and the second structure 200 may be combined by direct bonding between the first pixel pad 130 and the second pixel pad 230 and between the first peripheral pad 140 and the second peripheral pad 240.

[0042] That is, the image sensor 1000 may include a first substrate 110, a plurality of photoelectric conversion units PD in the first substrate 110, a first connection layer 150 arranged on the first substrate 110, a plurality of first pixel pads 130 and a plurality of first peripheral pads 140 arranged on the first connection layer 150, a plurality of second pixel pads 230 respectively located on the plurality of first pixel pads 130, a plurality of second peripheral pads 240 respectively located on the plurality of first peripheral pads 140, a second connection layer 250 arranged on the plurality of second pixel pads 230 and the plurality of second peripheral pads 240, a device 220 arranged on the second connection layer 250, and a second substrate 210 arranged on the second connection layer 250 and the device 220.

[0043] The first substrate 110 includes a pixel array area PXA, which includes a plurality of pixel areas PX. The plurality of pixel areas PX may be arranged at a constant pitch in the X direction and the Y direction. For example, the pixel areas PX may be equally spaced from each other throughout the pixel array area PXA. In an exemplary embodiment, the spacing DX3 of the plurality of pixel areas PX in the X direction is the same as the length of each pixel area PX in the X direction, and the spacing DY3 of the plurality of pixel areas PX in the Y direction is the same as the length of each pixel area PX in the Y direction. In an exemplary embodiment, the spacing DX3 of the plurality of pixel areas PX in the X direction is the same as the spacing DY3 of the plurality of pixel areas PX. In an exemplary embodiment, the spacing DX3 of the plurality of pixel areas PX in the X direction and the spacing DY3 of the plurality of pixel areas PX in the Y direction are about 0.5 μm to about 5 μm. In some embodiments, the first substrate 110 further includes a peripheral area PR around the pixel array area PXA. In an exemplary embodiment, the peripheral area PR of the first substrate 110 surrounds the pixel array area PXA of the first substrate 110. The second substrate 210 may be spaced apart from the first substrate 110 in the Z direction. An upper surface of the second substrate 210 faces a lower surface of the first substrate 110 .

[0044] The first substrate 110 and the second substrate 210 may include, for example, a group IV semiconductor material, a group III-V semiconductor material, a group II-VI semiconductor material, or a combination thereof. The group IV semiconductor material may include, for example, silicon (Si), germanium (Ge), or a combination thereof. The group III-V semiconductor material may include, for example, gallium arsenide (GaAs), indium phosphide (InP), gallium phosphide (GaP), indium arsenide (InAs), indium antimonide (InSb), or a combination thereof. The group II-VI semiconductor material may include, for example, zinc telluride (ZnTe), cadmium sulfide (CdS), or a combination thereof.

[0045] In an exemplary embodiment, a plurality of photoelectric conversion units PD are respectively located in a plurality of pixel regions PX of the first substrate 110. The photoelectric conversion units PD may include, for example, photodiodes, phototransistors, photogates, or a combination thereof. In an embodiment, the photodiode includes two impurity regions having different conductivity types.

[0046] The photoelectric conversion unit PD may be included in the pixel circuit P. The transfer gate TG and the floating diffusion region FD included in the pixel circuit P may be located on the pixel region PX of the first substrate 110. Figure 4, the transfer gate TG is omitted. In some embodiments, the floating diffusion region FD may be separated from the photoelectric conversion unit PD by an isolation pattern (not shown). In an exemplary embodiment, the floating diffusion region FD includes impurities of a conductive type different from that of the first substrate 110. The driving transistor DX (see Figure 2 ), select transistor SX (see Figure 2 ) and reset transistor RX (see Figure 2 ) may be located in the pixel region PX of the first substrate 110. The pixel circuit P may further include a transistor connected to the photoelectric conversion unit PD, a transfer gate TG, a floating diffusion region FD, a driving transistor DX (see Figure 2 ), select transistor SX (see Figure 2 ) and reset transistor (RX (see Figure 2 ))a portion of the first conductive pattern 152 of at least one of the first connection layers 150.

[0047] In an exemplary embodiment, the first structure 100 further includes a pixel separation pattern 160 disposed between the plurality of photoelectric conversion units PD. The pixel separation pattern 160 may be located at a boundary between the plurality of pixel regions PX of the first substrate 110. The pixel separation pattern 160 may surround each photoelectric conversion unit PD. The pixel separation pattern 160 may include an insulating material, which may include, for example, silicon oxide, silicon nitride, or a combination thereof.

[0048] In an exemplary embodiment, the first structure 100 further includes a peripheral device 120 disposed on the peripheral region PR of the first substrate 110. The peripheral device 120 may include, for example, a transistor, a capacitor, a resistor, or a combination thereof. The peripheral device 120 and a portion of the first conductive pattern 152 of the first connection layer 150 connected to the peripheral device 120 may constitute a peripheral circuit. The peripheral circuit may include a logic circuit, a memory circuit, or a combination thereof. The peripheral circuit may include, for example Figure 1 At least one of the control register block 1100 , the timing generator 1200 , the ramp generator 1300 , the buffer unit 1400 , the row driver 1600 , the correlated double sampler 1700 , the comparator 1800 , and the analog-to-digital converter 1900 is shown.

[0049] The device 220 disposed on the second substrate 210 may overlap the pixel array area PXA of the first substrate 110 in the Z direction, overlap the peripheral area PR of the first substrate 110 in the Z direction, or overlap the pixel array area PXA and the peripheral area PR of the first substrate 110 in the Z direction. The device 220 may include, for example, a transistor, a capacitor, a resistor, or a combination thereof. The device 220 and a portion of the second conductive pattern 252 of the second connection layer 250 connected to the device 220 may constitute a circuit. The circuit may include a logic circuit, a memory circuit, or a combination thereof. The circuit may include, for example, Figure 1 At least one of the control register block 1100, the timing generator 1200, the ramp generator 1300, the buffer unit 1400, the row driver 1600, the correlated double sampler 1700, the comparator 1800, and the analog-to-digital converter 1900 is shown. For example, the circuit may include part or all of a circuit for controlling a pixel circuit (e.g., P, 2SP, 4SP) or a photoelectric conversion unit (e.g., PD, PDa, Pdb, Pdc, or Pdd).

[0050] The first connection layer 150 may be located on the lower surface of the first substrate 110, and the second connection layer 250 may be located on the upper surface of the second substrate 210. In an exemplary embodiment, the first connection layer 150 includes a first insulating layer 151 disposed on the lower surface of the first substrate 110 and a first conductive pattern 152 disposed in the first insulating layer 151. In an exemplary embodiment, the second connection layer 250 includes a second insulating layer 251 disposed on the upper surface of the second substrate 210 and a second conductive pattern 252 disposed in the second insulating layer 251. Each of the first insulating layer 151 and the second insulating layer 251 may include a plurality of insulating layers. Each of the first conductive pattern 152 and the second conductive pattern 252 may include a plurality of conductive lines (e.g., wires) and a plurality of conductive vias.

[0051] The first insulating layer 151 and the second insulating layer 251 may include an insulating material, which may include, for example, silicon oxide, silicon nitride, a low-k material, or a combination thereof. The low-k material may be a material having a lower dielectric constant than silicon oxide, for example, phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), fluorosilicate glass (FSG), organic silicon glass (OSG), spin-on glass (SOG), spin-on polymer, or a combination thereof. The first conductive pattern 152 and the second conductive pattern 252 may include a conductive material, which may include, for example, tungsten (W), copper (Cu), aluminum (Al), gold (Au), silver (Ag), or a combination thereof.

[0052] In an exemplary embodiment, the material constituting the first insulating layer 151 and the second insulating layer 251 has a higher transmittance with respect to light of an operating wavelength range, such as a visible spectrum, an IR spectrum, or a UV spectrum, than the material constituting the first conductive pattern 152 and the second conductive pattern 252. In an exemplary embodiment, the material constituting the first conductive pattern 152 and the second conductive pattern 252 has a higher reflectivity with respect to light of an operating wavelength range than the material constituting the first conductive layer 151 and the second conductive layer 251.

[0053] The first connection layer 150 may electrically connect a plurality of pixel circuits P, a peripheral device 120, and a plurality of first peripheral pads 140. That is, the first conductive pattern 152 of the first connection layer 150 may contact a plurality of pixel circuits P, a peripheral device 120, and a plurality of first peripheral pads 140. The first conductive pattern 152 of the first connection layer 150 may include a portion (e.g., a first line) connecting a plurality of pixels P to the peripheral device 120 and a portion (e.g., a second line) connecting the peripheral device 120 to the plurality of first peripheral pads 140. In an exemplary embodiment, the first conductive pattern 152 of the first connection layer 150 does not contact at least one of the plurality of first pixel pads 130. In another exemplary embodiment, the first conductive pattern 152 of the first connection layer 150 does not contact all of the plurality of first pixel pads 130. That is, the first connection layer 150 does not electrically connect the plurality of pixel circuits P to the plurality of first pixel pads 130. In other words, the plurality of first pixel pads 130 may be dummy pads that do not provide electrical connection.

[0054] The second connection layer 250 may electrically connect the device 220 to the plurality of second peripheral pads 240. That is, the second conductive pattern 252 of the second connection layer 250 may contact the device 220 and the plurality of second peripheral pads 240. In an exemplary embodiment, the second conductive pattern 252 of the second connection layer 250 does not contact at least one of the plurality of second pixel pads 230. In another exemplary embodiment, the second conductive pattern 252 of the second connection layer 250 does not contact all of the plurality of second pixel pads 230. That is, the second connection layer 250 does not electrically connect the device 220 to the plurality of second pixel pads 230. In other words, the plurality of second pixel pads 230 may be dummy pads that do not provide electrical connection.

[0055] A plurality of first pixel pads 130 may be located on a portion of the first connection layer 150 on the pixel array area PXA of the first substrate 110. That is, the plurality of first pixel pads 130 may overlap the pixel array area PXA of the first substrate 110 in the Z direction. In an exemplary embodiment, the first pixel pads 130 are positioned so that they do not overlap the photoelectric conversion unit PD in the Z direction. A plurality of second pixel pads 230 may be located on the plurality of first pixel pads 130, respectively, to contact the plurality of first pixel pads 130, respectively. The plurality of first pixel pads 130 and the plurality of second pixel pads 230 may be used to directly combine the first structure 100 and the second structure 200.

[0056] In an exemplary embodiment, each first pixel pad 130 includes a filling layer 131 and a barrier layer 132 between the filling layer 131 and the first connection layer 150. In an exemplary embodiment, each second pixel pad 230 includes a filling layer 231 and a barrier layer 232 between the filling layer 231 and the second connection layer 250. The filling layer 131 of the first pixel pad 130 and the filling layer 231 of the second pixel pad 230 can be used for direct bonding. In an exemplary embodiment, the filling layers 131 and 231 include a material with high reflectivity. For example, the filling layers 131 and 231 corresponding to the pixel area PX can reflect light toward the photoelectric conversion unit PD in the same pixel area PX. For example, the filling layer 131 of the first pixel pad 130 and the filling layer 231 of the second pixel pad 230 may include copper (Cu), aluminum (Al), or a combination thereof. The barrier layer 132 of the first pixel pad 130 and the barrier layer 232 of the second pixel pad 230 can prevent the material of the filling layer 131 of the first pixel pad 130 and the filling layer 231 of the second pixel pad 230 from diffusing to the first insulating layer 151 of the first connection layer 150 and the second insulating layer 251 of the second connection layer 250, respectively. In an exemplary embodiment, the barrier layers 132 and 232 include a material having a high reflectivity. For example, the barrier layers 132 and 232 corresponding to the pixel region PX can reflect light toward the photoelectric conversion unit PD in the same pixel region PX. For example, the barrier layer 132 of the first pixel pad 130 and the barrier layer 232 of the second pixel pad 230 may include titanium (Ti), tantalum (Ta), tin (Sn) and copper (Cu), aluminum (Al), gold (Au), silver (Ag) or a combination thereof.

[0057] In an exemplary embodiment, a plurality of first pixel pads 130 are provided to alleviate the bonding stress that may occur when the first structure 100 is bonded to the second structure 200 due to the difference in thermal expansion coefficients between various materials. In an exemplary embodiment, the center C130 of the plurality of first pixel pads 130 does not overlap with the pixel separation pattern 160 in the Z direction. The positioning of the center C130 so as not to overlap with the pixel separation pattern 160 can alleviate the bonding stress. In an exemplary embodiment, the plurality of first pixel pads 130 do not overlap with the pixel separation pattern 160 in the Z direction. The positioning of the first pixel pad 130 so as not to overlap with the pixel separation pattern 160 can alleviate the bonding stress. In another exemplary embodiment, the plurality of first pixel pads 130 do not overlap with the boundaries between the plurality of pixel regions PX of the first substrate 110 in the Z direction. That is, any first pixel pad 130 may not be distributed on two or more adjacent pixel regions PX of the first substrate 110. In an exemplary embodiment, none of the first pixel pads 130 extends to overlap with a pair of adjacent pixel regions PX.

[0058] In an exemplary embodiment, a plurality of first pixel pads 130 are arranged in the X direction at a pitch DX1 substantially the same as a pitch DX3 of a plurality of pixel regions PX in the X direction. In an exemplary embodiment, a plurality of first pixel pads 130 are arranged in the Y direction at a pitch DY1 substantially the same as a pitch DY3 of a plurality of pixel regions PX in the Y direction. Therefore, a plurality of first pixel pads 130 may overlap with a plurality of pixel regions PX of the first substrate 110 in a vertical direction, respectively. By arranging a plurality of first pixel pads 130 as described above, when the first structure 100 is planarized using chemical mechanical polishing (CMP), not only can bonding stress be alleviated, but also a planar surface can be obtained.

[0059] In an exemplary embodiment in which the pitch DX1 of the plurality of first pixel pads 130 in the X direction is substantially the same as the pitch DX3 of the plurality of pixel regions PX of the first substrate 110 in the X direction, a width DX7 of each of the first pixel pads 130 and the second pixel pads 230 in the X direction is greater than 0 and is less than or equal to half of the pitch DX3 of the plurality of pixel regions PX of the first substrate 110 in the X direction. Similarly, in an exemplary embodiment in which the pitch DY1 of the plurality of first pixel pads 130 in the Y direction is substantially the same as the pitch DY3 of the plurality of pixel regions PX of the first substrate 110 in the Y direction, a width DY7 of each of the first pixel pads 130 and the second pixel pads 230 in the Y direction is greater than 0 and is less than or equal to half of the pitch DY3 of the plurality of pixel regions PX of the first substrate 110 in the Y direction. As a result, when the first structure 100 and the second structure 200 are combined together, even when the first structure 100 and the second structure 200 are not aligned, one first pixel pad 130 may be prevented from contacting two second pixel pads 230 or one second pixel pad 230 may be prevented from contacting two first pixel pads 130. For example, the width DX7 and the width DY7 of the first pixel pad 130 and the second pixel pad 230 in the X direction and the Y direction, respectively, may be about 0.1 μm to about 2.5 μm. In the case where the width DX7 and the width DY7 of the first pixel pad 130 and the second pixel pad 230 in the X direction and the Y direction, respectively, are too small, when the first structure 100 and the second structure 200 are combined together, it may be difficult to align the plurality of first pixel pads 130 with the plurality of second pixel pads 230, respectively.

[0060] In an exemplary embodiment, a plurality of first pixel pads 130 are arranged to reflect light that is not absorbed by a plurality of photoelectric conversion units PD and is emitted from a plurality of photoelectric conversion units PD through the first connection layer 150. For example, the first pixel pads 130 may reflect the unabsorbed light back at the photoelectric conversion units PD so that they absorb more light. To this end, a plurality of first pixel pads 130 may be arranged on a portion of the first connection layer 150 having a high transmittance. For example, a portion of the first connection layer 150 on the pixel region PX of the first substrate 110 includes an overlapping portion 150a that overlaps with the first pixel pad 130 in the Z direction and a non-overlapping portion 150b that does not overlap with the first pixel pad 130 in the Z direction. In an exemplary embodiment, the transmittance of the overlapping portion 150a of the first connection layer 150 is higher than the transmittance of the non-overlapping portion 150b of the first connection layer 150.

[0061] In other words, in view of the fact that the first insulating layer 151 of the first connection layer 150 includes a material having a high transmittance and the first conductive pattern 152 includes a material having a high reflectance, the plurality of first pixel pads 130 may be arranged on a portion of the first connection layer 150 where the volume ratio of the first conductive pattern 152 relative to the first insulating layer 151 is small. For example, a ratio of the total volume of the portion of the first conductive pattern 152 in the overlapping portion 150a of the first connection layer 150 relative to the total volume of the portion of the first insulating layer 151 in the overlapping portion 150a of the first connection layer 150 may be smaller than a ratio of the total volume of the portion of the first conductive pattern 152 in the non-overlapping portion 150b of the first connection layer 150 relative to the total volume of the portion of the first insulating layer 151 in the non-overlapping portion 150b of the first connection layer 150.

[0062] Here, the total volume of the portion of the first insulating layer 151 in the overlapping portion 150a of the first connection layer 150 may be, for example, the sum of the volume of the portion of the first insulating layer 151 in the overlapping portion 150a of the portion of the first connection layer 150 located on one pixel region and the volume of the portion of the first insulating layer 151 in the overlapping portion 150a of the other portion of the first connection layer 150 located on the other pixel region when the pixel array region PXA includes two pixel regions PX. That is, the volume ratio of the first conductive pattern 152 to the first insulating layer 151 in any one overlapping portion 150a may be the same as the volume ratio of the first conductive pattern 152 to the first insulating layer 151 in any one non-overlapping portion 150b, but the volume ratio of the first conductive pattern 152 to the first insulating layer 151 distributed on all overlapping portions 150a in the first connection layer 150 may be smaller than the volume ratio of the first conductive pattern 152 to the first insulating layer 151 on all non-overlapping portions 150b in the first connection layer 150. By arranging a plurality of first pixel pads 130 as described above, the amount of light leaking through a relatively low density region (eg, overlapping portion 150 a ) of the first conductive pattern 152 may be reduced, and thus, the sensitivity of the image sensor 1000 may be improved and crosstalk may be reduced.

[0063] As a result of arranging the plurality of first pixel pads 130 to reduce leakage of light, according to an exemplary embodiment, the center C130 of the first pixel pad 130 exceeds the center CPX of the pixel region PX of the first substrate 110 in the horizontal direction. That is, the center C130 of the first pixel pad 130 does not overlap with the center CPX of the pixel region PX of the first substrate 110 in the Z direction. In addition, in an embodiment in which the spacing DX1 of the plurality of first pixel pads 130 in the X direction is substantially the same as the spacing DX3 of the plurality of pixel regions PX of the first substrate 110 in the X direction and / or the spacing DY1 of the plurality of first pixel pads 130 in the Y direction is substantially the same as the spacing DY3 of the plurality of pixel regions PX of the first substrate 110 in the Y direction, the center C130 of each first pixel pad 130 is located at a distance (e.g., DX6) from the center CPX of each pixel region PX of the first substrate 110 in the horizontal direction (e.g., in the X direction). Figure 3 and Figure 4 , the center C130 of the first pixel pad 130 and the center CPX of the pixel region PX are separated in the X direction, but the center C130 of the first pixel pad 130 and the center CPX of the pixel region PX may be separated in any horizontal direction (including the Y direction).

[0064] The plurality of first peripheral pads 140 may be arranged on a portion of the first connection layer 150 on the peripheral region PR of the first substrate 110. That is, the plurality of first peripheral pads 140 may overlap the peripheral region PR of the first substrate 110 in the Z direction. The plurality of second peripheral pads 240 may be respectively located on the plurality of first peripheral pads 140, and may respectively contact the plurality of first peripheral pads 140. The plurality of first peripheral pads 140 and the plurality of second peripheral pads 240 may be used for direct bonding of the first structure 100 and the second structure 200, and may be electrically connected between the first connection layer 150 and the second connection layer 250 (i.e., between the first structure 100 and the second structure 200).

[0065] In an exemplary embodiment, each first peripheral pad 140 includes a filling layer 141 and a barrier layer 142 between the filling layer 141 and the first connection layer 150. In an exemplary embodiment, each second peripheral pad 240 includes a filling layer 241 and a barrier layer 242 between the filling layer 241 and the second connection layer 250. The filling layer 141 of the first peripheral pad 140 and the filling layer 241 of the second peripheral pad 240 can be used for direct bonding. In an exemplary embodiment, the filling layers 141 and 241 include a conductive material. For example, the filling layer 141 of the first peripheral pad 140 and the filling layer 241 of the second peripheral pad 240 may include copper (Cu), aluminum (Al), or a combination thereof. The barrier layer 142 of the first peripheral pad 140 and the barrier layer 242 of the second peripheral pad 240 may include a material that can prevent the filling layer 141 of the first peripheral pad 140 and the filling layer 241 of the second peripheral pad 240 from diffusing into the first insulating layer 151 of the first connection layer 150 and the second insulating layer 251 of the second connection layer 250, respectively. For example, the barrier layer 142 of the first peripheral pad 140 and the barrier layer 242 of the second peripheral pad 240 may include titanium (Ti), tantalum (Ta), tin (Sn), copper (Cu), aluminum (Al), gold (Au), silver (Ag), or a combination thereof.

[0066] In an exemplary embodiment, the plurality of first peripheral pads 140 are arranged to relieve bonding stress. For example, the spacing DX2 of the plurality of first peripheral pads 140 in the X direction may be substantially the same as the spacing DX1 of the plurality of first pixel pads 130 in the X direction. Similarly, the spacing DY2 of the plurality of first peripheral pads 140 in the Y direction may be substantially the same as the spacing DY1 of the plurality of first pixel pads 130 in the Y direction. Therefore, in an embodiment in which the spacing DX1 of the plurality of first pixel pads 130 in the X direction is the same as the spacing DX3 of the plurality of pixel regions PX of the first substrate 110 in the X direction, the spacing DX2 of the plurality of first peripheral pads 140 in the X direction may be substantially the same as the spacing DX3 of the plurality of pixel regions PX of the first substrate 110 in the X direction. Similarly, in an embodiment where the pitch DY1 of the plurality of first pixel pads 130 in the Y direction is the same as the pitch DY3 of the plurality of pixel regions PX of the first substrate 110 in the Y direction, the pitch DY2 of the plurality of first peripheral pads 140 in the Y direction may be substantially the same as the pitch DY3 of the plurality of pixel regions PX of the first substrate 110 in the Y direction. By arranging the plurality of first peripheral pads 140 as described above, when the first structure 100 is planarized using CMP, not only can bonding stress be alleviated, but also a planar surface can be obtained.

[0067] In an exemplary embodiment of the present inventive concept, the image sensor 1000 further includes a plurality of microlenses 380 disposed on the upper surface of the first substrate 110. The plurality of microlenses 380 may respectively overlap the plurality of photoelectric conversion units PD in the Z direction. The microlenses 380 may collect or focus light into the photoelectric conversion units PD.

[0068] In an exemplary embodiment, the image sensor 1000 further includes a plurality of color filters 370 disposed on the upper surface of the first substrate 110. When the image sensor 1000 includes a plurality of microlenses 380, the plurality of color filters 370 may be positioned between the first substrate 110 and the plurality of microlenses 380, respectively. The plurality of color filters 370 may be arranged on the plurality of photoelectric conversion units PD, respectively. The color filters 370 may allow light having a specific wavelength to pass through so that the light having the specific wavelength reaches the photoelectric conversion unit PD. The plurality of color filters 370 may form, for example, a color filter array including a red filter, a green filter, and a blue filter. However, the color filters 370 may also include a yellow filter, a magenta filter, a cyan filter, and / or a white filter.

[0069] The image sensor 1000 according to an exemplary embodiment of the inventive concept includes a plurality of first pixel pads 130 and a plurality of second pixel pads 230. The plurality of first pixel pads 130 and the plurality of second pixel pads 230 may be used for direct bonding of the first structure 100 and the second structure 200. By properly arranging the plurality of first pixel pads 130 and the plurality of second pixel pads 230, bonding stress that may occur when bonding the first structure 100 to the second structure 200 due to differences in thermal expansion coefficients between various materials may be alleviated. Additionally or alternatively, by properly arranging the plurality of first pixel pads 130 and the plurality of second pixel pads 230, light that is not absorbed by the photoelectric conversion unit PD and is emitted from the photoelectric conversion unit PD through the first connection layer 150 may be reflected, and thus, leakage of light may be reduced. Therefore, the sensitivity of the image sensor 1000 may be improved and crosstalk may be reduced.

[0070] Figure 5 It is along Figure 3 A cross-sectional view of an image sensor 1000b according to an exemplary embodiment of the inventive concept taken along line BB′ is shown. Figure 4 The image sensor 1000 shown in FIG. Figure 5 The differences between the image sensor 1000b shown in FIG.

[0071] refer to Figure 5, the first conductive pattern 152 of the first connection layer 150 contacts at least one of the plurality of first pixel pads 130. In another exemplary embodiment, the first conductive pattern 152 of the first connection layer 150 contacts all of the plurality of first pixel pads 130. In other words, the plurality of first pixel pads 130 are not dummy pads. In some embodiments, the first connection layer 150 may electrically connect the peripheral device 120 to the plurality of first pixel pads 130. That is, the first conductive pattern 152 of the first connection layer 150 may also include a portion that electrically connects the peripheral device 120 to the plurality of first pixel pads 130. In an exemplary embodiment, the first connection layer 150 electrically connects the plurality of pixel circuits P to the plurality of first pixel pads 130, respectively. That is, the first conductive pattern 152 of the first connection layer 150 may also include a portion that electrically connects the plurality of pixel circuits P to the plurality of first pixel pads 130, respectively.

[0072] In an exemplary embodiment, the second conductive pattern 252 of the second connection layer 250 contacts at least one of the plurality of second pixel pads 230. In another exemplary embodiment, the second connection layer 250 contacts all of the plurality of second pixel pads 230. In other words, the plurality of second pixel pads 230 are not dummy pads. In an exemplary embodiment, the second connection layer 250 electrically connects the device 220 to the plurality of second pixel pads 230. That is, the second conductive pattern 252 of the second connection layer 250 may also include a portion that electrically connects the device 220 to the plurality of second pixel pads 230.

[0073] In an exemplary embodiment, the second structure 200b further includes a plurality of pixel devices 260 disposed on the second substrate 210. The plurality of pixel devices 260 may include, for example, capacitors, resistors, transistors, or a combination thereof. The pixel devices 260 may overlap the pixel array area PXA of the first substrate 110 in the Z direction.

[0074] In an exemplary embodiment, the second connection layer 250 connects the plurality of pixel devices 260 to the device 220. That is, the second conductive pattern 252 of the second connection layer 250 may also include a portion connecting the plurality of pixel devices 260 to the device 220. In an exemplary embodiment, the second connection layer 250 electrically connects the plurality of pixel devices 260 to the plurality of second pixel pads 230, respectively. That is, the second conductive pattern 252 of the second connection layer 250 may also include a portion electrically connecting the plurality of pixel devices 260 to the plurality of second pixel pads 230, respectively.

[0075] Figure 6 is a plan view of a first structure 100 c included in an image sensor 1000 c according to an exemplary embodiment of the inventive concept. Figure 7 It is along Figure 6A cross-sectional view of an image sensor 1000c according to an embodiment of the inventive concept taken along line BB′. Figure 3 and Figure 4 The image sensor 1000 shown in FIG. Figure 6 and Figure 7 The differences between the image sensor 1000c shown in FIG.

[0076] refer to Figure 6 and Figure 7 In an exemplary embodiment, the spacing DX1 of the plurality of first pixel pads 130 in the X direction is substantially equal to twice the spacing DX3 of the plurality of pixel regions PX of the first substrate 110 in the X direction. In an exemplary embodiment, the spacing DX1 of the plurality of first pixel pads 130 in the X direction is substantially the same as a value obtained by multiplying the spacing DX3 of the plurality of pixel regions PX of the first substrate 110 in the X direction by a natural number. The natural number may be any natural number of 1 or greater, such as 1, 2, 3, 4, etc. Similarly, in an exemplary embodiment, the spacing DY1 of the plurality of first pixel pads 130 in the Y direction is substantially the same as a value obtained by multiplying the spacing DY3 of the plurality of pixel regions PX of the first substrate 110 in the Y direction by an arbitrary natural number (e.g., 2). By arranging the plurality of first pixel pads 130 as described above, when the first structure 100c is planarized using CMP, not only can the bonding stress be relieved, but also a planar surface can be obtained.

[0077] In an exemplary embodiment, the pitch DX2 of the plurality of first peripheral pads 140 in the X direction is substantially the same as a value obtained by multiplying the pitch DX3 of the plurality of pixel regions PX of the first substrate 110 in the X direction by an arbitrary natural number (e.g., 2). In an exemplary embodiment, the pitch DY2 of the plurality of first peripheral pads 140 in the Y direction is substantially the same as a value obtained by multiplying the pitch DX3 of the plurality of pixel regions PX of the first substrate 110 in the Y direction by an arbitrary natural number (e.g., 2). By arranging the plurality of first peripheral pads 140 as described above, when the first structure 100c is planarized using CMP, not only can bonding stress be alleviated, but also a planar surface can be obtained.

[0078] Figure 8 yes Fig.10 , a circuit diagram of a shared pixel circuit 2SP included in an image sensor 1000d according to an exemplary embodiment of the inventive concept is shown in FIG. Figure 2 The pixel circuit P shown in FIG. Figure 8 The difference between the shared pixel circuit 2SP shown in .

[0079] refer to Figure 8 The shared pixel circuit 2SP includes a shared floating diffusion region FD (see Figure 2 ) of two pixel circuits P (see Figure 2 ). Specifically, the shared pixel circuit 2SP includes a first photoelectric conversion unit PDa, a second photoelectric conversion unit PDb, a first transfer transistor TXa, a second transfer transistor TXb, a shared floating diffusion region 2SFD, a drive transistor DX, a selection transistor SX, and a reset transistor RX. The first transfer transistor TXa may include a first transfer gate TGa, and the second transfer transistor TXb may include a second transfer gate TGb. The first transfer gate TGa may transfer the charge accumulated in the first photoelectric conversion unit PDa to the shared floating diffusion region 2SFD, and the second transfer gate TGb may transfer the charge accumulated in the second photoelectric conversion unit PDb to the shared floating diffusion region 2SFD. The drive transistor DX, the selection transistor SX, and the reset transistor RX may be connected to the shared floating diffusion region 2SFD.

[0080] Fig. 9 is a plan view of a first structure 100d included in an image sensor 1000d according to an exemplary embodiment of the inventive concept. Fig.10 It is along Fig. 9 A cross-sectional view of an image sensor 1000d according to an exemplary embodiment of the inventive concept taken along line BB′. Figure 3 and Figure 4 The image sensor 1000 shown in FIG. Fig. 9 and Fig.10 The differences between the image sensor 1000d shown in FIG.

[0081] refer to Fig. 9 and Fig.10 , the pixel array area PXA of the first substrate 110 includes a plurality of shared pixel areas 2SPX. Each shared pixel area 2SPX includes a first pixel area PXa and a second pixel area PXb adjacent to each other. In an exemplary embodiment, the plurality of shared pixel areas 2SPX are arranged at a specific spacing in the X direction and the Y direction. In an exemplary embodiment, the spacing DX5 of the plurality of shared pixel areas 2SPX in the X direction is the same as the length of each shared pixel area 2SPX in the X direction, and the spacing DY5 of the plurality of shared pixel areas 2SPX in the Y direction is the same as the length of each shared pixel area 2SPX in the Y direction. In an exemplary embodiment, the spacing DX5 is twice the spacing DY5.

[0082] A plurality of first photoelectric conversion units PDa are respectively located in a plurality of first pixel regions PXa of the first substrate 110, and a plurality of second photoelectric conversion units PDb are respectively located in a plurality of second pixel regions PXb of the first substrate 110. In an exemplary embodiment, a pixel separation pattern 160 is located between the first photoelectric conversion unit PDa and the second photoelectric conversion unit PDb.

[0083] The first photoelectric conversion unit PDa and the second photoelectric conversion unit PDb are included in the shared pixel circuit 2SP. In an exemplary embodiment, the first transmission gate TGAa included in the shared pixel circuit 2SP is located on the first pixel area PXa of the first substrate 110, and the second transmission gate TGb included in the shared pixel circuit 2SP is located on the second pixel area PXb of the first substrate 110. The shared floating diffusion region 2SFD included in the shared pixel circuit 2SP may be distributed on the first pixel area PXa and the second pixel area PXb of the first substrate 110. For example, the shared floating diffusion region 2SFD may be extended to overlap with the first pixel area PXa and the second pixel area PXb. The driving transistor DX (see Figure 8 ), select transistor SX (see Figure 8 ) or reset transistor RX (see Figure 8 ) may be located on the shared pixel region 2SPX of the first substrate 110.

[0084] A plurality of first pixel pads 130a and a plurality of second pixel pads 130b are located on the first connection layer 150, and a plurality of third pixel pads 230a and a plurality of fourth pixel pads 230b are located on the second connection layer 250. In an exemplary embodiment, a plurality of third pixel pads 230a are located on a plurality of first pixel pads 130a to contact the plurality of first pixel pads 130a, respectively. In an exemplary embodiment, a plurality of fourth pixel pads 230b are located on a plurality of second pixel pads 130b to contact the plurality of second pixel pads 130b, respectively. A plurality of first pixel pads 130a and a plurality of second pixel pads 130b may be located on a portion of the first connection layer 150 on the pixel array region PXA of the first substrate 110. That is, a plurality of first pixel pads 130a and a plurality of second pixel pads 130b may overlap the pixel array region PXA of the first substrate 110 in the Z direction.

[0085] In an exemplary embodiment, the distance DXFa between the first pixel pad 130a and the shared floating diffusion region 2SFD in the horizontal direction (e.g., X direction) is substantially the same as the distance DXFb between the second pixel pad 130b and the shared floating diffusion region 2SFD in the horizontal direction (e.g., X direction). Here, the distance DXFa between the first pixel pad 130a and the shared floating diffusion region 2SFD in the horizontal direction (e.g., X direction) may be defined as the distance between the center C130a2 of the first pixel pad 130a and the center CFD of the shared floating diffusion region 2SFD in the horizontal direction (e.g., X direction). In addition, the distance DXFb between the second pixel pad 130b and the shared floating diffusion region 2SFD in the horizontal direction (e.g., X direction) may be defined as the distance between the center C130b2 of the second pixel pad 130b and the center CFD of the shared floating diffusion region 2SFD in the horizontal direction (e.g., X direction).

[0086] In an exemplary embodiment, the center C130a2 of the plurality of first pixel pads 130a and the center C130b2 of the plurality of second pixel pads 130b do not overlap with the pixel separation pattern 160 in the Z direction. In another exemplary embodiment, the plurality of first pixel pads 130a and the plurality of second pixel pads 130b do not overlap with the pixel separation pattern 160 in the Z direction. In another exemplary embodiment, each of the first pixel pad 130a and the second pixel pad 130b does not overlap with the boundary between the first pixel region PXa and the second pixel region PXb of the first substrate 110 in the Z direction. That is, any first pixel pad 130a may not be distributed on the first pixel region PXa and the second pixel region PXb, and any second pixel pad 130b may not be distributed on the first pixel region PXa and the second pixel region PXb. In an exemplary embodiment, the first pixel pad 130a does not extend to overlap with the second pixel region PXb, and the second pixel pad 130b does not extend to overlap with the first pixel region PXa.

[0087] In an exemplary embodiment, the spacing DX1a of the plurality of first pixel pads 130a in the X direction and the spacing DX1b of the plurality of second pixel pads 130b in the X direction are substantially the same as the value obtained by multiplying the spacing DX5 of the plurality of shared pixel regions 2SPX in the X direction by a natural number. For example, the spacing DX1a of the plurality of first pixel pads 130a in the X direction and the spacing DX1b of the plurality of second pixel pads 130b in the X direction may be substantially the same as the spacing DX5 of the plurality of shared pixel regions 2SPX in the X direction. In an exemplary embodiment, the spacing DY1a of the plurality of first pixel pads 130a in the Y direction and the spacing DY1b of the plurality of second pixel pads 130b in the Y direction are substantially the same as the value obtained by multiplying the spacing DY5 of the plurality of shared pixel regions 2SPX in the Y direction by a natural number. For example, the spacing DY1a of the plurality of first pixel pads 130a in the Y direction and the spacing DY1b of the plurality of second pixel pads 130b in the Y direction may be substantially the same as the spacing DY5 of the plurality of shared pixel regions 2SPX in the Y direction. In an exemplary embodiment, the first pixel pad 130a overlaps the first pixel region PXa of the first substrate 110 in the Z direction, and the second pixel pad 130b overlaps the second pixel region PXb of the first substrate 110 in the Z direction. By arranging the plurality of first pixel pads 130a and the plurality of second pixel pads 130b as described above, when the first structure 100d is planarized using CMP, not only can bonding stress be relieved, but also a planar surface can be obtained.

[0088] When the portion of the first connection layer 150 disposed on the shared pixel area 2SPX of the first substrate 110 includes an overlapping portion (the overlapping portion includes a first overlapping portion 150a1 overlapping with the first pixel pad 130a in the Z direction and a second overlapping portion 150a2 overlapping with the second pixel pad 130b in the Z direction) and a non-overlapping portion 150b that does not overlap with the first pixel pad 130a in the Z direction and does not overlap with the second pixel pad 130b in the Z direction, the transmittance of the overlapping portions 150a1 and 150a2 of the first connection layer 150 can be higher than the transmittance of the non-overlapping portion 150b of the first connection layer 150.

[0089] In an exemplary embodiment, a ratio of a total volume of a portion of the first conductive pattern 152 in the overlapping portions 150a1 and 150a2 of the first connection layer 150 to a total volume of a portion of the first insulating layer 151 in the overlapping portions 150a1 and 150a2 of the first connection layer 150 is smaller than a ratio of a total volume of a portion of the first conductive pattern 152 in a non-overlapping portion 150b of the first connection layer 150 to a total volume of a portion of the first insulating layer 151 in the non-overlapping portion 150b of the first connection layer 150. By arranging the plurality of first pixel pads 130 as described above, leakage of light may be reduced, and thus the sensitivity of the image sensor 1000d may be improved, and crosstalk may be reduced.

[0090] As a result of arranging a plurality of first pixel pads 130a and a plurality of second pixel pads 130b to reduce leakage of light, an intra-shared pixel region distance DXab1 between a first pixel pad 130a of a first shared pixel region and a second pixel pad 130b of the first shared pixel region in a horizontal direction (e.g., X direction) may be substantially different from an inter-shared pixel region distance DXab2 between a first pixel pad 130a of a first shared pixel region and a second pixel pad 130b of a second adjacent shared pixel region in a horizontal direction (e.g., X direction). Here, an intra-shared pixel region distance DXab1 between a first pixel pad 130a and a second pixel pad 130b in a horizontal direction (e.g., X direction) may be defined as a distance between a center C130a2 of a first pixel pad 130a and a center C130b2 of a second pixel pad 130b that overlaps with the same shared pixel region 2SPX in the Z direction in a horizontal direction (e.g., X direction). In addition, the distance DXab2 between the first pixel pad 130a and the second pixel pad 130b in the horizontal direction (e.g., the X direction) can be defined as the distance between the center C130a2 of the first pixel pad 130a and the center C130b1 of the second pixel pad 130b that overlap with two adjacent shared pixel regions 2SPX in the Z direction, respectively, in the horizontal direction (e.g., the X direction).

[0091] A plurality of first peripheral pads 140a and a plurality of second peripheral pads 140b may be located on a portion of the first connection layer 150 on the peripheral region PR of the first substrate 110. That is, the plurality of first peripheral pads 140a and the plurality of second peripheral pads 140b may overlap with the peripheral region PR of the first substrate 110 in the Z direction. In an exemplary embodiment, a plurality of third peripheral pads 240a are respectively located on the plurality of first peripheral pads 140a to contact the plurality of first peripheral pads 140a, respectively. In an exemplary embodiment, a plurality of fourth peripheral pads 240b are respectively located on the plurality of second peripheral pads 140b to contact the plurality of second peripheral pads 140b, respectively.

[0092] In an exemplary embodiment, the spacing DX2a of the plurality of first peripheral pads 140a in the X direction is substantially the same as the spacing DX1a of the plurality of first pixel pads 130a in the X direction, and the spacing DX2b of the plurality of second peripheral pads 140b in the X direction is substantially the same as the spacing DX1b of the plurality of second pixel pads 130b in the X direction. Similarly, in an exemplary embodiment, the spacing DY2a of the plurality of first peripheral pads 140a in the Y direction is substantially the same as the spacing DY1a of the plurality of first pixel pads 130a in the Y direction, and the spacing DY2b of the second peripheral pads 140b in the Y direction is substantially the same as the spacing DY1b of the plurality of second pixel pads 130b in the Y direction. Therefore, the spacing DX2a of the plurality of first peripheral pads 140a in the X direction and the spacing DX2b of the plurality of second peripheral pads 140b in the X direction may be substantially the same as the spacing DX5 of the plurality of shared pixel regions 2SPX of the first substrate 110 in the X direction. The pitch DY2a of the plurality of first peripheral pads 140a in the Y direction and the pitch DY2b of the plurality of second peripheral pads 140b in the Y direction may be substantially the same as the pitch DY5 of the plurality of shared pixel regions 2SPX of the first substrate 110 in the Y direction. By arranging the plurality of first peripheral pads 140a and the plurality of second peripheral pads 140b as described above, when the first structure 100d is planarized using CMP, not only can bonding stress be alleviated but also a flat surface can be obtained.

[0093] Fig.11 4 is a circuit diagram of a shared pixel circuit 4SP included in an image sensor according to an exemplary embodiment of the inventive concept. Figure 2 The pixel circuit P shown in FIG. Fig.11 The difference between the shared pixel circuit 4SP shown in FIG.

[0094] refer to Fig.11 The shared pixel circuit 4SP includes a shared floating diffusion region FD (see Figure 2 ) of the four pixel circuits P (see Figure 2). Specifically, the shared pixel circuit 4SP includes the first to fourth photoelectric conversion units PDa, PDb, PDc and PDd, the first to fourth transfer transistors TXa, TXb, TXc and TXd, the shared floating diffusion region 4SFD, the drive transistor DX, the selection transistor SX and the reset transistor RX. The first to fourth transfer transistors TXa, TXb, TXc and TXd may include the first to fourth transfer gates TGa, TGb, TGc and TGd, respectively. The first to fourth transfer gates TGa, TGb, TGc and TGd may transfer the charges accumulated in the first to fourth photoelectric conversion units PDa, PDb, PDc and PDd, respectively, to the shared floating diffusion region 4SFD. The drive transistor DX, the selection transistor SX and the reset transistor RX may be connected to the shared floating diffusion region 4SFD.

[0095] Fig.12 1 is a plan view of a first structure 100e included in an image sensor according to an exemplary embodiment of the inventive concept. Fig. 9 The first structure 100d shown in FIG. Fig.12 The difference between the first structure 100e shown in FIG.

[0096] refer to Fig.12 , the pixel array area PXA of the first substrate 110 includes a plurality of shared pixel areas 4SPX. Each shared pixel area 4SPX includes adjacent first to fourth pixel areas PXa, PXb, PXc, and PXd. A plurality of third photoelectric conversion units PDc are respectively located in a plurality of third pixel areas PXc of the first substrate 110, and a plurality of fourth photoelectric conversion units PDd are located in a plurality of fourth pixel areas PXd of the first substrate 110. In an exemplary embodiment, the third transmission gate TGc is located on the third pixel area PXc of the first substrate 110, and the fourth transmission gate TGd is located on the fourth pixel area PXd of the first substrate 110. The shared floating diffusion area 4SFD may be distributed on the first pixel area PXa, the second pixel area PXb, the third pixel area PXc, and the fourth pixel area PXd of the first substrate 110. For example, the shared floating diffusion area 4SFD may extend to overlap the first pixel area PXa, the second pixel area PXb, the third pixel area PXc, and the fourth pixel area PXd.

[0097] The first structure 100e further includes a plurality of fifth pixel pads 130c and a plurality of sixth pixel pads 130d. The plurality of fifth pixel pads 130c and the plurality of sixth pixel pads 130d may overlap the pixel array area PXA of the first substrate 110 in the Z direction.

[0098] In an exemplary embodiment, the distance DYFa between the first pixel pad 130a and the shared floating diffusion region 4SFD in the horizontal direction (e.g., Y direction) and the distance DYFc between the fifth pixel pad 130c and the shared floating diffusion region 4SFD in the horizontal direction (e.g., Y direction) are substantially the same. Here, the distance DYFa between the first pixel pad 130a and the shared floating diffusion region 4SFD in the horizontal direction (e.g., Y direction) may be defined as the distance between the center C130a2 of the first pixel pad 130a and the center C4FD of the shared floating diffusion region 4SFD in the horizontal direction (e.g., Y direction). In addition, the distance DYFc between the fifth pixel pad 130c and the shared floating diffusion region 4SFD in the horizontal direction (e.g., Y direction) may be defined as the distance between the center C130c2 of the fifth pixel pad 130c and the center C4FD of the shared floating diffusion region 4SFD in the horizontal direction (e.g., Y direction).

[0099] In an exemplary embodiment, the spacing DX1c of the plurality of fifth pixel pads 130c in the X direction and the spacing DX1d of the plurality of sixth pixel pads 130d in the X direction are substantially the same as the value obtained by multiplying the spacing DX5 of the plurality of shared pixel regions 4SPX in the X direction by a natural number. For example, the spacing DX1c of the plurality of fifth pixel pads 130c in the X direction and the spacing DX1d of the plurality of sixth pixel pads 130d in the X direction may be substantially the same as the spacing DX5 of the plurality of shared pixel regions 4SPX in the X direction. In addition, the spacing DY1c of the plurality of fifth pixel pads 130c in the Y direction and the spacing DY1d of the plurality of sixth pixel pads 130d in the Y direction may be substantially the same as the value obtained by multiplying the spacing DY5 of the plurality of shared pixel regions 4SPX in the Y direction by a natural number. For example, the spacing DY1c of the plurality of fifth pixel pads 130c in the Y direction and the spacing DY1d of the plurality of sixth pixel pads 130d in the Y direction may be substantially the same as the spacing DY5 of the plurality of shared pixel regions 4SPX in the Y direction. In an exemplary embodiment, the fifth pixel pad 130c overlaps the third pixel region PXc of the first substrate 110 in the Z direction, and the sixth pixel pad 130d overlaps the fourth pixel region PXd of the first substrate 110 in the Z direction. By arranging the plurality of fifth pixel pads 130c and the plurality of sixth pixel pads 130d as described above, when the first structure 100e is planarized using CMP, not only can bonding stress be relieved, but also a planar surface can be obtained.

[0100] As a result of arranging the plurality of fifth pixel pads 130c and the plurality of sixth pixel pads 130d to reduce leakage of light, the distance DYac1 between the first pixel pad 130a of the first shared pixel area and the fifth pixel pad 130c of the first shared pixel area in the horizontal direction (e.g., the Y direction) may be substantially different from the distance DYac2 between the first pixel pad 130a of the second shared pixel area and the fifth pixel pad 130c of the first shared pixel area in the horizontal direction (e.g., the Y direction). Here, the distance DYac1 between the first pixel pad 130a and the fifth pixel pad 130c in the horizontal direction (e.g., the Y direction) may be defined as the distance between the center C130a2 of the first pixel pad 130a and the center C130c2 of the fifth pixel pad 130c overlapping the same shared pixel area 4SPX in the Z direction in the horizontal direction (e.g., the Y direction). In addition, the shared pixel area distance DYac2 between the first pixel pad 130a and the fifth pixel pad 130c in the horizontal direction (e.g., the Y direction) can be defined as the distance in the horizontal direction (e.g., the Y direction) between the center C130a4 of the first pixel pad 130a and the center C130c2 of the fifth pixel pad 130c which overlap with two adjacent shared pixel areas 4SPX in the Z direction, respectively.

[0101] The plurality of fifth peripheral pads 140c and the plurality of sixth peripheral pads 140d may overlap the peripheral region PR of the first substrate 110 in the Z direction. In an exemplary embodiment, the pitch DX2c of the plurality of fifth peripheral pads 140c in the X direction is substantially the same as the pitch DX1c of the plurality of fifth pixel pads 130c in the X direction, and the pitch DX2d of the plurality of sixth peripheral pads 140d in the X direction is substantially the same as the pitch DX1d of the plurality of sixth pixel pads 130d in the X direction. Similarly, in an exemplary embodiment, the pitch DY2c of the plurality of fifth peripheral pads 140c in the Y direction is substantially the same as the pitch DY1c of the plurality of fifth pixel pads 130c in the Y direction, and the pitch DY2d of the plurality of sixth peripheral pads 140d in the Y direction is substantially the same as the pitch DY1d of the plurality of sixth pixel pads 130d in the Y direction. Therefore, the pitch DX2c of the plurality of fifth peripheral pads 140c in the X direction and the pitch DX2d of the plurality of sixth peripheral pads 140d in the X direction may be substantially the same as the pitch DX5 of the plurality of shared pixel regions 4SPX of the first substrate 110 in the X direction. The pitch DY2c of the plurality of fifth peripheral pads 140c in the Y direction and the pitch DY2d of the plurality of sixth peripheral pads 140d in the Y direction may be substantially the same as the pitch DY5 of the plurality of shared pixel regions 4SPX of the first substrate 110 in the Y direction. By arranging the plurality of fifth peripheral pads 140c and the plurality of sixth peripheral pads 140d as described above, when the first structure 100e is planarized using CMP, not only can bonding stress be alleviated, but also a planar surface can be obtained.

[0102] While the inventive concept has been particularly shown and described with reference to embodiments thereof, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the inventive concept.

Claims

1. An image sensor, comprising: A first substrate including a pixel array region, wherein the pixel array region includes a plurality of pixel regions and a peripheral region around the pixel array region; A plurality of photoelectric conversion units are respectively located in a plurality of pixel areas of the first substrate; A first connection layer is provided on the pixel array region and the peripheral region of the first substrate; A plurality of first pixel pads are disposed on a portion of the first connection layer on a pixel array region of the first substrate; a plurality of first peripheral pads disposed on a portion of the first connection layer on a peripheral region of the first substrate; A plurality of second pixel pads, respectively located on the plurality of first pixel pads; A plurality of second peripheral pads, respectively located on the plurality of first peripheral pads; A second connection layer is disposed on the plurality of second pixel pads and the plurality of second peripheral pads; A device is disposed on the second connection layer; as well as A second substrate is disposed on the second connection layer and the device, The spacing between the plurality of first pixel pads in the first horizontal direction is substantially the same as the spacing between the plurality of pixel regions of the first substrate in the first horizontal direction. wherein a center of each of the plurality of first pixel pads is spaced apart from a center of each of the plurality of pixel regions of the first substrate by a predetermined distance in the second horizontal direction, in, The portion of the first connection layer disposed on each of the plurality of pixel regions of the first substrate includes an overlapping portion overlapping with each of the plurality of first pixel pads in a plan view and a non-overlapping portion not overlapping with each of the plurality of first pixel pads in a plan view, and The transmittance of the overlapping portion of the first connecting layer is higher than the transmittance of the non-overlapping portion of the first connecting layer.

2. The image sensor according to claim 1, wherein: A pitch of the plurality of first peripheral pads in the first direction is substantially the same as a pitch of the plurality of pixel regions of the first substrate in the first horizontal direction.

3. The image sensor according to claim 1, wherein: A width of each of the plurality of first pixel pads and the plurality of second pixel pads in the first horizontal direction is greater than 0 and is less than or equal to half of a pitch of the plurality of pixel regions of the first substrate in the first horizontal direction.

4. The image sensor according to claim 1, further comprising: A pixel separation pattern is disposed between the plurality of photoelectric conversion units, wherein a center of each of the plurality of first pixel pads does not overlap with the pixel separation pattern in a plan view.

5. The image sensor according to claim 4, wherein: The plurality of first pixel pads do not overlap the pixel separation pattern in a plan view.

6. The image sensor according to claim 1, wherein: Each of the plurality of first pixel pads includes a filling layer and a barrier layer disposed between the filling layer and the first connection layer.

7. The image sensor according to claim 6, wherein: The filling layer includes copper (Cu), aluminum (Al), or a combination thereof, and the barrier layer includes titanium (Ti), tantalum (Ta), tin (Sn), copper (Cu), aluminum (Al), gold (Au), silver (Ag), or a combination thereof.

8. The image sensor according to claim 1, wherein: The first connection layer does not electrically connect a plurality of pixel circuits respectively including a plurality of first photoelectric conversion units to the plurality of first pixel pads.

9. The image sensor according to claim 1, wherein: The first connection layer electrically connects a plurality of pixel circuits, each including a plurality of first photoelectric conversion units, to the plurality of first pixel pads, respectively.

10. The image sensor according to claim 9, further comprising: A plurality of pixel devices are arranged on the second substrate, wherein the second connection layer electrically connects the plurality of pixel devices to the plurality of second pixel pads respectively.

11. An image sensor, comprising: A first structure includes: a first substrate including a plurality of pixel regions; a plurality of photoelectric conversion units respectively located in the plurality of pixel regions of the first substrate; a first connection layer disposed on the first substrate; and a plurality of first pixel pads disposed on the first connection layer; and The second structure includes: a second substrate; a device disposed on the second substrate; a second connection layer disposed on the second substrate and the device; and a plurality of second pixel pads disposed on the second connection layer. Wherein, the plurality of first pixel pads are respectively in contact with the plurality of second pixel pads, The first connection layer includes an insulating layer disposed on the first substrate and a conductive pattern disposed in the insulating layer. The portion of the first connection layer located on the plurality of pixel regions of the first substrate includes: a plurality of overlapping portions, which overlap with the plurality of first pixel pads respectively in a plan view; and a plurality of non-overlapping portions, which do not overlap with the plurality of first pixel pads in a plan view. wherein the transmittance of the multiple overlapping portions of the first connecting layer is higher than the transmittance of the multiple non-overlapping portions of the first connecting layer, and wherein the ratio of the total volume of the multiple portions of the conductive pattern respectively located in the multiple overlapping portions of the first connecting layer to the total volume of the multiple portions of the insulating layer respectively located in the multiple overlapping portions of the first connecting layer is smaller than the ratio of the total volume of the multiple portions of the conductive pattern respectively located in the multiple non-overlapping portions of the first connecting layer to the total volume of the multiple portions of the insulating layer respectively located in the multiple non-overlapping portions of the first connecting layer.

12. The image sensor according to claim 11, wherein: The boundaries between the plurality of first pixel pads and the plurality of pixel regions of the first substrate do not overlap in a plan view.

13. The image sensor according to claim 11, wherein: A pitch of the plurality of first pixel pads in the horizontal direction is substantially the same as a value obtained by multiplying a natural number by a pitch of the plurality of pixel regions of the first substrate in the horizontal direction.

14. The image sensor according to claim 13, wherein: A pitch between the plurality of first pixel pads in the horizontal direction is substantially the same as a pitch between the plurality of pixel regions of the first substrate in the horizontal direction.

15. The image sensor according to claim 11, wherein: The conductive pattern does not contact at least one of the plurality of pixel pads.

16. The image sensor according to claim 11, wherein: The conductive pattern contacts at least one of the plurality of pixel pads.

17. An image sensor comprising: A first structure, comprising: a first substrate, comprising a plurality of shared pixel regions, each of which comprises a first pixel region and a second pixel region; a plurality of first photoelectric conversion units, each of which is located in a first pixel region of each of the plurality of shared pixel regions of the first substrate; a plurality of second photoelectric conversion units, each of which is located in a second pixel region of each of the plurality of shared pixel regions of the first substrate; a plurality of shared floating diffusion regions, located on the first pixel region and the second pixel region of each of the plurality of shared pixel regions; a first connection layer, disposed on the first substrate, and a plurality of first pixel pads and a plurality of second pixel pads, disposed on the first connection layer; and The second structure includes: a second substrate; a device disposed on the second substrate; a second connection layer disposed on the second substrate and the device; and a plurality of third pixel pads and a plurality of fourth pixel pads disposed on the second connection layer. The plurality of first pixel pads respectively contact the plurality of third pixel pads, and the plurality of second pixel pads respectively contact the plurality of fourth pixel pads. wherein the spacing between the plurality of first pixel pads in the first horizontal direction and the spacing between the plurality of second pixel pads in the first horizontal direction are substantially the same as the spacing between the plurality of shared pixel regions in the first horizontal direction, The portion of the first connection layer located on the plurality of shared pixel regions of the first substrate includes a plurality of first overlapping portions respectively overlapping with the plurality of first pixel pads in a plan view and a plurality of second overlapping portions respectively overlapping with the plurality of second pixel pads in a plan view, and a plurality of non-overlapping portions respectively not overlapping with the plurality of first pixel pads in a plan view and the plurality of second pixel pads in a plan view, wherein the transmittance of the plurality of overlapping portions of the first connecting layer is higher than the transmittance of the plurality of non-overlapping portions of the first connecting layer, and The distance between the first pixel pads and the second pixel pads in the shared pixel region in the second horizontal direction is substantially different from the distance between the first pixel pads and the second pixel pads in the shared pixel region in the second horizontal direction.

18. The image sensor according to claim 17, wherein: A distance between the plurality of first pixel pads and the plurality of shared floating diffusion regions in the second horizontal direction is substantially the same as a distance between the plurality of second pixel pads and the plurality of shared floating diffusion regions in the second horizontal direction.

19. The image sensor according to claim 17, wherein the first connection layer comprises an insulating layer disposed on the first substrate and a conductive pattern disposed in the insulating layer, as well as in, The ratio of the total volume of multiple portions of the conductive pattern respectively located in the multiple overlapping portions of the first connecting layer to the total volume of multiple portions of the insulating layer respectively located in the multiple overlapping portions of the first connecting layer is smaller than the ratio of the total volume of multiple portions of the conductive pattern respectively located in the multiple non-overlapping portions of the first connecting layer to the total volume of multiple portions of the insulating layer respectively located in the multiple non-overlapping portions of the first connecting layer.

Images