Charge pump circuit configured for positive and negative voltage generation

Abstract

Various embodiments of the present disclosure relate to charge pump circuits configured for generating positive and negative voltages. A charge pump includes an intermediate node that is capacitively coupled to receive a first clock signal that oscillates between ground and a positive supply voltage, the intermediate node generating a first signal that oscillates between a first voltage and a second voltage. A level shifting circuit shifts the first signal in response to a second clock signal to generate a second signal that oscillates between a first voltage and a third voltage. A CMOS switch circuit includes: a first transistor having a source coupled to an input; a second transistor having a source coupled to an output and having a gate coupled to receive the second signal. A common drain of the CMOS switch circuit is capacitively coupled to receive the first clock signal. When positively pumped, the first voltage is twice the second voltage, and the third voltage is ground. When negatively pumped, the first voltage and the third voltage have opposite polarity, and the second voltage is ground.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to U.S. Provisional Patent Application No. 62 / 885,533, filed on August 12, 2019, the disclosure of which is incorporated herein by reference. Technical Field

[0003] The present invention relates to a charge pump circuit configured to generate positive and negative voltages. Background Art

[0004] refer to Figure 1A , which shows a circuit diagram for a positive charge pump circuit 100p. Circuit 100p includes an n-channel MOS transistor MN1 having a source terminal coupled to a power supply node 102 and a drain terminal coupled to an intermediate node NA1; and an n-channel MOS transistor MN2 having a source terminal coupled to the power supply node 102 and a drain terminal coupled to an intermediate node NA2. Circuit 100p also includes a p-channel MOS transistor MP1 having a source terminal coupled to an output node 104 and a drain terminal coupled to node NA1; and a p-channel MOS transistor MP2 having a source terminal coupled to output node 104 and a drain terminal coupled to an intermediate node NA2. The gate terminals of transistors MN1 and MP1 are connected together and further connected to an intermediate node NA2. The gate terminals of transistors MN2 and MP2 are connected together and further connected to the intermediate node NA1. Transistors MN1, MN2, MP1, and MP2 form a CMOS latch circuit.

[0005] Capacitor C1 has one terminal coupled to node NA1 and has another terminal coupled to receive a logical inversion of the clock signal CK, which is generated by CMOS inverter circuit 106. CMOS inverter circuit 106 is powered by positive supply voltage Vdd and receives clock signal CK as an input. Capacitor C2 has one terminal coupled to node NA2 and has another terminal coupled to receive a logical inversion of the clock signal CKN (which is a logical inversion of the clock signal CK). This logical inversion is generated by CMOS inverter circuit 108. CMOS inverter circuit 108 is powered by positive supply voltage Vdd and receives clock signal CKN as an input.

[0006] The load 106 of the circuit 100 p is schematically represented by a load capacitor Cload having one terminal coupled to the output node 104 and having a second terminal coupled to a ground node, and a current source Iload coupled between the output node 104 and the ground node.

[0007] The supply node 102 is configured to receive a positive supply voltage Vdd. The output node 104 is configured to generate an increasing positive output voltage Vpos, where Vpos is approximately 2*Vdd.

[0008] refer to Figure 1B , which shows a circuit diagram of a negative charge pump circuit 100n. Circuit 100n includes a p-channel MOS transistor MP1 having a source terminal coupled to a power supply node 102 and a drain terminal coupled to an intermediate node NA1; and a p-channel MOS transistor MP2 having a source terminal coupled to the power supply node 102 and a drain terminal coupled to an intermediate node NA2. Circuit 100n also includes an n-channel MOS transistor MN1 having a source terminal coupled to an output node 104 and a drain terminal coupled to an intermediate node NA1; and an n-channel MOS transistor MN2 having a source terminal coupled to the output node 104 and a drain terminal coupled to an intermediate node NA2. The gate terminals of transistors MN1 and MP1 are connected together and further connected to an intermediate node NA2. The gate terminals of transistors MN2 and MP2 are connected together and further connected to an intermediate node NA1. Transistors MN1, MN2, MP1, and MP2 form a CMOS latch circuit.

[0009] Capacitor C1 has one terminal coupled to node NA1 and has another terminal coupled to receive a logical inversion of the clock signal CK, which is generated by CMOS inverter circuit 106. CMOS inverter circuit 106 is powered by positive supply voltage Vdd and receives clock signal CK as an input. Capacitor C2 has one terminal coupled to node NA2 and has another terminal coupled to receive a logical inversion of the clock signal CKN (which is a logical inversion of the clock signal CK). This logical inversion is generated by CMOS inverter circuit 108. CMOS inverter circuit 108 is powered by positive supply voltage Vdd and receives clock signal CKN as an input.

[0010] The load 106 of the circuit 100 n is schematically represented by a load capacitor Cload having one terminal coupled to the output node 104 and having a second terminal coupled to the ground node, and a current source Iload coupled between the positive supply voltage Vdd and the output node 104 .

[0011] The supply node 102 is configured to receive a ground voltage Vgnd. The output node 104 is configured to generate a multiplied negative output voltage Vneg, wherein Vneg is approximately equal to -Vdd.

[0012] The output impedance at the output node 104 depends on the frequency of the clock signals CK and CKN and the on-resistance (Rds_on) of the switching transistors MN1, MN2, MP1 and MP2 that perform the charge transfer. The output impedance is given by the following formula:

[0013]

[0014] Where: C is the capacitance of the flying capacitor (ie, C1 or C2 depending on the phase of the clock).

[0015] The on-resistance (Rds_on) of transistors MN1, MN2, MP1, and MP2 is given by the following formula:

[0016]

[0017] Where: L is the length of the transistor, W is the width of the transistor, C OX is the gate capacitance, V GS is the gate-to-source voltage, and V TH is the threshold voltage.

[0018] If the transistor width W is reduced, the on-resistance (Rds_on) increases, and there will be a larger voltage drop across each switching transistor, with a corresponding reduction in efficiency.

[0019] The switch capacitance is given by:

[0020] C SW =C OX *W*L eff

[0021] Where: L eff is the effective length of the transistor switch.

[0022] It will be noted that if the transistor width W is increased, this will result in an increase in capacitance on the upper plate of the capacitor, with a corresponding increase in charge losses and a decrease in efficiency.

[0023] Therefore, a solution is needed Figure 1A and Figure 1B The circuits shown in 100p / 100n have the disadvantages of positive / negative charge pump circuits. Summary of the Invention

[0024] In one embodiment, a charge pump circuit includes: an input voltage node; an output voltage node; a first transistor and a second transistor in a cross-coupled configuration, wherein the first transistor is coupled between the input voltage node and a first intermediate node, and the second transistor is coupled between the input voltage node and the second intermediate node; wherein the first intermediate node and the second intermediate node are capacitively coupled to receive a first clock signal and a second clock signal, the first clock signal and the second clock signal being logically inverted from each other; a first CMOS switch circuit includes: a first transistor and a second transistor, the first transistor having a source node coupled to receive the first signal at the first intermediate node; the second transistor having a source node coupled to receive a third clock signal, wherein the second clock signal is a logical inversion of the third clock signal; a second CMOS switch circuit includes: a third transistor and a fourth transistor, the third transistor having a source node coupled to receive the second signal at the second intermediate node; the fourth transistor a transistor having a source node coupled to receive a fourth clock signal, wherein the first clock signal is a logical inversion of the fourth clock signal; a third CMOS switch circuit comprising: a fifth transistor having a source node coupled to the input node; a sixth transistor having a source node coupled to the output node; and wherein a gate node of at least one of the fifth and sixth transistors is coupled to receive the third signal at a common drain of the first CMOS switch circuit; a fourth CMOS switch circuit comprising: a seventh transistor having a source node coupled to the input node; an eighth transistor having a source node coupled to the output node; and wherein a gate node of at least one of the seventh and eighth transistors is coupled to receive the fourth signal at a common drain of the second CMOS switch circuit; wherein the common drain of the third CMOS switch circuit and the common drain of the fourth CMOS switch circuit are capacitively coupled to receive the first clock signal and the second clock signal, respectively.

[0025] In one embodiment, a charge pump circuit includes: a first intermediate node and a second intermediate node, capacitively coupled to receive a first clock signal and a second clock signal, the first clock signal and the second clock signal being logically inverted from each other, the first clock signal and the second clock signal oscillating between a ground voltage and a positive supply voltage, the first intermediate node and the second intermediate node generating a first signal and a second signal, respectively, the first signal and the second signal being logically inverted from each other and oscillating between a first voltage and a second voltage; a first level shift circuit configured to shift the first signal and generate a third signal oscillating between a first voltage and a third voltage; a second level shift circuit configured to shift the second signal and generate a fourth signal oscillating between the first voltage and the third voltage; wherein the third and fourth signals are logical inversions of each other; a first CMOS switch circuit comprising: a first transistor having a source node coupled to an input node; a second transistor having a source node coupled to an output node; and wherein a gate node of at least one of the first transistor and the second transistor is coupled to receive a third signal; a second CMOS switch circuit comprising: a third transistor having a source node coupled to the input node; a fourth transistor having a source node coupled to the output node, and wherein a gate node of at least one of the third transistor and the fourth transistor is coupled to receive a fourth signal; and wherein a common drain of the first CMOS switch circuit and a common drain of the second CMOS switch circuit are capacitively coupled to receive a first clock signal and a second clock signal, respectively.

[0026] In one embodiment, a positive charge pump circuit includes: a bootstrap-based level shifting circuit that receives a positive supply voltage at an input node and is configured to generate a switching control signal that oscillates between a ground voltage and a boosted positive voltage substantially equal to twice the positive supply voltage; a circuit including an intermediate node that is capacitively coupled to receive a clock signal that oscillates between a ground voltage and a positive supply voltage and is configured to generate a signal at the intermediate node that oscillates between a voltage substantially equal to the positive supply voltage and a voltage substantially equal to twice the positive supply voltage; and a charge transfer switch circuit having a control node driven by the switching control signal and configured to control the transfer of charge from the intermediate node to an output node to generate an output voltage substantially equal to twice the positive supply voltage.

[0027] In one embodiment, a negative charge pump circuit includes: a bootstrap-based level shifting circuit that receives a ground voltage at an input node and is configured to generate a switching control signal that oscillates between the ground voltage and a boosted negative voltage that is substantially equal to a negative positive supply voltage; a circuit that includes an intermediate node that is capacitively coupled to receive a clock signal that oscillates between the ground voltage and the positive supply voltage and is configured to generate a signal at the intermediate node that oscillates between a voltage substantially equal to the positive supply voltage and a voltage substantially equal to the negative positive supply voltage; and a charge transfer switch circuit having a control node driven by the switching control signal and configured to control the transfer of charge from the intermediate node to an output node to generate an output voltage substantially equal to the negative positive supply voltage. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] For a better understanding of the embodiments, reference will now be made, by way of example only, to the accompanying drawings, in which:

[0029] Figure 1A This is a circuit diagram for a positive charge pump circuit;

[0030] Figure 1B This is a circuit diagram for a negative charge pump circuit;

[0031] Figure 2A This is a circuit diagram for a positive charge pump circuit;

[0032] Figure 2B This is a circuit diagram for a positive charge pump circuit;

[0033] Figure 2C This is a circuit diagram for a positive charge pump circuit;

[0034] Figure 2D This is a circuit diagram for a positive charge pump circuit;

[0035] Figure 2E This is a circuit diagram for a negative charge pump circuit;

[0036] Figure 2F This is a circuit diagram for a negative charge pump circuit;

[0037] Figure 2G This is a circuit diagram for a negative charge pump circuit;

[0038] Figure 2H This is a circuit diagram for a negative charge pump circuit;

[0039] Figure 3A The diagram shows Figure 2A-2D The operating waveform of the circuit; and

[0040] Figure 3B The diagram shows Figure 2E-2HThe operating waveform of the circuit. DETAILED DESCRIPTION

[0041] Now refer to Figure 2A , which shows a circuit diagram for a positive charge pump circuit 200p. Circuit 200p includes a bootstrap circuit comprising: n-channel MOS transistor MN1 and n-channel MOS transistor MN2, each having a source terminal coupled to supply node 202 and a drain terminal coupled to intermediate node NA1; n-channel MOS transistor MN2 having a source terminal coupled to supply node 202 and a drain terminal coupled to intermediate node NA2. Transistors MN1 and MN2 are cross-coupled, with the gate terminal of transistor MN1 coupled to the drain terminal of transistor MN2 at node NA2, and the gate terminal of transistor MN2 coupled to the drain terminal of transistor MN1 at node NA1.

[0042] Bootstrap capacitor Cbs1 has one terminal coupled to node NA1 and has another terminal coupled to receive a logical inversion of clock signal CK, which is generated by CMOS inverter circuit 206p. CMOS inverter circuit 206p is powered by positive supply voltage Vdd and receives clock signal CK as input. Bootstrap capacitor Cbs2 has one terminal coupled to node NA2 and has another terminal coupled to receive a logical inversion of clock signal CKN (which is a logical inversion of clock signal CK). Logic inversion CK1 is generated by CMOS inverter circuit 208p. CMOS inverter circuit 208p is powered by positive supply voltage Vdd and receives clock signal CKN as input.

[0043] CMOS switch circuit 210p has a first terminal coupled to receive a positive supply voltage Vdd and a second terminal at an intermediate node NB1. The source terminal of p-channel MOS transistor MP1 in switch circuit 210p is coupled to node NA1, and the source terminal of n-channel MOS transistor MN3 in switch circuit 210p is coupled to receive a clock signal CKN. A second terminal is located at the common drain of transistors MP1 and MN3. The gates of transistors MP1 and MN3 are coupled to a first terminal (Vdd).

[0044] CMOS switch circuit 212p has a first terminal coupled to receive a positive supply voltage Vdd and a second terminal at an intermediate node NB2. The source terminal of p-channel MOS transistor MP2 in switch circuit 212p is coupled to node NA2, and the source terminal of n-channel MOS transistor MN4 in switch circuit 212p is coupled to receive a clock signal CK. A second terminal is at the common drain of transistors MP2 and MN4. The gates of transistors MP2 and MN4 are coupled to a first terminal (Vdd).

[0045] Circuits 210p and 212p form a bootstrap-based level shift circuit with the bootstrap circuit.

[0046] CMOS switch circuit 220p has a first terminal coupled to node NB1 and a second terminal at an intermediate node NC1. The source terminal of n-channel MOS transistor MN5 in switch circuit 220p is coupled to supply node 202, and the source terminal of p-channel MOS transistor MP3 in switch circuit 220p is coupled to output node 204. A second terminal is at the common drain of transistors MN5 and MP3. The gate terminals of transistors MN5 and MP3 are coupled to a first terminal (NB1).

[0047] CMOS switch circuit 222p has a first terminal coupled to node NB2 and a second terminal at an intermediate node NC2. The source terminal of n-channel MOS transistor MN6 in switch circuit 222p is coupled to supply node 202, and the source terminal of p-channel MOS transistor MP4 in switch circuit 222p is coupled to output node 204. A second terminal is at the common drain of transistors MN6 and MP4. The gate terminals of transistors MN6 and MP4 are coupled to a first terminal (NB2).

[0048] Capacitor C1 has one terminal coupled to node NC1 and another terminal coupled to receive a logical inversion of clock signal CK1N, which is generated by CMOS inverter circuit 216p, which is powered by positive supply voltage Vdd and receives clock signal CK1N as an input. Capacitor C2 has one terminal coupled to node NC2 and another terminal coupled to receive a logical inversion of clock signal CK1, which is generated by CMOS inverter circuit 218p, which is powered by positive supply voltage Vdd and receives clock signal CK1 as an input.

[0049] The load 206 of the circuit 200p is schematically represented by a load capacitor Cload having one terminal coupled to the output node 204 and having a second terminal coupled to a ground node, and a current source Iload coupled between the output node 204 and the ground node.

[0050] The supply node 202 is configured to receive a positive supply voltage Vdd. The output node 204 is configured to generate an increased positive output voltage Vpos, where Vpos is approximately 2*Vdd.

[0051] Figure 3A Shown for Figure 2A The waveforms of the clock signals CK, CKN, CK1 and CK1N and the signals at the nodes NA1, NA2, NB1, NB2, NC1 and NC2 are shown for the operation of the circuit 200p. Figure 3A It will also be noted that the voltage levels of the clock signals are idealized, and in practice, the voltages will be substantially equal to the ideal Vdd and 2*Vdd voltage levels (e.g., within 1%-20%), but need not necessarily be equal to the ideal Vdd and 2*Vdd voltage levels.

[0052] The circuit arrangement formed by transistors MN1 and MN2, bootstrap capacitors Cbs1 and Cbs2, and inverters 206p and 208p is a bootstrap circuit that generates clock signals referenced to 2*Vdd and Vdd at nodes NA1 and NA2 in response to a reference power supply Vdd and grounded clock signals CK and CKN. When clock signal CK is at a logic high (Vdd), clock signal CK1N output by inverter 206p will be at a logic low (Gnd). Because node NA2 is boosted to a voltage level of 2*Vdd by capacitor Cbs2, transistor MN1 is turned on (i.e., because the gate voltage of transistor MN1 exceeds Vdd at its source terminal by more than Vth), and bootstrap capacitor Cbs1 is charged to the Vdd voltage level. In the next phase of the clock signal, clock signal CK is at a logic low, and clock signal CK1N output by inverter 206p will be at a logic high. Because the node NA2 is at the Vdd voltage level, the transistor MN1 is turned off (i.e., because the gate voltage of the transistor MN1 is equal to the source voltage Vdd and therefore does not exceed Vth, it is turned off), and the voltage at the node NA1 is boosted to a voltage level of 2*Vdd by the bootstrap voltage Vdd stored on the capacitor Cbs1. A similar process occurs in response to the phase of the clock signals CKN and CK1.

[0053] The circuit arrangement formed by CMOS switch circuits 210p and 212p functions as a level shifting stage to shift the clock signals referenced to 2*Vdd and Vdd at nodes NA1 and NA2 to generate clock signals referenced to 2*Vdd and ground at nodes NB1 and NB2. Regarding the operation of circuit 210p, consider the following: when clock signal CKN is logic low, transistor MN3 is turned on (i.e., because the gate voltage of transistor MN3 exceeds ground at its source terminal by more than Vth) and node NB1 is clamped to ground. Because node NB1 is at 2*Vdd, transistor MP1 is turned off. In the next phase of the clock signal, clock signal CKN is logic high, which causes transistor MN3 to turn off (i.e., because the gate voltage of transistor MN3 is equal to the source voltage Vdd and therefore does not exceed Vth). In this same phase, node NA1 is at a voltage level of 2*Vdd (see discussion above), and transistor MP1 is turned on (i.e., Vgs of transistor MP1 exceeds Vth), which passes the 2*Vdd voltage level to node NB1. A similar process occurs with respect to circuit 212p in response to the phase of clock signal CK.

[0054] The circuit arrangement formed by capacitors C1, C2 and inverters 216p, 218p is used to generate clock signals referenced to 2*Vdd and Vdd at nodes NC1 and NC2 in response to clock signals CK1 and CK1N, which are referenced to a power supply Vdd and ground. Consider the following operation for the circuit having capacitor C1 and inverter 216p: When clock signal CK1N is logic high, the output of inverter 216p is logic low. Simultaneously, as discussed below, transistor MN5 is turned on and capacitor C1 is charged to the Vdd voltage level. In the next phase of the clock signal, clock signal CK1N is logic low, and the output of inverter 216p is logic high. The voltage at node NC1 is boosted to the 2*Vdd voltage level by capacitor C1. A similar process occurs for the circuit having capacitor C2 and inverter 218p, depending on the phase of clock signal CK1.

[0055] The circuit arrangement formed by CMOS switch circuits 220p and 222p functions as a charge transfer driver stage to selectively pass the 2*Vdd voltage at nodes NC1 and NC2 to output node 204 to drive capacitive load and current load 206. Regarding the operation of circuit 220p, consider the following: when clock signals CKN and CK1N are both logic high, the voltage at node NB1 is at a 2*Vdd voltage level, and transistor MN5 is turned on (i.e., Vgs of transistor MN5 exceeds Vth) to charge capacitor C1 to the Vdd voltage level. In the next phase of the clock signals, when clock signals CKN and CK1N are both logic low, the voltage at node NB1 is at ground level, and transistor MP3 is turned on (i.e., Vgs of transistor MP3 exceeds Vth) to pass the 2*Vdd voltage level at node NC1 to output node 204. A similar process occurs with circuit 222p in response to the phases of clock signals CK and CK1.

[0056] The advantage of this circuit implementation is the increase in Vgs of the charge transfer switching transistor, thereby reducing the on-resistance (Rds_on). Figure 1A Compared to the charge pump circuit, there is a corresponding reduction in output impedance.

[0057] Now refer to Figure 2B , which shows a circuit diagram for a positive charge pump circuit 200p'. The same reference numerals refer to similar or identical components and will not be described again. Figure 2B The circuit 200p' with Figure 2A Circuit 200p differs from circuit 200p in the driving of CMOS switch circuits 220p' and 222p'. As with circuit 200p, the gate of transistor MP3 is driven by the signal at node NB1, but the gate of transistor MN5 is driven by the signal at node NA1. As with circuit 200p, the gate of transistor MP4 is driven by the signal at node NB2, but the gate of transistor MN6 is driven by the signal at node NA2. The operation of circuit 200p' is similar to that described for circuit 200p, with the following differences: Figure 3A The waveform shown in .

[0058] Now refer to Figure 2C , which shows a circuit diagram for a positive charge pump circuit 200p". The same reference numerals refer to similar or identical components and will not be described again. Figure 2C The circuit 200p" with Figure 2BThe circuit 200p' differs from the circuit 200p' in the driving of the CMOS switch circuits 210p' and 212p'. The gates of the transistors MN3 and MP1 are driven by the signal at the node NA2. The gates of the transistors MN4 and MP2 are driven by the signal at the node NA1. The operation of the circuit 200p' is similar to that described for the circuit 200p, with the following features: Figure 3A The waveform shown in .

[0059] Now refer to Figure 2D , which shows a circuit diagram for a positive charge pump circuit 200p″′. The same reference numerals refer to similar or identical components and will not be described again. Figure 2D The circuit 200p'' with Figure 2A Circuit 200p differs from circuit 200p in the driving of CMOS switch circuits 220p" and 222p". As with circuit 200p, the gate of transistor MP3 is driven by the signal at node NB1, but the gate of transistor MN5 is driven by the signal at node NC2. As with circuit 200p, the gate of transistor MP4 is driven by the signal at node NB2, but the gate of transistor MN6 is driven by the signal at node NC1. The operation of circuit 200p'" is similar to that described for circuit 200p, with the following differences: Figure 3A The waveform shown in .

[0060] Now refer to Figure 2E , which shows a circuit diagram of a negative charge pump circuit 200n. Circuit 200n includes a bootstrap circuit comprising: a p-channel MOS transistor MP1 having a source terminal coupled to a supply node 202 and a drain terminal coupled to an intermediate node NA1; and a p-channel MOS transistor MP2 having a source terminal coupled to the supply node 202 and a drain terminal coupled to an intermediate node NA2. Transistors MP1 and MP2 are cross-coupled, with the gate terminal of transistor MP1 coupled to the drain terminal of transistor MP2 at node NA2, and the gate terminal of transistor MP2 coupled to the drain terminal of transistor MP1 at node NA1.

[0061] Bootstrap capacitor Cbs1 has one terminal coupled to node NA1 and has another terminal coupled to receive a logical inversion of clock signal CK, the logical inversion CK1N generated by CMOS inverter circuit 206n, which is powered by positive supply voltage Vdd and receives clock signal CK as input. Bootstrap capacitor Cbs2 has one terminal coupled to node NA2 and has another terminal coupled to receive a logical inversion of clock signal CKN (which is a logical inversion of clock signal CK), the logical inversion CK1 generated by CMOS inverter circuit 208n, which is powered by positive supply voltage Vdd and receives clock signal CKN as input.

[0062] CMOS switch circuit 210n has a first terminal coupled to receive ground voltage Gnd and a second terminal at intermediate node NB1. The source terminal of p-channel MOS transistor MP3 in switch circuit 210 is coupled to receive clock signal CKN, and the source terminal of n-channel MOS transistor MN1 in switch circuit 210 is coupled to node NA1. A second terminal is located at the common drain of transistors MP3 and MN1. The gates of transistors MP3 and MN1 are coupled to a first terminal (Gnd).

[0063] CMOS switch circuit 212n has a first terminal coupled to receive ground voltage Gnd and a second terminal at intermediate node NB2. The source terminal of p-channel MOS transistor MP4 in switch circuit 212n is coupled to receive clock signal CK, and the source terminal of n-channel MOS transistor MN2 in switch circuit 212 is coupled to NA2. A second terminal is at the common drain of transistors MP4 and MN2. The gate terminals of transistors MP4 and MN2 are coupled to a first terminal (Gnd).

[0064] Circuits 210n and 212n form a bootstrap-based level shift circuit with the bootstrap circuit.

[0065] CMOS switch circuit 220n has a first terminal coupled to node NB1 and a second terminal at an intermediate node NC1. The source terminal of p-channel MOS transistor MP5 in switch circuit 220n is coupled to supply node 202, and the source terminal of n-channel MOS transistor MN3 in switch circuit 220n is coupled to output node 204. A second terminal is at the common drain of transistors MP5 and MN3. The gates of transistors MP5 and MN3 are coupled to a first terminal (NB1).

[0066] CMOS switch circuit 222n has a first terminal coupled to node NB2 and a second terminal at an intermediate node NC2. The source terminal of p-channel MOS transistor MP6 in switch circuit 222n is coupled to node 202, and the source terminal of n-channel MOS transistor MN4 in switch circuit 222n is coupled to output node 204. The second terminal is at the common drain of transistors MP6 and MN4. The gates of transistors MP6 and MN4 are coupled to the first terminal (NB2).

[0067] Capacitor C1 has one terminal coupled to node NC1 and another terminal coupled to receive a logical inversion of clock signal CK1N, which is generated by CMOS inverter circuit 216n, which is powered by positive supply voltage Vdd and receives clock signal CK1N as an input. Capacitor C2 has one terminal coupled to node NC2 and another terminal coupled to receive a logical inversion of clock signal CK1, which is generated by CMOS inverter circuit 218n, which is powered by positive supply voltage Vdd and receives clock signal CK1 as an input.

[0068] The load 206 of the circuit 200 n is schematically represented by a load capacitor Cload having one terminal coupled to the output node 204 and having a second terminal coupled to the ground node, and a current source Iload coupled between the positive supply voltage Vdd and the output node 204 .

[0069] The supply node 202 is configured to receive a ground voltage. The output node 204 is configured to generate an increasing negative output voltage Vneg, wherein Vneg is approximately -Vdd.

[0070] Figure 3B Shown for Figure 2E The waveforms of the clock signals CK, CKN, CK1 and CK1N and the signals at the nodes NA1, NA2, NB1, NB2, NC1 and NC2 are shown for the operation of the circuit 200n. Figure 3B It will also be noted that the voltage levels of the clock signals are idealized, and in practice, the voltages will be substantially equal to the Vdd and -Vdd voltage levels (e.g., within 1-20%), but need not necessarily be equal to the Vdd and -Vdd voltage levels.

[0071] The circuit arrangement formed by transistors MP1 and MP2, bootstrap capacitors Cbs1 and Cbs2, and inverters 206n and 208n is a bootstrap circuit that generates clock signals referenced to -Vdd and ground at nodes NA1 and NA2 in response to a reference power supply Vdd and grounded clock signals CK and CKN. When clock signal CKN is at a logic low (Gnd), clock signal CK1 output by inverter 208n will be at a logic high (Vdd). Because node NA1 is boosted to a -Vdd voltage level by capacitor Cbs1, transistor MP2 is turned on (i.e., because the gate voltage of transistor MP2 is less than ground at its source terminal by more than Vth), and bootstrap capacitor Cbs2 is charged to ground. In the next phase of the clock signal, clock signal CKN is at a logic high, and clock signal CK1 output by inverter 208n will be at a logic low. Because the node NA1 is at the ground voltage level, the transistor MP2 is turned off (e.g., because the gate voltage of the transistor MP2 is equal to the source ground voltage and therefore does not exceed Vth), and the voltage at the node NA2 is boosted to the -Vdd voltage level by the bootstrap ground voltage stored on the capacitor Cbs2. A similar process occurs in response to the phase of the clock signals CK and CK1N.

[0072] The circuit arrangement formed by CMOS switch circuits 210n and 212n functions as a level shifting stage to shift the clock signals referenced to -Vdd and ground at nodes NA1 and NA2 to generate clock signals referenced to -Vdd and +Vdd at nodes NB1 and NB2. Regarding the operation of circuit 212n, consider the following: when clock signal CK is logic high, transistor MP4 turns on (i.e., because the gate voltage of transistor MP4 is less than the source terminal by more than Vth) and node NB2 is clamped to Vdd. In the next phase of the clock signal, clock signal CK is logic low, which causes transistor MP4 to turn off (i.e., because the gate voltage of transistor MP4 is equal to the source voltage ground and therefore does not exceed Vth). In this same phase, node NA2 is at a -Vdd voltage level (see discussion above), and transistor MN2 turns on (i.e., the Vgs of transistor MN2 exceeds Vth), which passes the -Vdd voltage level to node NB1. A similar process occurs with respect to circuit 210n in response to the phase of clock signal CKN.

[0073] The circuit arrangement formed by capacitors C1 and C2 and inverters 216n and 218n is used to generate clock signals referenced to -Vdd and ground at nodes NC1 and NC2 in response to clock signals CK1 and CK1N referenced to power supply Vdd and ground. Consider the following operation for the circuit having capacitor C2 and inverter 218n: When clock signal CK1 is logic low, the output of inverter 218n is logic high. Simultaneously, as discussed below, transistor MP6 turns on, and capacitor C2 discharges to ground. In the next phase of the clock signal, clock signal CK1 is logic high, and the output of inverter 218n is logic low. The voltage at node NC2 is boosted to -Vdd by capacitor C2. A similar process occurs for the circuit having capacitor C1 and inverter 216n, depending on the phase of clock signal CK1N.

[0074] The circuit arrangement formed by CMOS switch circuits 220n and 222n functions as a charge transfer driver stage to selectively pass the −Vdd voltage at nodes NC1 and NC2 to output node 204 to drive capacitive and current loads 206. Regarding the operation of circuit 222n, consider the following: when both clock signals CK and CK1 are logic low, the voltage at node NB2 is at a −Vdd voltage level and transistor MP6 is turned on (i.e., Vgs of transistor MP6 exceeds Vth) to discharge capacitor C2 to ground. In the next phase of the clock signals, when both clock signals CK and CK1 are logic high, the voltage at node NB2 is at a Vdd level and transistor MN4 is turned on (i.e., Vgs of transistor MN4 exceeds Vth) to pass the −Vdd voltage level at node NC2 to node 204. A similar process occurs with respect to circuit 220n in response to the phases of clock signals CKN and CK1N.

[0075] The advantage of this circuit implementation is that the Vgs of the charge transfer switching transistor is increased, thereby reducing the on-resistance (Rds_on). Figure 1B Compared to the charge pump circuit, there is a corresponding reduction in output impedance.

[0076] Now refer to Figure 2F , which shows a circuit diagram for a negative charge pump circuit 200n'. The same reference numerals refer to similar or identical components and will not be described again. Figure 2F The circuit 200n' and Figure 2ECircuit 200n differs from circuit 200n in the driving of CMOS switch circuits 220n' and 222n'. As in circuit 200n, the gate of transistor MN3 is driven by the signal at node NB1, but the gate of transistor MP5 is driven by the signal at node NA1. As in circuit 200n, the gate of transistor MN4 is driven by the signal at node NB2, but the gate of transistor MP6 is driven by the signal at node NA2. The operation of circuit 200n' is similar to that described for circuit 200n, with the following differences: Figure 3B The waveform shown in .

[0077] Now refer to Figure 2G , which shows a circuit diagram for a negative charge pump circuit 200n". The same reference numerals refer to similar or identical components and will not be described again. Figure 2G The circuit 200n" with Figure 2F The difference between circuit 200n' and CMOS switch circuits 210' and 212' is the driving of transistors MP3 and MN1. The gates of transistors MP4 and MN2 are driven by the signal at node NA1. The operation of circuit 200n' is similar to that described for circuit 200n, with the following features: Figure 3B The waveform shown in .

[0078] Now refer to Figure 2H , which shows a circuit diagram for a negative charge pump circuit 200n″′. The same reference numerals refer to similar or identical components and will not be described again. Figure 2H The circuit 200n'' with Figure 2F Circuit 200n differs from circuit 200n in the driving of CMOS switch circuits 220″ and 222″. As with circuit 200n, the gate of transistor MN3 is driven by the signal at node NB1, but the gate of transistor MP5 is driven by the signal at node NC2. As with circuit 200n, the gate of transistor MN4 is driven by the signal at node NB2, but the gate of transistor MP6 is driven by the signal at node NC1. The operation of circuit 200n′″ is similar to that described for circuit 200n, with the following features: Figure 3B The waveform shown in .

[0079] The foregoing description has provided by way of exemplary and non-limiting examples a complete and informative description of the exemplary embodiments of the present invention. However, various modifications and adaptations will become apparent to those skilled in the art in view of the foregoing description when read in conjunction with the accompanying drawings and the appended claims. Nevertheless, all such and similar modifications of the teachings of this invention will still fall within the scope of the invention as defined by the appended claims.

Claims

1. A charge pump circuit, comprising: Input voltage node; Output voltage node; a first transistor and a second transistor in a cross-coupled configuration, wherein the first transistor is coupled between the input voltage node and a first intermediate node, and the second transistor is coupled between the input voltage node and a second intermediate node; wherein the first intermediate node and the second intermediate node are capacitively coupled to receive a first clock signal and a second clock signal, the first clock signal and the second clock signal being logically inverted with respect to each other; a first CMOS switch circuit comprising a first transistor and a second transistor, the first transistor having a source node coupled to receive a first signal at the first intermediate node, the second transistor having a source node coupled to receive a third clock signal, wherein the second clock signal is a logical inversion of the third clock signal; a second CMOS switch circuit comprising a third transistor and a fourth transistor, the third transistor having a source node coupled to receive a second signal at the second intermediate node, the fourth transistor having a source node coupled to receive a fourth clock signal, wherein the first clock signal is a logical inversion of the fourth clock signal; a third CMOS switch circuit comprising a fifth transistor and a sixth transistor, the fifth transistor having a source node coupled to the input voltage node, the sixth transistor having a source node coupled to the output voltage node, and wherein a gate node of at least one of the fifth and sixth transistors is coupled to receive a third signal at a common drain of the first CMOS switch circuit; a fourth CMOS switch circuit comprising: a seventh transistor having a source node coupled to the input voltage node; an eighth transistor having a source node coupled to the output voltage node; and wherein a gate node of at least one of the seventh transistor and the eighth transistor is coupled to receive a fourth signal at a common drain of the second CMOS switch circuit; The common drain of the third CMOS switch circuit and the common drain of the fourth CMOS switch circuit are capacitively coupled to receive the first clock signal and the second clock signal respectively.

2. The charge pump circuit of claim 1 , wherein the gate nodes of both the fifth transistor and the sixth transistor are coupled to receive the third signal, and wherein the gate nodes of both the seventh transistor and the eighth transistor are coupled to receive the fourth signal.

3. The charge pump circuit of claim 1 , configured to operate as a positive charge pump, wherein: The input voltage node receives a positive supply voltage; and The output voltage node generates a positive output voltage substantially equal to twice the positive supply voltage.

4. The charge pump circuit of claim 1 , configured to operate as a positive charge pump, wherein: The input voltage node receives a positive supply voltage; and Gate nodes of the first transistor, the second transistor, the third transistor, and the fourth transistor receive the positive supply voltage.

5. The charge pump circuit of claim 1 , configured to operate as a positive charge pump, wherein: The input voltage node receives a positive supply voltage; a gate node of the first transistor and the second transistor coupled to receive the second signal; and Gate nodes of the third transistor and the fourth transistor are coupled to receive the first signal. 6 . The charge pump circuit of claim 1 , configured to operate as a positive charge pump, wherein the first transistor and the third transistor are p-channel transistors. 7 . The charge pump circuit of claim 1 , configured to operate as a positive charge pump, wherein the fifth transistor and the seventh transistor are n-channel transistors.

8. The charge pump circuit of claim 1 , configured to operate as a positive charge pump, wherein: The input voltage node receives a positive supply voltage; and The first signal and the second signal oscillate between a first voltage substantially equal to the positive supply voltage and a second voltage substantially equal to twice the positive supply voltage. 9 . The charge pump circuit of claim 8 , wherein the third signal and the fourth signal oscillate between the second voltage and a ground voltage.

10. The charge pump circuit of claim 1 , configured to operate as a positive charge pump, wherein: The input voltage node receives a positive supply voltage; the gate node of the fifth transistor being coupled to receive the first signal; the gate node of the sixth transistor being coupled to receive the third signal; the gate node of the seventh transistor being coupled to receive the second signal; and The gate node of the eighth transistor is coupled to receive the fourth signal.

11. The charge pump circuit according to claim 10, wherein: A gate node of the first transistor and the second transistor is coupled to receive the second signal; and Gate nodes of the third transistor and the fourth transistor are coupled to receive the first signal.

12. The charge pump circuit of claim 1 , configured to operate as a positive charge pump, wherein: The input voltage node receives a positive supply voltage; the gate node of the fifth transistor being coupled to receive a signal at the common drain of the fourth CMOS switch circuit; the gate node of the sixth transistor being coupled to receive the third signal; the gate node of the seventh transistor being coupled to receive a signal at the common drain of the third CMOS switch circuit; and The gate node of the eighth transistor is coupled to receive the fourth signal. 13 . The charge pump circuit of claim 12 , wherein the gate nodes of the first transistor, the second transistor, the third transistor, and the fourth transistor receive the positive supply voltage.

14. The charge pump circuit of claim 1 , configured to operate as a negative charge pump, wherein: The input voltage node receives a ground supply voltage; and The output voltage node generates a negative output voltage.

15. The charge pump circuit of claim 1 , configured to operate as a negative charge pump, wherein: The input voltage node receives a ground supply voltage; and Gate nodes of the first transistor, the second transistor, the third transistor, and the fourth transistor receive the ground supply voltage.

16. The charge pump circuit of claim 1 , configured to operate as a negative charge pump, wherein: The input voltage node receives a ground supply voltage; a gate node of the first transistor and the second transistor coupled to receive the second signal; and Gate nodes of the third transistor and the fourth transistor are coupled to receive the first signal. 17 . The charge pump circuit of claim 1 , configured to operate as a negative charge pump, wherein the first transistor and the third transistor are n-channel transistors.

18. The charge pump circuit of claim 1, configured to operate as a negative charge pump, wherein the fifth transistor and the seventh transistor are p-channel transistors.

19. The charge pump circuit of claim 1 , configured to operate as a negative charge pump, wherein: The input voltage node receives a ground supply voltage; and The first signal and the second signal oscillate between the ground supply voltage and a negative voltage. 20 . The charge pump circuit of claim 19 , wherein the third signal and the fourth signal oscillate between the negative voltage and a positive voltage.

21. The charge pump circuit of claim 1 , configured to operate as a negative charge pump, wherein: The input voltage node receives a ground supply voltage; the gate node of the fifth transistor being coupled to receive the first signal; the gate node of the sixth transistor being coupled to receive the third signal; the gate node of the seventh transistor being coupled to receive the second signal; and The gate node of the eighth transistor is coupled to receive the fourth signal.

22. The charge pump circuit of claim 21 , wherein: A gate node of the first transistor and the second transistor is coupled to receive the second signal; and Gate nodes of the third transistor and the fourth transistor are coupled to receive the first signal.

23. The charge pump circuit of claim 1 , configured to operate as a negative charge pump, wherein: The input voltage node receives a ground supply voltage; the gate node of the fifth transistor being coupled to receive a signal at the common drain of the fourth CMOS switch circuit; the gate node of the sixth transistor being coupled to receive the third signal; the gate node of the seventh transistor being coupled to receive a signal at the common drain of the third CMOS switch circuit; and The gate node of the eighth transistor is coupled to receive the fourth signal. 24 . The charge pump circuit of claim 23 , wherein the gate nodes of the first, second, third, and fourth transistors receive a positive supply voltage.

25. The charge pump circuit of claim 1, configured to operate as a positive charge pump, wherein the first transistor and the second transistor are n-channel transistors.

26. The charge pump circuit of claim 1, configured to operate as a negative charge pump, wherein the first transistor and the second transistor are p-channel transistors.

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