Motor step driver with sinusoidal digital to analog converter

Abstract

A motor step driver with a sinusoidal digital-to-analog converter is disclosed. A step driver for a motor includes an H-bridge (HS1, HS2, LS1, LS2), a sense transistor (SNS*FET) coupled to the H-bridge, a voltage-to-current (VtoI) converter (214), and a sinusoidal digital-to-analog converter (DAC, 121). The VtoI converter (214) has a VtoI converter input and a VtoI converter output. The VtoI converter output is coupled to the sense transistor (SNS*FET). The sinusoidal DAC (121) has a sinusoidal DAC digital input, a reference input, and a sinusoidal DAC output. The sinusoidal DAC output is coupled to the VtoI converter input. The sinusoidal DAC includes an R-2R network, an offset control circuit coupled to the R-2R network, and a gain control circuit also coupled to the R-2R network.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to U.S. Provisional Application No. 62 / 886,981, filed August 15, 2019, and U.S. Provisional Application No. 62 / 954,332, filed December 27, 2019, which are incorporated herein by reference. Background Technology

[0003] At least one type of stepper motor includes two coils that receive current from a stepper driver. The current to each coil should be sinusoidal, wherein the current to one coil is 90 degrees out of phase with the current to the other coil. The angular position of the stepper motor is a function of the ratio of the magnitudes of the currents in the coils (e.g., the arctangent of the ratio). Inaccuracy in the magnitudes of the coil currents can lead to inaccuracy in the motor's rotational position. Summary of the Invention

[0004] In at least one example, a stepper driver for a motor includes: an H-bridge; a sensing transistor coupled to the H-bridge; a voltage-to-current (VtoI) converter; and a sinusoidal digital-to-analog converter (DAC). The VtoI converter has a VtoI converter input and a VtoI converter output. The VtoI converter output is coupled to the sensing transistor. The sinusoidal DAC has a sinusoidal DAC digital input, a reference input, and a sinusoidal DAC output. The sinusoidal DAC output is coupled to the VtoI converter input. The sinusoidal DAC includes: an R-2R network; offset control circuitry coupled to the R-2R network; and gain control circuitry also coupled to the R-2R network. Attached Figure Description

[0005] For a detailed description of the various examples, reference will now be made to the accompanying drawings, in which:

[0006] Figure 1 An example of a stepper motor system is shown.

[0007] Figure 2 An example of a stepper driver including a sinusoidal digital-to-analog converter (DAC) is shown.

[0008] Figure 3 An example of a sinusoidal DAC including an R-2R network, gain control circuitry, and offset control circuitry is shown.

[0009] Figure 4 The linear relationship between the DAC output and the digital code input of the R-2R network is shown, as well as the desired sinusoidal relationship for a sinusoidal DAC implementation.

[0010] Figure 5 The piecewise linear relationship implemented using gain control circuitry and offset control circuitry is shown.

[0011] Figure 6 The piecewise linear relationship implemented using gain control circuitry and offset control circuitry is further illustrated.

[0012] Figure 7 It shows that it can be used Figure 2 An example of a voltage-to-current converter used in a stepper driver.

[0013] Figure 8 Another example implementation of a sine DAC is shown.

[0014] Figure 9 Another example implementation of a sine DAC is shown.

[0015] Figure 10 An example implementation of a stepper driver integrated circuit (IC) including multiple sine DACs is shown. Detailed Implementation

[0016] One type of stepper driver includes multiple current source devices (e.g., transistors) that can be operatively switched in and out of the circuit to provide a variable trip current, thereby controlling the current flowing to the coil. Each current source can be configured to have the same current (e.g., 1 microamp). A 2-microamp trip current is generated by switching on two current sources connected in parallel. Three current sources connected in parallel generate a 3-microamp trip current, and so on. This type of stepper driver can be used for 1 / 4-microsteps, where there can be four current levels for each quarter-cycle of a sinusoidal current, resulting in four motor positions.

[0017] To increase the resolution of position control for stepper motors, higher levels of microstepping, such as 1 / 256, 1 / 1024, and 1 / 4096, should be achieved. Higher resolution stepper motors are useful in various applications, such as camera zoom. One way to increase the microstepping level of a stepper motor is to increase the number of current sources, where each current source provides less current than in the case of a 1 / 4 microstep. However, as the current level decreases, current mismatch between the current source devices becomes a greater problem. Larger transistors can be used for current sources to solve the mismatch problem, but larger transistors occupy more area on the die and have larger parasitic capacitances, which in turn increase the settling time when transitioning from one current level to another. Furthermore, the quiescent current for current source-based current control of stepper motors can be undesirably large. Power headroom can also become problematic, especially when lower supply voltages are desired.

[0018] The examples disclosed herein relate to a stepper driver including a sinusoidal digital-to-analog converter (DAC). The sinusoidal DAC receives a digital code input and produces an analog output voltage that has an approximately sinusoidal relationship with the digital code input. A voltage-to-current (VtoI) converter then converts the sinusoidal DAC output voltage into a tripping current to control the current flowing through the coils of the stepper motor. The sinusoidal DAC includes an R-2R network, offset control circuitry, and gain control circuitry. Without gain control and offset control circuitry, the relationship between the output voltage of the R-2R network and its digital code input is typically linear. The gain control and offset control circuitry operate to modify the linear transfer function of the R-2R network to an approximately sinusoidal function.

[0019] Figure 1 An example of a stepper motor system 100 is shown. The example stepper motor system 100 includes a controller 102 coupled to a stepper motor driver 120, which in turn is coupled to a stepper motor M. The stepper motor M includes coil 1 and coil 2, and the stepper driver 120 controls the current flowing through the coils. The current flowing through the coils is approximately sinusoidal, and the current flowing through coil 2 is 90 degrees out of phase with respect to coil 1.

[0020] In one example, controller 102 includes a processor or other type of digital control circuitry. Controller 102 is coupled to stepper driver 120 via a STEP signal, a direction (DIR) signal, and a programming interface. The programming interface may include any suitable interface, such as Serial Peripheral Interconnect (SPI). Each rising edge of the STEP signal causes stepper driver 120 to advance the motor position one step, and the DIR signal specifies the direction of the motor change (forward or reverse). Stepper driver 120 includes a sine DAC 121 (described below).

[0021] Figure 2 An example of at least a portion of a stepper driver 120 is shown. A coil 1 is shown in the schematic, but the coil itself is not typically an assembly of the semiconductor die containing the other components shown for the stepper driver 120. In this example, the stepper driver 120 includes high-side transistors HS1 and HS2, low-side transistors LS1 and LS2, a comparator 210, digital logic and a driver 211, a voltage-to-current (VtoI) converter 214, and a sine DAC 121. Each of transistors HS1, HS2, LS1, and LS2 may include a metal-oxide-semiconductor field-effect transistor (FET). In this example, transistors HS1, HS2, LS1, and LS2 include n-type FETs (NMOS), but may be implemented as other types of transistors as needed. The stepper driver 120 also includes a sense transistor (SNS FET). Transistors HS1, HS2, LS1, and LS2 are coupled together to form an H-bridge. Figure 2 As shown in the example, the drains of HS1 and HS2 are coupled together at the positive supply voltage node (VDD), and the sources of LS1 and LS2 are coupled together at the ground node. The source of HS1 is connected to the drain of LS1 at node A. Similarly, the source of HS2 is connected to the drain of LS2 at node B. One coil of the motor (e.g., coil 1) is coupled between nodes A and B. A separate H-bridge and sensing FET are provided for the other coil (coil 2). Figure 9 An example of a stepper driver that includes both an H-bridge and a sensing FET is shown.

[0022] Digital logic and driver 211 includes logic 212 coupled to gate driver 213. Gate driver 213 asserts gate signals Hson1, Hson2, Lson1, and Lson2 for the gates of transistors HS1, HS2, LS1, and LS2, respectively. Comparator 210 includes a positive (+) input, a negative (-) input, and an output. The comparator's output is coupled to digital logic and driver 211. The comparator's positive input is coupled to node B, which also represents the drain-source voltage of transistor LS2. The gate of transistor LS2 is connected to the gate of an SNS FET, and the drain of the SNS FET is coupled to the negative input of the comparator. The source of the SNS FET is connected to ground.

[0023] The sine DAC 121 includes one input that receives a microstepping indexer bit (s[n:0]) and another input that receives a reference voltage VREF. The microstepping indexer bit represents control signals for the switches internal to the sine DAC 121, as will be discussed below. The microstepping indexer bit is generated based on the DAC code, and... Figure 9 An example of a digital core that converts DAC code into microstepped indexer bits is shown. In one example, the DAC code is a 3-bit binary value, and the corresponding indexer bits consist of 8 bits. The output of the sine DAC 121 is labeled Vsine and coupled to the input of the VtoI converter 214. The output of the VtoI converter 214 is coupled to the drain of the SNS FET and the negative input of comparator 210.

[0024] Figure 3An example implementation of the sinusoidal DAC 121 is shown. This example includes an R-2R network 310, gain control circuitry 320, and offset control circuitry 330. Gain control circuitry 320 and offset control circuitry 330 are coupled to the R-2R network. The R-2R network 310 includes repeating instances of unit resistors R coupled to 2R resistors. A unit resistor R may comprise a single resistor having a resistance of R or multiple resistors connected in series or parallel with an effective resistance of R. As shown, unit resistors are coupled in series between node Nout and ground, and 2R resistors are coupled to each node between adjacent unit resistors R. Each 2R resistor is coupled to a switch operable to electrically couple the corresponding 2R resistor to a reference voltage VREF or ground. A microstepping indexer bit controls the switch. Figure 3 The example includes eight switches and eight microstepping indexer bits [7:0]. The voltage on node Nout represents the Vsine output of the sine DAC.

[0025] Without gain control circuit 320 and offset control circuit 330, the relationship between the digital code and Vsine is linear, such as... Figure 4 As shown in 410. However, for proper operation of the stepper motor, it is desirable that the relationship between the DAC code and the Vsine be sinusoidal, as shown in sine curve 420. Gain control circuit 320 operates to modify the slope of the Vsine-DAC code relationship, and offset control circuit 330 operates to introduce offset where needed to establish a piecewise linear approximate sinusoidal relationship between the Vsine and DAC, as shown in 420. Figure 5 As shown.

[0026] Reference Figure 5 ,from Figure 4 Repeat the linear relationship 410 and the expected sinusoidal relationship. Figure 5 Piecewise linear segments 509, 510, 511, 512, 513, and 514, generated by the operation of gain control circuit 320, are also shown. As illustrated, the gain (slope) of the Vsine-DAC code relationship can be varied between DAC codes using gain control circuit 320. Initially (i.e., when the DAC code is 0), the slope (509) of the Vsine-DAC code relationship is greater than the slope inherent to the linear R-2R network. As the DAC code increases to the next code (e.g., 1), an offset is generated, and offset control circuit 330 counteracts this offset to “push” the piecewise linear segment 510 upward to track the overall profile of the desired sine curve 420. At each DAC code, gain control circuit 320 modifies the slope inherent to the R-2R network by the desired amount, and offset control circuit 330 introduces an appropriate offset to make the resulting piecewise linear segment approximate the sine curve 420. Figure 6An example of relationship 600 between Vsine and the DAC code, including piecewise linear relationships 601, 602, 603, 604, 605, and 606, is shown. Relationship 600 is approximately sinusoidal. Among other factors, the amount of gain modification and offset for each piecewise linear segment depends on the number of steps implemented by the stepper driver 120 and the desired accuracy. Therefore, the amounts of gain and offset control are application-specific.

[0027] Figure 7 An example of a VtoI converter 214 is shown. In this example, the VtoI converter 214 includes an amplifier 705, a current mirror 707, a transistor M1, and a trimmable resistor R1. The positive input of amplifier 705 is coupled to the output of a sine DAC 121. The output of amplifier 705 is coupled to the gate of M1 (an NMOS device in this example). The current mirror 707 includes a pair of PMOS devices that mirror the current flowing through the SNS FET. R1 (and therefore the voltage across R1) is coupled to the negative input of amplifier 705. The VtoI converter 214 generates I1, which is mirrored to the SNSFET using the current mirror 707.

[0028] Figure 8 Another example of the sine DAC 121 is shown, with additional details for the gain control circuitry 320 and the offset control circuitry 330. The gain control circuitry 320 includes multiple resistors. Each resistor is coupled to a different node within a serial chain of unit resistors R. This example uses a two-bit DAC code, and therefore, in this example, the R-2R network 310a includes four switches coupled to the 2R resistors. Thus, the R-2R network 310a includes three nodes N1, N2, and N3 between resistors R. However, as shown, of the three nodes N1-N3, only nodes N1 and N2 are coupled to the corresponding resistors 720 and 725. Resistors 720 and 725 are coupled between Vsine and the R-2R network 310a. In this example, node N3 is not connected to the gain control circuitry 320. Resistor 720 is shown as "X*R", meaning that resistor 720 is a function of unit resistance X. "X" is a function of the DAC code. Thus, the resistance of resistor 720 may vary depending on the DAC code, and for some DAC codes it may even be "off" (e.g., decoupled from node N1). Similarly, resistor 725 is Y*R, where Y is a function of the DAC code that is different from X. The offset control circuit 330 also includes a configurable resistor 730, whose resistance is f1*R, where f1 is a function of the DAC code that is different from both X and Y. As shown, resistor 730 is connected between VREF and Vsine.

[0029] Figure 9An example of a sinusoidal DAC 821 is shown. In this example, the sinusoidal DAC 821 includes an R-2R network 810, a gain control circuit 820, and an offset control circuit 830. As shown and as described above, switches SW selectively connect each 2R resistor to VREF or ground, thus achieving a linear R-2R DAC. Resistors R (along with a 2R resistor) are connected in series between Vsine and ground. As shown, the nodes between resistors R are labeled nodes 21-26. In this example, the DAC is a 3-bit binary value, and therefore there are eight 2R resistors and eight corresponding switches SW. The 3-bit DAC code is decoded into eight bits, where each bit controls the corresponding switch SW.

[0030] The gain control circuit 820 includes resistors R20-R29 and switches SW1-SW8. Resistors R20, R21, R22, R23, and R24 are connected in series between node 25 and SW1. Resistors R25 and R26 are connected in parallel. A parallel combination of resistors R20, R21, R22, R23, R24, and R25 and R26 is connected in series between node 25 and SW2. The node between resistors R21 and R22 is connected to switch SW3, and therefore resistors R20 and R21 are connected in series between node 25 and switch SW3. Resistors R20, R21, R22, R23, and R24 are connected in series between node 25 and SW4. Resistors R27, R28, and R29 are connected in series between node 24 and SW5, and also in series between node 24 and switch SW6. The node between resistors R27 and R28 is connected to switch SW7, and therefore resistor R27 is connected between node 24 and switch SW7. The node between resistors R20 and R21 is connected to switch SW8, and therefore resistor R20 is connected between node 25 and switch SW8. In one example, a unit resistor (R) equals 100 kiloohms, and a 2R resistor equals 200 kiloohms. Unit resistors (e.g., 100 kiloohms) can be combined in series and parallel to form different resistors to achieve resistors including R20-R29. That is, R20-R29 can be the same or different resistors and are application-specific. In one example, SW1 to SW8 have different resistors coupled between the switches and their corresponding nodes. To save area, one or more resistors are reused across multiple switches. For example, if SW3 requires 2R between SW3 and node 25, instead of connecting 2R from SW8 to node 25, the 2R used for SW1 is reused because SW1 is off when SW3 is on. Reusing resistors to save area is also implemented for the offset control circuit 830.

[0031] Based on the state of at least some bits of the DAC code, control signals for SW1-SW16 are generated, thereby coupling specific resistance values ​​between Vsine and the various internal nodes of the R-2R network 810 to provide the predetermined gain amount as described above.

[0032] Example Figure 9 The offset control circuit 830 includes resistors R30-R42 and switches SW11-SW16. Resistors R30, R31, R32, R33, R34, R35, R36, R37, and R38 are connected in series between VREF and switch SW11. Resistors R30, R31, R32, R33, R34, R35, R36, and R37 are connected in series between VREF and switch SW12. Resistors R30-R35 are connected in series between VREF and switch SW13. Resistors R39 and R40 are connected in series and in parallel with resistor R31. Similarly, resistors R41 and R42 are connected in series and in parallel with resistor R33. Resistors R30-R33 (and resistors R41 and R42, connected in series and in parallel with resistor R33) are connected in series between VREF and switch SW14. Resistors R30 and R31 (and R39 and R40, connected in series and in parallel with R31) are connected in series between VREF and switch SW15. Resistor R30 is connected between VREEF and switch SW16. In one example, each of R30-R42 comprises a 25 kΩ resistor. The control signals for switches SW11-SW16 are the same as those for switches SW3-SW8. Since only one of SW3-SW8 is on at any given time, the resistor used for SW3 is reused when SW3 is off, saving significant area compared to not using the same resistor for different switches.

[0033] Figure 10 Another example of a stepper driver integrated circuit (IC) 900 for controlling a stepper motor 980 is shown. The coil 1 of the stepper motor 980 is controlled by an H-bridge, senses 925 and 926, a sine DAC 915, a VtoI converter 916, and a comparator 927. The H-bridge of coil 1 includes FETs 921, 922, 923, and 924, where FETs 921 and 923 represent high-side FETs, and FETs 922 and 924 represent low-side FETs. A digital core 910 generates and / or otherwise receives DAC code for the stepper motor 980 and decodes the DAC code to generate microstepping indexer bits. The sine DAC 915 is coupled to the digital core 910 via (one or more) signal lines 911, which provide the microstepping indexer bits to the sine DAC.

[0034] The stepper driver IC 900 includes a substantially identical set of components to drive coil 2. Coil 2 of the stepper motor 980 is controlled by another H-bridge, sensors 935 and 936, a sine DAC 945, a V-to-I converter 946, and a comparator 937. The H-bridge for coil 2 includes FETs 931, 932, 933, and 934, where FETs 931 and 933 represent high-side FETs, and FETs 932 and 934 represent low-side FETs. The sine DAC 945 is coupled to the digital core 910 via (one or more) signal lines 941, which provide microstepping indexer bits to the sine DAC 945.

[0035] The term "coupled" is used throughout this specification. This term can encompass a connection, communication, or signaling path that achieves a functional relationship consistent with the description of this disclosure. For example, in a first example, if device A generates a signal to control device B to perform an action, then device A is coupled to device B via intermediate component C. Alternatively, in a second example, if intermediate component C substantially does not alter the functional relationship between device A and device B such that device B is controlled by device A via control signals generated by device A, then device A is coupled to device B via intermediate component C.

[0036] Modifications to the described embodiments are possible within the scope of the claims, and other embodiments are also possible.

Claims

1. A stepper driver for a motor, comprising: an H-bridge; a sense transistor coupled to the H-bridge; a voltage-to-current converter (VtoI converter) having a VtoI converter input and a VtoI converter output, the VtoI converter output coupled to the sense transistor; and a sinusoidal digital-to-analog converter (sinusoidal DAC) having a sinusoidal DAC digital input, a reference input, and a sinusoidal DAC output, the sinusoidal DAC output coupled to the VtoI converter input, the sinusoidal DAC comprising: an R-2R network; an offset control circuit coupled to the R-2R network; and a gain control circuit also coupled to the R-2R network, wherein the gain control circuit is configured to adjust a gain of the sinusoidal DAC based on a digital code provided to the sinusoidal DAC, and the offset control circuit is configured to adjust an offset of the sinusoidal DAC based on the digital code provided to the sinusoidal DAC to modify a linear transfer function of the R-2R network to an approximately sinusoidal function.

2. The stepper driver of claim 1, wherein the gain control circuit comprises a first plurality of resistors and a second plurality of switches; and each switch in the second plurality of switches is coupled to at least one resistor in the first plurality of resistors.

3. The stepper driver of claim 1, wherein the gain control circuit comprises a first plurality of resistors and a second plurality of switches; the switches in the second plurality of switches are coupled together at the sinusoidal DAC output; a first resistor in the first plurality of resistors is coupled to a first node within the R-2R network; a second resistor in the first plurality of resistors is coupled to a second node within the R-2R network; and each switch in the second plurality of switches is coupled to at least one resistor in the first plurality of resistors.

4. The stepper driver of claim 1, wherein: the offset control circuit comprises a first plurality of resistors and a second plurality of switches; at least one of the first plurality of resistors is coupled to the reference input; and the switches in the second plurality of switches are coupled together at the sinusoidal DAC output.

5. The stepper driver of claim 1, wherein: the offset control circuit comprises a first plurality of resistors and a second plurality of switches; at least one of the first plurality of resistors is coupled to the reference input; each switch in the second plurality of switches is coupled to at least one resistor in the first plurality of resistors; and the switches in the second plurality of switches are coupled together at the sinusoidal DAC output.

6. The stepper driver of claim 1, further comprising a comparator having a first comparator input and a second comparator input, the first comparator input coupled to the H-bridge and the second comparator input coupled to the sense transistor and the VtoI converter output.

7. A stepper driver for a motor, comprising: an H-bridge configured to provide current to a motor coil; ​ ​ ​ a sense transistor coupled to the H-bridge, the sense transistor configured to sense the current of the motor coil; a voltage-to-current converter (VtoI converter) having a VtoI converter input and a VtoI converter output, the VtoI converter output coupled to the sense transistor; and a sine digital-to-analog converter (sine DAC) having a sine DAC digital input, a reference input, and a sine DAC output, the sine DAC output coupled to the VtoI converter input, the sine DAC comprising: an R-2R network; an offset control circuit coupled to the R-2R network; and a gain control circuit also coupled to the R-2R network, the gain control circuit configured to adjust a gain of the sine DAC based on a digital code provided to the sine DAC, and the offset control circuit configured to adjust an offset of the sine DAC based on the digital code provided to the sine DAC to modify a linear transfer function of the R-2R network to an approximately sinusoidal function.

8. The stepper driver of claim 7, wherein the gain control circuit comprises a first plurality of resistors and a second plurality of switches; and each switch of the second plurality of switches is coupled to at least one resistor of the first plurality of resistors.

9. The stepper driver of claim 7, wherein the gain control circuit comprises a first plurality of resistors and a second plurality of switches; the switches of the second plurality of switches are coupled together at the sine DAC output; a first resistor of the first plurality of resistors is coupled to a first node within the R-2R network; a second resistor of the first plurality of resistors is coupled to a second node within the R-2R network; and each switch of the second plurality of switches is coupled to at least one resistor of the first plurality of resistors.

10. The stepper driver of claim 7, wherein: the offset control circuit comprises a first plurality of resistors and a second plurality of switches; at least one of the first plurality of resistors is coupled to the reference input; and the switches of the second plurality of switches are coupled together at the sine DAC output.

11. The stepper driver of claim 7, wherein: the offset control circuit comprises a first plurality of resistors and a second plurality of switches; at least one of the first plurality of resistors is coupled to the reference input; each switch of the second plurality of switches is coupled to at least one resistor of the first plurality of resistors; and the switches of the second plurality of switches are coupled together at the sine DAC output.

12. The stepper driver of claim 7, further comprising a comparator having a first comparator input and a second comparator input, the first comparator input coupled to the H-bridge and the second comparator input coupled to the sense transistor and the VtoI converter output.

13. A stepper motor system, comprising: a stepper motor; a stepper driver comprising: an H-bridge coupled to the stepper motor; ​ ​ a sense transistor coupled to the H-bridge; a voltage-to-current converter (VtoI converter) having a VtoI converter input and a VtoI converter output, the VtoI converter output coupled to the sense transistor; and a sinusoidal digital-to-analog converter (sinusoidal DAC) having a sinusoidal DAC digital input, a reference input, and a sinusoidal DAC output, the sinusoidal DAC output coupled to the VtoI converter input, the sinusoidal DAC comprising: an R-2R network; an offset control circuit coupled to the R-2R network; and a gain control circuit also coupled to the R-2R network, wherein the gain control circuit is configured to adjust a gain of the sinusoidal DAC based on a digital code provided to the sinusoidal DAC; and the offset control circuit is configured to adjust an offset of the sinusoidal DAC based on the digital code provided to the sinusoidal DAC to modify a linear transfer function of the R-2R network to an approximately sinusoidal function.

14. The stepper motor system of claim 13, wherein: the gain control circuit comprises a first plurality of resistors and a second plurality of switches; the switches of the second plurality of switches are coupled together at the sinusoidal DAC output; a first resistor of the first plurality of resistors is coupled to a first node within the R-2R network; a second resistor of the first plurality of resistors is coupled to a second node within the R-2R network; and each switch of the second plurality of switches is coupled to at least one resistor of the first plurality of resistors.

15. The stepper motor system of claim 14, wherein: the offset control circuit comprises a first plurality of resistors and a second plurality of switches; at least one of the first plurality of resistors is coupled to the reference input; each switch of the second plurality of switches is coupled to at least one resistor of the first plurality of resistors; and the switches of the second plurality of switches are coupled together at the sinusoidal DAC output.

16. The stepper motor system of claim 14, wherein the stepper driver is configured to implement at least one of 1 / 32, 1 / 64, 1 / 128, 1 / 256, 1 / 512, 1 / 1024, and 1 / 2148, and 1 / 4196 microsteps.

17. The stepper motor system of claim 13, wherein the stepper motor comprises a first coil and a second coil, and the H-bridge, the sense transistor, the VtoI converter, and the sinusoidal DAC are for the first coil, and the stepper driver further comprises a second set of the following for the second coil: H-bridge, sense transistor, VtoI converter, and sinusoidal DAC.

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