Split-gate nonvolatile memory cell with three-dimensional fin field effect transistor structure and method for manufacturing the same

Abstract

The present invention discloses a memory device, which includes a plurality of upwardly extending fins in the upper surface of a semiconductor substrate. A memory cell is formed on a first fin in the fins and includes a source region and a drain region, the source region and the drain region are spaced apart in the first fin, wherein a channel region extends between the source region and the drain region along the top surface and the opposite side surface of the first fin. A floating gate extends along a first portion of the channel region. A select gate extends along a second portion of the channel region. A control gate extends along the floating gate. An erase gate extends along the source region. A second fin in the fin has a length extending in a first direction, the first direction being perpendicular to a second direction extending from the length of the first fin. A source region is formed in the first fin at the intersection of the first fin and the second fin.

Description

[0001] Priority declaration

[0002] This patent application claims priority to U.S. Patent Application No. 16 / 028,244 filed on July 5, 2018, entitled "Split Gate Non-volatile Memory Cells With Three-Dimensional FINFET Structure, And Method Of Making Same." Technical Field

[0003] The present invention relates to non-volatile flash memory cell arrays. Background Art

[0004] Split gate non-volatile memory devices are well known in the art. For example, US Pat. No. 7,927,994 discloses a split gate non-volatile memory cell. Figure 1 An example of such a split gate memory cell formed on a semiconductor substrate 12 is shown. A source region 16 and a drain region 14 are formed in the substrate 12 in the form of diffusion regions and define a channel region 18 therebetween. The memory cell includes four conductive gates: a floating gate 22 disposed over and insulated from a first portion of the channel region 18 and a portion of the source region 16; a control gate 26 disposed over and insulated from the floating gate 22; an erase gate 24 disposed over and insulated from the source region 16; and a select gate 20 disposed over and insulated from a second portion of the channel region 18. A conductive contact 10 may be formed to electrically connect to the drain region 14. Since the channel region is formed along a planar surface of the semiconductor substrate, the total area (e.g., width) of the channel region decreases as device geometries decrease. This reduces the current flow between the source and drain regions, thereby requiring a more sensitive sense amplifier or the like to detect the state of the memory cell.

[0005] Because the problem of reducing lithographic dimensions and thereby reducing channel width affects all semiconductor devices, a fin field effect transistor type structure has been proposed. In a fin field effect transistor type structure, a fin-shaped member of semiconductor material connects a source region to a drain region. The fin-shaped member includes two side surfaces that terminate at a top surface. Then, the current from the source region to the drain region can flow along the two side surfaces and the top surface. Therefore, the width of the channel region is increased, thereby increasing the current. However, the width of the channel region is increased by "folding" the channel region into two side surfaces and a top surface without sacrificing more semiconductor substrate surface, thereby reducing the "footprint" of the channel region. Non-volatile memory cells using such fin field effect transistors have been disclosed, in which a floating gate is disposed adjacent to one of the side surfaces of the fin-shaped member. Some examples of prior art fin field effect transistor non-volatile memory structures (although the number and configuration of gates differ from Figure 1 Examples of the above planar structures in the present invention include U.S. Patent Nos. 7,423,310, 7,410,913, and 8,461,640 and U.S. Patent Publication 2017 / 0345,840. It has also been proposed to form logic devices on fin-shaped members. See, for example, U.S. Patent Publication 2017 / 0125,429 and pending U.S. Patent Application 15 / 933,124.

[0006] However, these prior art FinFET structures have disclosed the use of floating gates in a stacked gate configuration, or the use of trapping materials, or the use of silicon rich oxide (SRO) or the use of nanocrystalline silicon to store charge, or other more complex memory cell configurations. Summary of the invention

[0007] The above problems and needs are solved by a memory device, which includes a semiconductor substrate having an upper surface with a plurality of fins extending upward, wherein each of the fins includes a first side surface and a second side surface opposite to each other and terminating at a top surface. A memory cell is formed on a first fin of the plurality of fins. The memory cell includes: a source region and a drain region, the source region and the drain region are spaced apart in a first fin, wherein a channel region of the first fin extends between the source region and the drain region along a top surface and an opposite side surface of the first fin; a floating gate, the floating gate extending along a first portion of the channel region, wherein the floating gate extends along a first side surface and a second side surface and a top surface of the first fin and is insulated from the first side surface and the second side surface and the top surface of the first fin; a select gate, the select gate extending along a second portion of the channel region, wherein the select gate extends along a first side surface and a second side surface and a top surface of the first fin and is insulated from the first side surface and the second side surface and the top surface of the first fin; a control gate, the control gate extending along the floating gate and being insulated from the floating gate; and an erase gate extending along the source region and being insulated from the source region. A second fin among the plurality of fins has a length extending in a first direction, wherein the first fin has a length extending in a second direction perpendicular to the first direction, and wherein a source region is formed in the first fin at an intersection of the first fin and the second fin.

[0008] The memory device includes a semiconductor substrate having an upper surface having a plurality of first fins extending upward and a plurality of second fins extending upward. Each of the first fins and the second fins includes a first side surface and a second side surface opposite to each other and terminating at the top surface. Each of the first fins has a length extending in a first direction. Each of the second fins has a length extending in a second direction perpendicular to the first direction. The first fins intersect the second fins in a grid-like manner. A plurality of memory cells are formed on a first fin, wherein each of the memory cells is formed on one of the first fins and includes: a source region and a drain region, the source region and the drain region being spaced apart in the one first fin, wherein a channel region of the one first fin extends between the source region and the drain region along a top surface and an opposite side surface of the one first fin; a floating gate, the floating gate extending along a first portion of the channel region, wherein the floating gate extends along a first side surface and a second side surface and a top surface of the one first fin and is insulated from the first side surface and the second side surface and the top surface of the one first fin; a select gate, the select gate extending along a second portion of the channel region, wherein the select gate extends along a first side surface and a second side surface and a top surface of the one first fin and is insulated from the first side surface and the second side surface and the top surface of the one first fin; a control gate, the control gate extending along the floating gate and being insulated from the floating gate; and an erase gate, the erase gate extending along the source region and being insulated from the source region, wherein the source region is formed at the intersection of one of the one first fin and the second fin.

[0009] A method for forming a memory device includes: forming a plurality of upwardly extending fins in an upper surface of a semiconductor substrate, wherein each of the fins includes a first side surface and a second side surface opposite to each other and terminating at a top surface; and forming a memory cell on a first fin of the plurality of fins. The memory cell is formed by: forming a source region and a drain region, the source region and the drain region being spaced apart in a first fin, wherein a channel region of the first fin extends between the source region and the drain region along a top surface and opposite side surfaces of the first fin; forming a floating gate, the floating gate extending along a first portion of the channel region, wherein the floating gate extends along a first side surface and a second side surface and a top surface of the first fin and is insulated from the first side surface and the second side surface and the top surface of the first fin; forming a select gate, the select gate extending along a second portion of the channel region, wherein the select gate extends along a first side surface and a second side surface and a top surface of the first fin and is insulated from the first side surface and the second side surface and the top surface of the first fin; forming a control gate, the control gate extending along the floating gate and being insulated from the floating gate; and forming an erase gate, the erase gate extending along the source region and being insulated from the source region. A second fin of the plurality of fins has a length extending in a first direction, wherein the first fin has a length extending in a second direction perpendicular to the first direction, and wherein a source region is formed in the first fin at an intersection of the first fin and the second fin.

[0010] A method for forming a memory device includes: forming a plurality of first fins extending upward and a plurality of second fins extending upward in an upper surface of a semiconductor substrate, wherein each of the first fins and the second fins includes a first side surface and a second side surface opposite to each other and terminating at a top surface, each of the first fins has a length extending in a first direction, each of the second fins has a length extending in a second direction perpendicular to the first direction, and the first fins intersect with the second fins in a grid-like manner. The method also includes: forming a plurality of memory cells on the first fin, wherein each memory cell is formed on one of the first fins by: forming a source region and a drain region, the source region and the drain region being spaced apart in the one first fin, wherein a channel region of the one first fin extends between the source region and the drain region along a top surface and an opposite side surface of the one first fin; forming a floating gate, the floating gate extending along a first portion of the channel region, wherein the floating gate extends along a first side surface and a second side surface and a top surface of the one first fin and is insulated from the first side surface and the second side surface and the top surface of the one first fin; forming a select gate, the select gate extending along a second portion of the channel region, wherein the select gate extends along a first side surface and a second side surface and a top surface of the one first fin and is insulated from the first side surface and the second side surface and the top surface of the one first fin; forming a control gate, the control gate extending along the floating gate and being insulated from the floating gate; and forming an erase gate, the erase gate extending along the source region and being insulated from the source region, wherein the source region is formed at the intersection of one of the one first fin and the second fin.

[0011] Other objects and features of the present invention will become apparent by examining the specification, claims and drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 is a side cross-sectional view of a conventional nonvolatile memory cell.

[0013] Figure 2 is a top view of the memory area, showing the various cross-sectional view orientations of the other figures.

[0014] Figure 3A , Figure 4A , Figure 5A , Fig. 6A , Fig. 7A , Fig. 8A , Fig.9A , Fig. 10A , FIG. 11A to FIG. 11C , FIG. 12A to FIG. 12D , FIG. 13A to FIG. 13D , FIG. 14A to FIG. 14D , FIG. 15A to FIG. 15D , FIG. 16A to FIG. 16D , FIG. 17A to FIG. 17D , 18A to 18D , 19A to 19D , FIG. 20A to FIG. 20D , FIG. 22A to FIG. 22D , FIG. 23A to FIG. 23D , FIG. 24A to FIG. 24D , FIG. 25A to FIG. 25D , FIG. 26A to FIG. 26B , FIG. 27A to FIG. 27B and Fig.28 are side cross-sectional views of different cross-sectional locations and orientations of a memory region, illustrating the steps of forming a memory device of the present invention.

[0015] Figure 3B , Figure 4B , Figure 5B , Figure 6B , Figure 7B , Figure 8B , Fig. 9B , Fig. 10B , Fig.11D , Fig.12E , Fig.13E , Fig.14E , Fig.15E , Fig.16E , Fig.17E , Fig.18E , Fig.19E , Fig.20E , Fig.21 , Fig.22E , Fig.23E , Fig.24E , Fig.25E and Fig.26C is a side cross-sectional view of a logic device area illustrating the steps of forming the memory device of the present invention.

[0016] Fig. 9C is a top view of the memory area showing the vertical and horizontally extending fins of the substrate. DETAILED DESCRIPTION

[0017] The present invention is a memory device having FinFET split-gate memory cells, each cell having four gates: floating gate 28, control gate 30, select gate 32, and erase gate 34. FinFET logic devices are formed on the same substrate as the memory cells. Figure 2 is a top view showing a configuration of a mirror image pair of memory cells in a memory region of a substrate. The memory cells of the mirror image pair share a common source region 36 (i.e., a region of the substrate having a second conductivity type different from the first conductivity type of the substrate), wherein a drain region 38 (of the second conductivity type) is shared between adjacent pairs of memory cells (not shown). The substrate includes intersecting fin-shaped portions 40 and 41 of an upper surface of a semiconductor substrate 42. The memory cells are formed on the fin-shaped portions 40. Figure 2 Also shown are the cross-sectional view directions a, b, c and d for the subsequently described figures.

[0018] The manufacturing process begins by selectively implanting different regions of a semiconductor substrate 42. Figure 3A and Figure 3B It is shown in (that is, Figure 3A and Figure 3B 4 (showing different regions of the same substrate 42), where the substrate has four regions associated with memory cells and logic devices: a memory region 42a (wherein memory cells are formed), an HV region 42b (wherein high voltage logic devices are formed), a logic core region 42c (wherein core logic devices are formed), and a logic IO region 42d (wherein input / output logic devices are formed). Regions 42b, 42c, and 42d are collectively referred to herein as logic regions. Preferably, the selective implant begins by covering the substrate except for the HV region with a mask material, which is subjected to one or more implant steps (e.g., an anti-punch-through implant that will prevent source-to-drain leakage in the high voltage logic device formed in that region). This can be repeated for the memory region (e.g., covering other regions with a mask material and performing an anti-punch-through implant that will prevent source-to-drain leakage in the memory cells formed in that region).

[0019] Then, the upper surface of the memory region of the substrate is recessed (lowered) compared to the logic region of the substrate 42, as shown in FIG. Figure 4A and Figure 4B As shown. This is preferably accomplished by forming a layer of material (e.g., silicon nitride) on substrate 42, followed by a masking step (i.e., photoresist deposition, selective photolithography exposure, and selective photoresist removal) to leave photoresist on the silicon nitride in the logic area, but leaving the silicon nitride exposed in the memory area. Silicon nitride etching is used to remove the silicon nitride from the memory area, exposing the substrate surface. The exposed portion of substrate 42 (in the memory area) is oxidized, followed by a wet oxide etch to remove the oxidized portion of the substrate, which effectively removes the top portion of the substrate (effectively lowering / depressing its upper surface). These steps can be repeated until a desired level of surface depression R is achieved (e.g., 300nm to 500nm). A nitride etch is then used to remove the nitride.

[0020] Fins are then formed in the upper surface of the substrate. Specifically, cross-fins are formed in the memory region, while parallel fins are formed in the logic region. A silicon dioxide (oxide) layer 46 is formed on the upper surface of the substrate 42 in all four regions (memory region, HV region, logic core region, and logic IO region). A silicon nitride (nitride) layer 48 is formed on the oxide layer 46. A hard mask material (e.g., amorphous carbon) 50 is formed on the nitride layer 48. A photoresist 52 is formed on the hard mask material and patterned using a masking step to expose strips of the hard mask material, such as Figure 5A and Figure 5B Etching is performed to remove the exposed portions of the hard mask material, leaving Fig. 6A and Figure 6B Strips of hard mask material are shown (after photoresist removal).

[0021] An oxide layer 54 is formed over the structure. This layer is conformal in the logic region because the spacing between the hard mask material strips is greater than the spacing in the memory region (where the layer fills the spaces between the hard mask material strips), as shown in FIG. Fig. 7A and Figure 7B Next, an anisotropic oxide etch is performed, which leaves spacers on the vertical sidewalls of the hard mask strips. A carbon wet strip etch is used to remove the carbon hard mask material, as shown in FIG. Fig. 8A and Figure 8B The memory area Fig. 6A The spacing between two adjacent patterns in is preferably less than or equal to twice the thickness of the oxide layer 54, so as to form Fig. 8A The merged spacers shown. A photoresist is formed over the structure and patterned to leave strips of photoresist that cover the alternating oxide spacers / blocks in the memory area and possibly cover portions of the oxide spacers in the logic area. An oxide etch is then used to remove those remaining oxide spacers exposed by the photoresist. After the photoresist is removed, one or more etches are performed to remove those portions of the nitride 48, oxide 46, and upper portions of the substrate 42 that are not beneath the oxide spacers, which results in the formation of trenches 56 that extend into the substrate and a thin fin structure 58 of the substrate 42 between adjacent trenches 56. The fins 58 extend in both the vertical / column direction and the horizontal / row direction in the memory area. The resulting structure is shown in FIG. FIG. 9A to FIG. 9B in (after removing the oxide spacers). Fig. 9C A top view of a memory region is shown, wherein fins 58 extend in a grid pattern in the row and column directions (i.e., vertically extending fins having a length extending in the column direction intersect with horizontally extending fins having a length extending in the row direction in a grid-like manner). In the memory region, the final width of each fin 58 may be approximately 10 nm to 50 nm.

[0022] Although Fig. 9B Only one fin 58 in each of the HV region, the logic core region, and the logic IO region is shown, and Fig.9AOnly two fins 58 are shown in the memory region, but multiple fins are formed in each region. Although not shown, the spacing between the fins will vary based on the region. For example, the distance between adjacent fins in the logic core region is preferably about half the distance separating adjacent fins in the memory region. An insulating material 60 (e.g., oxide) is formed over these structures (including filling the trenches 56 with oxide 60), followed by oxide planarization (e.g., CMP) to remove any portion of the oxide 60 on top of the nitride 48. A hard mask layer (e.g., nitride) 62 is formed over the logic region but not over the memory region. An oxide etch is then used to recess the oxide 60 in the memory region (i.e., remove the upper portion of the oxide). The resulting structure is Fig. 10A and Fig. 10B Shown in.

[0023] The nitride 48 and oxide 46 on top of the fins 58 in the memory area are removed (photoresist is used to protect the nitride layer 62 in the logic area). An oxide layer 64 is then formed on both side surfaces and the top surface of each fin 58 in the memory area (e.g., by oxidation). A polysilicon (poly) conformal layer 66 is then formed over the structure (including over the oxide 64), such as FIG. 11A to FIG. 11D As shown. In-situ doping of the polysilicon layer 66 is then performed. A masking step and polysilicon etching are performed to remove selected portions of the polysilicon layer 66 in the bottom of the trench 56 in the memory area (between the fins 58), as shown. FIG. 12A to FIG. 12E An insulating layer 67 (e.g., ONO with oxide-nitride-oxide sublayers) is formed over these structures. A thick layer of polysilicon 68 is then formed over the ONO layer 67 (which may be subjected to in-situ doping). A hard mask layer 69 (e.g., amorphous carbon) is then formed over the polysilicon layer 68. The resulting structure is shown in FIG. 13A to FIG. 13E middle.

[0024] A masking step and one or more etches are performed to remove selected portions of the hard mask layer 69, the polysilicon layer 68, and the ONO layer 67 along the top of the fins 58 in the memory region, thereby leaving a pair of gate stacks S1 and S2 on the top surface of each fin 58 in the memory region, as shown in FIG. FIG. 14A to FIG. 14E HTO deposition and annealing are performed to form an oxide layer 70 along the sides of the gate stacks S1 and S2. Nitride deposition and etching are performed to form a nitride layer 71 along the oxide layer 70. Sacrificial oxide spacers 72 are formed along the nitride layer 71 by oxide deposition and etching. The resulting structure is shown in FIG. 15A to FIG. 15E middle.

[0025] A photoresist 74 is formed between each of the gate stack pair S1 and S2 using a masking step. A WLVT implant is then performed, followed by an oxide etch, to remove the oxide spacers 72 on the outside of the stack pair S1 and S2, as shown in FIG. FIG. 16A to FIG. 16E After removing the photoresist, a polysilicon etch is used to remove the exposed portion of the floating gate polysilicon layer 66 (from between stack S1 and stack S2), as shown in FIG. FIG. 17A to FIG. 17E Then, oxide spacers 75 are formed along the sides of stacks S1 and S2 by oxide deposition and etching, as shown in FIG. 18A to 18E As shown. A photoresist is selectively formed on portions of the memory region using a masking step, and then etching is performed to remove the hard mask 69, polysilicon layers 68 and 66, and ONO layer 67 from selected portions of the logic region and the memory region. After removing the photoresist, a masking step is used to cover the structure except the HV region with photoresist, which is subjected to oxide and nitride etching to remove the nitride and oxide on the fin 58 and recess the oxide 60 on either side of the fin 58. An oxide layer 80 is then formed on the exposed fin 58 in the HV region (e.g., RTO+HTO and annealing) and the memory region, as shown. FIG. 19A to FIG. 19E shown.

[0026] A masking step is used to cover the structure except for the area between each of the gate stack pairs S1 and S2 with photoresist. Implantation is performed in the substrate between each of the gate stack pairs S1 and S2 (i.e., source line implantation for forming source lines SL, i.e., source regions as shown in cross section b; and source lines in fins 58 extending in the horizontal / row direction as shown in cross sections a and c). Oxide etching is then used to remove the spacers 75 and 72 in the same area, followed by formation of a tunnel oxide layer 84 on the exposed surface of the polysilicon layer 66 and the inner sidewalls of the gate stacks S1 and S2 (e.g., by wet or partial wet deposition to thicken the oxide on the substrate, followed by HTO deposition to achieve the desired thickness on the polysilicon layer 66), as shown in FIG. FIG. 20A to FIG. 20E shown (after removing the photoresist).

[0027] The memory area and the HV area are covered with photoresist PR, and the logic core area and the logic IO area are subjected to oxide etching to recess the oxide 60, as shown in FIG. Fig.21 As shown. One or more implants are then performed (which preferably include an anti-punch-through implant that will prevent source-to-drain leakage in the logic devices formed in these regions). After removing the photoresist, a photoresist PR is formed in the region between the gate stacks S1 and S2 and each of the logic regions, followed by an oxide etch to remove oxide on the substrate fins 58 that is outside the stack pair, as shown. FIG. 22A to FIG. 22EAs shown. A photoresist is then formed on the memory region and the HV region, followed by oxide and nitride etching to remove the oxide and nitride on the fin 58. An oxide 86 is then formed on the exposed fins 58 in the logic core region and the logic IO region (and other exposed portions of the substrate 42), as shown. FIG. 23A to FIG. 23E The oxide 86 on the fin 58 in the logic core region and the logic IO region is thinner than the oxide 80 on the fin in the HV region.

[0028] A polysilicon layer 88 is formed on these structures, such as FIG. 24A to FIG. 24E Chemical mechanical polishing (CMP) is used to remove the upper portion of the structure and planarize the structure, as shown in FIG. FIG. 25A to FIG. 25E The masking step and polysilicon etching are used to remove a portion of the polysilicon layer 88 between adjacent pairs of gate stacks, thereby leaving polysilicon blocks 88a between each of the gate stacks S1 and S2, and leaving polysilicon blocks 88b and 88c on the outer portions of each pair of gate stacks S1 and S2, as shown in FIG. Fig.26A and Fig.26B The polysilicon etch also removes portions of the polysilicon layer 88 on the fins 58 in the logic region, leaving polysilicon blocks 88d, as shown. Fig.26C The substrate is selectively implanted in logic areas using one or more masking and implanting steps.

[0029] One or more implants are performed to form source and drain regions in substrate 42 for memory cells and logic devices. Specifically, memory cell drain region 38 is formed adjacent to polysilicon blocks 88b and 88c. Logic source and logic drain regions are formed in the HV, logic core, and logic IO regions adjacent to the remaining polysilicon block 88d. An insulating layer (e.g., oxide) 98 is formed over these structures and planarized (e.g., by CMP using polysilicon block 88 as a grinding stop). Self-aligned polycrystal silicide 100 is preferably formed on the exposed surfaces of polysilicon blocks 88 and 68. The resulting structure is Fig.27A and Fig.27B Shown in.

[0030] Additional insulating material is formed over the structure. Contact holes are formed in the insulating material that extend to and expose the drain region 38 and the polysilicon blocks 88 and 68. Preferably, the source and drain regions of the fins for the drain regions of the logic device and the memory cell may be at least partially etched away, followed by a SiGe (for PFet devices) or SiC (for NFet devices) epitaxial process to form a raised drain region 38a for the memory cell and a raised source and drain region for the logic device, which induces compressive stress or tensile stress that improves mobility (i.e., reduces series resistance). The contact holes are then filled with metal to form metal contacts 110 electrically connected to the drain region 38 and the polysilicon blocks 88 and 68, as shown in FIG. Fig.28 shown.

[0031] The final structure on fin 58 in memory region 42a is Fig.28 . The memory cell pairs are formed end to end along each fin 58. Each memory cell includes a channel region 112 of the substrate extending between the source region 36 and the drain region 38 (i.e., those portions of the substrate along the two side surfaces and the top surface of the fin 58 between the source region / drain region 36 / 38). Polysilicon 66 is a floating gate 28, which is disposed over and insulated from a first portion of the channel region 112. Polysilicon 68 is a control gate 30, which extends over and insulated from the floating gate 28. Polysilicon 88b / c is each a select gate 32, each of which is disposed over and insulated from a second portion of the channel region 112. Polysilicon 88a is each an erase gate 34, each of which is adjacent to and insulated from a pair of floating gates 28, and is over and insulated from the source region 36. The erase gate 34 includes a notch facing the corner of the floating gate. The fin 58 has two opposing side surfaces and a top surface. The floating gate 28 is wrapped around the fin 58 so that it is adjacent to and insulated from the two opposing side surfaces and the top surface of the fin 58. The select gate 32 is also wrapped around the fin 58 so that it is adjacent to and insulated from the two opposing side surfaces and the top surface of the fin 58. Therefore, one advantage of the present configuration is that the surface area of ​​the channel region 112 is larger in size relative to a memory cell of equal size above a planar channel region (i.e., the amount of surface overlap between the floating gate and the select gate and the substrate is greater than the horizontal area of ​​the substrate occupied by these elements).

[0032] The final structures on and around the fins 58 in the HV region 42b, the logic core region 42c, and the logic IO region 42d are similar in that the gates are each wrapped around a respective fin 58 so that they are adjacent to and insulated from two opposing side surfaces and the top surface of the fin 58. Thus, another advantage of the present configuration is that the surface area of ​​the channel region of each of the logic devices is larger in size relative to an equal sized logic device above a planar channel region (i.e., the amount of surface overlap between the logic gate and the substrate is greater than the horizontal area of ​​the substrate occupied by the element). For higher voltage operation, the gate oxide 80 in the HV region is thicker than the gate oxide 86 in the other logic regions. Each logic device includes a logic source region and a logic drain region with a logic channel region therebetween.

[0033] Other advantages include that conformal gates wrapped around the top and both side surfaces of the fin 58 are formed in both the memory region (i.e., floating gate and select gate) and the logic region (i.e., logic gate). In addition, by recessing the fin in the memory region, the top of the memory cell and the logic device are approximately equal to each other even if the gate stack of the memory cell is higher than the logic gate of the logic device. In addition, the memory cell and the three different types of logic devices are all formed on the fin-shaped substrate structure of the same semiconductor substrate, where each memory cell is formed on a single fin and each logic device is formed on a single fin, which enables the inter-fin spacing to be reduced.

[0034] Finally, each of the source lines SL extends along one of the horizontally extending fins 58 and through a row of memory cells, thereby providing a continuous source line that extends across the isolation region between adjacent cells (in the row direction). This allows the cells to be scaled down to smaller sizes because this configuration does not require the formation of source line contacts for each pair of memory cells. Instead, the continuous source line extending along the fins can be electrically connected to the strips through periodic strip contacts (e.g., every 32 or 64 columns). By having a contact once every 32 or 64 columns instead of once per column, the size of the memory cells, and therefore the memory array of memory cells, can be significantly reduced.

[0035] It should be understood that the present invention is not limited to the embodiments described above and shown herein, but encompasses any and all variations within the scope of any claims supported thereby. For example, reference to the present invention herein is not intended to limit the scope of any claim or claim term, but only to refer to one or more features that may be covered by one or more claims. The examples of materials, processes, and numerical values ​​described above are exemplary only and should not be considered to limit any claim. In addition, not all method steps need to be performed in the exact order shown. The fin may extend continuously between the memory area and the logic area. For example, one or more fins in a memory area (on which a memory cell is formed) may extend continuously out of the memory area and into the logic area (on which a logic device is formed), in which case the memory device and the logic device may be formed on the same continuously formed fin. Finally, a single material layer may be formed as a plurality of such or similar material layers, and vice versa.

[0036] It should be noted that, as used herein, the terms "above" and "on" both include inclusively "directly on" (without intermediate materials, elements, or spaces disposed therebetween) and "indirectly on" (with intermediate materials, elements, or spaces disposed therebetween). Similarly, the term "adjacent" includes "directly adjacent" (without intermediate materials, elements, or spaces disposed therebetween) and "indirectly adjacent" (with intermediate materials, elements, or spaces disposed therebetween), "mounted to" includes "mounted directly to" (without intermediate materials, elements, or spaces disposed therebetween) and "mounted indirectly to" (with intermediate materials, elements, or spaces disposed therebetween), and "electrically coupled to" includes "directly electrically coupled to" (without intermediate materials or elements electrically connecting the elements together) and "indirectly electrically coupled to" (with intermediate materials or elements electrically connecting the elements together). For example, forming an element "above a substrate" may include forming the element directly on the substrate without intermediate materials / elements therebetween, and indirectly forming the element on the substrate with one or more intermediate materials / elements therebetween.

Claims

1. A memory device, comprising: A semiconductor substrate having an upper surface, wherein the upper surface has a plurality of first fins extending upward, a plurality of second fins extending upward, and a plurality of third fins extending upward, wherein: Each of the first fin, the second fin, and the third fin includes a first side surface and a second side surface that are opposite to each other and terminate at a top surface, Each of the plurality of third fins extends higher than each of the plurality of first fins and each of the plurality of second fins relative to the substrate, Each of the first fins has a length extending in a first direction, Each of the second fins has a length extending in a second direction perpendicular to the first direction, and The first fin intersects the second fin in a grid-like manner; a plurality of memory cells, each of the plurality of memory cells being formed on one of the first fins and comprising: a source region and a drain region, the source region and the drain region being spaced apart in the one first fin, wherein a channel region of the one first fin extends between the source region and the drain region along the top surface and the opposite side surface of the one first fin, wherein the source region is formed at an intersection of the one first fin and one of the second fins, a floating gate extending along a first portion of the channel region, wherein the floating gate is wrapped around the one first fin so that the floating gate extends along and is insulated from the first side surface, the second side surface, and the top surface of the one first fin, a select gate extending along a second portion of the channel region, wherein the select gate is wrapped around the one first fin so that the select gate extends along and is insulated from the first side surface, the second side surface, and the top surface of the one first fin, a control gate extending along the floating gate and insulated from the floating gate, and an erase gate extending along the first side surface, the second side surface and the top surface of the one first fin and being insulated from the first side surface, the second side surface and the top surface of the one first fin, and extending along the first side surface, the second side surface and the top surface of the one second fin and being insulated from the first side surface, the second side surface and the top surface of the one second fin, A plurality of logic devices, each logic device being formed on one of the third fins and comprising: a logic source region and a logic drain region, the logic source region and the logic drain region being spaced apart in the one third fin, wherein a logic channel region of the one third fin extends between the logic source region and the logic drain region along the top surface and the opposing side surface of the one third fin, and A logic gate extending along the logic channel region, wherein the logic gate is wrapped around the one third fin so that the logic gate extends along the first side surface, the second side surface and the top surface of the one third fin and is insulated from the first side surface, the second side surface and the top surface of the one third fin.

2. The memory device of claim 1, wherein the memory cells are arranged in rows extending in the second direction and in columns extending in the first direction, and wherein each of the second fins electrically connects the source regions of a row of the memory cells together.

3. The memory device of claim 1, wherein for each of the memory cells, the erase gate extends along and is insulated from an upper edge of the floating gate and includes a notch facing the upper edge of the floating gate.

4. The memory device according to claim 1, wherein one of the logic gates is insulated from one of the third fins by a first insulating material, another of the logic gates is insulated from another of the third fins by a second insulating material, and a thickness of the first insulating material is greater than a thickness of the second insulating material.

5. A method of forming a memory device, the method comprising: A plurality of first fins extending upward, a plurality of second fins extending upward, and a plurality of third fins extending upward are formed in an upper surface of a semiconductor substrate, wherein: Each of the first fin, the second fin, and the third fin includes a first side surface and a second side surface that are opposite to each other and terminate at a top surface, Each of the plurality of third fins extends higher than each of the plurality of first fins and each of the plurality of second fins relative to the substrate, Each of the first fins has a length extending in a first direction, Each of the second fins has a length extending in a second direction perpendicular to the first direction, and The first fin intersects the second fin in a grid-like manner; A plurality of memory cells are formed on the first fin, wherein each memory cell is formed on one of the first fins by: forming a source region and a drain region, the source region and the drain region being spaced apart in the one first fin, wherein a channel region of the one first fin extends between the source region and the drain region along the top surface and the opposite side surface of the one first fin, wherein the source region is formed at an intersection of the one first fin and one of the second fins, forming a floating gate extending along a first portion of the channel region, wherein the floating gate is wrapped around the one first fin so that the floating gate extends along and is insulated from the first side surface, the second side surface, and the top surface of the one first fin, forming a select gate extending along a second portion of the channel region, wherein the select gate is wrapped around the one first fin so that the select gate extends along and is insulated from the first side surface, the second side surface, and the top surface of the one first fin, forming a control gate extending along the floating gate and insulated from the floating gate, and forming an erase gate extending along the first side surface, the second side surface and the top surface of the one first fin and being insulated from the first side surface, the second side surface and the top surface of the one first fin, and extending along the first side surface, the second side surface and the top surface of the one second fin and being insulated from the first side surface, the second side surface and the top surface of the one second fin, A plurality of logic devices are formed on the third fins, wherein each logic device is formed on one of the third fins in the following manner: forming a spaced-apart logic source region and a logic drain region in the one third fin, wherein a logic channel region of the one third fin extends between the logic source region and the logic drain region along the top surface and the opposite side surface of the one third fin, and A logic gate extending along the logic channel region is formed, wherein the logic gate is wrapped around the one third fin so that the logic gate extends along the first side surface, the second side surface and the top surface of the one third fin and is insulated from the first side surface, the second side surface and the top surface of the one third fin. 6 . The method of claim 5 , wherein the memory cells are arranged in rows extending in the second direction and in columns extending in the first direction, and wherein each of the second fins electrically connects the source regions of a row of the memory cells together.

7. The method of claim 5, wherein for each of the memory cells, the erase gate extends along and is insulated from an upper edge of the floating gate and includes a notch facing the upper edge of the floating gate.

8. The method according to claim 5, wherein one of the logic gates is insulated from one of the third fins by a first insulating material, another of the logic gates is insulated from another of the third fins by a second insulating material, and a thickness of the first insulating material is greater than a thickness of the second insulating material.

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