Memory device and method for executing security commands

Abstract

The present invention provides a memory device and method for executing a security command. The memory device includes: a security command decoder, and an input / output interface. The security command decoder implements security logic, the security logic is used to detect a command carrying an encrypted real-time data payload from a requesting host, authenticate the host as the source of the command, decode the real-time data and use the non-command portion of the decrypted real-time data to execute a memory access command required by the command portion of the decrypted real-time data on a storage unit of the memory device, and encrypt any result from executing the command portion before returning the result to the requesting host. The input / output interface is used to input / output data units and supports multiple hosts.

Description

Technical Field

[0001] The present invention belongs to the field of storage technology, and relates to a memory device and method for executing security commands, and more particularly to an integrated circuit memory device that supports secure storage and retrieval, such as a flash memory device, and more specifically, to a security command decoder for providing secure storage and retrieval from the memory. Background Art

[0002] In modern information storage technology, many different types of memory architectures have been established, each providing storage of digital (multi-bit) data and addressing different needs and requirements of various applications. For example, flash memory devices, resistive RAM (ReRAM), erasable programmable read-only memory (EPROM), phase-change memory (PCM), etc. can be used to store digital data in various applications.

[0003] Digital data is easy to store and transmit, and easy to access, however, this makes security-sensitive data stored as digital data susceptible to interception and theft by unauthorized parties.

[0004] In view of the above, it is desirable to provide a mechanism for more securely storing digital data. Summary of the invention

[0005] The memory device includes a secure command decoder that implements security logic to detect a command carrying an encrypted real-time data payload from a requesting host, authenticate the host, decode the real-time data for the authenticated host, and use the non-command portion of the decrypted real-time data to execute the memory access command required by the command portion of the decrypted real-time data on the storage unit of the memory device. The command decoder circuit can also decode unencrypted commands. Some embodiments also encrypt any results from executing the command portion before returning the results to the requesting host. The input / output interface for the I / O (input / output) data unit supports transactions with multiple hosts. The input / output interface may include a serial interface (e.g., a bus serial bus interface (SPI)) or a parallel interface. The technology provides encryption of significant input parameters such as command codes, addresses, byte counts, options, etc., so that the device implementing the technology can protect sensitive information from being detected by unauthorized third parties. In addition, the technology described herein can provide authentication data to the requesting host.

[0006] In a representative secure command mechanism implementation scheme, a multi-step command decoding process is used. In the first step, a command decoder receives a command from a host. The command decoder detects that the received command carries an encrypted real-time data "payload". The real-time data may include one or more commands, addresses, any valid input parameters, and data for performing operations on the memory of the access device. In response to the host, the command decoder performs authentication decryption to authenticate information originating from the host and recovers the memory access command, address, and valid input parameters and data contained in the real-time data payload. In the second step, if the authentication in the first step is successful, the decryption command is decoded and the decryption command is executed using the address decrypted from the real-time data and the decrypted input parameters.

[0007] A representative embodiment includes a circuit for decoding a novel command sequence. An exemplary command decoder circuit receives a command sequence including a command code field and an intermediate data payload. The command decoder circuit decodes the command code field, the command code field including an operation code (op code), the operation code indicating one of (i) an unencrypted command and (ii) a secure command, wherein the intermediate data payload includes an encrypted memory access command operation code, an encrypted address field, and one or more encrypted input variables, the encrypted address field indicating one or more locations to read data from a memory, the encrypted input variables including an encrypted result indicator. The secure logic circuit has an encryption / decryption circuit, and when the operation code indicates a secure command, the encryption / decryption circuit encrypts data read from a memory, the encrypted memory access command operation code indicates a read from a memory, and the encrypted result indicator of the one or more encrypted input variables displays the encryption result.

[0008] Another representative embodiment includes a circuit for decoding a novel command sequence. Another exemplary command decoder circuit receives a command sequence including a command code field and an intermediate data payload. The command decoder circuit decodes the command code field, the command code field including an operation code, the operation code indicating one of (i) an unencrypted command and (ii) a secure command, wherein the intermediate data payload includes an encrypted memory access command operation code, an encrypted address field, encrypted data, and one or more encrypted input variables, the encrypted address field indicating one or more locations in memory where data is to be written, the encrypted input variables including an encrypted result indicator. The secure logic circuit has an encryption / decryption circuit, and when the operation code indicates a secure command, the encryption / decryption circuit encrypts a return code generated by writing data to memory, the encrypted memory access command operation code indicating writing to memory, and the encrypted result indicator of the one or more encrypted input variables indicating the encrypted result.

[0009] In a representative embodiment, a memory device includes a memory array including a plurality of bit lines, an input / output interface for an I / O data unit, a data path circuit connected between the memory array and the input / output interface, and a command decoder circuit. The command decoder circuit receives secure and unsecure commands at the input / output interface. The secure logic circuit decrypts the encrypted real-time data payload when the secure command operation code is received to obtain the decrypted information, and performs a memory operation corresponding to the decrypted information. Some embodiments will include a secure logic circuit that authenticates whether the host is an identified host in response to an input tag received using the secure command operation code. The implementation of the command decoder is also capable of decoding unsecure commands.

[0010] The disclosed techniques are applicable to all types of memories having a command interface. Example embodiments are described where the memory array includes a flash memory device, however, the techniques described herein may also be applied to other types of memory devices. Some embodiments implement the secure command decoder mechanism in a NOR flash memory. Other embodiments implement the secure command decoder mechanism in a NAND flash memory. Still other embodiments implement the secure command decoder mechanism in a memory that is not a flash memory.

[0011]

[0013] Other embodiments and advantages of the techniques described herein will become apparent after reference to the following figures, detailed description, and claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1A is a simplified block diagram of an integrated circuit memory device with a secure command decoder mechanism according to an embodiment.

[0013] Figure 1Bis a simplified block diagram of an integrated circuit memory device with a secure command decoder mechanism according to another embodiment.

[0014] Figure 2 To illustrate the use of Figure 1A and Figure 1B FIG. 1 is a diagram of a data flow for a write operation of an embodiment of an integrated circuit memory device having a secure command decoder mechanism.

[0015] Figure 3 To illustrate the use of Figure 1A and Figure 1B FIG. 1 is a diagram of a data flow for a read operation of an embodiment of an integrated circuit memory device having a security command decoder.

[0016] Figure 4 To illustrate the use of Figure 1A and Figure 1B Flowchart of the operating mode of the secure command decoder of a system as described herein.

[0017] Figure 5 To illustrate the use of Figure 1A and Figure 1B FIG. 2 is a diagram of a data flow for a block encryption counter mode of a secure command decoder of a system as described herein.

[0018] Figure 6 To illustrate the use of Figure 1A and Figure 1B Flowchart of the block encryption counter mode operation of the security command decoder of the system as described herein.

[0019] Figure 7 To illustrate the use of Figure 1A and Figure 1B Flowchart of a process for a system of the invention for generating an authentication tag for verifying data integrity using a block encryption counter mode operation as described herein.

[0020] Figure 8 To illustrate the use of Figure 1A and Figure 1B A flowchart of a process of a system for operating a memory device as described herein for executing security commands.

[0021]

Explanation of symbols

[0022] 11: State Machine

[0023] 14: Address Generator

[0024] 15: Clock generator

[0025] 17: High voltage generator

[0026] 19: Sense Amplifier

[0027] 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39: Process

[0028] 71: Output buffer

[0029] 81: Data register

[0030] 82: SRAM buffer

[0031] 84, 85, 91, 184, 185, 191: Data bus

[0032] 91a: Security Command

[0033] 91b: Encrypted payload

[0034] 92: Input tag

[0035] 93a: Encrypted memory access command

[0036] 93b: Encrypted address information

[0037] 93c: Encrypted input variable

[0038] 93d: Encrypted data

[0039] 94a: Memory access command

[0040] 94b: Address

[0041] 94c: Input variables

[0042] 94d: Data

[0043] 95: Output payload

[0044] 97A~97N:Host A~Host N

[0045] 98: Output tag (authentication tag)

[0046] 99: Output data

[0047] 100: Integrated circuit memory device

[0048] 105: Interface

[0049] 108: Command decoder circuit

[0050] 110: Control Logic

[0051] 112: Safety logic circuit

[0052] 114: Encryption / decryption circuit

[0053] 116: Key management circuit, key

[0054] 118: Additional authentication data (associated data)

[0055] 402, 404, 406, 408, 410, 412, 414, 601, 602, 603, 604, 605, 606, 701, 702, 703, 704, 705, 801, 802, 803, 804: Steps

[0056] 120: Bias configuration state machine

[0057] 122: Initialization Vector (IV), Initialization Vector Circuit

[0058] 124: Plaintext buffer

[0059] 124a, 124b: plaintext blocks

[0060] 126: Ciphertext buffer

[0061] 126a, 126b: Ciphertext blocks

[0062] 128: Label check circuit

[0063] 130, 175, 176: Bus

[0064] 140: Address decoder

[0065] 141: X-Decoder

[0066] 143: Y-decoder

[0067] 145: Word Line

[0068] 160: Memory array, memory

[0069] 165: Bit line

[0070] 171: Sense Amplifier / Buffer

[0071] 181: Buffer BUF_A

[0072] 182: Buffer BUF_B

[0073] 195: I / O ports

[0074] 200, 300, 500: Data flow diagram

[0075] 400, 600, 700, 800: Flowchart

[0076] 501a: Counter 0

[0077] 501b: Counter 1

[0078] 501c: Counter 2

[0079] 502: Block encryption operation

[0080] 504: Circuit

[0081] 506: Cascade Operation DETAILED DESCRIPTION

[0082] In order to make the objectives, technical solutions and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with specific embodiments and with reference to the accompanying drawings.

[0083] refer to Figure 1A , Figure 1B , Figure 2 , Figure 3 , Figure 4 , Figure 5 , Figure 6 , Figure 7 as well as Figure 8 A detailed description of embodiments of the present invention is provided.

[0084] Figure 1A and Figure 1B (collectively referred to as FIG. 1 ) is a simplified block diagram of an embodiment of an integrated circuit memory device having a secure command decoder mechanism. The integrated circuit memory device 100 includes a memory array 160 on an integrated circuit substrate, the memory array 160 including multi-level cells MLC, each cell in the multi-level cells MLC can store two or more bits of data (each cell in the triple-level cells TLC can store 3 bits of data). The memory array 160 can be a flash memory implemented using two-dimensional or three-dimensional array technology. One embodiment of the memory array 160 stores data in an unencrypted (plain text) format, but will provide data in an encrypted (ciphertext) form according to the disclosed technology. An alternative embodiment of the memory array 160 stores data in an encrypted (ciphertext) form. The memory device as described herein can also be implemented using multi-chip modules, stacked chips, and other configurations. The memory device can be implemented on a single integrated circuit chip, on a multi-chip module including one or more integrated circuits in a common package, or on multiple chips to suit a particular need.

[0085] The integrated circuit memory device 100 has a command decoder circuit 108 and a control logic 110 and a security logic circuit 112, and the integrated circuit memory device 100 includes logic, such as a state machine, which performs secure memory access operations as described herein in response to received commands. The command decoder circuit 108 responds to commands received at the input / output interface to decode command information received from the host A 97A to the host N 97N, wherein the command information includes a secure memory command (also referred to as a security command), and the secure memory command includes encrypted information. The security logic circuit 112 decrypts the security command detected by the control logic 110, authenticates the host A 97A to the host N 97N that issued the security command, and encrypts the data generated by the memory array 160 executing the decrypted security command. The control logic 110 outputs control signals represented by arrows in the figure and is addressed on the bus 130. The addressing applied on bus 130 may include, for example, the output of address generator 14 and / or an address counter in control logic 110 (not shown in FIG. 1 for clarity), or an address carried in an immediate data payload decrypted by a secure command received by an authenticated host.

[0086] The security logic circuit 112 includes an encryption / decryption circuit 114 that implements one or more encryption algorithms that can be implemented using IP cores, programmable logic, and processors, circuits, or a combination thereof. Some examples of encryption algorithms include, but are not limited to, Authenticated Encryption Standard (AES) in Galois / Counter Mode (GCM) mode (i.e., AES-GCM), Authenticated Encryption Standard with Counter in Cipher Block Chaining Message Authentication Code (CBC-MAC) mode (i.e., AES-CCM), or the like. For background information on AES-GCM and AES-CCM, reference may be made to NIST Special Publication 800-38D entitled "Recommendation for Block Cipher Modes of Operation: Galois / Counter Mode (GCM) and GMAC" ( / / nvlpubs.nist.gov / nistpubs / Legacy / SP / nistspecialpublication800-38d.pdf), Internet Engineering Task Force IETF RFC 5288 ( / / tools.ietf.org / html / rfc5288), and Internet Engineering Task Force IETF RFC 5084 ( / / tools.ietf.org / html / rfc5084), respectively; all of which are incorporated herein by reference for all purposes. Block ciphers implementing AES such as Galois Counter Mode (GCM) perform encryption and decryption operations on fixed-length strings of bits. The length of this string of bits is called the "block size" and a size of 128 bits (16 bytes) is used for implementation. However, example encryption and decryption implementations of the disclosed technology can support blocks and key sizes of 128, 192, and 256 bits.

[0087] The key management circuit 116 generates and stores keys to be used in secure memory operations with Host A 97A-Host N 97N. Although an example using symmetric keys is used herein, the disclosed technology does not require symmetric keys and implementations using public key configurations are within the scope of the operation. Keys may be provided to Host A 97A-Host N 97N using a Diffie-Hellman key exchange pre-installed by the manufacturer, locally generated by a random number generator, a combination of these, and other key exchange protocols. For background information on a particular variant of the Diffie-Hellman key exchange, reference may be made to Internet Engineering Task Force IETF RFC 2631 ( / / tools.ietf.org / html / rfc2631); the entire contents of said reference are incorporated herein by reference for all purposes.

[0088] In the illustrated embodiment, a set of parameter registers is included in the memory device 100 and is coupled to the control logic 110 and the security logic circuit 112. The parameter registers in the set may store parameter inputs and outputs for a plurality of cryptographic and security-related program operations that may be selected according to the processes described herein. For example, the parameter registers may store a key 116, additional authentication data 118 (AAD), an initialization vector 122, and input tags 92 and output tags 98 for providing authenticated secure communications with an authenticator. In addition, the parameter registers may store key generation and pairing, block details such as pulse height, pulse width, and pulse magnitude increments used in cryptographic algorithms such as the incremental stepped pulse programming (ISPP) algorithm.

[0089] Plain text buffer 124 stores plain text, which includes (i) output data from a decryption process performed on a secure command ciphertext as input or (ii) input data from the result of a decrypted operation performed on memory array 160. Plain text buffer 124 is sized to accommodate a block of input plain text to be encrypted or the output of decrypted plain text in a block of data, depending on the amount of data that can be encrypted or decrypted by encryption / decryption circuit 114. In an embodiment implementing Galois Counter Mode (GCM), block ciphers are defined to have a block size of 128 bits (16 byte groups).

[0090] Additional authentication data 118 includes input parameters, identifiers, counter values, and any other fields that indicate how plain text input is to be processed. For example, within a network protocol, AAD may include addresses, ports, sequence numbers, protocol version numbers, and other fields that indicate how plain text should be processed. In another example, AAD may include authenticated but unencrypted input data for an authenticated encryption function. Figure 5 , Figure 7 Further description of using AAD for authenticating a host as a source of information is provided. For additional details, reference may be made to NIST Special Publication 800-38D entitled "Recommendations for Block Encryption Modes of Operation: Galois / Counter Mode (GCM) and GMAC" ( / / nvlpubs.nist.gov / nistpubs / Legacy / SP / nistspecialpublication800-38d.pdf); the entire contents of said publication are incorporated herein by reference for all purposes.

[0091] The initialization vector circuit 122 generates an initialization vector (IV) or starting variable (SV) comprising a random or pseudo-random fixed-size input to the encryption algorithm. The IV is essentially a random number, that is, a value unique within a specified context, which determines the invocation of the authenticated encryption function on the input data to be protected.

[0092] Ciphertext buffer 126 stores ciphertext including (i) input encrypted data for a decryption process performed on a security command or (ii) output encrypted data from a result of an encryption operation performed on a result of an operation performed on memory array 160. Ciphertext buffer 126 is sized to accommodate output of encrypted ciphertext in a block of input ciphertext or a block of data to be decrypted, depending on the amount of data that may be encrypted or decrypted by encryption / decryption circuit 114. In an embodiment implementing Galois Counter Mode (GCM), a block cipher is defined to have a block size of 128 bits (16 byte groups).

[0093] Output tag 98 may be an authentication tag generated by encryption / decryption circuit 114 in embodiments implementing Galois Counter Mode (GCM) and may be added to the ciphertext. In embodiments employing a hash-based message authentication code (HMAC), output tag 98 is a special type of authentication code created using a cryptographic hash function and key 116, appended to the plaintext message, and checked by the recipient to verify the integrity of the message. Figure 5 and Figure 7Tag generation in an example embodiment implementing Galois Counter Mode (GCM) is described. The hash message authentication code (HMAC) in the example embodiment includes calculating equation (1):

[0094] HMAC(K,m)=H((K′XOR opad)||H(K′XOR ipad)||m)) (1)

[0095] Where H is a cryptographic hash function, m is the information to be authenticated, K is a secret key, K′ is a block-sized key derived from the secret key K; by padding right with zeros up to the block size, or by first hashing down to less than the block size and then padding right with zeros, || indicates concatenation, opad is the outer padding of the block size, including repeated byte values ​​0x5c, and ipad is the inner padding of the block size, including repeated byte values ​​0x36. For additional details, reference may be made to Internet Engineering Task Force IETF RFC 2104 ( / / tools.ietf.org / html / rfc2104); the entire contents of said reference are incorporated herein by reference for all purposes.

[0096] Figure 1A1 is a simplified block diagram of an integrated circuit memory device with a secure command decoder mechanism according to an embodiment. This figure is only an example and should not unduly limit the scope of the claims herein. A person of ordinary skill in the art will recognize other changes, modifications and substitutions. As shown, the integrated circuit memory device 100 includes several input blocks coupled to corresponding input / output pins. In one embodiment, the interface 105 is a serial interface including a set of I / O (input / output) ports 195, through which commands, addresses and data are transmitted. The serial interface may be based on or compatible with the Serial Peripheral Interface (SPI) bus specification, in which the command channel shares the I / O pins used by the address and data. For example, the integrated circuit memory device 100 may include an input / output port using pins for receiving and transmitting SPI bus signals. One pin may be connected to an input data line, which carries a serial input data / address signal SI and can also be used for commands. Another pin or multiple other pins may be connected to one or more output data lines, which carry a serial output data signal SO. Another pin may be connected to a clock line carrying a serial clock signal (SCLK), which is coupled to a clock generator 15, which in turn is coupled to a command decoder circuit 108 and control logic 110. Control logic 110 is operably coupled to receive a chip select signal CS# on a CS# input terminal of interface 105. Commands or instructions may be input via an input SI / SIO0 block, for example, and then transferred to data register 81 and control logic 110. Control logic 110, in combination with state machine 11, interprets and executes commands, such as read, erase, or program operations. In one embodiment, control logic 110 also receives a signal from a WP# / ACC block of interface 105 to perform a write protection function, and receives a signal from a HOLD# block of interface 105 to prevent the clock signal from entering state machine 11.

[0097] Data may be input via the SI / SIO0 block, SO / SIO1 block, WP# / ACC block, and HOLD# block coupled to data register 81. Data register 81 is coupled to SRAM (static random access memory) buffer 82, which is used for temporary storage during decryption operations performed by security logic 112. Security logic circuit 112 is coupled to SRAM buffer 82 and data register 81 via data bus 84 and data bus 85. Data bus 84 and data bus 85 may have a bus width less than the block size, such as one byte or one word, and are used by security logic circuit 112 to cycle between plaintext and ciphertext stored in the block to extract data from one buffer, perform encryption / decryption operations, and store the results in another buffer. Security logic circuit 112 may also or alternatively be coupled to interface 105 via data bus 91 to move data back and forth as needed.

[0098] Data may be output via the SI / SIO0 block, SO / SIO1 block, WP# / ACC block, and HOLD# block coupled to output buffer 71. In some embodiments, output buffer 71 may store additional spare bits including associated tag program code. A page may include multiple blocks, where a block includes a segment of data that may be encrypted or decrypted by security logic circuit 112. In an embodiment implementing Galois Counter Mode (GCM), block encryption is defined to have a block size of 128 bits.

[0099] The address corresponding to the location in the memory array 160 can be supplied from the data register 81 to the address generator 14. The address is then decoded by the X-decoder 141 and the Y-decoder 143. In some implementations, the page buffer (for clarity, Figure 1A160 to provide temporary storage for memory operations. In a read operation, data is transferred from the memory array 160 to the output buffer 71 via the sense amplifier 19. For a write operation, data is transferred from the data register 81, buffered in the SRAM buffer 82 for decryption, and then written to the memory array 160. For high voltage operations, for example, for a write operation, a high voltage (HV) generator 17 is activated. Other types of interfaces, including parallel interfaces, may also be used. The I / O port 195 on a particular integrated circuit memory device 100 may be used to provide output data having an I / O data width in parallel with each interface clock (e.g., a serial clock signal (SCLK)) cycle. For some examples, the I / O data width may be 1 bit, 4 bits, 8 bits, 16 bits, 32 bits, or greater than 32 bits. The I / O interface 105 may include FIFO buffers, shift register buffers or other supporting circuits and transmitters for transmitting data received at the interface on the port at the port clock rate, such as the serial clock signal (SCLK) rate for an SPI interface.

[0100] Figure 1B 1 is a simplified block diagram of an integrated circuit memory device with a security command decoder mechanism according to another embodiment. This figure is merely an example, which should not unduly limit the scope of the claims herein. A person of ordinary skill in the art will recognize other changes, modifications, and substitutions. As shown, the integrated circuit memory device 100 includes an address decoder 140, which is coupled to a plurality of word lines 145 configured along columns in a memory array 160, and is coupled to a sense amplifier / buffer 171. The sense amplifier / buffer 171 may be coupled to a plurality of bit lines 165, which are configured along rows in the memory array 160 for reading data from the memory array 160 and writing data to the memory array 160. In other examples, an input / output port may be used, where addresses and data may be provided on a common line in an address / data bus. In addition, a serial interface may be deployed.

[0101] The sense amplifier / buffer 171 may include one or more storage elements for each bit line. The address decoder 140 may select specific memory cells in the memory array 160 and couple the specific memory cells to the sense amplifier / buffer 171 via corresponding connecting bit lines. The sense amplifier / buffer 171 may store data written to or read from these specific memory cells in parallel. The sense amplifier / buffer 171 may have a page width for a page that includes thousands of bits, such as 2K bits or 4K bits or greater than 2K bits or 4K bits. In some embodiments, the sense amplifier / buffer 171 may store additional spare bits that include associated tag program code. A page may include multiple blocks, where a block includes a segment of data that can be encrypted or decrypted by the security logic circuit 112. In an embodiment implementing the Galois Counter Mode (GCM), block encryption is defined as having a block size of 128 bits.

[0102] In this embodiment, the buffer memory structure includes a second buffer level, which in this example includes two portions indicated as buffer BUF_A 181 and buffer BUF_B 182, wherein each portion of the second buffer level can store a portion, such as half, of the contents of the output buffer, wherein the portion of the contents of the output buffer preferably includes one or more unencrypted plaintext data portions. In addition, each portion of the second buffer level can be read and written independently. In some embodiments, buffer BUF_A 181, buffer BUF_B 182 can be implemented using dual-port or multi-port memory technology, thereby allowing independent reading and writing to different addresses, or can be implemented using multiple memory banks, which have separate address decoding and readout circuits. Other embodiments may include a three-level buffer structure, which includes a sense amplifier / buffer 171 and two additional buffer levels. In addition, other configurations of the buffer memory structure in the data path circuit between the output buffer and the interface can be implemented.

[0103] The sense amplifier / buffer 171 may be coupled to the memory array 160 via a plurality of bit lines 165. In some embodiments, the bit lines 165 include at least one page in width (plus the ECC program code when the ECC program code is included). The sense amplifier / buffer 171 may be coupled to the buffer BUF_A 181 and the buffer BUF_B 182 of the buffer structure via the bus 175 and the bus 176. In some embodiments, the bus 175 and the bus 176 may have a width equal to half the width of the sense amplifier / buffer 171. The second level buffer BUF_A and the second level buffer BUF_B may each be implemented as a cache memory using a static random access memory (SRAM) memory structure, for example, the cache memory has a one-column-by-multiple-row architecture. For example, a page may include 2048 bits plus spare bits including ECC code, and BUF_A may have a width of one column and 1024 (plus spare bits including ECC code) rows or 1024 rows plus spare bits including ECC code.

[0104] The security logic circuit 112 is coupled to the buffer memory structure (buffer BUF_A 181, buffer BUF_B 182) via data bus 184 and data bus 185. Data bus 184 and data bus 185 may have a bus width less than the block size, such as one byte or one word, and are used by the security logic circuit 112 to cycle between plaintext and ciphertext stored in buffer BUF_A 181 and buffer BUF_B 182 in blocks to retrieve data from one buffer, perform encryption / decryption operations, and store the results in the opposite buffer. The security logic circuit 112 may also or alternatively be coupled to the buffer memory structure (buffer BUF_A 181, buffer BUF_B 182) via data bus 191 to move data back and forth as needed.

[0105] I / O interface 105 may include a byte-wide or multiple byte-wide transfer registers or FIFOs coupled to security logic circuit 112 via data bus 191 and coupled to a buffer memory structure (buffer BUF_A 181 , buffer BUF_B 182 ).

[0106] Input / output data and control signals move between interface 105, command decoder circuit 108, and control logic 110 on integrated circuit memory device 100, and I / O port 195, or other data sources internal or external to integrated circuit memory device 100. In some embodiments, I / O port 195 may be connected to on-chip host circuitry, such as a general-purpose processor or dedicated application circuitry, or a combination of modules that provide system-on-a-chip functionality supported by memory array 160.

[0107] exist Figure 1B In the example shown in FIG. 1 , control logic 110 using bias configuration state machine 120 controls the application of bias configuration supply voltages such as read, program, and erase voltages generated or provided via one or more voltage supplies in bias configuration state machine 120, including page reads to transfer data from a page in a memory array to an output buffer. Control logic 110 is coupled to a multi-level buffer structure including buffer BUF_A 181, buffer BUF_B 182, and sense amplifier / buffer 171, security logic circuit 112, and memory array 160.

[0108] The control logic 110 and the command decoder circuit 108 constitute a controller that can be implemented using dedicated logic circuits including a state machine and support logic. In alternative embodiments, the control logic includes a general purpose processor that can be implemented on an integrated circuit that executes a computer program to control the operation of the device. In still other embodiments, the control logic can be implemented using a combination of dedicated logic circuits and a general purpose processor.

[0109] The controller's command decoder circuit 108 and control logic 110 are used to detect encrypted commands and execute encrypted commands to storage memory. In the embodiments described herein, the controller controls memory operations in response to commands received at the input / output interface, the memory operations including detecting and executing encrypted commands to store and retrieve information to the storage memory and outputting the results in encrypted form at the I / O interface.

[0110] The memory array 160 may include floating gate memory cells or dielectric charge trapping memory cells, which are used to store multiple bits per cell by establishing multiple programming levels corresponding to the amount of stored charge, thereby establishing a memory cell threshold voltage VT. This is based on the use of charge trapping memory cells, such as floating gate flash memory and dielectric charge trapping flash memory. The technology can be used with other memory cell technologies. In other examples, the memory cells may include programmable resistance memory cells, which are used for multiple bits per cell by establishing multiple programming levels corresponding to the amount of resistance.

[0111] In an embodiment, host A 97A to host N 97N may include a general purpose processor, a special purpose processor, a processor used as a memory controller, or other processor using an integrated circuit memory device 100. All or part of host A 97A to host N 97N may be implemented on the same integrated circuit as the memory. Although the above has been shown using a selected group of components for an integrated circuit device, there may be many alternatives, modifications, and changes. For example, some of the components may be expanded and / or combined. Other components may be inserted into the above. Depending on the embodiment, the configuration of the components may be interchangeable with other alternatives. Additional details of these components may be throughout this specification and more specifically described below.

[0112] After describing an example security architecture for storage memory, reference is made to Figure 2 and Figure 3 Figure 1.2 shows the data flow diagram and Figure 4 1 is used to describe subsequent examples of write and read operations using a security mechanism similar to that of FIG. 1 . Figure 2 1 is a diagram illustrating a data flow for a write operation of an embodiment of an integrated circuit memory device having a secure command decoder mechanism similar to that of FIG. 1 , and Figure 4 1 is a flow chart illustrating a mode of operation of a secure command decoder as described herein for a system similar to that of FIG. 1 .

[0113] Now refer to Figure 2 Figure 200 and the data flow Figure 4 400, an example of a secure command with an encrypted write command will be described. Figure 2 FIG. 1 is a diagram illustrating the data flow for a write operation of an embodiment of an integrated circuit memory device having a secure command decoder mechanism similar to FIG. Figure 4 Step 402 and Figure 2 In process 20 of FIG. 1 , host A 97A has sent a security command 91a and an encrypted payload 91b (also referred to as an intermediate data payload) and an input tag 92 to the integrated circuit memory device 100 via the I / O port 195. In process 21, the I / O interface 105 (for simplicity and clarity, Figure 2 108). In process 22, the command decoder circuit 108 identifies the security command 91a as a security command carrying encrypted information and triggers the security logic circuit 112 to perform authenticated decryption of the encrypted information of the security command 91a.

[0114] The secure command 91a contains real-time data including the encrypted payload 91b and may also contain specific non-encrypted parameters, such as one or more options for the secure command 91a. Depending on the command type, design goals, and specific hardware and / or software implementation, the implementation will be different and the content and configuration of the encrypted payload 91b will vary. Figure 2 The configuration of the encrypted payload 91b illustrated is exemplary and not limiting. Although, the exemplary encrypted payload 91b includes an encrypted memory access command 93a, encrypted address information 93b, encrypted input variables 93c, and encrypted data 93d. The encrypted data 93d includes data to be written to the memory in the integrated circuit memory device 100 whenever the encrypted memory access command 93a is a write command. The encrypted input variables 93c may include byte counts, options, and the like.

[0115] exist Figure 4 In step 404, the integrated circuit memory device 100 authenticates whether it recognizes the host A 97A. In process 23, the input tag 92 from the host A 97A is received by the I / O interface 105 (for clarity, Figure 2 The tag check circuit 128 determines whether the incoming tag 92 authenticates the host A 97A as the sender. The tag check circuit 128 may implement a Galois Counter Mode (GCM), a Hash Message Authentication Code (HMAC), or other alternative algorithms to authenticate the incoming tag 92. In the event that the tag check circuit 128 cannot use the incoming tag 92 to authenticate the sender, a return code is returned and no further action is taken on the security command 91a.

[0116] exist Figure 4 In step 406, the integrated circuit memory device 100 decrypts the encrypted information of the security command 91a. In process 25, the I / O interface 105 (for clarity, Figure 2 181). In process 26, the data of the encrypted payload stored in buffer BUF_A 181 is moved to the ciphertext buffer 126 of the security logic circuit 112 in blocks having a block size suitable for the algorithm implemented by the encryption / decryption circuit 114. In the example embodiment implementing Galois Counter Mode (GCM), the block encryption is defined to have a block size of 128 bits. In process 27, the encryption / decryption circuit 114 decrypts the contents of the ciphertext buffer 126 and writes the result to the plaintext buffer 124. In process 28, the block of decrypted information read from the plaintext buffer 124 is written to the buffer BUF_B 182 as the decrypted content. As shown by Figure 2As illustrated, the decrypted contents of buffer BUF_B 182 may include memory access commands 94a, addresses 94b, input variables 94c, and data 94d.

[0117] exist Figure 4 In step 408, the decrypted memory access command 94a is decoded. In process 29, the memory access command 94a is routed to the command decoder circuit 108. The command decoder circuit 108 identifies the memory access command 94a as a write command to write data 94d to address 94b in the memory 160 using input variable 94c.

[0118] exist Figure 4 In step 410, the memory command is executed by the memory device. In process 30, the command decoder circuit 108 triggers the control logic 110 to execute the write command, thereby writing data 94d to address 94b in the memory 160 using the input variable 94c. In process 31, the control logic 110 triggers the movement of the write data 94d to the sense amplifier / buffer 171 in preparation for writing the data to the memory array 160. In process 32, the control logic 110 triggers the provision of address 94b to the address decoder 140. In process 33, the control logic 110 triggers the writing of data 94d to the location of the memory array 160 activated by the address decoder 140. In process 34, the output payload 95 including a return code or other type of response generated by performing the write command is stored in the sense amplifier / buffer 171. If this operation is successful, a successful return code may be returned as an output in an encrypted or non-encrypted format in step 412; otherwise, an error code may be returned in step 414; otherwise, an error code may be returned in step 415. Figure 4 The output payload 95 is returned as output in encrypted or non-encrypted format in step 414 of FIG. 35. In process 36, the read data 94d and the output payload are copied in block size portions if required by the plaintext buffer 124 of the security logic circuit 112. In process 37, the encryption / decryption circuit 114 uses the contents of the plaintext buffer 124, for example, using the following reference Figure 4 , Figure 6 as well as Figure 7The method described herein establishes the output tag 98. In embodiments where the output is to be encrypted, the encryption / decryption circuitry 114 will additionally or in some implementations in parallel encrypt the contents of the plaintext buffer 124 and store the result in the ciphertext buffer 126. In process 38, the encrypted fetch data 94d from the ciphertext buffer 126 and the block of output payload 95 are combined into buffer BUF_A 181. In process 39, the contents of buffer BUF_A 181 (output data 99) are provided to calling host A 97A in an encrypted or decrypted form suitable for use with the memory access command 94a, along with the output tag 98 generated by the encryption / decryption circuitry 114 in process 39.

[0119] Safe read operations

[0120] After describing an example of a write operation using a security mechanism similar to that of FIG. 1 , reference will be made to Figure 3 Figure 1.2 shows the data flow diagram and Figure 4 The flowchart of is used to describe the next read operation using a similar security mechanism. Figure 3 1 is a diagram illustrating a data flow for a read operation of an embodiment of an integrated circuit memory device having a secure command decoder mechanism similar to that of FIG. 1 , and Figure 4 1 is a flow chart illustrating a mode of operation of a secure command decoder as described herein for a system similar to that of FIG. 1 .

[0121] Reference Figure 3 The data flow diagram 300 and re-reference Figure 4 400, an example of a secure command with an encrypted read command will be described. Figure 3 FIG. 1 is a diagram illustrating data flow for a read operation of an embodiment of an integrated circuit memory device having a secure command decoder mechanism similar to FIG. Figure 4 Step 402 and Figure 3 In process 20 of FIG. 1 , host A 97A has sent a security command 91a and an encrypted payload 91b and an input tag 92 to the integrated circuit memory device 100 via the I / O port 195. In process 21, the I / O interface 105 (for clarity, Figure 3 108). In process 22, the command decoder circuit 108 identifies the security command 91a as a security command carrying encrypted information and triggers the security logic circuit 112 to perform authenticated decryption of the encrypted information of the security command 91a.

[0122] The secure command 91a contains real-time data including the encrypted payload 91b. Depending on the command type, design goals, and specific hardware and / or software implementation, the implementation will be different, and the content and configuration of the encrypted payload 91b will vary accordingly. Figure 3 The configuration of the encrypted payload 91b illustrated is exemplary and not limiting. Although, the exemplary encrypted payload 91b includes an encrypted memory access command 93a, encrypted address information 93b, encrypted input variables 93c, and encrypted data 93d. The encrypted data 93d is used for write operations and may not contain data during read operations. Optionally, the encrypted data 93d includes control information, and / or addresses identifying buffer locations to which data read from the memory in the integrated circuit memory device 100 may be written whenever the encrypted memory access command 93a is a read command. The data read from the memory integrated circuit memory device 100 is sent to the host A 97A, thereby generating a request in an encrypted format or, optionally, in a plain text format. The encrypted input variables 93c may include byte counts, options, and the like.

[0123] exist Figure 4 In step 404, the integrated circuit memory device 100 authenticates whether it recognizes the host A 97A. In process 23, the input tag 92 from the host A 97A is received by the I / O interface 105 (for clarity, Figure 3 The tag check circuit 128 determines whether the incoming tag 92 authenticates the host A 97A as the sender. The tag check circuit 128 may implement a Galois Counter Mode (GCM), a Hash Message Authentication Code (HMAC), or other alternative algorithms to authenticate the incoming tag 92. In the event that the tag check circuit 128 cannot use the incoming tag 92 to authenticate the sender, a return code is returned and no further action is taken on the security command 91a.

[0124] exist Figure 4 In step 406, the integrated circuit memory device 100 decrypts the encrypted information of the security command 91a. In process 25, the I / O interface 105 (for simplicity and clarity, Figure 2181). In process 26, the data of the encrypted payload stored in buffer BUF_A 181 is moved to the ciphertext buffer 126 of the security logic circuit 112 in blocks having a block size suitable for the algorithm implemented by the encryption / decryption circuit 114. In the example embodiment implementing the Galois Counter Mode (GCM), the block encryption is defined to have a block size of 128 bits. In process 27, the encryption / decryption circuit 114 decrypts the contents of the ciphertext buffer 126 and writes the result to the plaintext buffer 124. In process 28, the block of decrypted information read from the plaintext buffer 124 is written to the buffer BUF_B 182 as the decrypted content. As shown by Figure 3 As illustrated, the decrypted contents of buffer BUF_B 182 may include memory access commands 94a, addresses 94b, input variables 94c, and data 94d.

[0125] exist Figure 4 In step 408, the decrypted memory access command 94a is decoded. In process 29, the memory access command 94a is routed to the command decoder circuit 108. The command decoder circuit 108 identifies the memory access command 94a as a read command to read data from address 94b in the memory 160 using input variable 94c.

[0126] exist Figure 4 In step 410, the memory command is executed by the memory device. In process 30, the command decoder circuit 108 triggers the control logic 110 to execute a read command, thereby using the input variable 94c to read data from address 94b in the memory 160. In process 32, the control logic 110 triggers to provide address 94b to the address decoder 140. In process 33, the control logic 110 triggers to read data 94d from the location of the memory array 160 activated by the address decoder 140 into the sense amplifier / buffer 171. In process 34, the output payload 95 including a return code or other type of response generated by performing the read command is stored in the sense amplifier / buffer 171. The security logic circuit 112 provides an authentication result or information authentication result based on the result of the aforementioned memory operation, that is, if the read operation is successful, a successful return code is provided to be returned as an output in an encrypted or non-encrypted format in step 412; otherwise, an error code is provided to be returned in step 412. Figure 4In process 31, the control logic 110 triggers to move the read data 94d read from the memory array 160 from the sense amplifier / buffer 171 to the buffer BUF_B 182. In process 35, the output payload 95 is moved to the buffer BUF_B 182. In process 36, if required by the plaintext buffer 124 of the security logic circuit 112, the read data 94d and the output payload are copied in the block size portion. In process 37, the encryption / decryption circuit 114 uses the contents of the plaintext buffer 124, for example, using the following reference Figure 4 , Figure 6 as well as Figure 7 The method described is to establish the output tag 98. In embodiments where the output is to be encrypted, the encryption / decryption circuit 114 will additionally or in some implementations in parallel encrypt the contents of the plaintext buffer 124 and store the result in the ciphertext buffer 126. In flow 38, the encrypted read data 94d and the block of output payload 95 from the ciphertext buffer 126 are combined into the buffer BUF_A 181. In flow 39, the contents of the buffer BUF_A 181 (output data 99) are provided to the calling host A 97A in an encrypted or decrypted form suitable for the memory access command 94a, along with the output tag 98 generated by the encryption / decryption circuit 114 in flow 39.

[0127] After this example of a read operation using a security mechanism similar to FIG. 1 , reference will be made to Figure 5 Data flow diagram 500 and Figure 6 600 is used to describe a next example authenticated encryption service implementing Galois Counter Mode encryption used in some encryption / decryption circuit 114 embodiments.

[0128] Reference Figure 5 and Figure 6 . Figure 5 FIG. 5 is a diagram illustrating data flow for a block encryption counter mode of a secure command decoder as described herein for a system similar to FIG. 1. Data flow diagram 500 includes counter 0 501a, counter 1 501b, and counter 2 501c. Figure 6 The flowchart is a flow chart illustrating the block encryption counter mode operation of the secure command decoder as described herein for a system similar to FIG. 1 .

[0129] In step 601, IV 122 is generated using a secure pseudo-random number generator. In an embodiment, IV 122 has a length of 96 bits (or 12 octets). The IV must be known only to the sender and receiver.

[0130] In step 602, IV 122 is then concatenated with 32-bit counter 0 501a. In one embodiment, counter 0 501a counts from zero. In another embodiment, counter 0 501a counts from one. The counter starts at zero in embodiments that use counter mode for encrypting plaintext. The concatenated block has a size of 128 bits and can be encrypted.

[0131] In step 603, the block formed by the concatenation of IV 122 and counter 0 501a is encrypted using the authenticated encryption standard (block cipher encryption operation 502) using key 116. This results in a string s of 16 bytes or 128 bits.

[0132] In step 604 , the obtained string s is XORed with the first block of plaintext stored in the plaintext buffer 124 to obtain the first block of ciphertext, which is then stored in the ciphertext buffer 126 .

[0133] In step 605, the value of the counter is then increased by one.

[0134] In step 606 , steps 601 to 605 are repeatedly executed for each value of the counter and a different plaintext block (plaintext block 124 a and plaintext block 124 b ) in the plaintext buffer 124 , thereby forming a ciphertext to be stored in the ciphertext buffer 126 .

[0135] In one embodiment, for the last block of plaintext, if the plaintext block is not a multiple of 16 (i.e., the block size), the resulting encrypted ciphertext string s will be divided into a length equal to the length of the last block of plaintext and then XORed with the last block of plaintext.

[0136] After describing how encryption / decryption circuit 114 may encrypt plaintext to form ciphertext, reference will be made to Figure 5 The data flow diagram 500 and reference Figure 7 700 is used to describe a process for ensuring the integrity of data.

[0137] One implementation of the process for generating the authentication tag 98 (output tag 98) is based on the Encrypt-then-MAC construction and the Wegman-Carter MAC. The function for generating the authentication tag is also referred to as GHASH(). The function GHASH is defined by GHASH(H, A, C) = Xm+n+1, where the inputs A and C are the associated data 118 (additional authentication data 118) and the ciphertext 126 formatted as described above, respectively, and the variables Xi (i = 0, ..., m+n+1) are defined by equation (2):

[0138]

[0139] Reference Figure 5 and Figure 7 . Figure 5 1 is a diagram illustrating data flow for a block encryption counter mode of a secure command decoder as described herein for a system similar to that of FIG. 1 . Figure 7 1 for generating an authentication tag used to verify data integrity using the block encryption counter mode operation as described herein.

[0140] In step 701, a secret string H is generated by encrypting an empty string using the encryption key 116, that is, H=Ek("\x00"*16); wherein "\x00"*16 is an empty string of 16 bytes.

[0141] In step 702, the authentication tag is generated block by block in a series of steps. Thus, for each block Ai of the associated data 118 (i.e., the additional authentication data 118), a string Xi is generated by the circuit 504 using the following calculation, and this contributes to the final authentication tag: Xi = GmulH (Xi-1 xor Ai), where i = 1, ..., m, X0 = 0. Here, m is simply the number of blocks (blocks of associated data) to be authenticated.

[0142] In step 703, the associated data block Ai is now included in the authentication tag, the current authentication tag will be processed by circuit 504, and n ciphertext blocks 126a and 126b will also be included in the authentication tag: Xi+m=GmulH(Xi+m-1xor Ci), where i=1, ..., n. Here, n is the number of ciphertext blocks.

[0143] In step 704, the 64-bit representation of the length of the associated data A is concatenated with the 64-bit representation of the length of the ciphertext C (concatenation operation 506). The resulting string is supplied as a parameter to GmulH() as follows: S = GmulH = (Xm + n xor (len(A) || len(C))).

[0144] In step 705, an authentication tag T 98 (output tag 98) is generated using T = S xor Ek (J0), where J0 is formed by the concatenation of the initialization vector 122 and the counter 0501a.

[0145] In one embodiment, the authentication tag (ie, output tag 98) may be generated in parallel with the generation of each block of ciphertext from the encryption function.

[0146] In step 705, the service returns the concatenation of the ciphertext C and the corresponding authentication tag T as the final output.

[0147] Figure 8 1 is a flow chart illustrating a process for operating a memory device that executes security commands as described herein for use similar to the system of Figure 1. The memory device typically includes encryption / decryption logic circuitry and an input / output interface.

[0148] Please refer to Figure 8 In step 801, the memory device determines whether command information received from a host includes a secure memory command, wherein the secure memory command includes encrypted information.

[0149] In step 802, the memory device authenticates whether the host is a recognized host in response to the secure memory command.

[0150] In step 803, the memory device decrypts the encrypted information from the identified host to obtain decrypted information.

[0151] In step 804, the memory device performs a memory operation corresponding to the decrypted information.

[0152] Other implementations of the method described in this section may include a non-transitory computer-readable storage medium storing instructions executable by a processor to perform any of the methods described above. Still another implementation of the method described in this section may include a system including a memory and one or more processors operable to execute instructions stored in the memory to perform any of the methods described above.

[0153] Any data structures and program codes described or referred to above are stored according to numerous implementations on a computer-readable storage medium, which may be any device or medium that can store program code and / or data for use by a computer system. This includes, but is not limited to, volatile memory, non-volatile memory, application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), magnetic and optical storage devices such as magnetic disk drives, magnetic tapes, compact discs (CDs), digital versatile discs, or digital video discs (DVDs), or other media now known or later developed that are capable of storing computer-readable media.

[0154] A bit group is a basic storage unit used in many integrated circuit logic and memory circuits and consists of 8 bits. The basic storage unit may have other sizes, including, for example, 1 bit, 2 bits, 4 bits, 16 bits, etc. Therefore, the description of the encryption / decryption logic circuits described above and in other examples described in the present invention using the term bit group generally applies to circuits using storage units of different sizes as described by replacing the term bit group or set of bit groups by storage unit or set of storage units. In addition, in some embodiments, storage units of different sizes may be used for a single command sequence, such as one or more 4-bit storage units combined with 8-bit storage units.

[0155] A plurality of flow charts of logic executed by a memory controller or by a memory device are described herein. The logic can be implemented by a processor programmed with a computer program stored in a computer system accessible memory, and can be executed by a processor, by dedicated logic hardware (dedicated logic circuit ASIC, including field programmable gate array), and by a combination of dedicated logic hardware and computer programs. As with all flow charts herein, it should be understood that many steps can be combined, executed in parallel, or executed in different sequences without affecting the functions achieved. In some cases, as the reader will understand, the reconfiguration steps will achieve the same results as long as certain other changes are also made. In other cases, as the reader will understand, the reconfiguration steps will achieve the same results as long as certain conditions are met. In addition, it will be understood that the flow charts herein only show steps related to understanding the described technology, and it will be understood that a large number of additional steps for achieving other functions can be performed before, after, and between those steps shown.

[0156] An apparatus having a controller and a method for responding to a command sequence including a security command is described in the present invention.

[0157] An apparatus having a controller and a method for responding to a command sequence including an unsafe command is described herein.

[0158] Devices having a controller and methods are described herein that respond to a command sequence having a security command that also includes an encrypted real-time data payload.

[0159] The present invention describes a device having a controller and a method for executing a security command including encrypted command parameters, including detecting a security command carrying a real-time data payload, authenticating whether a host is an identified host in response to a secure memory command, decrypting encrypted information from the identified host to obtain decrypted information, and performing a memory operation corresponding to the decrypted information.

[0160] An apparatus and method having a controller with secure commands that also include an encrypted real-time data payload that can be decrypted into a memory access command that can be executed later on a memory array; to eliminate the possibility of third parties interfering with or intercepting the memory access commands is described in the present invention.

[0161] In the present invention, a device and method are described having a controller with a secure command that also contains an encrypted real-time data payload; the payload will have command information of the memory operation to be performed when executed.

[0162] In the present invention, an apparatus and method are described having a controller with a secure command that also contains an encrypted real-time data payload; the payload will have command information to be executed, wherein the command information is sent over a memory array.

[0163] In the present invention, an apparatus and method are described having a controller with a secure command that also contains an encrypted immediate data payload; the payload will have command information to be executed on a memory array, wherein the command is sent only when the secure command is authenticated.

[0164] Devices and methods having a controller that performs memory access operations in response to a security command including an encrypted real-time data payload are described in this disclosure.

[0165] An apparatus and method with a controller is described for having a security command that also includes an encrypted real-time data payload, a first stage decryption process and a second stage decoding process using first stage and second stage buffering.

[0166] Although the present invention is disclosed with reference to the preferred embodiments and examples described above, it should be understood that these examples are intended to be illustrative rather than restrictive. It is expected that various modifications and combinations will be easily conceived by those skilled in the art, and the modifications and combinations will be within the spirit of the present invention and the scope of the following claims.

[0167] The specific embodiments described above further illustrate the objectives, technical solutions and beneficial effects of the present invention in detail. It should be understood that the above description is only a specific embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. A memory device, characterized in that: include: a memory array comprising a plurality of bit lines; An input / output interface for inputting / outputting a data unit; a data path circuit connected between the memory array and the input / output interface; a command decoder circuit that decodes command information received from a host in response to a command received at the input / output interface, the command information comprising a secure memory command, the secure memory command comprising encrypted information; as well as a secure logic circuit that authenticates whether the host is an identified host in response to the secure memory command, decrypts encrypted information from the identified host to obtain decrypted information, and performs a memory operation corresponding to the decrypted information; wherein the command decoder circuit receives a command sequence, the command sequence comprising a command code field and an intermediate data payload, the command code field comprising an operation code, wherein the operation code indicates one of an unencrypted command and a secure command, wherein the intermediate data payload comprises an encrypted memory access command operation code, an encrypted address field, and one or more encrypted input variables, wherein the encrypted address field indicates one or more locations where data is to be read from a memory, wherein the encrypted input variables include encrypted result indicators; or The command decoder circuit receives a command sequence, the command sequence including a command code field and an intermediate data payload, the command code field including an operation code, wherein the operation code indicates one of an unencrypted command and a secure command, wherein the intermediate data payload includes an encrypted memory access command operation code, an encrypted address field, encrypted data, and one or more encrypted input variables, wherein the encrypted address field indicates one or more locations in a memory where data is to be written, and wherein the encrypted input variables include encryption result indicators.

2. The memory device according to claim 1, further comprising: The security logic circuit includes an encryption / decryption circuit, wherein when the operation code indicates a security command, the encryption result indicator displays an encryption result, and the encrypted memory access command operation code indicates reading from the memory, the encryption / decryption circuit encrypts data read from the memory.

3. The memory device according to claim 1, further comprising: The security logic circuit includes an encryption / decryption circuit, wherein when the job code indicates a security command, the encryption result indicator displays an encryption result, and the encrypted memory access command job code indicates writing to the memory, the encryption / decryption circuit encrypts the return code generated by the write data.

4. The memory device according to claim 1, further comprising: The command decoder circuit decodes unencrypted commands.

5. The memory device of claim 1, wherein the security logic circuit provides a first memory operation result performed in an unencrypted form.

6. The memory device of claim 5, wherein: The security logic circuit calculates an information authentication code in an unencrypted form based on the first memory operation result, The security logic circuit provides an information authentication result according to the first memory operation result and the information authentication code in an unencrypted form.

7. The memory device of claim 1 , wherein the security logic circuit provides a second memory operation result, wherein the second memory operation result calculates an authentication code based on performing the memory operation in encrypted form, wherein the security logic circuit provides an authentication result based on the second memory operation result together with the authentication code in encrypted form.

8. The memory device of claim 7 , wherein the security logic circuit uses a block encryption counter mode to encrypt the second memory operation result to encrypt a block of the second memory operation result to form a block of ciphertext information; and concatenates at least two blocks of the ciphertext information together in a buffer register of the memory device.

9. The memory device of claim 8 , wherein the security logic circuit encrypts the second memory operation result performed using the block encryption counter mode by encrypting a block of an initialization vector concatenated with a counter using a symmetric key shared with an intended recipient to obtain an intermediate result, and performs an exclusive OR operation on the intermediate result and a corresponding plaintext block to form a block of the ciphertext information.

10. The memory device of claim 1 , wherein the security logic circuit decrypts encrypted information from the identified host using a block encryption counter mode to decrypt blocks of encrypted information to form blocks of plaintext information; and concatenates at least two blocks of the plaintext information together in a buffer register of the memory device.

11. A method for operating a memory device according to any one of claims 1 to 10 for executing a security command, characterized in that: The memory device includes a security logic circuit and an input / output interface, and the method includes: determining whether command information received from a host includes a secure memory command, wherein the secure memory command includes encrypted information; authenticating whether the host is an identified host in response to the secure memory command; decrypting the encrypted information from the identified host to obtain decrypted information; and A memory operation corresponding to the decrypted information is performed.

12. The method for operating the memory device of any one of claims 1 to 10 for executing a security command according to claim 11, further comprising: Calculating a message authentication code based on generating a first memory operation result by performing the memory operation; And according to the first memory operation result together with the information authentication code in an unencrypted form, an information authentication result is provided.

13. The method for operating a memory device according to any one of claims 1 to 10 for executing a security command according to claim 11, further comprising calculating an authentication code based on generating a second memory operation result based on the memory operation performed by encryption; and providing an authentication result based on the second memory operation result together with the authentication code in encrypted form.

14. A method for operating a memory device according to any one of claims 1 to 10 for executing a security command according to claim 13, wherein the memory operation performed based on encryption to generate a second memory operation result further comprises: encrypting a block of the second memory operation result using a block encryption counter mode to form a block of ciphertext information; and concatenating at least two blocks of the ciphertext information together in a buffer register of the memory device.

15. A method for operating a memory device according to any one of claims 1 to 10 for executing a security command according to claim 14, wherein the block of the second memory operation result encrypted using a block encryption counter mode further comprises: using a symmetric key shared with an intended recipient to encrypt a block of an initialization vector concatenated with a counter to obtain an intermediate result, and performing a mutual exclusive OR operation on the intermediate result and a block of corresponding plaintext to form a block of the ciphertext information.

16. A method for operating a memory device as described in any one of claims 1 to 10 for executing security commands according to claim 11, wherein decrypting the encrypted information from the identified host further comprises: decrypting a block of the encrypted information using a block encryption counter mode to form a block of plaintext information; and concatenating at least two blocks of the plaintext information together in a buffer register of the memory device.

17. A memory device, characterized in that: include: a memory array comprising a plurality of bit lines; An input / output interface for inputting / outputting a data unit; a data path circuit connected between the memory array and the input / output interface; a command decoder circuit that receives secure and unsecure commands at the input / output interface, the decoder having a secure logic circuit that decrypts the encrypted immediate data payload when a secure command operation code is received to obtain decrypted information and performs a memory operation corresponding to the decrypted information; wherein the command decoder circuit receives a command sequence, the command sequence comprising a command code field and an intermediate data payload, the command code field comprising an operation code, wherein the operation code indicates one of an unencrypted command and a secure command, wherein the intermediate data payload comprises an encrypted memory access command operation code, an encrypted address field, and one or more encrypted input variables, wherein the encrypted address field indicates one or more locations where data is to be read from a memory, wherein the encrypted input variables include encrypted result indicators; or The command decoder circuit receives a command sequence, the command sequence including a command code field and an intermediate data payload, the command code field including an operation code, wherein the operation code indicates one of an unencrypted command and a secure command, wherein the intermediate data payload includes an encrypted memory access command operation code, an encrypted address field, encrypted data, and one or more encrypted input variables, wherein the encrypted address field indicates one or more locations in a memory where data is to be written, and wherein the encrypted input variables include encryption result indicators.

18. The memory device of claim 17, further comprising: The security logic circuit further authenticates whether the host is an identified host in response to an input tag received together with the security command operation code.

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