An SCR device with high holding voltage, low trigger voltage and high ESD characteristics

Abstract

The present invention discloses an SCR device with high holding voltage, low trigger voltage and high ESD characteristics, including a first P+ doped region, a first N+ doped region, a second P+ doped region, a second N+ doped region, a first trigger structure and a resistor R, wherein: one end of the first P+ doped region is connected to a PAD end, and one end is connected to the first N+ doped region; the two ends of the first N+ doped region are respectively connected to the first and second P+ doped regions; the two ends of the second P+ doped region are respectively connected to the first and second N+ doped regions; one end of the second N+ doped region is connected to the second P+ doped region, and one end is connected to a grounding end; the first trigger structure connection end is connected to the PAD end through a trigger structure; one end of the resistor R is connected to the first trigger structure, and one end is connected to a grounding end. The beneficial effects of the present invention: the BE junction of the NPN is forward biased to turn on the thyristor; the stacked SCR principle is adopted to achieve bidirectional voltage protection and high holding voltage, and latch-up immunity.

Description

Technical Field

[0001] The present invention relates to the field of analog integrated circuits, and in particular to an SCR device with high sustaining voltage, low triggering voltage and high ESD characteristics. Background Art

[0002] In analog integrated circuits, in order to meet the normal production, packaging, transportation, etc. of integrated circuits, IC chips need to reach a certain ESD level, usually requiring an ESD level of 2KV or above in the ESD test standard. Some special devices will face more severe environments in system applications, such as EOS, surges, etc. The 2KV ESD level in the ESD test standard usually cannot meet the requirements, and the 15KV ESD level in IEC61000-4-2 must be reached. In order to achieve the 15KV ESD level, conventional chips need to be equipped with TVS or varistors to achieve this purpose. In integrated circuits, 15KV ESD capability can also be achieved through an integrated SCR structure.

[0003] In order to save system costs and improve chip reliability, users also require the chip's ESD level to be 15KVESD. In the Multi-Function Electric Energy Meter Communication Protocol, it is clearly required that the driver and receiver must reach 15KVESD or above.

[0004] In existing 15KV ESD devices, SCR structures are usually integrated into the chip, but the process portability of SCR structures is poor and the trigger voltage varies greatly with the process. Conventional SCR structures have low maintenance voltages and are prone to latch-up risks. Summary of the invention

[0005] The object of the present invention is to provide a SCR device with high sustaining voltage, low triggering voltage and high ESD characteristics in view of the above problems.

[0006] A SCR device with high sustaining voltage, low triggering voltage and high ESD characteristics comprises a first P+ doping region, a first N+ doping region, a second P+ doping region, a second N+ doping region, a first triggering structure and a resistor R, wherein: one end of the first P+ doping region is connected to a PAD end, and one end is connected to the first N+ doping region; two ends of the first N+ doping region are respectively connected to the first and second P+ doping regions; two ends of the second P+ doping region are respectively connected to the first and second N+ doping regions; one end of the second N+ doping region is connected to the second P+ doping region, and one end is connected to a ground end; the first triggering structure connecting end is connected to the PAD end through a triggering structure; one end of the resistor R is connected to the first triggering structure, and one end is connected to a ground end.

[0007] Preferably, the second P+ doped region and the first trigger structure connection end form a circuit structure.

[0008] Preferably, the four layers of PNPN structures are connected in series.

[0009] The beneficial effects of the present invention are as follows: the BE junction of the NPN is forward biased to turn on the thyristor; the stacked SCR principle is adopted to achieve bidirectional voltage protection and high holding voltage, and latch-up immunity. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 It is a structural principle diagram of the low trigger voltage, positive withstand voltage, and high sustaining voltage SCR of the present invention.

[0011] Figure 2 It is a schematic diagram of the low trigger voltage, positive and negative withstand voltage, and high sustaining voltage SCR structure of the present invention.

[0012] Figure 3 Schematic diagram of the SCR structure of the prior art.

[0013] Figure 4 It is a typical trigger structure.

[0014] Figure 5 This is the SCR structure diagram of Example 1.

[0015] Figure 6 This is the SCR structure diagram of Example 2.

[0016] Figure 7 This is the SCR structure diagram of Example 3.

[0017] Figure 8 This is the SCR structure diagram of Example 4.

[0018] Fig. 9 This is the SCR structure diagram of Example 5.

[0019] Fig.10 This is the SCR structure diagram of Example 6.

[0020] Fig.11 This is the SCR structure diagram of Example 7. DETAILED DESCRIPTION

[0021] The present invention will be further described below in conjunction with the accompanying drawings.

[0022] like Figure 1As shown in (a), an SCR device with high holding voltage, low trigger voltage and high ESD characteristics includes a first P+ doped region, a first N+ doped region, a second P+ doped region, a second N+ doped region, a first trigger structure and a first resistor R, wherein: one end of the first P+ doped region is connected to the PAD end, and the other end is connected to the first N+ doped region; the two ends of the first N+ doped region are respectively connected to the first and second P+ doped regions; the two ends of the second P+ doped region are respectively connected to the first and second N+ doped regions; one end of the second N+ doped region is connected to the second P+ doped region, and one end is connected to the ground end; the first trigger structure connection end is connected to the PAD end through the trigger structure; one end of the resistor R is connected to the first trigger structure, and one end is connected to the ground end.

[0023] It should be understood that the second P+ doped region and the first trigger structure connection end form a circuit structure.

[0024] It should be understood that the four layers of PNPN structures are connected in series.

[0025] like Figure 1 As shown in (b), when the PAD is subjected to a positive high voltage, the trigger structure will first trigger and sink current, and form an IR voltage drop on the first resistor R; when the IR voltage drop exceeds VBE, the parasitic NPN is turned on, and a large current is formed from the PAD to GND, and the PNP is also turned on, thereby turning on the SCR structure.

[0026] like Figure 2 As shown in (a), an SCR device with high sustaining voltage, low triggering voltage and high ESD characteristics can be further transformed, including a first N+ doped region, a first P+ doped region, a second N+ doped region, a second P+ doped region, a third P+ doped region, a third N+ doped region, a first trigger structure, a second trigger structure and a resistor R; wherein: one end of the first N+ doped region is connected to the PAD end, and the other end is connected to the first P+ doped region; the two ends of the first P+ doped region are respectively connected to the first and second N+ doped regions; the second N+ doped region is respectively connected to the first, second and third P+ doped regions; the two ends of the third P+ doped region are respectively connected to the second and third N+ doped regions; the first trigger structure connection end is connected to the PAD through the trigger structure; the resistor R is connected to the ground through the second trigger structure connection end.

[0027] It should be understood that in order to reduce the trigger voltage of the SCR structure, a trigger structure of the SCR structure is introduced and connected to the gate of the SCR structure.

[0028] Figure 3 Schematic diagram of the SCR structure of the prior art.

[0029] Figure 4 It is a typical trigger structure.

[0030] like Figure 5 As shown, the P and N in NWELL form a first P-doped region and a first N-doped region respectively; the P and N on PSUB form a second P-doped region and a second N-doped region respectively; thus, a PNPN four-layer structure is formed.

[0031] like Figure 6 As shown in the figure, the P and N in NWELL form the first P doping region and the first N doping region respectively; the P and N on PWELL form the second P doping region and the second N doping region respectively; thus forming a PNPN four-layer structure. There is also a P doping region on PSUB, so that a PNP structure to SUB can be formed to improve ESD capability.

[0032] Figure 7 Structure and Figure 6 The difference is that an N-doped region is added to PSUB; thus, not only a PNPN four-layer structure is formed with PWELL, but also a PNPN four-layer structure is formed between PSUB, which can greatly improve the discharge capacity of the device.

[0033] Figure 8 for Figure 7 The symmetrical structure of PWELL not only forms a PNPN four-layer structure with NWELL, but also forms a PNPN structure with PSUB.

[0034] Fig. 9 for Figure 6 symmetrical structure.

[0035] Fig.10 It is formed by stacking two structures in FIG. 9 to meet the requirements of positive and negative withstand voltage and high sustain voltage; its trigger structure is P-type doped.

[0036] Fig.11 Structure and Fig.10 Similar, but different Fig.11 The trigger structure is P / PWELL.

Claims

1. An SCR device with high holding voltage, low trigger voltage and high ESD characteristics, characterized in that: It includes a first P+ doping region, a first N+ doping region, a second P+ doping region, a second N+ doping region, a first trigger structure and a resistor R, wherein: one end of the first P+ doping region is connected to the PAD end, and one end is connected to the first N+ doping region; two ends of the first N+ doping region are respectively connected to the first and second P+ doping regions; two ends of the second P+ doping region are respectively connected to the first and second N+ doping regions; one end of the second N+ doping region is connected to the second P+ doping region, and one end is connected to the ground end; the first trigger structure connection end is connected to the PAD end through the trigger structure; one end of the resistor R is connected to the first trigger structure, and one end is connected to the ground end; The second P+ doped region and the first trigger structure connection end form a circuit structure; The four-layer PNPN structure is connected in series, and the formation of the four-layer PNPN structure includes: When the SCR device structure includes PSUB and NWELL, P and N in NWELL form a first P-doped region and a first N-doped region respectively, and P and N on PSUB form a second P-doped region and a second N-doped region respectively, thereby forming a PNPN four-layer structure; When the SCR device structure includes PSUB, NWELL and PWELL, P and N in NWELL form a first P-doped region and a first N-doped region respectively, and P and N on PWELL form a second P-doped region and a second N-doped region respectively, thereby forming a PNPN four-layer structure; at the same time, there is a P-doped region on PSUB, thereby forming a PNP structure to PSUB; Add an N-doped region on PSUB to form a PNPN four-layer structure with PWELL, or form a PNPN four-layer structure between PSUB; PWELL not only forms a PNPN four-layer structure with NWELL, but also forms a PNPN structure with PSUB.

Images