image sensor

Abstract

An image sensor includes a substrate, first and second insulating structures, a first wiring structure, a through via, and first and second connection patterns. The substrate includes a sensor array region and a pad region and includes first and second surfaces opposite each other. The first insulating structure is disposed on the second surface of the substrate and includes a third surface facing the second surface and a fourth surface opposite the third surface. The first wiring structure is formed in the first insulating structure and includes a first conductive layer and a first via. The through via penetrates the substrate in the pad region and is connected to the first wiring structure. The first connection pattern is connected to the first wiring structure. The second insulating structure is disposed on the fourth surface of the first insulating structure. The second connection pattern is connected to the first connection pattern. The first conductive layer includes a first wire and a second wire more distanced from the substrate than the first wire. The through via contacts the second wire.

Description

Technical Field

[0001] This disclosure relates to an image sensor and a method of manufacturing the image sensor, and more specifically, to an image sensor including a pad region and a method of manufacturing the image sensor. Background Technology

[0002] An image sensor is a semiconductor device that converts light information into electrical signals. Such image sensors can include charge-coupled device (CCD) image sensors and complementary metal-oxide-semiconductor (CMOS) image sensors.

[0003] Recently, in order to improve the light receiving efficiency and light sensitivity of pixels formed in image sensors, back-illuminated (BSI) image sensors in which light is incident through the back side of a semiconductor substrate have been studied. Summary of the Invention

[0004] On the one hand, it provides an image sensor with improved performance by shortening the electrical signal path in the pad area.

[0005] On the other hand, a method is provided for manufacturing image sensors with improved performance by shortening the electrical signal path in the pad area.

[0006] According to one aspect of an embodiment, an image sensor is provided, comprising: a substrate including a sensor array region and a pad region disposed around the sensor array region, and including a first surface and a second surface opposite to each other; a first insulating structure disposed on the second surface of the substrate, and including a third surface facing the second surface and a fourth surface opposite to the third surface; a first wiring structure formed in the first insulating structure and including a plurality of first conductive layers and a plurality of first vias; a through-path extending through the substrate in the pad region and connected to the first wiring structure; a first connection pattern exposed from the fourth surface of the first insulating structure and connected to the first wiring structure; a second insulating structure disposed on the fourth surface of the first insulating structure; and a second connection pattern exposed from the surface of the second insulating structure facing the fourth surface and connected to the first connection pattern, wherein the first conductive layer includes the first wiring and the second wiring spaced further away from the substrate than the first wiring, and the through-path contacts the second wiring.

[0007] According to another aspect of one embodiment, an image sensor is provided, comprising: a substrate including a photoelectric conversion layer and including a first surface and a second surface opposite to the first surface, light being incident on the first surface; conductive pads disposed on the first surface of the substrate; a first insulating structure disposed on the second surface of the substrate, including a third surface facing the second surface and a fourth surface opposite to the third surface; a first wiring formed in the first insulating structure and including a first opening; a second wiring formed in the first insulating structure and spaced further from the substrate than the first wiring; a through-path extending through the substrate and the first opening to connect the conductive pads and the second wiring; a first connection pattern exposed from the fourth surface of the first insulating structure and connected to the second wiring; a second insulating structure disposed on the fourth surface of the first insulating structure; and a second connection pattern exposed from the surface of the second insulating structure facing the fourth surface and connected to the first connection pattern.

[0008] According to another aspect of one embodiment, an image sensor is provided, comprising: a first substrate including a sensor array region and a pad region disposed around the sensor array region, and including a first surface and a second surface opposite to the first surface, wherein light is incident on the first surface; a color filter disposed on the first surface of the first substrate in the sensor array region; a microlens disposed on the color filter; conductive pads disposed on the first surface of the first substrate in the pad region; a first insulating structure disposed on the second surface of the substrate, and including a third surface facing the second surface and a fourth surface opposite to the third surface; and a first wiring structure formed in the first insulating structure and including a plurality of first conductive layers and a plurality of first... The plurality of first conductive layers include a first wiring, the first wiring being the first conductive layer among the plurality of first conductive layers closest to the first substrate; a first through-path that penetrates the first substrate in the pad region to connect the conductive pad and the first wiring structure; a first connection pattern that is exposed from a fourth surface of the first insulating structure and connected to the first wiring structure; a second insulating structure disposed on the fourth surface of the first insulating structure; a second wiring structure formed in the second insulating structure and including a plurality of second conductive layers and a plurality of second paths; and a second connection pattern that is exposed from the surface of the second insulating structure facing the fourth surface and connects the first connection pattern and the second wiring structure, wherein the first through-path does not contact the first wiring. Attached Figure Description

[0009] These and / or other aspects will become apparent and more readily understood from the following description of the embodiments in conjunction with the accompanying drawings, in which:

[0010] Figure 1 This is a schematic block diagram of an image sensor according to an embodiment;

[0011] Figure 2 This is a schematic layout diagram of the image sensor according to an embodiment;

[0012] Figure 3 This is a schematic cross-sectional view of an image sensor according to an embodiment;

[0013] Figure 4 yes Figure 3 A magnified view of region S1 of the image sensor;

[0014] Figure 5 Is Figure 4 An example circuit diagram of a unit pixel is shown in region S1;

[0015] Figures 6 to 8 According to the implementation method Figure 3 Enlarged views of various examples of region S2 of the image sensor;

[0016] Figure 9 Is Figures 6 to 8 The layout diagram of the first wiring structure and the first through path shown in region S2;

[0017] Figures 10 to 16 This is a view illustrating various examples of the first wiring structure and the first through path of an image sensor according to an embodiment;

[0018] Figure 17 This is a schematic cross-sectional view of an image sensor according to an embodiment;

[0019] Figure 18 This is a schematic cross-sectional view of an image sensor according to an embodiment;

[0020] Figure 19 yes Figure 18 A magnified view of region S3 of the image sensor;

[0021] Figure 20 This is a schematic cross-sectional view of an image sensor according to an embodiment;

[0022] Figure 21 yes Figure 20 A magnified view of region S4 of the image sensor;

[0023] Figure 22 A schematic cross-sectional view of an image sensor according to an embodiment; and

[0024] Figures 23 to 27 This is a view illustrating the steps of a method for manufacturing an image sensor according to an embodiment. Detailed Implementation

[0025] Now refer to Figures 1 to 22Describe an image sensor according to an embodiment.

[0026] Figure 1 This is a schematic block diagram of an image sensor according to an embodiment.

[0027] Reference Figure 1 The image sensor according to various embodiments includes an active pixel sensor (APS) array 10, a row decoder 20, a row driver 30, a column decoder 40, a timing generator 50, a correlated double sampler (CDS) 60, an analog-to-digital converter (ADC) 70, and an input / output (I / O) buffer 80.

[0028] The APS array 10 may include multiple unit pixels arranged in a two-dimensional manner and can convert optical signals into electrical signals. The APS array 10 can be driven by multiple drive signals received from the row driver 30, such as pixel selection signals, reset signals, and charge transfer signals. In addition, the electrical signals output from the APS array 10 can be provided to the CDS 60.

[0029] The row driver 30 can provide multiple drive signals for driving multiple unit pixels of the APS array 10 based on the decoding results of the row decoder 20. When the unit pixels are arranged in a matrix, the drive signals can be provided to each row.

[0030] The timing generator 50 can provide timing signals and control signals to the row decoder 20 and the column decoder 40.

[0031] The CDS 60 can receive electrical signals generated by the APS array 10, retain the received electrical signals, and sample the received electrical signals. The CDS 60 can double sample a specific noise level and a signal level of the electrical signal, and output the difference level between the noise level and the signal level.

[0032] The ADC 70 can convert the analog signal corresponding to the difference level output from the CDS 60 into a digital signal and output the digital signal.

[0033] I / O buffer 80 can latch digital signals and output the latched signals sequentially to the image signal processor (not shown) according to the decoding results of column decoder 40.

[0034] Figure 2 This is a schematic layout diagram of an image sensor according to an embodiment.

[0035] Reference Figure 2 The image sensor according to various embodiments may include a first stacked structure 100 and a second stacked structure 200.

[0036] The first stack structure 100 may be stacked on the second stack structure 200. In some embodiments, the first stack structure 100 may include a sensor array region SAR, a first connection region CR1, and a first pad region PR1.

[0037] Sensor array area SAR can include and Figure 1 The region corresponding to the APS array 10. For example, the sensor array region SAR may include multiple unit pixels arranged (e.g., arranged in a matrix) in a two-dimensional manner in a plane including the first direction X and the second direction Y. Each unit pixel may include a photoelectric conversion layer. (See below for further details.) Figures 3 to 5 This will be described in detail.

[0038] The first connection region CR1 can be disposed around the sensor array region SAR. The first connection region CR1 can electrically connect the sensor array region SAR of the first stacked structure 100 to the second stacked structure 200. (See below for further details.) Figure 3 This will be described in detail.

[0039] A first pad region PR1 can be disposed around the sensor array region SAR. Conductive pads can be formed in the first pad region PR1. According to an embodiment, the conductive pads can be connected to external devices and configured to transmit and receive electrical signals between the external devices and the image sensor. See below for further details. Figure 3 and Figures 6 to 9 This will be described in detail.

[0040] Figure 2 The arrangement of the first connection region CR1 and the first pad region PR1 in the diagram is merely an example, and the technical spirit of this disclosure is not limited to this example.

[0041] In some implementations, the second stack structure 200 may include a logic circuit region LR, a second connection region CR2, and a second pad region PR2.

[0042] Multiple electronic devices can be formed in the logic circuit region LR. These electronic devices may include, for example, transistors. The logic circuit region LR can be electrically connected to the sensor array region SAR and can send electrical signals to and receive electrical signals from each unit pixel of the sensor array region SAR. For example, the logic circuit region LR may include... Figure 1 The corresponding areas for the row decoder 20, row driver 30, column decoder 40, timing generator 50, CDS 60, ADC 70 and I / O buffer 80.

[0043] The second connection region CR2 can be disposed around the logic circuit region LR. The second connection region CR2 can electrically connect the logic circuit region LR of the second stacked structure 200 to the first stacked structure 100. Therefore, the sensor array region SAR can be electrically connected to the logic circuit region LR, and can send electrical signals to and receive electrical signals from the logic circuit region LR. The second connection region CR2 can be formed in the region of the second stacked structure 200 corresponding to the first connection region CR1, but the implementation is not limited to this.

[0044] The second pad region PR2 can be disposed around the logic circuit region LR. The second pad region PR2 can be electrically connected to the first pad region PR1. The second pad region PR2 can be formed in the region of the second stack structure 200 corresponding to the first pad region PR1, but the implementation is not limited to this. Each of the first pad region PR1 and the second pad region PR2 can include multiple pads.

[0045] Figure 3 This is a schematic cross-sectional view of an image sensor according to an embodiment. Figure 4 yes Figure 3 A magnified view of region S1 of the image sensor. Figure 5 Is Figure 4 An example circuit diagram per unit pixel is shown in region S1. Figures 6 to 8 yes Figure 3 Enlarged views of various examples of region S2 of the image sensor. Figure 9 Is Figures 6 to 8 The layout diagram of the first wiring structure and the first through path is shown above. For ease of description and brevity, the above references are... Figure 1 and Figure 2 Repeated descriptions of the components and features will be given only briefly or omitted.

[0046] Reference Figures 3 to 9 The image sensor according to various embodiments includes a first substrate 110, a first insulating structure 130, a first wiring structure IS1, a first connection pattern 140, a first through-path 160, a conductive pad 170, a second substrate 210, a second insulating structure 230, a second wiring structure IS2, and a second connection pattern 240.

[0047] In some embodiments, the first substrate 110 and the first insulating structure 130 may be included in the first stacked structure 100, and the second substrate 210 and the second insulating structure 230 may constitute a second stacked structure 200. The sensor array region SAR of the first stacked structure 100 may correspond to Figure 2The sensor array region SAR. The connection region CR of the first stacked structure 100 and the connection region CR of the second stacked structure 200 can respectively correspond to Figure 2 The first connection region CR1 and the second connection region CR2. The pad region PR of the first stacked structure 100 and the pad region PR of the second stacked structure 200 can respectively correspond to Figure 2 The first pad area PR1 and the second pad area PR2.

[0048] The first substrate 110 may include a first surface 110a and a second surface 110b that are opposite to each other (see example...). Figure 4 In some embodiments, the first surface 110a of the first substrate 110 may be a light-receiving surface on which light is incident. The first substrate 110 may be a semiconductor substrate. For example, the first substrate 110 may be bulk silicon or silicon-on-insulator (SOI). The first substrate 110 may be a silicon substrate or a substrate made of other materials such as silicon germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide. Alternatively, the first substrate 110 may include a base substrate and an epitaxial layer formed on the base substrate.

[0049] The first substrate 110 in the sensor array region SAR may include a photoelectric conversion layer PD. For example, such as Figure 4 As shown, each unit pixel may include a photoelectric conversion layer PD, an active region 112, a first transistor TR1, a first device isolation layer 114, a second device isolation layer 116, a first planarization layer 120, a color filter 124, a grid pattern 122, a second planarization layer 126, and a microlens 128.

[0050] A photoelectric conversion layer PD can be formed in the first substrate 110 in the sensor array region SAR. The photoelectric conversion layer PD can generate a charge proportional to the amount of light incident from the outside.

[0051] The photoelectric conversion layer (PD) may include, but is not limited to, photodiodes, phototransistors, optical gates, pinned photodiodes, organic photodiodes, quantum dots, or combinations thereof.

[0052] Active region 112 can be formed in the first substrate 110 below the second surface 110b. Active region 112 can be formed, for example, by doping the first substrate 110 with impurities. Active region 112 can form various active regions per unit pixel. For example, active region 112 can form what will be described later. Figure 5 Floating diffusion area FD or Figure 5 The source / drain regions of various transistors TG, RG, SF and SEL.

[0053] The first transistor TR1 can be formed on the second surface 110b of the first substrate 110. The first transistor TR1 can be connected to the photoelectric conversion layer PD to form various transistors for processing electrical signals. For example, the first transistor TR1 can be formed as described later. Figure 5 Various transistors including TG, RG, SF, and SEL.

[0054] In some embodiments, the first transistor TR1 may be a metal-oxide-semiconductor (MOS) transistor. For example, the first transistor TR1 may include a gate electrode TR1a, a gate dielectric layer TR1b, and a gate spacer TR1c. The gate dielectric layer TR1b may be interposed between the gate electrode TR1a and the first substrate 110. The gate spacer TR1c may extend along the side surface of the gate electrode TR1a.

[0055] The first device isolation layer 114 may define each unit pixel in the sensor array region SAR. For example, the first device isolation layer 114 may surround each unit pixel. The first device isolation layer 114 may be formed by filling an insulating material in a deep trench formed via a patterned first substrate 110. For example, the first device isolation layer 114 may extend from a first surface 110a to a second surface 110b. Depending on the patterning process, the first device isolation layer 114 may have a width in a horizontal direction parallel to the first surface 111a that varies from the first surface 110a toward the second surface 110b (e.g., in the third direction Z).

[0056] In some embodiments, the first device isolation layer 114 may include an insulating material having a refractive index lower than that of the first substrate 110. For example, when the first substrate 110 is made of silicon, the first device isolation layer 114 may include a silicon oxide layer, a silicon nitride layer, an undoped polysilicon layer, air, or a combination thereof. Therefore, the first device isolation layer 114 can cause total internal reflection of light incident at an angle onto the photoelectric conversion layer PD. Furthermore, the first device isolation layer 114 can prevent charges generated in a particular pixel by incident light from moving to adjacent unit pixels due to random drift. That is, the first device isolation layer 114 can improve the quality of image data by increasing the light reception rate of the photoelectric conversion layer PD.

[0057] The second device isolation layer 116 can define an active region 112 in each unit pixel. For example, the second device isolation layer 116 can be formed in the first substrate 110 below the second surface 110b. The second device isolation layer 116 can define the region in which the second device isolation layer 116 is not formed as the active region 112.

[0058] The second device isolation layer 116 can be formed by filling an insulating material into a shallow trench formed via a patterned first substrate 110. For example, the depth of the second device isolation layer 116 can be less than the depth of the first device isolation layer 114.

[0059] A first planarization layer 120 may be formed on a first surface 110a of the first substrate 110. The first planarization layer 120 may cover the first surface 110a of the first substrate 110. The first planarization layer 120 may include an insulating material. For example, the first planarization layer 120 may include silicon oxide.

[0060] Color filters 124 can be formed on a first planarization layer 120 in the sensor array region SAR. Each color filter 124 can correspond to a corresponding one in a unit pixel. For example, the color filters 124 can be arranged two-dimensionally (e.g., arranged in a matrix) in a plane including the first direction X and the second direction Y.

[0061] Depending on the unit pixel corresponding to the color filter 124, the color filter 124 can be a red filter, a green filter, or a blue filter. Alternatively, the color filter 124 can include a yellow filter, a magenta filter, and a cyan filter. Alternatively, the color filter 124 can also include a white filter.

[0062] The grid pattern 122 can be formed in a grid shape on the first surface 110a of the first substrate 110. For example, the grid pattern 122 can be formed on the first planarization layer 120 and interposed between the color filters 124. The grid pattern 122 can reflect light that is obliquely incident on the first substrate 110, thereby providing more incident light to the photoelectric conversion layer PD.

[0063] A second planarization layer 126 may be formed on the color filter 124. The second planarization layer 126 may cover the color filter 124. The second planarization layer 126 may include an insulating material. For example, the second planarization layer 126 may include silicon oxide.

[0064] Microlenses 128 may be disposed on the second planarization layer 126. Each microlens 128 may correspond to a specific one in a unit pixel. For example, the microlenses 128 may be arranged in two dimensions (e.g., in a matrix) in a plane including the first direction X and the second direction Y.

[0065] The microlens 128 may be convex and may have a predetermined radius of curvature. Therefore, the microlens 128 can concentrate incident light onto the photoelectric conversion layer PD. The microlens 128 may include, for example, a light-transmitting resin.

[0066] Each pixel in a SAR sensor array can receive light and convert the optical signal into an electrical signal. For example, ... Figure 5 As shown, each unit pixel in the sensor array region SAR may include a photoelectric conversion layer PD, a transmission transistor TG, a floating diffusion region FD, a reset transistor RG, a source follower transistor SF, and a selection transistor SEL.

[0067] The photoelectric conversion layer PD generates a charge proportional to the amount of light incident from the outside. The PD can be coupled to a transfer transistor TG, which transfers the generated and accumulated charge to a floating diffusion region FD. The floating diffusion region FD is the region that converts the charge into voltage and can accumulate and store charge due to its parasitic capacitance.

[0068] One end (i.e., the source or drain) of the transfer transistor TG can be connected to the photoelectric conversion layer PD, and the other end (i.e., the drain or source) of the transfer transistor TG can be connected to the floating diffusion region FD. The transfer transistor TG can be formed as a transistor driven by a predetermined bias (e.g., a transfer signal TX). That is, the transfer transistor TG can transfer the charge generated by the photoelectric conversion layer PD to the floating diffusion region FD according to the transfer signal TX.

[0069] The source follower transistor SF can amplify the potential change in the floating diffusion region FD that receives charge from the photoelectric conversion layer PD, and can output the amplified change to the output line V. OUT When the source follower transistor SF is turned on, a predetermined potential (e.g., power supply voltage V) is supplied to the drain of the source follower transistor SF. DD It can be transmitted to the drain region of the select transistor SEL.

[0070] The select transistor SEL can select the unit pixel to be read line by line. The select transistor SEL can be a transistor driven by a select line with a predetermined bias applied (e.g., the line select signal SX).

[0071] The reset transistor RG can periodically reset the floating diffuse region FD. The reset transistor RG can be a transistor driven by a reset line that applies a predetermined bias (e.g., a reset signal RX). When the reset transistor RG is turned on by the reset signal RX, a predetermined potential (e.g., a power supply voltage V) is supplied to the drain of the reset transistor RG. DD It can be transmitted to the floating diffusion region FD.

[0072] Refer to Figure 3 The first insulating structure 130 may be formed on the second surface 110b of the first substrate 110. The first insulating structure 130 may cover the second surface 110b of the first substrate 110. For example, the first insulating structure 130 may include a third surface 130a and a fourth surface 130b opposite to each other (see example). Figure 6Here, the third surface 130a of the first insulating structure 130 may face the second surface 110b of the first substrate 110. The first insulating structure 130 may consist of one or more layers.

[0073] The first insulating structure 130 may include an insulating material. For example, the first insulating structure 130 may include at least one of silicon oxide, silicon nitride, silicon nitride, and a low-k material having a dielectric constant lower than that of silicon oxide.

[0074] The first wiring structure IS1 may be formed on the second surface 110b of the first substrate 110. For example, the first wiring structure IS1 may be formed in the first insulating structure 130. The first wiring structure IS1 may include a plurality of first conductive layers 132 and a plurality of first channels 134. Figure 3 The number and arrangement of the first conductive layer 132 and the number and arrangement of the first passage 134 are merely examples, and the implementation is not limited to these examples.

[0075] The first conductive layer 132 can be formed as a multilayer structure. Each first conductive layer 132 can extend along a plane including, for example, a first direction X and a second direction Y.

[0076] For example, such as Figure 6 As shown, the first conductive layer 132 may include a first wiring M1, a second wiring M2, a third wiring M3, a fourth wiring M4, and a fifth wiring M5, which are sequentially stacked from the second surface 110b of the first substrate 110. That is, the first wiring M1 to the fifth wiring M5 may be gradually spaced apart from the first substrate 110 in this order. In the following description, for example, the first wiring M1 will be described as the first conductive layer in the first conductive layer 132 that is closest to the first substrate 110, and the fifth wiring M5 will be described as the first conductive layer in the first conductive layer 132 that is farthest from the first substrate 110.

[0077] The first passage 134 can connect the first conductive layers 132 to each other. Each first passage 134 can extend, for example, in a third direction Z to electrically connect the first conductive layers 132. Each first passage 134 can have various column shapes, such as cylinder, truncated cone, polygonal column or truncated pyramid.

[0078] The first conductive layer 132 and the first passage 134 may include a conductive material. For example, the first conductive layer 132 and the first passage 134 may include at least one of tungsten (W), copper (Cu), aluminum (Al), gold (Au), silver (Ag), and alloys thereof.

[0079] In some implementations, multiple unit pixels in the sensor array region SAR can be electrically connected to a first wiring structure IS1 in the sensor array region SAR. For example, as Figure 3 and Figure 4 As shown, the active region 112 and / or the first transistor TR1 can be connected to the first conductive layer 132 through the first passage 134. The first passage 134 can contact the gate electrode TR1a of the active region 112 or the first transistor TR1.

[0080] The first connection pattern 140 may be connected to the first wiring structure IS1. For example, the first connection pattern 140 may be connected to the bottom surface of the first conductive layer 132. The first connection pattern 140 may be exposed from the surface of the first insulating structure 130. For example, the first connection pattern 140 may extend in a third direction Z to be exposed from the fourth surface 130b of the first insulating structure 130. The first connection pattern 140 may have various columnar shapes, such as cylinders, truncated cones, polygonal cylinders, or truncated pyramidal shapes.

[0081] The first connection pattern 140 may include a conductive material. The first connection pattern 140 may include, for example, copper (Cu).

[0082] In some embodiments, the first connection pattern 140 may contact the first conductive layer 132 that is furthest from the first substrate 110. For example, as Figure 6 As shown, the first connection pattern 140 can contact the fifth wiring M5.

[0083] A first through-path 160 may be formed in the pad region PR. The first through-path 160 may penetrate the first substrate 110 in the pad region PR and may be connected to the first wiring structure IS1. For example, the first through-path 160 may extend in a third direction Z to connect to the upper surface of the first conductive layer 132. The first through-path 160 may have various column shapes, such as a cylinder, a truncated cone, a polygonal column, or a truncated pyramid.

[0084] The first through-path 160 may include a conductive material. For example, the first through-path 160 may include at least one of tungsten (W), copper (Cu), aluminum (Al), gold (Au), silver (Ag), and alloys thereof.

[0085] In some embodiments, the first through-path 160 can contact a first conductive layer 132 that is further away from the first conductive layer 110 than the first conductive layer closest to the first substrate 110. For example, as Figure 6 As shown, the first through-path 160 can contact the second wiring M2, which is farther away from the first wiring M1 and the first substrate 110. In the following description, the first conductive layer 132 that contacts the first through-path 160 may be referred to as a "landing pad". For example, in Figure 6 In this context, the second wiring M2 can be referred to as the landing pad.

[0086] In some implementations, in a top view, the first wiring M1 may surround the first through path 160. For example, as... Figure 6 and Figure 9 As shown, the first wiring M1 may include a first opening M1o. A first through-path 160 may pass through the first opening M1o to contact the second wiring M2. Although the first opening M1o is in Figure 9 The opening is shown as a square, but this is just an example. For example, the first opening M1o could also be circular or other polygonal in shape.

[0087] In some embodiments, the first path 134 connecting the first wiring M1 and the second wiring M2 may surround the first through path 160. For example, as Figure 9 As shown, the first passage 134 may surround the side surface of the first through passage 160 in a shape similar to that of the first wiring M1.

[0088] In some implementations, the first through-path 160 may not contact the first wiring M1. For example, as... Figure 6 As shown, the width W11 of the first through-path 160 can be smaller than the width W21 of the first opening M1o. Here, the term "width" refers to the length in the first direction X (or the second direction Y). Therefore, the first through-path 160 can penetrate the first wiring M1 to contact the second wiring M2.

[0089] In some embodiments, a first device isolation layer 114 in the first substrate 110 may be formed on the side of the first through-path 160. For example, the first device isolation layer 114 formed in the pad region PR may surround the side surface of the first through-path 160. In some embodiments, the first device isolation layer 114 formed in the pad region PR may be spaced apart from the side surface of the first through-path 160. The first device isolation layer 114 may electrically isolate the first through-path 160 in the first substrate 110.

[0090] In some embodiments, the first through-path 160 can contact the first conductive layer 132, which is further away from the first substrate 110 than the second wiring M2. For example, as Figure 7 As shown, the first through-path 160 can contact the third wiring M3. That is, in Figure 7 In the middle, the third wiring M3 can be the landing pad.

[0091] In some implementations, in a top view, the second wiring M2 may surround the first through path 160. For example, as... Figure 7 and Figure 9 As shown, the second wiring M2 may include a second opening M2o. The first through-path 160 may pass through the first opening M1o and the second opening M2o to contact the third wiring M3.

[0092] In some embodiments, the first through-path 160 can contact the first conductive layer 132 that is furthest from the first substrate 110. For example, as Figure 8 As shown, the first through-path 160 can contact the fifth wiring M5. That is, in Figure 8 In the middle, the fifth wiring M5 can be the landing pad.

[0093] In some implementations, in a top view, the first wiring M1 to the fourth wiring M4 may surround the first through path 160. For example, as... Figure 8 and Figure 9 As shown, the third wiring M3 may include a third opening M3o, and the fourth wiring M4 may include a fourth opening M4o. The first through-path 160 may extend through the first opening M1o to the fourth opening M4o to contact the fifth wiring M5. Alternatively, in some embodiments, the first through-path 160 may contact the fourth wiring M4.

[0094] Refer to Figure 3 Conductive pads 170 can be formed in the pad region PR. Furthermore, conductive pads 170 can be formed on the first surface 110a of the first substrate 110. For example, conductive pads 170 can be formed and exposed on the first planarization layer 120. Conductive pads 170 can be connected to a first through-path 160. For example, the first through-path 160 can penetrate the first substrate 110 and the first planarization layer 120, and can be connected to the bottom surface of the conductive pads 170.

[0095] The conductive pad 170 may include a conductive material. The conductive pad 170 may include at least one of, for example, tungsten (W), copper (Cu), aluminum (Al), gold (Au), silver (Ag), and alloys thereof. According to an embodiment, the conductive pad 170 may be connected to an external device and configured to transmit and receive electrical signals between the external device and the image sensor.

[0096] The second substrate 210 may be bulk silicon or SOI. The second substrate 210 may be a silicon substrate or a substrate made of other materials such as silicon germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide. Alternatively, the second substrate 210 may include a base substrate and an epitaxial layer formed on the base substrate.

[0097] Multiple electronic devices can be formed on the second substrate 210. For example, a second transistor TR2 can be formed on the second substrate 210. The second transistor TR2 can be configured as follows: Figure 2 The logic circuit area LR.

[0098] The second insulating structure 230 may be formed on the second substrate 210. The second insulating structure 230 may cover the second substrate 210. The second insulating structure 230 may be attached to the first insulating structure 130. For example, the second insulating structure 230 may be formed and attached to the fourth surface 130b of the first insulating structure 130.

[0099] The second insulating structure 230 may include one or more layers.

[0100] The second insulating structure 230 may include an insulating material. For example, the second insulating structure 230 may include at least one of silicon oxide, silicon nitride, silicon nitride, and a low-k material having a dielectric constant lower than that of silicon oxide. In some embodiments, the second insulating structure 230 may include the same material as the first insulating structure 130.

[0101] The second wiring structure IS2 can be formed on the fourth surface 130b of the first insulating structure 130. For example, the second wiring structure IS2 can be formed in the second insulating structure 230. The second wiring structure IS2 may include a plurality of second conductive layers 232 and a plurality of second channels 234. Figure 3 The number and arrangement of the second conductive layer 232 and the number and arrangement of the second passage 234 are merely examples, and the implementation is not limited to this example.

[0102] The second conductive layer 232 can be formed as a multilayer structure. Each second conductive layer 232 can extend along a plane including, for example, a first direction X and a second direction Y.

[0103] The second passage 234 can connect the second conductive layers 232 to each other. Each second passage 234 can extend, for example, in a third direction Z to electrically connect the second conductive layers 232. Each second passage 234 can have various column shapes, such as cylinder, truncated cone, polygonal cylinder or truncated pyramid.

[0104] The second conductive layer 232 and the second passage 234 may include a conductive material. For example, the second conductive layer 232 and the second passage 234 may include at least one of tungsten (W), copper (Cu), aluminum (Al), gold (Au), silver (Ag), and alloys thereof.

[0105] In some implementations, the second transistor TR2 may be electrically connected to the second wiring structure IS2. For example, as... Figure 3 As shown, the second transistor TR2 can be connected to the second conductive layer 232 through the second path 234.

[0106] In some implementations, the first wiring structure IS1 in the sensor array region SAR can be electrically connected to the second wiring structure IS2 in the connection region CR. For example, as Figure 3As shown, the first wiring structure IS1 in the sensor array region SAR can be connected to the second wiring structure IS2 in the connection region CR through the second through path 150.

[0107] A second through-path 150 can be formed in the connection region CR. The second through-path 150 can penetrate the first substrate 110 in the connection region CR to connect the first wiring structure IS1 and the second wiring structure IS2. For example, the second through-path 150 can extend in a third direction Z to connect the first conductive layer 132 and the second conductive layer 232 in the connection region CR. Therefore, the second transistor TR2 can be electrically connected to a unit pixel of the sensor array region SAR and send electrical signals to and receive electrical signals from each unit pixel of the sensor array region SAR.

[0108] Although the second through passage 150 is shown in the figures as extending conformally, this is merely an example. For instance, like the first through passage 160, the second through passage 150 could also have a column shape.

[0109] In some embodiments, a first device isolation layer 114 formed in the connection region CR may surround a side surface of the second through-path 150. In some embodiments, the first device isolation layer 114 formed in the connection region CR may be spaced apart from a side surface of the second through-path 150. The first device isolation layer 114 may electrically isolate the second through-path 150 in the first substrate 110.

[0110] The second connection pattern 240 can be connected to the second wiring structure IS2. The second wiring structure IS2 can connect the second connection pattern 240 and the second substrate 210. For example, the second connection pattern 240 can be connected to the upper surface of the second conductive layer 232. The second connection pattern 240 can be exposed from the surface of the second insulating structure 230. The second connection pattern 240 can have various columnar shapes, such as cylinders, truncated cones, polygonal cylinders, or truncated pyramids.

[0111] Furthermore, the second connection pattern 240 can be connected to the first connection pattern 140. For example, the surface of the first connection pattern 140 exposed from the first insulating structure 130 and the surface of the second connection pattern 240 exposed from the second insulating structure 230 can be in contact with each other. That is, the second connection pattern 240 can electrically connect the first connection pattern 140 and the second wiring structure IS2. Therefore, the second wiring structure IS2 can be electrically connected to the conductive pads 170 in the pad area PR and transmit and receive electrical signals between the image sensor and external devices according to the embodiment.

[0112] The second connection pattern 240 may include a conductive material. The second connection pattern 240 may include, for example, copper (Cu). In some embodiments, the second connection pattern 240 may include the same material as the first connection pattern 140.

[0113] In some embodiments, the second connection pattern 240 may contact the second conductive layer 232 that is furthest from the second substrate 210. For example, as Figure 6 As shown, the second connection pattern 240 can contact the sixth wiring M6.

[0114] As image sensors become more highly integrated, the area of ​​a single pixel gradually decreases. To improve the sensitivity of image sensors by compensating for this reduced pixel area, the thickness of the substrate, including the photoelectric conversion layer, and the thickness of the wiring structure used to transmit electrical signals generated from the photoelectric conversion layer are increased. However, the increased thickness of the wiring structure lengthens the path along which the electrical signal is transmitted, resulting in loss of data or electrical signals due to IR drop.

[0115] However, the image sensor according to the embodiment shortens the path along which the electrical signal is transmitted by using the first through-path 160. Therefore, an image sensor with improved performance can be provided. For example, as described above, the first through-path 160 can contact the first conductive layer 132 (e.g., the second wiring M2) which is farther from the first substrate 110 than the first wiring M1 closest to the first substrate 110. Therefore, the electrical signal path from the conductive pad 170 to the second wiring structure IS2 can be shortened, and the electrical signal of the pad region PR can be transmitted stably.

[0116] Figures 10 to 16 This is a view illustrating various examples of the first wiring structure and the first through path of an image sensor according to an embodiment. For ease of description and brevity, the above references... Figures 1 to 9 Repeated descriptions of the components and features will be given briefly or omitted. Figures 10 to 16 The description will primarily focus on the case where the landing pad is the second routing M2. However, those skilled in the art will understand from the above description that in some cases, the landing pad may also be one of the third to fifth routings M3 to M5.

[0117] Reference Figure 3 and Figure 10 In an image sensor according to various embodiments, the pad region PR includes a first region I and a second region II.

[0118] The first region I and the second region II may be adjacent to each other or spaced apart. In some embodiments, the first through-path 160 formed in the first region I and the first through-path 160 formed in the second region II may contact different first conductive layers 132. That is, the pads on which the first through-path 160 in the first region I and the pads on which the first through-path 160 in the second region II land may be different from each other.

[0119] For example, such as Figure 10 As shown, the first through path 160 formed in the first region I can contact the second wiring M2, and the first through path 160 formed in the second region II can contact the third wiring M3.

[0120] Reference Figure 3 , Figure 11A and Figure 11B In image sensors according to various embodiments, the first through-path 160 may contact a plurality of first conductive layers 132. For reference, Figure 11B yes Figure 11A The layout diagram of the first wiring structure IS1 and the first through path 160.

[0121] For example, the first through path 160 can contact the second wiring M2 and the third wiring M3.

[0122] In some embodiments, the first through-path 160 may contact the second wiring M2, and the second wiring M2 may include a second opening M2o. The first through-path 160 may pass through the second opening M2o of the second wiring M2 to contact the third wiring M3. Although the second opening M2o is in Figure 11B The middle part is shown as a square, but this is just an example. For example, the second opening M2o could also be circular or other polygonal shapes.

[0123] In some embodiments, the width W11 of the portion of the first through-path 160 that contacts the upper surface of the second wiring M2 (or the portion of the first through-path 160 that penetrates the first substrate 110) may be greater than the width W12 of the portion of the first through-path 160 that contacts the upper surface of the third wiring M3 (or the portion of the first through-path 160 that penetrates the second opening M2o). Furthermore, in some embodiments, the width W12 of the portion of the first through-path 160 that contacts the upper surface of the third wiring M3 (or the portion of the first through-path 160 that penetrates the second opening M2o) may be the same as the width W22 of the second opening M2o. As used herein, the term "same" not only covers being completely identical but also covers minor differences caused by process allowances, etc. Alternatively, in some embodiments, to be with Figure 11ASimilarly, the first through-path 160 can contact both the third wiring M3 and the fourth wiring M4, or both the fourth wiring M4 and the fifth wiring M5 (these two cases use different methods). Figure 11B (The reference numerals in parentheses are used to indicate this).

[0124] Because the first through-path 160 contacts the plurality of first conductive layers 132, the resistance between the first through-path 160 and the first wiring structure IS1 can be reduced. Therefore, the performance of the image sensor according to the embodiment can be improved.

[0125] Reference Figure 3 , Figure 12A and Figure 12B In image sensors according to various embodiments, a plurality of first through-paths 160 may be connected to a first conductive layer 132. For reference, Figure 12B yes Figure 12A The layout diagram of the first wiring structure IS1 and the first through path 160.

[0126] For example, the first through-path 160, which is spaced apart from each other, can contact the second wiring M2. Figure 12A and Figure 12B The number and arrangement of the first through passage 160 are merely examples, and the implementation is not limited to this example.

[0127] In some embodiments, the first through passages 160 can be arranged in a row. For example, as... Figure 12B As shown, the first through-path 160 can be arranged along the first direction X. Alternatively, in some embodiments, multiple first through-paths 160 can contact one of the third wiring M3 to the fifth wiring M5 (these cases use...). Figure 12B (The reference numerals in parentheses are used to indicate this).

[0128] Because the multiple first through-paths 160 contact the first conductive layer 132, the resistance between the first through-paths 160 and the first wiring structure IS1 can be reduced. Therefore, the performance of the image sensor according to the embodiment can be improved.

[0129] Reference Figure 3 , Figure 13A and Figure 13B In image sensors according to various embodiments, the landing pads may include multiple openings. For reference, Figure 13B yes Figure 13A The layout diagram of the first wiring structure IS1 and the first through path 160.

[0130] For example, the first through path 160 can contact the second wiring M2. That is, the second wiring M2 can be a landing pad. Here, the second wiring M2 can include multiple second openings M2o.

[0131] In some implementations, in a top view, the second opening M2o may not overlap with the first through passage 160. For example, as Figure 13B As shown, each second opening M2o can be inserted between the first through-paths 160. Alternatively, in some embodiments, the first through-path 160 can contact one of the third wiring M3 to the fifth wiring M5, and said one of the third wiring M3 to the fifth wiring M5 may include a plurality of corresponding openings (e.g., a plurality of third openings M3o, a plurality of fourth openings M4o, and a plurality of fifth openings M5o) that do not overlap with the first through-path 160 (these cases respectively use...) Figure 13B (The reference numerals in parentheses are used to indicate this).

[0132] Because the landing pads include multiple openings, warping caused by the difference in the coefficients of thermal expansion between the first through-path 160 and the first wiring structure IS1 can be mitigated. Therefore, the reliability of the image sensor according to the embodiment can be improved.

[0133] Reference Figure 3 , Figure 14A and Figure 14B In image sensors according to various embodiments, at least one of the first conductive layers 132 that is not attached to a pad may include a plurality of openings. For reference, Figure 14B yes Figure 14A The layout diagram of the first wiring structure IS1 and the first through path 160.

[0134] For example, the first through path 160 may contact the second wiring M2, but may not contact the third wiring M3 and the fourth wiring M4. That is, the second wiring M2 may be a landing pad, while the third wiring M3 and the fourth wiring M4 may not be landing pads. Here, the third wiring M3 may include multiple third openings M3o, and the fourth wiring M4 may include multiple fourth openings M4o.

[0135] In some embodiments, the second wiring M2 contacting the first through-path 160 and the fifth wiring M5 contacting the first connection pattern 140 may not include openings. Alternatively, in some embodiments, the first through-path 160 may contact the third wiring M3, and the fourth wiring M4 may include multiple fourth openings M4o (in this case, ...). Figure 14B (The reference numerals in parentheses are used to indicate this).

[0136] Because at least one of the first conductive layers 132 that is not a bonding pad includes multiple openings, warping caused by the difference in the coefficient of thermal expansion between the first through-path 160 and the first wiring structure IS1 can be mitigated. Therefore, the reliability of the image sensor according to the embodiment can be improved.

[0137] Reference Figure 3 and Figure 15 In image sensors according to various embodiments, multiple openings can be arranged in a matrix.

[0138] For example, the second wiring M2 may include a plurality of second openings M2o. The second openings M2o may be arranged in a matrix in a plane including the first direction X and the second direction Y. Therefore, in a top view, the second wiring M2 may have a grid shape. In some embodiments, the second wiring M2 may be a landing pad.

[0139] In some implementations, in a top view, the second opening M2o may at least partially overlap with the first through passage 160. For example, as Figure 15 As shown, at least a portion of each second opening M2o may overlap with one of the first through-paths 160. Alternatively, in some embodiments, the first through-path 160 may contact one of the third wiring M3 to the fifth wiring M5, and said one of the third wiring M3 to the fifth wiring M5 may include having a connection with... Figure 15 Multiple corresponding openings of similar shape to the multiple second openings M2o shown (e.g., multiple third openings M3o, multiple fourth openings M4o, or multiple fifth openings M5o) (these cases use respectively) Figure 15 (The reference numerals in parentheses are used to indicate this).

[0140] Reference Figure 3 and Figure 16 In image sensors according to various embodiments, multiple openings can be in the shape of slits.

[0141] For example, the second wiring M2 may include a plurality of second openings M2o. Each second opening M2o may extend, for example, in the first direction X.

[0142] In some embodiments, each second opening M2o may extend in the same direction as the direction in which the plurality of first through-paths 160 are arranged (e.g., first direction X). Alternatively, in some embodiments, the first through-path 160 may contact one of the third wiring M3 to the fifth wiring M5, and said one of the third wiring M3 to the fifth wiring M5 may include having a... Figure 16 Multiple corresponding openings of similar shape to the multiple second openings M2o shown (e.g., multiple third openings M3o, multiple fourth openings M4o, or multiple fifth openings M5o) (these cases use respectively) Figure 16 (The reference numerals in parentheses are used to indicate this).

[0143] Figure 17 This is a schematic cross-sectional view of an image sensor according to various embodiments. For ease of description and brevity, the above references... Figures 1 to 9 Repeated descriptions of the components and features will be given briefly or omitted.

[0144] Reference Figure 17 The image sensor according to various embodiments may also include an insulating spacer 162.

[0145] An insulating spacer 162 may be formed on the side surface of the first through-passage 160. For example, the insulating spacer 162 may extend along the side surface of the first through-passage 160. In some embodiments, the insulating spacer 162 may contact the side surface of the first through-passage 160. The insulating spacer 162 may electrically insulate the first through-passage 160 from the first substrate 110.

[0146] In some embodiments, the insulating spacer 162 may also be formed on the side surface of the second through-passage 150. For example, the insulating spacer 162 may extend along the side surface of the second through-passage 150. In some embodiments, the insulating spacer 162 may contact the side surface of the second through-passage 150. The insulating spacer 162 may electrically insulate the second through-passage 150 from the first substrate 110.

[0147] The insulating spacer 162 may include an insulating material. For example, the insulating spacer 162 may include at least one of silicon oxide, silicon nitride, silicon nitride, and a low-k material having a dielectric constant lower than that of silicon oxide.

[0148] Figure 18 This is a schematic cross-sectional view of an image sensor according to various embodiments. Figure 19 yes Figure 18 A magnified view of region S3. For ease of description and brevity, the above references... Figures 1 to 9 Repeated descriptions of the components and features will be given briefly or omitted.

[0149] Reference Figure 18 and Figure 19 In image sensors according to various embodiments, the first conductive layer connected to the landing pad may be omitted between the landing pad and the first substrate 110.

[0150] For example, the first through-path 160 can contact the second wiring M2. That is, the second wiring M2 can be a landing pad. Here, a first conductive layer connecting the second wiring M2 to the first substrate 110 may not be formed. For example, as Figure 19 As shown, Figure 6 The first wiring M1 can be omitted.

[0151] Figure 20 This is a schematic cross-sectional view of an image sensor according to various embodiments. Figure 21yes Figure 20 A magnified view of region S4. For ease of description and brevity, the above references are... Figures 1 to 9 Repeated descriptions of the components and features will be given briefly or omitted.

[0152] Reference Figure 20 and Figure 21 In the image sensor according to various embodiments, the conductive layer that is furthest from the first substrate 110 among the plurality of first conductive layers 132 can be formed to be larger than the other conductive layers.

[0153] For example, the fifth wiring M5 can be formed to be larger than the first wiring M1 through the fourth wiring M4. For example, as Figure 21 As shown, the width W31 of the fifth wiring M5 can be greater than the width W32 of the fourth wiring M4. Here, width refers to the length in the first direction X (or the second direction Y).

[0154] In some implementations, multiple connection patterns 140 may be connected to the first conductive layer 132. For example, first connection patterns 140 spaced apart from each other may contact the fifth wiring M5.

[0155] In some embodiments, the conductive layer 232 that is furthest from the second substrate 210 can be formed larger than the other conductive layers. For example, the width W41 of the sixth wiring M6 can be greater than the width of the other second conductive layers 232 (e.g., Figure 21 (as shown in W42). In some embodiments, the width W41 may be the same as the width W31. In other embodiments, the width W41 may be different from the width W31.

[0156] In some implementations, a plurality of second connection patterns 240 may be connected to the second conductive layer 232. For example, second connection patterns 240 spaced apart from each other may contact the sixth wiring M6.

[0157] Figure 20 and Figure 21 The number and arrangement of the first connecting pattern 140 and the second connecting pattern 240 are merely examples, and the implementation is not limited to this example.

[0158] Figure 22 This is a schematic cross-sectional view of an image sensor according to various embodiments. For ease of description and brevity, the above references... Figures 1 to 9 Repeated descriptions of the components and features will be given briefly or omitted.

[0159] Reference Figure 22In an image sensor according to various embodiments, a first connection pattern 140 and a second connection pattern 240 connect a first wiring structure IS1 and a second wiring structure IS2 in a sensor array region SAR.

[0160] For example, at least some of the first connection patterns 140 may be formed in the first insulating structure 130 in the sensor array region SAR. Furthermore, at least some of the second connection patterns 240 may be connected to the first connection pattern 140 in the sensor array region SAR.

[0161] In some embodiments, the first connection pattern 140 and the second connection pattern 240 may also be connected to the first wiring structure IS1 and the second wiring structure IS2 in the connection area CR.

[0162] For example, at least some of the first connection patterns 140 may be formed in the first insulating structure 130 in the connection region CR. Furthermore, at least some of the second connection patterns 240 may be connected to the first connection pattern 140 in the connection region CR.

[0163] Now refer to Figures 23 to 27 Methods for manufacturing an image sensor according to various embodiments are described.

[0164] Figures 23 to 27 This is a view illustrating the steps of a method for manufacturing an image sensor according to various embodiments. For ease of description and brevity, the above references... Figures 1 to 9 Repeated descriptions of the components and features will be given briefly or omitted.

[0165] Reference Figure 23 A first insulating structure 130 is formed on the first substrate 110. The first substrate 110 and the first insulating structure 130 may be included in the first stacked structure 100.

[0166] A photoelectric conversion layer PD, an active region 112, and a first device isolation layer 114 can be formed in the first substrate 110. In addition, a first transistor TR1 can be formed on the first substrate 110.

[0167] Then, a first insulating structure 130 can be formed on the first substrate 110. In some embodiments, the first insulating structure 130 can be formed on the front side of the first substrate 110 (e.g., Figure 4 The second surface 110b).

[0168] A first wiring structure IS1 and a first connection pattern 140 may be formed in the first insulating structure 130. The first wiring structure IS1 may include a plurality of first conductive layers 132 and a plurality of first vias 134. The first connection pattern 140 may be connected to the first wiring structure IS1 and exposed from the first insulating structure 130.

[0169] Reference Figure 24 A second insulating structure 230 can be formed on the second substrate 210. The second substrate 210 and the second insulating structure 230 can constitute a second stacked structure 200.

[0170] A second transistor TR2 can be formed on the second substrate 210.

[0171] Then, a second insulating structure 230 can be formed on the second substrate 210. A second wiring structure IS2 and a second connection pattern 240 can be formed in the second insulating structure 230. The second wiring structure IS2 may include a plurality of second conductive layers 232 and a plurality of second vias 234. The second connection pattern 240 can be connected to the second wiring structure IS2 and exposed from the second insulating structure 230.

[0172] Reference Figure 25 The first insulating structure 130 and the second insulating structure 230 can be attached to each other.

[0173] For example, it can be Figure 23 The upper surface of the first insulating structure 130 is attached to Figure 24 The upper surface of the second insulating structure 230. In some embodiments, the first insulating structure 130 and the second insulating structure 230 can be attached by copper-to-copper bonding. Therefore, the first connection pattern 140 exposed from the first insulating structure 130 and the second connection pattern 240 exposed from the second insulating structure 230 can be connected to each other. In addition, the first wiring structure IS1 and the second wiring structure IS2 can be electrically connected to each other.

[0174] Reference Figure 26 A first planarization layer 120, a color filter 124, a grid pattern 122, a second planarization layer 126, and a microlens 128 can be sequentially formed on the first substrate 110.

[0175] In some embodiments, the first planarization layer 120, color filter 124, grid pattern 122, second planarization layer 126, and microlens 128 may be formed on the rear side of the first substrate 110 (e.g., Figure 4 The first surface 110a).

[0176] Reference Figure 27 This can form the first hole H1 and the second hole H2.

[0177] A first via H1 may be formed in the pad region PR. The first via H1 may penetrate the first substrate 110 in the pad region PR. In some embodiments, the first via H1 may expose a first conductive layer 132 in the pad region PR. In some embodiments, the first via H1 may expose a first conductive layer 132 closest to the first substrate 110 (e.g., ...). Figure 6 The first wiring M1) is further away from the first substrate 110 than the first conductive layer 132 (e.g. Figure 6 The second wiring M2).

[0178] In some implementations, the first hole H1 may be surrounded by a first device isolation layer 114 formed in the pad region PR.

[0179] A second hole H2 may be formed in the connection region CR. The second hole H2 may penetrate the first substrate 110 in the connection region CR. In some embodiments, the second hole H2 may expose the first conductive layer 132 and the second conductive layer 232 in the connection region CR.

[0180] In some embodiments, the second hole H2 can be formed simultaneously with the first hole H1. Alternatively, the first hole H1 can be formed before or after the formation of the second hole H2.

[0181] Next, refer to Figure 3 This forms the first through passage 160 and the second through passage 150.

[0182] The first through passage 160 can be formed as a filling Figure 27 The first hole H1. Then, a conductive pad 170 can be formed on the first through-path 160. Therefore, the second wiring structure IS2 can be electrically connected to the conductive pad 170 in the pad area PR to transmit and receive electrical signals between external devices and the image sensor according to the embodiment.

[0183] In some embodiments, the first through passage 160 may be formed to be completely filled. Figure 27 The first hole H1. Or, the first through passage 160 can be along... Figure 27 The profile (e.g., inner surface) of the first hole H1 extends.

[0184] The second through passage 150 can be formed as a filling Figure 27 The second hole H2. Therefore, the second transistor TR2 can be electrically connected to the unit pixel of the sensor array region SAR, and can send electrical signals to and receive electrical signals from each unit pixel of the sensor array region SAR.

[0185] In some embodiments, the second through passage 150 can be along... Figure 27The contour (e.g., inner surface) of the second hole H2 extends. Alternatively, the second through passage 150 can be formed to be completely filled. Figure 27 The second hole, H2.

[0186] In concluding this detailed description, those skilled in the art will recognize that many variations and modifications can be made to the various embodiments without substantially departing from the principles of the inventive concept. Therefore, the various embodiments disclosed are used only in a general and descriptive sense and not for limiting purposes.

[0187] This application claims priority to Korean Patent Application No. 10-2019-0101623, filed on August 20, 2019, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety.

Claims

1. An image sensor, comprising: The substrate includes a sensor array region and a pad region disposed around the sensor array region, and includes a first surface and a second surface that are opposite to each other; A first insulating structure is disposed on the second surface of the substrate and includes a third surface facing the second surface and a fourth surface opposite to the third surface; A first wiring structure is formed in the first insulating structure and includes a plurality of first conductive layers and a plurality of first channels; A through-path that extends through the substrate in the pad area and connects to the first wiring structure; A first connection pattern is exposed from the fourth surface of the first insulating structure and connected to the first wiring structure; A second insulating structure is disposed on the fourth surface of the first insulating structure; as well as A second connection pattern is exposed from the surface of the second insulating structure facing the fourth surface and connected to the first connection pattern. The plurality of first conductive layers include a first wiring and a second wiring that is further away from the substrate than the first wiring, and the through-path contacts the second wiring. The first wiring includes a first opening that at least partially overlaps with the first connection pattern and the second connection pattern in the direction in which the through-path extends.

2. The image sensor according to claim 1, wherein the first wiring is the first conductive layer among the plurality of first conductive layers that is closest to the substrate.

3. The image sensor of claim 1, wherein the second wiring contacts the first connection pattern.

4. The image sensor of claim 3, wherein the second wiring is the first conductive layer among the plurality of first conductive layers that is furthest from the substrate.

5. The image sensor of claim 1, wherein the first wiring structure further includes a third wiring that is further away from the substrate than the second wiring, and the third wiring contacts the first connection pattern.

6. The image sensor of claim 5, wherein the third wiring is the first conductive layer among the plurality of first conductive layers that is furthest from the substrate.

7. The image sensor according to claim 5, wherein the width of the third wiring is greater than the width of the first wiring and the width of the second wiring.

8. The image sensor of claim 1 further includes conductive pads disposed on the first surface of the substrate in the pad region and connected to the through-path.

9. The image sensor according to claim 1, wherein, In the top view, the first wiring surrounds the through path.

10. An image sensor, comprising: A substrate comprising a photoelectric conversion layer, a first surface, and a second surface opposite to the first surface, wherein light is incident on the first surface; Conductive pads are disposed on the first surface of the substrate; A first insulating structure is disposed on the second surface of the substrate and includes a third surface facing the second surface and a fourth surface opposite to the third surface; A first wiring is formed in the first insulating structure and includes a first opening; The second wiring is formed in the first insulating structure and is further away from the substrate than the first wiring; A through-path that extends through the substrate and the first opening to connect the conductive pad to the second wiring; A first connection pattern is exposed from the fourth surface of the first insulating structure and connected to the second wiring; A second insulating structure is disposed on the fourth surface of the first insulating structure; as well as A second connection pattern is exposed from the surface of the second insulating structure facing the fourth surface and connected to the first connection pattern. In the direction in which the through passage extends, the first opening at least partially overlaps with the first connection pattern and the second connection pattern.

11. The image sensor of claim 10, wherein the width of the through-path is smaller than the width of the first opening.

12. The image sensor of claim 10, wherein the first width of the portion of the through-path penetrating the substrate is greater than the width of the first opening, and the second width of the portion of the through-path penetrating the first opening is equal to the width of the first opening.

13. The image sensor of claim 12, wherein the through-path contacts both the first wiring and the second wiring.

14. The image sensor of claim 10, wherein the second wiring includes a second opening, and the through-path contacts at least a portion of the second wiring.

15. The image sensor according to claim 14, wherein, In the top view, the second opening does not overlap with the through passage.

16. The image sensor according to claim 14, wherein, In the top view, at least a portion of the second opening overlaps with the through passage.

17. An image sensor, comprising: A first substrate includes a sensor array region and a pad region disposed around the sensor array region, and includes a first surface and a second surface opposite to the first surface, on which light is incident; A color filter is disposed on the first surface of the first substrate in the sensor array region; Microlenses are disposed on the color filter; A conductive pad is disposed on the first surface of the first substrate in the pad area. A first insulating structure is disposed on the second surface of the first substrate and includes a third surface facing the second surface and a fourth surface opposite to the third surface; A first wiring structure is formed in the first insulating structure and includes a plurality of first conductive layers and a plurality of first channels. The plurality of first conductive layers include a first wiring and a second wiring. The first wiring is the first conductive layer among the plurality of first conductive layers that is closest to the first substrate, and the second wiring is farther away from the first substrate than the first wiring. A first through-path extends through the first substrate in the pad region to connect the conductive pad and the first wiring structure; A first connection pattern is exposed from the fourth surface of the first insulating structure and connected to the first wiring structure; A second insulating structure is disposed on the fourth surface of the first insulating structure; A second wiring structure is formed in the second insulating structure and includes a plurality of second conductive layers and a plurality of second channels; as well as A second connection pattern is exposed from the surface of the second insulating structure facing the fourth surface and connects the first connection pattern and the second wiring structure. The first through-path does not contact the first wiring, but the first through-path contacts the second wiring. The first wiring includes a first opening that at least partially overlaps with the first connection pattern and the second connection pattern in the direction in which the through-path extends.

18. The image sensor of claim 17, further comprising a second substrate disposed on the second insulating structure, wherein the second wiring structure connects the second connection pattern and the second substrate.

19. The image sensor of claim 18, wherein the first substrate further includes a connection region disposed around the sensor array region, and the image sensor further includes a second through-path extending through the first substrate in the connection region to connect the first wiring structure and the second wiring structure.

Images