Imaging element and electronic device

Abstract

The present invention relates to an imaging element and an electronic device capable of reducing the size of the imaging element without degrading the performance of the imaging element. The imaging element includes: a pixel array unit in which pixels including photoelectric conversion elements are arranged two-dimensionally; a row circuit for controlling row scanning of the pixel array unit; and a column processing unit for converting an analog signal read out from the pixel array unit into a digital signal. The pixel array unit is arranged on a first-layer substrate, and the row circuit and the column processing unit are respectively arranged on different substrates which are lower layers of the first-layer substrate and laminated to the first-layer substrate. The present invention can be applied to an imaging element.

Description

[0001] This application is a divisional application of the patent application with application number 201580015655.9, titled "Imaging Element and Electronic Device", and the filing date is April 3, 2015. Technical Field

[0002] The present invention relates to an imaging element and an electronic device, and more particularly to an imaging element and an electronic device suitable for achieving a smaller size. Background Art

[0003] In the related art, imaging devices such as digital cameras and digital video cameras that use an imaging element to record a captured image have been proposed. The imaging element has a pixel unit and a peripheral circuit unit. The peripheral circuit unit reads out a signal from the pixel and outputs the signal as an image signal. The pixel unit performs photoelectric conversion by using a photodiode, and the signal obtained by the photoelectric conversion is read out to the peripheral circuit unit through a pixel circuit formed in the pixel unit.

[0004] In recent years, although it is desired that such an imaging device has more pixels, higher image quality, and faster speed, it is also desired that the imaging device be smaller. As an imaging device that meets these expectations, a stacked imaging device has been proposed. In the structure of the stacked imaging device, a chip on which a signal processing circuit is formed is used instead of the support substrate of the imaging device, and a pixel portion is stacked on the chip. It has been proposed to make the imaging device smaller by using such a structure (for example, see Patent Documents 1 to 3).

[0005] Citation List

[0006] Patent Documents

[0007] Patent Document 1: JP 2013 - 051674A

[0008] Patent Document 2: JP 2011 - 204915A

[0009] Patent Document 3: JP 2011 - 159958A Summary of the Invention

[0010] Technical Problem

[0011] Even when the imaging device has a stacked structure in which the pixel circuit and the peripheral circuit are arranged on a plurality of substrates, it is still desired to form an image area and a logic circuit that performs signal processing so that each can fully exhibit its performance while achieving higher performance and a smaller size.

[0012] The present invention is proposed in view of these circumstances and aims to make the imaging element smaller.

[0013] Solution to the Problem

[0014] The first imaging element according to one aspect of the present invention includes: a pixel array unit in which pixels including photoelectric conversion elements are arranged two-dimensionally; a row circuit for controlling row scanning of the pixel array unit; and a column processing unit for converting an analog signal read out from the pixel array unit into a digital signal. The pixel array unit is arranged on a first layer substrate, and the row circuit and the column processing unit are respectively arranged on different substrates, and the different substrates are lower layers of the first layer substrate and are laminated to the first layer substrate.

[0015] The length of the row circuit in the vertical direction may be equal to or greater than the length of the pixel array unit in the vertical direction.

[0016] The length of the column processing unit in the horizontal direction may be equal to or greater than the length of the pixel array unit in the horizontal direction.

[0017] When laminating the first substrate on which the pixel array unit is arranged and the second substrate on which the row circuit is arranged, the row circuit is arranged on the second substrate in such a manner that the central axis of the pixel array unit in the horizontal direction is offset in position from the central axis of the row circuit in the horizontal direction.

[0018] When laminating the first substrate on which the pixel array unit is arranged and the second substrate on which the column processing unit is arranged, the column processing unit is arranged on the second substrate in such a manner that the central axis of the pixel array unit in the vertical direction is offset in position from the central axis of the column processing unit in the vertical direction.

[0019] A memory may be arranged on the same substrate as the row circuit or the column processing unit.

[0020] The first electronic device according to one aspect of the present invention includes: an imaging element including a pixel array unit in which pixels including photoelectric conversion elements are arranged two-dimensionally, a row circuit for controlling row scanning of the pixel array unit, and a column processing unit for converting an analog signal read out from the pixel array unit into a digital signal, wherein the pixel array unit is arranged on a first layer substrate, and the row circuit and the column processing unit are respectively arranged on different substrates, and the different substrates are lower layers of the first layer substrate and are laminated to the first layer substrate; and a signal processing unit for performing signal processing on a signal output from the imaging element.

[0021] In a first imaging element according to one aspect of the present invention, there is included: a pixel array unit in which pixels including photoelectric conversion elements are arranged two-dimensionally; a row circuit for controlling row scanning of the pixel array unit; and a column processing unit for converting an analog signal read out from the pixel array unit into a digital signal. The pixel array unit is arranged on a first layer substrate, and the row circuit and the column processing unit are respectively arranged on different substrates which are lower layers of the first layer substrate and laminated to the first layer substrate.

[0022] A first electronic device according to one aspect of the present invention includes the first imaging element.

[0023] A second imaging element according to one aspect of the present invention includes: a pixel array unit in which pixels including photoelectric conversion elements are arranged two-dimensionally. The pixel array unit is arranged on a first layer substrate, and among a circuit for controlling the pixel array unit and a circuit for processing signals from the pixel array unit, a circuit for processing an analog signal and a circuit for processing a digital signal are arranged on different substrates which are lower layers of the first layer substrate and laminated to the first layer substrate.

[0024] Among column processing units for converting an analog signal read out from the pixel array unit into a digital signal, the circuit for processing the analog signal and the circuit for processing the digital signal may be arranged on the different substrates.

[0025] On each of the first layer substrate and a plurality of substrates which are lower layers of the first layer substrate, a circuit composed of only low breakdown voltage transistors or high breakdown voltage transistors is arranged.

[0026] A second electronic device according to one aspect of the present invention includes: an imaging element including a pixel array unit in which pixels including photoelectric conversion elements are arranged two-dimensionally, wherein the pixel array unit is arranged on a first layer substrate, and among a circuit for controlling the pixel array unit and a circuit for processing signals from the pixel array unit, a circuit for processing an analog signal and a circuit for processing a digital signal are arranged on different substrates which are lower layers of the first layer substrate and laminated to the first layer substrate; and a signal processing unit for performing signal processing on a signal output from the imaging element.

[0027] In a second imaging element according to one aspect of the present invention, it includes: a pixel array unit in which pixels including photoelectric conversion elements are arranged two-dimensionally. The pixel array unit is arranged on a first-layer substrate, and among the circuits for controlling the pixel array unit and the circuits for processing signals from the pixel array unit, the circuit for processing analog signals and the circuit for processing digital signals are arranged on different substrates, and the different substrates are lower layers of the first-layer substrate and are laminated to the first-layer substrate.

[0028] A second electronic device according to one aspect of the present invention includes the second imaging element.

[0029] Advantages of the invention

[0030] According to one aspect of the present invention, the imaging element can be further made smaller.

[0031] Note that the effects described here are not necessarily restrictive, and other effects expected to be described in the present invention may also be exhibited. Brief description of the drawings

[0032] Figure 1 It is a diagram illustrating the configuration of an imaging device.

[0033] Figure 2 It is a diagram illustrating the configuration of a solid-state imaging element.

[0034] Figure 3 It is a diagram for explaining the circuit arrangement.

[0035] Figure 4 It is a diagram for explaining the circuit arrangement.

[0036] Figure 5 It is a diagram for explaining the circuit arrangement.

[0037] Figure 6 It is a diagram for explaining the circuit arrangement.

[0038] Figure 7 It is a diagram for explaining the circuit arrangement.

[0039] Figure 8 It is a diagram for explaining the circuit arrangement.

[0040] Figure 9 It is a diagram for explaining the circuit arrangement.

[0041] Figure 10 It is a diagram for explaining the circuit arrangement.

[0042] Figure 11 It is a diagram for explaining the circuit arrangement.

[0043] Figure 12 is a diagram for illustrating a circuit arrangement.

[0044] Figure 13 is a diagram of a circuit arrangement for illustrating signal flow.

[0045] Figure 14 is a diagram of a circuit arrangement for illustrating analog and digital circuits.

[0046] Figure 15 is a diagram of a circuit arrangement for illustrating analog and digital circuits.

[0047] Figure 16 is a diagram of a circuit arrangement for illustrating analog and digital circuits.

[0048] Figure 17 is a diagram for illustrating an application example of the device according to the present invention.

[0049] Figure 18 is a diagram for illustrating an application example of the device according to the present invention.

[0050] Figure 19 is a diagram for illustrating an application example of the device according to the present invention. Detailed implementation manners

[0051] The implementation manners for implementing the present invention (hereinafter referred to as embodiments) will be described below. Note that the description will be made in the following order.

[0052] 1. Structure of the imaging device

[0053] 2. Structure of the imaging element

[0054] 3. Circuit arrangement when the imaging element is composed of multiple layers

[0055] 4. Signal flow and circuit arrangement

[0056] 5. Application examples

[0057] <Structure of the imaging device>

[0058] The following invention can be applied to general electronic devices such as imaging devices (e.g., digital cameras and video cameras, etc.), mobile terminal devices with imaging functions (e.g., mobile phones, etc.), and copying machines that use an imaging element as an image reading unit.

[0059] Figure 1 is a block diagram illustrating a structural example of an electronic device (e.g., an imaging device according to the present invention). As Figure 1As shown, the imaging device 10 according to the present invention includes an optical system including a lens group 21, etc., a solid-state imaging element (imaging device) 22, a digital signal processor (DSP) circuit 23, a frame memory 24, a display unit 25, a recording unit 26, an operation unit 27, a power supply unit 28, etc. The DSP circuit 23, the frame memory 24, the display unit 25, the recording unit 26, the operation unit 27, and the power supply unit 28 are connected to each other via a bus 29.

[0060] The lens group 21 receives incident light (image light) from a subject to form an image of the incident light on the imaging surface of the solid-state imaging element 22. The solid-state imaging element 22 converts the amount of light of the incident light formed on the imaging surface by the lens group 21 into an electrical signal and outputs the electrical signal as a pixel signal.

[0061] The DSP circuit 23 processes the signal from the solid-state imaging element 22. For example, although it will be described in detail later, the solid-state imaging element 22 having pixels for detecting focus performs the following processing: processing the signal from the pixels and detecting focus. In addition, the solid-state imaging element 22 having pixels for constructing a subject image also performs the following processing: processing the signal from the pixels and decompressing the image in the frame memory 24.

[0062] The display unit 25 formed of a panel display device such as a liquid crystal display device and an organic electroluminescence (EL) display device displays a moving image or a still image captured at the solid-state imaging element 22. The recording unit 26 records the moving image or the still image captured at the solid-state imaging element 22 in a recording medium such as a hard disk drive (HDD).

[0063] Under the operation of the user, the operation unit 27 issues operation commands related to various functions of the imaging device. The power supply unit 28 appropriately supplies various types of power to the DSP circuit 23, the frame memory 24, the display unit 25, the recording unit 26, and the operation unit 27, and the supplied power becomes the operation power of these power supply targets.

[0064] The imaging device having the above configuration can be used as an imaging device such as a camera module of a mobile device (e.g., a mobile phone, etc.), a video camera, and a digital camera.

[0065] <Configuration of the imaging element>

[0066] Figure 2 It is a diagram illustrating the configuration of the solid-state imaging element 22 and is a system configuration diagram schematically illustrating the configuration of, for example, a CMOS imaging element, where the CMOS imaging element is an imaging device having an X-Y addressing method. Here, the CMOS imaging element is a imaging element manufactured by applying or partially using a CMOS process.

[0067] Figure 2 The solid-state imaging device 22 therein has a pixel array unit 101, in which a plurality of pixels (not shown) including photoelectric conversion elements are arranged in a matrix in a two-dimensional manner. The solid-state imaging device 22 includes a vertical drive circuit (row scanning circuit) 102, a vertical decoder 103, a column processing unit 104, a reference signal supply unit 105, a horizontal scanning circuit (column scanning circuit) 106, a timing control circuit 107, and an image signal processing unit 108.

[0068] The solid-state imaging device 22 also has an I / F system circuit 109. The column processing unit 104 includes a comparator 1041 and a counter circuit 1042.

[0069] In this solid-state imaging device 22, the timing control circuit 107 generates a clock signal or a control signal based on a master clock, and the generated clock signal or control signal serves as a reference for the operations of the vertical drive circuit 102, the column processing unit 104, the reference signal supply unit 105, or the horizontal scanning circuit 106, etc.

[0070] As a unit pixel (although not shown here), a photoelectric conversion element (e.g., a photodiode) is provided. In addition to the photoelectric conversion element, the unit pixel also has, for example, a transfer transistor for transferring the charge obtained by performing photoelectric conversion at the photoelectric conversion element to a floating diffusion (FD) unit.

[0071] As a unit pixel, a pixel composed of three transistors can be applied. In addition to the transfer transistor, these three transistors also include a reset transistor for controlling the potential of the FD unit and an amplification transistor for outputting a signal consistent with the potential of the FD unit. Alternatively, as a unit pixel, a pixel composed of four transistors can be used, and these four transistors also include a selection transistor for performing pixel selection.

[0072] In the pixel array unit 101, the unit pixels of m rows and n columns are arranged in a two-dimensional manner, and for such an m-row and n-column pixel arrangement, there are row control lines wired for each row and column signal lines wired for each column. One end of each row control line is connected to the corresponding output terminal corresponding to each row of the vertical drive circuit 102. The vertical drive circuit 102 composed of a shift register, etc. controls the row addressing and row scanning of the pixel array unit 101 via the row control lines.

[0073] The column processing unit 104 has, for example, an analog-to-digital converter (ADC) provided for each pixel column of the pixel array unit 101 (i.e., for each vertical signal line LSGN), converts an analog signal output from each unit pixel of the pixel array unit 101 into a digital signal for each column, and outputs the digital signal.

[0074] The reference signal supply unit 105 has, for example, a digital-to-analog converter (DAC) as a unit that generates a so-called reference voltage Vref having a ramp waveform, and the level of the reference voltage changes obliquely with time.

[0075] Note that the unit that generates the reference voltage Vref having a ramp waveform is not limited to the DAC.

[0076] Under the control of the control signal provided from the timing control circuit 107, the DAC generates a reference voltage Vref having a ramp waveform based on the clock provided from the timing control circuit 107, and supplies the reference voltage Vref to the ADC of the column processing unit 104.

[0077] Note that the configuration of each ADC can selectively perform an AD conversion operation corresponding to each of the normal frame rate mode and the high-speed frame rate mode, where the normal frame rate mode has a progressive scanning method of reading out information of all unit pixels.

[0078] In the high-speed frame rate mode, the exposure period of the unit pixel is set to 1 / N of the exposure period in the normal frame rate mode, and the frame rate is, for example, N times (e.g., twice) the frame rate in the normal frame rate mode. The switching of the operation mode is performed under the control of the control signal provided from the timing control circuit 107. In addition, instruction information for switching between the normal frame rate mode and the high-speed frame rate mode is provided from an external system controller (not shown) to the timing control circuit 107.

[0079] Each ADC has the same configuration, and each ADC has a comparator 1041 and a counter circuit 1042. For example, it includes an up / down counter, a transfer switch, and a memory device.

[0080] The comparator 1041 compares the signal voltage that coincides with the signal output from each unit pixel in the nth column of the pixel array unit 101 on the vertical signal line with the reference voltage Vref having a ramp waveform provided from the reference signal supply unit 105.

[0081] The output Vco of the comparator 1041 becomes the "H" level when the reference voltage Vref is greater than the signal voltage, and the output Vco becomes the "L" level when the reference voltage Vref is equal to or less than the signal voltage Vx.

[0082] Under the control of the control signal provided from the timing control circuit 107, the clock from the timing control circuit 107 is provided to the DAC and also to the counter circuit 1042 which serves as an up / down counter and as an asynchronous counter. The counter circuit 1042 performs down counting or up counting in synchronization with the clock, thereby counting the comparison period from the start of the comparison operation by the comparator to the completion of the comparison operation.

[0083] In this way, the analog signal provided for each column from each unit pixel of the pixel array unit 101 via the column signal lines is converted into an N-bit digital signal by each operation of the comparator 1041 and the up / down counter circuit 1042, and is stored in the memory device.

[0084] The horizontal scanning circuit 106 composed of a shift register or the like controls the column addressing and column scanning of the ADC in the column processing unit 104. Under the control of the horizontal scanning circuit 106, the N-bit digital signal that has undergone AD conversion at the ADC is sequentially read out to the horizontal signal line LHR, and is output to the image signal processing unit 108 via this horizontal signal line LHR as imaging data.

[0085] The image signal processing unit 108, which is a circuit for performing various types of signal processing on the imaging data, includes an image signal processing circuit (ISP) 1081, a microprocessor 1082, a memory 1083, etc.

[0086] <Circuit arrangement when the imaging element is composed of multiple layers>

[0087] Figure 2 An example of the circuit arrangement when the solid-state imaging element 22 is composed of a single substrate is illustrated. Note that for the sake of explanation, in Figure 3 and the subsequent descriptions, the description continues on the assumption that the solid-state imaging element 22 is composed of a pixel array unit 101, a column processing unit 104, a peripheral circuit 130, and a row circuit 131.

[0088] The row circuit 131 and the column processing unit 104 are arranged to select any pixel in the pixel array unit 101 through operation. The column processing unit 104 processes the data of the vertical signal lines, and the row circuit 131 controls the pixel control signal. The row circuit 131 has a structure including a vertical drive circuit 102 etc., and includes a circuit for controlling the row addressing and row scanning of the pixel array unit 101 via the row control lines. The peripheral circuit 130 has a structure including the image signal processing unit 108 etc.

[0089] Refer to Figure 3, the pixel array unit 101 is arranged at the central portion of the substrate 150, the row circuit 131 is arranged on the left side of the pixel array unit 101, the column processing unit 104 is arranged below the pixel array unit 101, and the peripheral circuit 130 is arranged on the right side of the pixel array unit 101. The length of the pixel array unit 101 in the vertical direction is set to be length V11, and the length in the horizontal direction is set to be length H12. The length of the row circuit 131 in the vertical direction is the same as the length of the pixel array unit 101 in the vertical direction, and is length V11. Note that, here, although the description continues assuming that the length of the row circuit 131 in the vertical direction is the same as the length of the pixel array unit 101 in the vertical direction, the length of the row circuit 131 can be greater than the length of the pixel array unit 101.

[0090] The length of the row circuit 131 in the horizontal direction is set to be length H11. The length of the column processing unit 104 in the horizontal direction is the same as the length of the pixel array unit 101 in the horizontal direction, and is length H12. The length of the column processing unit 104 in the vertical direction is length V12. Note that, here, although the description continues assuming that the length of the column processing unit 104 in the horizontal direction is the same as the length of the pixel array unit 101 in the horizontal direction, the length of the column processing unit 104 can be greater than the length of the pixel array unit 101.

[0091] The layout pitch of the pixels of the pixel array unit 101, the layout pitch of the column processing unit 104, and the layout pitch of the row circuit 131 are preferably the same, or the layout pitch of the column processing unit 104 and the layout pitch of the row circuit 131 are preferably greater than the layout pitch of the pixels. The reason will be described in the following description.

[0092] The peripheral circuit 130 can be arranged in the remaining portion of the substrate 150 after arranging the column processing unit 104 and the row circuit 131, and the lengths in the vertical direction and the horizontal direction are not specified in the description.

[0093] The length of the substrate 150 in the vertical direction is length V1, and is equal to or greater than the combined length of the length V11 of the row circuit 131 and the length V12 of the column processing unit 104. In a similar manner, the length of the substrate 150 in the horizontal direction is length H1, and is equal to or greater than the combined length of the length H11 of the row circuit 131 and the length H12 of the column processing unit 104.

[0094] In this way, in Figure 1In the imaging device 10 and the like shown, it is desired to implement a solid-state imaging element 22 with more pixels, higher image quality, faster speed, and smaller size. For the solid-state imaging element 22 that meets these expectations, it is considered to stack substrates to make the solid-state imaging element 22 smaller. In the structure of the stacked solid-state imaging element 22, a substrate formed with a signal processing circuit is used instead of the support substrate of the solid-state imaging element 22, and a pixel portion is stacked on this substrate. By adopting this structure, the solid-state imaging element 22 can be made smaller.

[0095] When Figure 3 the solid-state imaging element 22 shown has a stacked structure, a circuit configuration as Figure 4 shown can be achieved.

[0096] Figure 4 is a diagram illustrating an example of the circuit configuration at each substrate when the solid-state imaging element 22 is composed of two substrates to achieve a configuration in which two substrates are stacked (i.e., the stacked solid-state imaging element 22). Note that in the following description, the stacked type is a chip having a configuration in which multiple substrates are stacked.

[0097] In addition, in the following description, when the substrates are described as the first-layer substrate and the second-layer substrate, the first layer refers to the substrate arranged on the top, and the second layer refers to the substrate arranged below the first layer. Similarly, the third layer refers to the substrate arranged below the second layer.

[0098] Figure 4 The solid-state imaging element 22 is illustrated to explain the circuit arrangement when the solid-state imaging element 22 is formed as a chip in which two substrates are stacked.

[0099] The pixel array unit 101 and the row circuit 131 are arranged on the first-layer substrate 151-1. The column processing unit 104 and the peripheral circuit 130 are arranged on the second-layer substrate 151-2. Compared with Figure 3 the solid-state imaging element 22 shown, Figure 4 the solid-state imaging element 22 shown can use two layers to construct the imaging element, so that the column processing unit 104 and the peripheral circuit 130 are arranged on the second-layer substrate 151-2, thereby the substrate size can be correspondingly reduced.

[0100] Figure 4 The length in the vertical direction of the first-layer substrate 151-1 of the solid-state imaging element 22 shown is length V2. The length V2 is at least shorter than the length V1 in the vertical direction when the solid-state imaging element 22 is composed of one layer ( Figure 3 ) by at least the length V12 of the column processing unit 104 in the vertical direction.

[0101] In addition, Figure 4The length of the first layer substrate 151-1 of the solid-state imaging device 22 in the horizontal direction is length H2. Length H2 is at least shorter than the length H1 in the horizontal direction when the solid-state imaging device 22 is composed of one layer ( Figure 3 ) by the length of the peripheral circuit 130 in the horizontal direction.

[0102] In this way, by constructing the solid-state imaging device 22 as a stacked imaging device with two substrates laminated, the lengths of the substrate 151-1 (151-2) in the vertical and horizontal directions can be made smaller than those of the substrate 150 ( Figure 3 ). That is, the solid-state imaging device 22 can be made smaller.

[0103] However, the solid-state imaging device 22 can be further made smaller than the solid-state imaging device 22 in the Figure 5 shown circuit configuration by using the Figure 4 shown circuit configuration.

[0104] Although the solid-state imaging device 22 shown in Figure 5 is a chip with two substrates laminated like the solid-state imaging device 22 shown in Figure 4 , the difference between the solid-state imaging device 22 shown in Figure 5 and the solid-state imaging device 22 shown in Figure 4 is that the row circuit 131 is arranged on the second layer substrate 152-2. That is, only the pixel array unit 101 is arranged on the first layer substrate 152-1 shown in Figure 5 , and the column processing unit 104, the peripheral circuit 130, and the row circuit 131 are arranged on the second layer substrate 152-2.

[0105] By arranging only the pixel array unit 101 on the first layer substrate 152-1 in this way, the size of the substrate 152-1 can be made substantially the same as the size of the pixel array unit 101. In addition, by making the size of the laminated substrate 152-2 the same as the size of the substrate 152-1, the size of the substrate 152-2 can be made substantially the same as the size of the pixel array unit 101.

[0106] In this case, the lengths of the substrate 152-1 and the substrate 152-2 in the vertical direction can be made length V2. Although the length in the vertical direction is the same as that in the Figure 4 shown case, the length in the horizontal direction is at least shorter than the length of the row circuit 131. Therefore, the solid-state imaging device 22 can be made smaller.

[0107] In the case of Figure 5In the case of the circuit arrangement shown, since the column processing unit 104 and the row circuit 131 are arranged on the substrate 152-2, the length of the column processing unit 104 in the horizontal direction becomes the length H32. The length H32 is smaller than the length H12 of the column processing unit 104 arranged on Figure 4 the substrate 151-2 shown.

[0108] In other words, in Figure 5 the case of the circuit arrangement shown, the length H32 of the column processing unit 104 arranged on the second-layer substrate 152-2 in the horizontal direction is smaller than the length H12 of the pixel array unit 101 arranged on the first-layer substrate 152-1 in the horizontal direction.

[0109] This difference in length requires a wiring area for pitch conversion between the pixel array unit 101 and the column processing unit 104. In addition, there is a possibility that the layout efficiency of the column processing unit 104 deteriorates and the area becomes larger as the pitch becomes narrower. Therefore, it is difficult to make the column processing unit 104 smaller to reduce the size of the substrate 152-2, and if the size is made smaller, there is a possibility that the performance of the column processing unit 104 will decrease.

[0110] In addition, the ADC (not shown) included in the column processing unit 104 has many transistors, and thus it is difficult to make the ADC smaller. Therefore, in order to make the ADC smaller, there is a possible way to share one ADC among multiple pixels. However, if one ADC is shared by multiple pixels, readout control is performed to switch signals from multiple pixels.

[0111] Therefore, if one ADC has many transistors, the time difference between the pixels to be read out becomes larger, and there is a possibility that when imaging a moving object, the object is imaged as a distorted object, or it takes time to read out one image.

[0112] In this way, since there is a possibility that the image quality deteriorates or high-speed shooting cannot be performed when the column processing unit 104 is made smaller, it is not preferable to make the column processing unit 104 smaller, for example, by making the length of the column processing unit 104 smaller than the length of the pixel array unit 101 in the horizontal direction. Therefore, it is preferable to design the length of the column processing unit 104 in the horizontal direction to be equal to or greater than the length H12 of the pixel array unit 101 in the horizontal direction.

[0113] Although as Figure 4 shown, it is preferable in terms of arranging the row circuit 131 on the first substrate 151-1, this arrangement makes the size of the substrate larger than Figure 5 the size of the substrate in the circuit arrangement shown.

[0114] <First circuit arrangement of a chip having a three-layer stack structure>

[0115] Therefore, as Figure 6 shown, a three-layer structure is used. Referring to Figure 6 , only the pixel array unit 101 is arranged on the first-layer substrate 153-1. The column processing unit 104 is arranged on the second-layer substrate 153-2. The peripheral circuit 130 and the row circuit 131 are arranged on the third-layer substrate 153-3.

[0116] By adopting this structure, the size of the first-layer substrate 153-1 can be made substantially the same as the size of the pixel array unit 101. In addition, the sizes of the stacked substrates 153-2 and 153-3 become the same as the size of the substrate 153-1. In this case, each substrate 153 has a length V2 in the vertical direction and a length H3 in the horizontal direction.

[0117] Since the size of each substrate 153 can be made substantially the same as the size of the pixel array unit 101, the chip can be made smaller. Note that although for illustration purposes, the size of the substrate 153-1 is made larger than Figure 6 the pixel array unit 101 in etc., the sizes can also be made substantially the same.

[0118] Since in the Figure 6 shown chip, a configuration in which only the column processing unit 104 is arranged on the second-layer substrate 153-2 can also be used, the chip can also be designed such that the size of the column processing unit 104 is the same as the size of the pixel array unit 101. This does not cause the above problems (e.g., the problem of a wiring area required for pitch conversion), and does not reduce the layout efficiency. Therefore, a reduction in the performance of the column processing unit 104 can be prevented.

[0119] In the Figure 6 shown chip, when increasing the parallelism of the column circuit to achieve higher speed, since a configuration in which only the column processing unit 104 is arranged on the second-layer substrate 153-2 can also be used, the chip can be designed such that the size of the column processing unit 104 is the same as the size of the pixel array unit 101.

[0120] This does not cause the above problems (e.g., the problem of a wiring area required for pitch conversion), and does not reduce the layout efficiency. Therefore, a reduction in the performance of the column processing unit 104 can be prevented. In addition, this is a beneficial effect obtained by applying the present invention, and such a beneficial effect can also be obtained in the following circuit arrangements.

[0121] In the Figure 6In the chip shown, the length of the row circuit 131 in the vertical direction can be made equal to or greater than the length of the pixel array unit 101 in the vertical direction, and the length of the column processing unit 104 in the horizontal direction can be made equal to or greater than the length of the pixel array unit 101 in the horizontal direction.

[0122] According to the present invention, since the pixel array unit 101, the column processing unit 104, and the row circuit 131 can be arranged on different substrates, the sizes of the column processing unit 104 and the row circuit 131 can be made larger within the size of the substrate on which the column processing unit 104 and the row circuit 131 are arranged. These substrates have substantially the same size as the substrate on which the pixel array unit 101 is arranged as described above. Therefore, the length of a predetermined side of the column processing unit 104 and the length of a predetermined side of the row circuit 131 can be made greater than the length of a predetermined side of the pixel array unit 101.

[0123] As described above, although there is a possibility that the image quality deteriorates or high-speed shooting cannot be performed when the column processing unit 104 is made smaller, since it is not necessary to make the column processing unit 104 and the row circuit 131 smaller than the required size, the possibility of image quality deterioration or inability to perform high-speed shooting can be eliminated.

[0124] In addition, in the case of a stacked chip, a chip on which a signal processing circuit is formed is used instead of the support substrate of the pixel portion, and the pixel portion is stacked on this chip. Therefore, even in the case of a three-layer structure as shown in Figure 6 For example, compared with the one-layer structure shown in Figure 3 or the two-layer structure as shown in Figure 4 and Figure 5 the thickness of the chip does not substantially change, and thus the stacking does not increase the thickness and it is not difficult to make the chip smaller.

[0125] Therefore, although not shown, it is also possible to construct a chip using three or more layers. For example, by applying the present invention, a four-layer structure can also be adopted, and a memory can be arranged on the fourth-layer substrate.

[0126] <Second Circuit Arrangement of a Chip Having a Three-Layer Stacked Structure>

[0127] In addition, as shown in Figure 7 it is also possible to use a configuration in which the memory 170 is arranged on the third layer. Like the chip shown in Figure 6 the chip shown in Figure 7 is a chip in which three substrates are stacked, and only the pixel array unit 101 is arranged on the first-layer substrate 154-1, and the column processing unit 104 is arranged on the second-layer substrate 154-2.

[0128] Therefore, havingFigure 7 The chip of the circuit arrangement shown is also capable of providing beneficial effects identical to those provided by the chip with Figure 6 the circuit arrangement shown.

[0129] The row circuit 131 and the memory 170 are arranged on the third layer substrate 154-3 of the chip shown. In this way, the memory 170 can be arranged on the third layer. Additionally, when multiple memories 170 are required (although not shown), a configuration in which the memory 170 is provided on the fourth layer substrate can also be adopted. The peripheral circuit 130 ( Figure 7 not shown in the figure) can be arranged at the remaining part on the second layer substrate 154-2 or the third layer substrate 154-3 or the fourth layer substrate. Figure 7 The remaining part is the part on the second layer substrate and the third layer substrate that has the same size as the first layer substrate after the column processing unit 104 and the row circuit 131 are arranged and on which no circuits are arranged.

[0130] Note that the remaining part is the part on the second layer substrate and the third layer substrate that has the same size as the first layer substrate after the column processing unit 104 and the row circuit 131 are arranged and on which no circuits are arranged.

[0131] <The Third Circuit Arrangement of the Chip with a Three-Layer Stacked Structure>

[0132] The circuit arrangement shown can also be adopted to arrange the peripheral circuit 130 at the remaining part on the substrate. Figure 8 The circuit arrangements of the chip shown in each layer are substantially the same as those of the chip with Figure 8 the circuit arrangement shown. Figure 7 the circuit arrangement shown.

[0133] Figure 8 The difference between the chip shown and the chip with Figure 7 the circuit arrangement shown is that the center of the column processing unit 104 arranged on the second layer substrate 155-2 is offset relative to the center of the substrate 155-2. For example, in the chip shown above in Figure 7 the example where the center of the second layer substrate 154-2 matches the center of the column processing unit 104 is illustrated. In other words, when stacking the substrates, Figure 7 the column processing unit 104 shown is arranged at a position directly below the pixel array unit 101.

[0134] On the other hand, Figure 8 the center of the column processing unit 104 shown is offset relative to the center of the substrate 155-2. In other words, when stacking the substrates, Figure 8 the column processing unit 104 shown is arranged at a position horizontally offset relative to the pixel array unit 101. Additionally, in other words, in Figure 8In the example shown, the central axis of the column processing unit 104 in the vertical direction is arranged at a position offset with respect to the central axis of the substrate 155-2 in the vertical direction (the central axis of the pixel array unit 101 in the vertical direction).

[0135] In Figure 8 the example shown, by shifting the column processing unit 104 to the left side of the substrate 155-2, a part is left at the right side of the substrate 155-2. The peripheral circuit 130 can be arranged at this part. Moreover, in this case, since the column processing unit 104 is arranged on the substrate 155-2 such that the length H12 of the column processing unit 104 in the horizontal direction is the same as the length H12 of the pixel array unit 101 in the horizontal direction, the performance of the column processing unit 104 is not degraded.

[0136] Note that in Figure 8 the circuit arrangement shown, although an example of shifting the column processing unit 104 to the left in the horizontal direction is illustrated, the column processing unit 104 can also be shifted to the right.

[0137] <The Fourth Circuit Arrangement of a Chip with a Three-Layer Stacked Structure>

[0138] In Figures 6 to 8 the circuit arrangement of the chip shown, an example in which the column processing unit 104 is arranged on the second-layer substrate is illustrated. The substrate on which the column processing unit 104 is arranged is not limited to the second-layer substrate, and the column processing unit 104 can be arranged on the third-layer substrate. Figures 9 to 11 An example of arranging the column processing unit 104 on the third-layer substrate is illustrated.

[0139] Figure 9 is a diagram illustrating an example of the circuit arrangement of a chip with a three-layer stacked structure. In Figure 9 the first-layer substrate 156-1 of the chip shown, only the pixel array unit 101 is arranged. The peripheral circuit 130 and the row circuit 131 are arranged on the second-layer substrate 156-2. The column processing unit 104 is arranged on the third-layer substrate 156-3.

[0140] In this circuit arrangement, the Figure 6 second layer and the third layer in the circuit arrangement of the chip shown are interchanged. Even when the second layer and the third layer are interchanged in this way and the column processing unit 104 is arranged on the third-layer substrate 156-3, it is obvious that beneficial effects the same as those provided in the case of arranging the column processing unit 104 on the second-layer substrate ( Figure 6 the chip shown) can be provided, and the chip can be made smaller.

[0141] <The Fifth Circuit Arrangement of a Chip with a Three-Layer Stacked Structure>

[0142] Figure 10 illustrates a configuration in which the second and third layers in the circuit layout of a chip having a three-layer stacked structure as shown are interchanged. In Figure 7 the example of the circuit layout of a chip having a three-layer stacked structure as shown, only the pixel array unit 101 is arranged on the first-layer substrate 157-1, the row circuit 131 and the memory 170 are arranged on the second-layer substrate 157-2, and the column processing unit 104 is arranged on the third-layer substrate 157-3. Figure 10 Even when the second and third layers are interchanged in this way and the column processing unit 104 is arranged on the third-layer substrate 157-3, beneficial effects identical to those provided in the case where the column processing unit 104 is arranged on the second-layer substrate (

[0143] the chip shown) can be provided, and the chip can be made smaller. Figure 7 <Beneficial effects identical to those provided in the case where the column processing unit 104 is arranged on the second-layer substrate (the chip shown) can be provided, and the chip can be made smaller.>

[0144] <The sixth circuit layout of a chip having a three-layer stacked structure>

[0145] In the above-mentioned Figure 8 circuit layout of a chip having a three-layer stacked structure as shown, it is illustrated that the column processing unit 104 arranged on the second-layer substrate 155-2 is located at a position different from the center of the substrate 155-2. The row circuit 131 can also be offset instead of the column processing unit 104.

[0146] Although Figure 11 the circuit layout of a chip having a three-layer stacked structure as shown is the same as Figure 10 the circuit layout of a chip having a three-layer stacked structure as shown, the arrangement position of the row circuit 131 on the second-layer substrate 158-2 is different. The center of the row circuit 131 arranged on the second-layer substrate 158-2 is located at a position offset relative to the center of the substrate 158-2.

[0147] Figure 11 The center of the row circuit 131 shown is offset in the upward direction relative to the center of the substrate 158-2. At the position of the length V11 indicated on the left side of the substrate 158-2 in Figure 11 is not the position after the row circuit 131 is offset, but the position in the case where the row circuit 131 is located at the position as shown in Figure 10 shown.

[0148] When laminating substrates, Figure 11 the row circuit 131 shown is arranged at a position offset in the vertical direction relative to the pixel array unit 101. In other words, in Figure 11In the example shown, the central axis of the row circuit 131 in the horizontal direction is arranged at a position offset with respect to the central axis of the substrate 158-2 in the horizontal direction (the central axis of the pixel array unit 101 in the horizontal direction).

[0149] In Figure 11 the example shown, by shifting the row circuit 131 to the upper side of the substrate 158-2 and leaving a part at the lower side of the substrate 158-2, the peripheral circuit 130 can be arranged at this part. Moreover, in this case, since the row circuit 131 is arranged on the substrate 158-2 such that the length V11 of the row circuit 131 in the vertical direction is the same as the length V11 of the pixel array unit 101 in the vertical direction, the performance of the row circuit 131 is not degraded.

[0150] Note that in Figure 11 the circuit arrangement shown, although an example in which the row circuit 131 is shifted upward in the vertical direction is illustrated, the row circuit 131 can also be shifted downward.

[0151] In addition, as Figure 8 shown, the column processing unit 104 can also be arranged such that the center of the column processing unit 104 is offset with respect to the center of the substrate, and as Figure 11 shown, the row circuit 131 can also be arranged such that the center of the row circuit 131 is offset with respect to the center of the substrate.

[0152] In addition, in Figure 8 and Figure 11 the example shown, although an example in which the position of the column processing unit 104 or the row circuit 131 arranged on the second-layer substrate is offset with respect to the substrate is illustrated, a configuration in which the position of the column processing unit 104 or the row circuit 131 arranged on the third-layer substrate is offset with respect to the substrate can also be used.

[0153] <The Seventh Circuit Arrangement of a Chip with a Three-Layer Stacked Structure>

[0154] Although an example in which the chip is composed of one column processing unit 104 is illustrated in Figures 6 to 11 , the column processing unit 104 can be divided into multiple parts and arranged on the substrate. In Figure 12 the circuit arrangement of the chip with a three-layer stacked structure shown, the pixel array unit 101 is arranged on the first-layer substrate 159-1, and the row circuit 131 and the memory 170 are arranged on the second-layer substrate 159-2.

[0155] On the third-layer substrate 159-3, the column processing unit 104 is divided, and the column processing unit 104-1 and the column processing unit 104-2 are arranged. In addition, the peripheral circuit 130 is arranged on the third-layer substrate between the column processing unit 104-1 and the column processing unit 104-2.

[0156] In this way, the column processing unit 104 can also be divided and the divided column processing unit 104 can be arranged on the substrate. In addition, Figure 12 In the illustrated example, although an example of arranging the column processing unit 104-1 and the column processing unit 104-2 on the third-layer substrate 159-3 is described, a configuration of arranging the column processing unit 104-1 and the column processing unit 104-2 on the second-layer substrate 159-2 can also be used.

[0157] In this way, by arranging the pixel array unit 101 on the first-layer substrate and arranging the column processing unit 104 and the row circuit 131 on respective substrates having the same size as the first-layer substrate and being different lower layers of the first layer, the chip can be made smaller without degrading the performance of each of the column processing unit 104 and the row circuit 131.

[0158] In addition, according to the present invention, by arranging the pixel array unit 101 on the first-layer substrate, the following beneficial effects can be provided. For example, as referred to Figure 4 When the pixel array unit 101 and the row circuit 131 are arranged on the first-layer substrate 151-1, the chip size does not become the minimum value. In addition, P-channel transistors for forming the row circuit 131 are also required.

[0159] However, for example, as Figure 6 shown, by arranging only the pixel array unit 101 on the first-layer substrate 153-1, the chip size can be minimized as described above. In addition, a process using only N-channel transistors (high breakdown voltage transistors) can be implemented, and the process cost associated with the formation of the first-layer substrate can be reduced.

[0160] <Signal Flow and Circuit Arrangement>

[0161] Next, the flow of control signals and the flow of data signals in a chip having a three-layer stacked structure will be described. Figure 13 is Figure 2 a simplified diagram of the configuration of the solid-state imaging device 22 shown for explaining the flow of control signals and data signals. In Figure 13 , the arrow with a thin line represents a control signal, and the arrow with a thick line represents a data signal. Note that in Figures 14 to 16 , the control signal and the data signal are represented in a similar manner.

[0162] The control signal from the input I / F 109 is supplied to the timing control circuit 107. The clock signal or control signal etc. generated at the timing control circuit 107 and serving as the operation reference for each unit is supplied to the vertical decoder 103, the analog circuit 200, the column processing unit 104, and the image signal processing unit 108.

[0163] The analog circuit 200 including the vertical drive circuit 102 or the reference signal supply unit 105 etc. Figure 2 ) processes analog signals. Note that the comparator 1041 Figure 2 ) in the column processing unit 104 is a circuit that processes analog signals, and in the example to be referred to later Figure 15 , an example in which the column processing unit 104 is divided into an analog circuit and a digital circuit and the analog circuit and the digital circuit are arranged on different substrates will be described.

[0164] When necessary, the control signal from the analog circuit 200 is supplied to the vertical decoder 103. Additionally, when necessary, the control signal from the analog circuit 200 is also supplied to the column processing unit 104. The control signal from the vertical decoder 103 is supplied to the pixel array unit 101.

[0165] The data signal read out from the pixels constituting the pixel array unit 101 is supplied to the image signal processing unit 108 via the column processing unit 104, and after being subjected to predetermined processing on this data signal, it is supplied to the output I / F 109.

[0166] When the chip having such a flow of control signal and data signal is configured as the chip having a three - layer stacked structure referred to Figures 6 to 12 in the description, the circuits arranged on the respective substrates of the first layer, the second layer, and the third layer will be described with reference to Figures 14 to 16 .

[0167] Reference Figures 6 to 12 The chip having a three - layer stacked structure described in the description has the following embodiment, in which mainly, the pixel array unit 101 is arranged on the first - layer substrate, and the column processing unit 104 and the row circuit 131 are arranged on different substrates among the stacked substrates.

[0168] Reference Figures 14 to 16 The chip having a three - layer stacked structure described in the description has the following embodiment, in which, according to the type of the signal to be processed, specifically, according to whether the circuit is a circuit for processing analog signals or a circuit for processing digital signals, the circuits are arranged on different substrates among the stacked substrates.

[0169] In Figure 14In the circuit arrangement of the chip shown, the pixel array unit 101 is arranged on the first-layer substrate 210-1. Additionally, the vertical decoder 103, the column processing unit 104, and the analog circuit 200 are arranged on the second-layer substrate 210-2. Additionally, the input I / F 109, the timing control circuit 107, the image signal processing unit 108, and the output I / F 109 are arranged on the third-layer substrate 210-3.

[0170] The vertical decoder 103, the column processing unit 104, and the analog circuit 200 arranged on the second-layer substrate 210-2 are analog circuits mainly processing analog signals. The input I / F 109, the timing control circuit 107, the image signal processing unit 108, and the output I / F 109 arranged on the third-layer substrate 210-3 are digital circuits mainly processing digital signals.

[0171] The circuits processing analog signals can also be arranged on the second-layer substrate and the circuits processing digital signals can be arranged on the third-layer substrate in this way.

[0172] Additionally, as Figure 15 shown, since there are analog circuits and digital circuits mixed in the column processing unit 104, the analog unit and the digital unit of the column processing unit 104 can be arranged in different substrates.

[0173] In Figure 15 the example shown, the analog unit of the column processing unit 104 is arranged on the second-layer substrate 211-2, and the digital unit of the column processing unit 104 is arranged on the third-layer substrate 211-3. The analog unit of the column processing unit 104 is, for example, Figure 2 the comparator 1041 shown, and the digital unit of the column processing unit 104 is the counter circuit 1042.

[0174] Moreover, in Figure 15 the example shown, only the pixel array unit 101 is arranged on the first-layer substrate 211-1. The vertical decoder 103, the analog circuit 200, and the column processing unit 104-1 as an analog unit are arranged on the second-layer substrate 211-2. The input I / F 109, the timing control circuit 107, the image signal processing unit 108, the output I / F 109, and the column processing unit 104-2 as a digital unit are arranged on the third-layer substrate 211-3.

[0175] The column processing unit 104 can also be divided into an analog unit and a digital unit, with the analog system circuit arranged on the second-layer substrate and the digital system circuit arranged on the third-layer substrate.

[0176] Additionally, as Figure 16As shown, the column processing unit 104 can also be arranged on the second-layer substrate 212-2 and other circuits can be arranged on the third-layer substrate 212-3. Moreover, in this case, only the pixel array unit 101 is arranged on the first-layer substrate 212-1.

[0177] The analog circuit 200 and the column processing unit 104 are arranged on the second-layer substrate 211-2, and the vertical decoder 103, the input I / F 109, the timing control circuit 107, the image signal processing unit 108, the output I / F 109, and the column processing unit 104-2 are arranged on the third-layer substrate 212-3.

[0178] In this way, the analog system circuit can be mainly arranged on the second-layer substrate and the digital system circuit can be arranged on the third-layer substrate.

[0179] Note that here, although an example of arranging the analog system circuit on the second-layer substrate and the digital system circuit on the third-layer substrate has been described, a configuration in which the digital system circuit is arranged on the second-layer substrate and the analog system circuit is arranged on the third-layer substrate can also be used.

[0180] By using a stacked structure in which the analog system circuit and the digital system circuit are arranged on different substrates, the chip of the solid-state imaging device 22 can be made smaller, and the following beneficial effects can be expected.

[0181] First, the pixel array unit 101 can be composed of high breakdown voltage transistors (HVTr.), the analog system circuit can be composed of high breakdown voltage transistors (HVTr.), and the digital system circuit can be composed of low breakdown voltage transistors (LVTr.).

[0182] That is, as described above, in the case of a chip having a three-layer stacked structure, the first layer, the second layer, and the third layer can be constructed with only high breakdown voltage transistors or low breakdown voltage transistors.

[0183] Although fine transistors provide a smaller effect in the analog system circuit, the benefits of high speed and low power consumption can be obtained by using fine transistors in the digital system circuit. However, since fine transistors are expensive, the cost can be reduced by arranging the analog system circuit and the digital system circuit on different substrates. In addition, by arranging the analog unit and the digital unit on different substrates, noise from the substrate can be suppressed.

[0184] In addition, there is a possibility that the performance of the analog circuit changes. Therefore, it is difficult to make the transistors smaller or reduce the voltage. Compared with the analog circuit, it is relatively easy to make the digital circuit smaller and reduce the voltage of the digital circuit.

[0185] Accordingly, the digital circuit can be made smaller, reducing the area on the substrate for the digital circuit and arranging the peripheral circuit 130 in the remaining portion of the substrate.

[0186] When arranging a plurality of small digital circuits and analog circuits close to each other, it becomes difficult to optimize the power supply voltage and breakdown voltage resistance of the transistors. However, according to the present invention, since the digital circuit and the analog circuit are arranged on different substrates, it is possible to eliminate the situation where the small digital circuit and the analog circuit are mixed in a close proximity manner.

[0187] Therefore, the chip can also be made smaller by eliminating the analog and digital boundary regions, and the chip can be made smaller by eliminating losses such as the disordered connection to different power supplies.

[0188] <Application Example>

[0189] An application example of the focus detection device including the above-described phase difference detection pixels will be described below. The solid-state imaging device 22 in the above-described embodiment can be applied to electronic devices in various fields, and here, in addition to Figure 1 the illustrated imaging device (camera), an endoscope camera and a vision chip (artificial retina) will also be described as an example.

[0190] Figure 17 FIG. is a functional block diagram illustrating the overall configuration of an endoscope camera (capsule endoscope camera 400A) according to the present application example. The capsule endoscope camera 400A includes an optical system 410, a shutter device 420, a solid-state imaging device 22, a drive circuit 440, a signal processing circuit 430, a data transmission unit 450, a drive battery 460, and an attitude (direction, angle) detection gyro circuit 470.

[0191] The optical system 410 includes one or more imaging lenses that form image light (incident light) from the subject on the imaging surface of the solid-state imaging device 22. The shutter device 420 controls the light irradiation period (exposure period) and the light shielding period for the solid-state imaging device 22. The drive circuit 440 performs the opening and closing drive of the shutter device 420 and drives the exposure operation and the signal readout operation at the solid-state imaging device 22.

[0192] The signal processing circuit 430 performs predetermined signal processing (for example, various types of correction processing such as demosaic processing and white balance adjustment processing) on the output signal from the solid-state imaging device 22.

[0193] Preferably, the optical system 410 can capture images in multiple directions (e.g., all directions) in a four-dimensional space and is composed of one or more lenses. However, in this example, the data transmission unit 450 wirelessly communicates the video signal D1 that has been signal-processed at the signal processing circuit 430 and the attitude detection signal D2 output from the gyroscope circuit 470 to an external device.

[0194] Note that the endoscope camera using the imaging element according to the above-described embodiment is not limited to the capsule-type endoscope camera as described above, and may be, for example, an insertable endoscope camera (insertable endoscope camera 400B) as Figure 18 shown.

[0195] As part of the configuration of the above-described capsule endoscope camera 400A, the insertable endoscope camera 400B includes an optical system 410, a shutter device 420, a solid-state imaging element 22, a drive circuit 440, a signal processing circuit 430, and a data transmission unit 450. However, the insertable endoscope camera 400B further includes an arm 480a that can be stored inside the device and a drive unit 480 for driving the arm 480a. Such an insertable endoscope camera 400B is connected to a cable 490 having wiring 490A and wiring 490B, where the wiring 490A is for transmitting an arm control signal CTL to the drive unit 480, and the wiring 490B is for transmitting a video signal Dout based on the captured image.

[0196] Figure 19 is a functional block diagram showing the overall configuration of a vision chip (vision chip 500) according to another application example. The vision chip 500 is an artificial retina and is used by being embedded in a part of the wall (retina E2 having an optic nerve) behind the eyeball E1 of the eye. The vision chip 500 is embedded in a part of, for example, one of the ganglion cells C1, horizontal cells C2, and photoreceptor cells C3 at the retina E2, and includes a solid-state imaging element 22, a signal processing circuit 510, and a stimulation electrode unit 520.

[0197] By this method, an electrical signal based on the incident light incident on the eye is acquired at the solid-state imaging element 22, and the electrical signal is processed at the signal processing circuit 510, thereby providing a predetermined control signal to the stimulation electrode unit 520. The stimulation electrode unit 520 has a function of providing a stimulation (electrical signal) consistent with the input control signal to the optic nerve.

[0198] The present invention can be applied to such a device.

[0199] Note that the effects described in this specification are merely examples and are not restrictive; other effects may also be exhibited.

[0200] In addition, embodiments of the present invention are not limited to the above embodiments, and various changes can be made within the scope of the present invention.

[0201] In addition, the present invention can also be configured as follows.

[0202] (1) An imaging element, comprising:

[0203] A pixel array unit in which pixels including photoelectric conversion elements are arranged two-dimensionally;

[0204] A row circuit for controlling row scanning of the pixel array unit; and

[0205] A column processing unit for converting an analog signal read out from the pixel array unit into a digital signal,

[0206] wherein the pixel array unit is arranged on a first-layer substrate, and

[0207] the row circuit and the column processing unit are respectively arranged on different substrates, and the different substrates are lower layers of the first-layer substrate and are laminated to the first-layer substrate.

[0208] (2) The imaging element according to (1),

[0209] wherein a length of the row circuit in a vertical direction is equal to or greater than a length of the pixel array unit in the vertical direction.

[0210] (3) The imaging element according to (1) or (2),

[0211] wherein a length of the column processing unit in a horizontal direction is equal to or greater than a length of the pixel array unit in the horizontal direction.

[0212] (4) The imaging element according to any one of (1) to (3),

[0213] wherein when the first substrate on which the pixel array unit is arranged and the second substrate on which the row circuit is arranged are laminated, the row circuit is arranged on the second substrate in such a manner that a central axis of the pixel array unit in a horizontal direction is offset in position from a central axis of the row circuit in the horizontal direction.

[0214] (5) The imaging element according to any one of (1) to (4),

[0215] Among them, when the first substrate on which the pixel array unit is arranged and the second substrate on which the column processing unit is arranged are stacked, the column processing unit is arranged on the second substrate in such a manner that the central axis of the pixel array unit in the vertical direction is offset in position from the central axis of the column processing unit in the vertical direction.

[0216] (6) The imaging element according to any one of (1) to (5),

[0217] wherein the memory is arranged on the same substrate as the row circuit or the column processing unit.

[0218] (7) An electronic device, comprising:

[0219] An imaging element, comprising:

[0220] A pixel array unit in which pixels including photoelectric conversion elements are arranged two-dimensionally;

[0221] A row circuit for controlling the row scanning of the pixel array unit; and

[0222] A column processing unit for converting an analog signal read out from the pixel array unit into a digital signal,

[0223] wherein the pixel array unit is arranged on a first layer substrate, and

[0224] the row circuit and the column processing unit are respectively arranged on different substrates, and the different substrates are the lower layers of the first layer substrate and are stacked to the first layer substrate; and

[0225] A signal processing unit for performing signal processing on the signal output from the imaging element.

[0226] (8) An imaging element, comprising:

[0227] A pixel array unit in which pixels including photoelectric conversion elements are arranged two-dimensionally in the pixel array unit,

[0228] wherein the pixel array unit is arranged on a first layer substrate, and

[0229] Among the circuits for controlling the pixel array unit and the circuits for processing signals from the pixel array unit, the circuits for processing analog signals and the circuits for processing digital signals are arranged on different substrates, and the different substrates are the lower layers of the first layer substrate and are stacked to the first layer substrate.

[0230] (9) The imaging element according to (8),

[0231] Among column processing units that convert an analog signal read out from the pixel array unit into a digital signal, a circuit for processing the analog signal and a circuit for processing the digital signal are arranged on different substrates.

[0232] (10) The imaging element according to (8) or (9),

[0233] wherein, on each of the first-layer substrate and a plurality of substrates underlying the first-layer substrate, a circuit composed of only low breakdown voltage transistors or high breakdown voltage transistors is arranged.

[0234] (11) An electronic device, comprising:

[0235] an imaging element, comprising:

[0236] a pixel array unit in which pixels including photoelectric conversion elements are arranged two-dimensionally,

[0237] wherein the pixel array unit is arranged on a first-layer substrate, and

[0238] among a circuit for controlling the pixel array unit and a circuit for processing signals from the pixel array unit, a circuit for processing an analog signal and a circuit for processing a digital signal are arranged on different substrates, the different substrates being underlying the first-layer substrate and laminated to the first-layer substrate; and

[0239] a signal processing unit for performing signal processing on a signal output from the imaging element.

[0240] List of reference numerals

[0241] 101 Pixel array unit 103 Vertical decoder 104 Column processing unit

[0242] 130 Peripheral circuit 131 Row circuit 153 Substrate

Claims

1. An imaging element, which comprises: a first substrate including a pixel array unit having a plurality of photoelectric conversion regions; a second substrate including a column processing unit; and a third substrate including a memory and a row circuit, wherein the first substrate, the second substrate, and the third substrate are stacked, wherein the length of the column processing unit in the horizontal direction is greater than the length of the memory in the horizontal direction, and the length of the column processing unit in the horizontal direction is equal to or greater than the length of the pixel array unit in the horizontal direction, the length of the row circuit in the vertical direction is equal to or greater than the length of the pixel array unit in the vertical direction.

2. The imaging element according to claim 1, wherein, the second substrate includes a peripheral circuit, and the length of the column processing unit in the horizontal direction is greater than the length of the peripheral circuit in the horizontal direction.

3. The imaging element according to claim 2, wherein, the peripheral circuit includes an image signal processing unit.

4. The imaging element according to claim 2, wherein, the column processing unit includes a comparator.

5. The imaging element according to claim 4, wherein, the column processing unit includes a counter circuit.

6. The imaging element according to claim 5, wherein, the comparator includes a first part and a second part, wherein the counter circuit includes a first part and a second part, wherein the first part of the comparator and the first part of the counter circuit are arranged adjacent to each other on a first region of the second substrate, wherein the second part of the comparator and the second part of the counter circuit are arranged adjacent to each other on a second region of the second substrate.

7. The imaging element according to claim 6, wherein, in a plan view, each of the first parts and each of the second parts are separated from each other in the vertical direction.

8. The imaging element according to claim 7, wherein, each of the first parts and each of the second parts have the same length in the horizontal direction and are aligned with each other in the vertical direction.

9. The imaging element according to any one of claims 1 to 8, wherein, the length of the memory in the horizontal direction is greater than the length of the row circuit in the horizontal direction.

10. The imaging element according to any one of claims 1 to 8, wherein, the column processing unit is configured to convert an analog signal read out from the pixel array unit into a digital signal.

11. The imaging element according to claim 6, wherein, in a plan view, the peripheral circuit is arranged between the first part of the column processing unit and the second part of the column processing unit, the first part of the column processing unit includes the first part of the comparator and the first part of the counter circuit, and the second part of the column processing unit includes the second part of the comparator and the second part of the counter circuit.

12. The imaging element according to any one of claims 1 to 8, wherein, The row circuit is used to control the row scanning of the pixel array unit.

13. An electronic device, comprising: an imaging element as described in any one of claims 1-12; and a signal processing unit for performing signal processing on a signal output from the imaging element.

Images