Semiconductor device and method for controlling signal amplitude in a semiconductor device

Abstract

A semiconductor device and a method for controlling a signal amplitude in a semiconductor device are provided. The semiconductor device includes a signal generator configured to output a sine wave, a comparator configured to compare an amplitude of the sine wave with an amplitude of a reference signal at a first timing corresponding to a timing control signal and output a comparison result, and a control signal adjuster configured to adjust one of a current control signal and the timing control signal depending on the comparison result of the comparator.

Description

Technical Field

[0001] The present invention relates to semiconductor devices and methods for controlling signal amplitude in semiconductor devices. Background Technology

[0002] Because temperature-compensated crystal oscillators (TCXOs) are expensive external components, many alternative oscillators using inexpensive external crystal components have been investigated.

[0003] The output frequency of an oscillator can be implemented, for example, by adjusting a capacitor, and can be classified as a digitally controlled crystal oscillator (DCXO), a voltage-controlled crystal oscillator (VCXO), etc., depending on the method of capacitor adjustment.

[0004] Oscillators using external crystals need to be tuned to optimized amplitude values ​​that minimize phase noise, and research on this is ongoing. Summary of the Invention

[0005] Various aspects of the present invention provide a semiconductor device capable of adjusting the optimal amplitude of a crystal oscillator at low cost.

[0006] The present invention also provides a method for adjusting the signal amplitude in a semiconductor device that can adjust the optimal amplitude of a crystal oscillator at low cost.

[0007] However, the aspects of the inventive concept are not limited to those set forth herein. These and other aspects of the inventive concept will become more apparent to those skilled in the art upon reference to the detailed description of the inventive concept given below.

[0008] According to one aspect of the present invention, a semiconductor device is provided, comprising: a signal generator configured to output a sine wave, the amplitude of which is adjusted depending on a current control signal supplied to the signal generator; a comparator configured to compare the amplitude of the sine wave supplied from the signal generator with the amplitude of a reference signal, and to output a comparison result at a first timing corresponding to a timing control signal; and a control signal conditioner configured to adjust one of the current control signal and the timing control signal depending on the comparison result of the comparator.

[0009] According to another aspect of the present invention, a semiconductor device is provided, comprising: a signal generator configured to output a sine wave; and an amplitude adjustment device configured to compare the amplitude of the sine wave with the amplitude of a reference signal at a first timing prior to the sine wave reaching a π / 2 phase, and to perform one of a first operation or a second operation based on the comparison result, the first operation comprising adjusting the amplitude of the sine wave, and the second operation comprising adjusting the timing of comparing the amplitude of the sine wave with the amplitude of the reference signal to a second timing different from the first timing, so as to compare the amplitude of the sine wave with the amplitude of the reference signal.

[0010] According to another aspect of the present invention, a semiconductor device is provided, comprising: a reference clock generator configured to generate a reference clock, the reference clock generator including: a signal generator configured to output a sine wave using a crystal oscillator; a frequency adjustment device configured to adjust the frequency of the sine wave depending on temperature changes; an amplitude adjustment device configured to compare the amplitude of the sine wave with the amplitude of a reference signal at a predetermined comparison timing before the phase of the sine wave reaches π / 2, to adjust the amplitude of the sine wave; a clock generator configured to convert the sine wave into a square wave to generate the reference clock; and a functional module configured to receive the reference clock from the reference clock generator and use the reference clock to perform a predetermined operation.

[0011] According to another aspect of the present invention, a method for adjusting the amplitude of a signal in a semiconductor device is provided, the method comprising: receiving a sine wave, and comparing the amplitude of the sine wave with the amplitude of a reference signal at a first timing prior to the sine wave reaching a π / 2 phase; and performing one of a first operation or a second operation based on the comparison result, the first operation comprising adjusting the amplitude of the sine wave, and the second operation comprising adjusting the timing of comparing the amplitude of the sine wave with the amplitude of the reference signal to a second timing different from the first timing, so as to compare the amplitude of the sine wave with the amplitude of the reference signal. Attached Figure Description

[0012] The above and other aspects and features of the present invention will become more apparent from the detailed description of exemplary embodiments of the invention with reference to the accompanying drawings, in which:

[0013] Figure 1 This is a block diagram of a semiconductor device according to some embodiments;

[0014] Figure 2 yes Figure 1 Example block diagram of an amplitude adjustment device;

[0015] Figure 3 yes Figure 2 Example block diagram of a signal generator;

[0016] Figure 4It is used for explanation Figure 2 A diagram of the reference signal;

[0017] Figure 5 yes Figure 2 Example block diagram of an enable signal generator;

[0018] Figure 6 yes Figure 2 Example block diagram of a control signal regulator;

[0019] Figure 7 This is a flowchart for explaining a method for adjusting the signal amplitude in a semiconductor device according to some embodiments;

[0020] Figure 8 This is a block diagram of a semiconductor device according to some embodiments;

[0021] Figure 9 and Figure 10 This is a diagram used to explain a method for adjusting the signal amplitude in a semiconductor device according to some embodiments;

[0022] Figure 11 This is a block diagram of a semiconductor device according to some embodiments;

[0023] Figure 12 This is a block diagram of a semiconductor device according to some embodiments;

[0024] Figure 13 It is a block diagram of a semiconductor device according to some embodiments; and

[0025] Figure 14 This is a block diagram of a semiconductor device according to some embodiments. Detailed Implementation

[0026] Embodiments of the technical concept according to the present invention will now be described with reference to the accompanying drawings.

[0027] Figure 1 This is a block diagram of a semiconductor device according to some embodiments.

[0028] refer to Figure 1 The semiconductor device may include an amplitude modulation device 100 and a signal generator 200.

[0029] Signal generator 200 can generate signals. For example, signal generator 200 can generate a sine wave SW. The sine wave SW generated from signal generator 200 can be provided to amplitude adjustment device 100.

[0030] The amplitude adjustment device 100 can receive a sine wave SW from the signal generator 200 and can provide an amplitude adjustment signal (AAS) to the signal generator 200 to adjust the amplitude of the sine wave SW output from the signal generator 200. In some embodiments, the amplitude adjustment device 100 can adjust the amplitude of the sine wave SW output from the signal generator 200 such that the amplitude of the sine wave SW output from the signal generator 200 becomes an optimized amplitude that minimizes or prevents phase noise. For example, the amplitude adjustment device 100 can adjust the amplitude of the sine wave SW by adjusting the oscillation between similar or equivalent peaks (e.g., the maximum to maximum peak or minimum to minimum peak of the sine wave SW).

[0031] In some embodiments, the amplitude adjustment device 100 compares the amplitude of the sine wave (SW) with the amplitude of a reference signal at a first timing before the phase of the sine wave (SW) reaches π / 2, and can perform one of a first operation or a second operation based on the comparison result. For example, the amplitude adjustment device 100 can compare the amplitude of the sine wave SW (e.g., the absolute magnitude of the sine wave SW) with the amplitude of the reference signal (e.g., the absolute magnitude of the reference signal) at the first timing.

[0032] In some embodiments, the first operation may include, for example, adjusting the amplitude of the sine wave SW via an amplitude adjustment signal (AAS), while the second operation may include adjusting the timing of comparing the amplitude of the sine wave SW with the amplitude of a reference signal to a second timing different from the first timing, so as to compare the amplitude of the sine wave with the amplitude of the reference signal. More specific details of this operation will be described later.

[0033] In some embodiments, although the semiconductor device may be, for example, an automatic amplitude calibration (AAC) that adjusts the amplitude of the signal output from the signal generator 200 by adjusting the sampling timing, the embodiments are not limited thereto.

[0034] The amplitude adjustment device 100 and the signal generator 200 can be implemented in various forms. For example, according to one or more example embodiments, the amplitude adjustment device 100 and the signal generator 200 can be implemented using hardware and / or a combination of hardware and software. For example, the hardware device can be implemented using processing circuitry, such as, but not limited to, a processor, central processing unit (CPU), controller, arithmetic logic unit (ALU), digital signal processor, microcomputer, field-programmable gate array (FPGA), system-on-a-chip (SoC), programmable logic unit, microprocessor, or any other device capable of responding to and executing instructions in a defined manner. The software can include computer programs, program code, instructions, or some combination thereof for independently or jointly instructing or configuring the hardware device to operate as desired. The computer program and / or program code can include programs or computer-readable instructions, software components, software modules, data files, data structures, etc., that can be implemented by one or more hardware devices (such as one or more of the hardware devices described above). In the following, although references will be made to... Figures 2 to 6 The configuration of a semiconductor device according to some embodiments will be described in more detail, but the embodiments of the inventive concept are not limited to the configurations described below.

[0035] Figure 2 yes Figure 1 Example block diagram of an amplitude adjustment device. Figure 3 yes Figure 2 Example block diagram of a signal generator. Figure 4 It is used for explanation Figure 2 A diagram of the reference signal. Figure 5 yes Figure 2 Example block diagram of the enable signal generator. Figure 6 yes Figure 2 Example block diagram of a control signal regulator.

[0036] refer to Figure 2 The amplitude adjustment device 100 may include an enable signal generator 110, a comparator 120, and a control signal conditioner 130.

[0037] refer to Figure 3 The signal generator 200 may include a current source ISRC. The current source ISRC can output a predetermined current I.

[0038] In some embodiments, the current source ISRC can receive a current control signal ICS and output a predetermined current I under the control of the current control signal ICS. For example, when the current control signal ICS is a first signal, the current source ISRC can output a current I with a first amplitude, while when the current control signal ICS is a second signal, the current source ISRC can output a current I with a second amplitude different from the first amplitude.

[0039] In some embodiments, the current control signal ICS can be a digital signal. Specifically, the current control signal ICS can include an m-bit digital signal, where m represents a natural number. When the current control signal ICS is a digital signal, the current source ISRC can include a digitally controlled current source (DCCS), in which the amount of current I to be output is adjusted according to the digital control signal. However, the embodiments are not limited to this.

[0040] The current I output from the current source ISRC can be supplied to transistor N1. Transistor N1 can be selected to the signal level of the output node VO.

[0041] In some embodiments, the current I output from the current source ISRC is provided to a crystal oscillator OX outside the semiconductor chip, and the crystal oscillator OX can accordingly generate a sine wave SW. The generated sine wave SW can be provided to the output node VO of the signal generator 200 through pads P1 and P2.

[0042] A variable resistor VR1 can be placed between pads P1 and P2. Pad P1 can be connected to a variable capacitor VC2, and pad P2 can be connected to a variable capacitor VC1. The signal generator 200 can output a sine wave SW to the outside through output node VO.

[0043] Refer again Figure 2 Comparator 120 can compare the amplitude of the sine wave SW output from signal generator 200 with the amplitude of a reference signal (VR, e.g., reference voltage) and output the comparison result (CS).

[0044] Here, the amplitude VR of the reference signal can be an optimized amplitude value at which the phase noise of the sine wave SW output from the signal generator 200 is reduced or minimized.

[0045] Specifically, refer to Figure 4 As shown by curve A, from the current source ( Figure 3 The current output by the ISRC (In-Speed ​​Rectifier) Figure 3 As the amplitude of current I increases, the amplitude of the sine wave can also increase. That is, as shown in curve A, as the amplitude of current I increases, the amplitude of the wave also increases.

[0046] On the other hand, as shown in graph B, the phase noise has a minimum value in a certain segment and an increasing value in other segments. Therefore, to optimize the signal, a sine wave with an optimized amplitude value should be generated for the current IA with minimum phase noise. In this embodiment, the amplitude VR of the reference signal can be set to an amplitude value with phase noise minimized in this way.

[0047] Refer again Figure 2 Comparator 120 compares the amplitude of the sine wave SW output from signal generator 200 with the amplitude VR of the reference signal and outputs the comparison result (CS). The comparison timing can be determined based on the enable signal (ES) output from enable signal generator 110.

[0048] In some embodiments, the enable signal generator 110 receives a sine wave SW from the signal generator 200, delays the sine wave SW according to a timing control signal TCS from the control signal conditioner 130, and then the enable signal generator 110 can provide the sine wave as an enable signal (ES) to the comparator, which can determine the comparison timing of the comparator 120.

[0049] In the following text, reference will be made to Figure 5 Describe an example configuration of enable signal generator 110.

[0050] refer to Figure 5 The enable signal generator 110 may include a square wave generator 112 and a digitally controlled delay line (DCDL) 114.

[0051] The square wave generator 112 can convert the provided sine wave SW into a square wave QW. For example, the square wave generator 112 can be an analog-to-digital converter (ADC).

[0052] DCDL 114 can delay the input square wave QW by a predetermined time according to the timing control signal TCS, and then output the delayed square wave DQW. In some embodiments, the timing control signal TCS may include an n-bit digital signal, where n represents a natural number.

[0053] In some embodiments, for example, if the timing control signal TCS is a first signal, then DCDL 114 can delay the input square wave QW by a first timing. If the timing control signal TCS is a second signal, then DCDL 114 can delay the square wave QW by a second timing different from the first timing.

[0054] In this way, the delayed square wave DQW can be used as an enable signal. Figure 2 The ES) is output from DCDL 114 to the comparator ( Figure 2 (of 120).

[0055] Refer again Figure 2 Depending on the comparison result of comparator 120, control signal regulator 130 can adjust current control signal ICS and / or timing control signal TCS.

[0056] When both the current control signal ICS and the timing control signal TCS include digital signals as described above, the control signal conditioner 130 may include, for example, the digital signals described above. Figure 6 The increment counter 132 and decrement counter 134 are shown.

[0057] When it is necessary to increase the bit values ​​of the current control signal ICS and the timing control signal TCS, the control signal conditioner 130 can use the increment counter 132 to increase the bit values ​​of the current control signal ICS and the timing control signal TCS. When it is necessary to decrease the bit values ​​of the current control signal ICS and the timing control signal TCS, the control signal conditioner 130 can use the decrement counter 134 to decrease the bit values ​​of the current control signal ICS and the timing control signal TCS. Although not shown, the control signal conditioner may include a bidirectional counter, and the bit values ​​of the current control signal ICS and the timing control signal TCS can be adjusted thereby.

[0058] In some embodiments, when the amplitude of the sine wave SW is greater than the amplitude VR of the reference signal, the control signal conditioner 130 can adjust the current control signal ICS. When the amplitude of the sine wave SW is less than the amplitude VR of the reference signal, the control signal conditioner 130 can adjust the timing control signal TCS.

[0059] More specifically, when the amplitude of the sine wave SW is greater than the amplitude VR of the reference signal, the control signal conditioner 130 can reduce the amplitude (e.g., bit value) of the current control signal, and when the amplitude of the sine wave SW is less than the amplitude VR of the reference signal, the control signal conditioner 130 can increase the amplitude (e.g., bit value) of the timing control signal TCS. In the following text, the reference... Figure 7 and Figure 8 A more detailed description of methods for adjusting signal amplitude in semiconductor devices.

[0060] Figure 7 This is a flowchart for explaining a method for adjusting the signal amplitude in a semiconductor device according to some embodiments. Figure 8 This is a block diagram of a semiconductor device according to some embodiments.

[0061] First, refer to Figure 7Initialize the control signal (S100).

[0062] For example, refer to Figure 8 The control signal conditioner 130 can initialize the current control signal ICS and the timing control signal TCS. In some embodiments, the control signal conditioner 130 can adjust the amplitude of the current control signal ICS to the maximum and the amplitude of the timing control signal TCS to the minimum. That is, the control signal conditioner 130 can initialize the current control signal ICS so that the current source ISRC outputs the current I with the maximum amplitude (or maximizes the amount of current I), and can initialize the timing control signal TCS so that the DCDL 114 does not delay the square wave QW.

[0063] refer to Figure 8 The remaining components, except for the crystal oscillator OX, may be located within the semiconductor chip 1000, and the crystal oscillator OX may be located outside the semiconductor chip 1000. Although the crystal oscillator OX may be connected to the semiconductor chip 1000 via pads P1 and P2, the embodiment is not limited thereto.

[0064] Next, refer to Figure 7 In response to the enable signal, the amplitude VS of the sine wave is compared with the amplitude VR of the reference signal (S200).

[0065] As a result of the comparison, when the amplitude VS of the sine wave is less than the amplitude VR of the reference signal, the timing control signal is adjusted (S300). Furthermore, it is determined whether the comparison timing corresponding to the timing control signal is before the sine wave reaches the π / 2 phase (S400). If the comparison point corresponding to the timing control signal is a timing point before the π / 2 sine wave phase, the comparison of the sine wave amplitude VS and the reference signal amplitude VR is repeated (S200). If the comparison timing corresponding to the timing control signal is a timing point after the π / 2 sine wave phase, the operation terminates.

[0066] On the other hand, if the comparison result shows that the amplitude VS of the sine wave is greater than the amplitude VR of the reference signal, the current control signal is adjusted (S500). Furthermore, the comparison between the amplitude VS of the sine wave and the amplitude VR of the reference signal is repeated (S200).

[0067] For example, refer to Figure 8 The comparator 120 compares the amplitude of the sine wave SW with the amplitude of the reference signal VR at a comparison timing corresponding to the enable signal DQW, and outputs a comparison signal CS including the comparison result. The control signal conditioner 130 can adjust one of the current control signal ICS and the timing control signal TCS according to the comparison result included in the comparison signal CS.

[0068] In some embodiments, if the amplitude of the sine wave SW is less than the amplitude VR of the reference signal at the comparison timing corresponding to the enable signal DQW, the control signal conditioner 130 adjusts the timing control signal TCS to delay the comparison timing of the comparator 120. If the amplitude of the sine wave SW is greater than the amplitude VR of the reference signal, the control signal conditioner 130 may adjust the current control signal ICS to reduce the amplitude of the sine wave SW output from the signal generator 200.

[0069] The operation of the control signal conditioner 130 continues when the comparison timing of the comparator 120 corresponding to the enable signal DQW is before the π / 2 phase of the sine wave, and the operation terminates if the comparison timing of the comparator 120 corresponding to the enable signal DQW is after the sine wave reaches the π / 2 phase.

[0070] In the following text, reference will be made to Figures 8 to 10 To describe this operation in more detail.

[0071] Figure 9 and Figure 10 This is a diagram used to explain a method for adjusting the signal amplitude in a semiconductor device according to some embodiments.

[0072] In the following description, for ease of explanation, an example will be given where both the current control signal ICS and the timing control signal TCS consist of 3-bit digital signals. However, those skilled in the art will recognize that the embodiments are not limited thereto, and, for example, can be applied to signals with more bits.

[0073] Furthermore, the following will describe examples where the amplitude of the sine wave is maximum when the current control signal ICS is 111 and minimum when the current control signal ICS is 000, as well as examples where the delay increases with the number of bits in the timing control signal TCS. However, such examples are for ease of explanation, and the embodiments are not limited thereto.

[0074] First, refer to Figure 9 During the initialization phase (Init), the current control signal ICS is initialized to 111, and the timing control signal TCS is initialized to 000.

[0075] refer to Figure 8 and Figure 10Because the current control signal ICS is initialized to 111, the amplitude of the current I output from the current source ISRC is maximized, and the signal generator 200 outputs a sine wave SW1 with maximum amplitude. On the other hand, because the timing control signal TCS is initialized to 000, no delay occurs in DCDL 114. Therefore, the comparator 120 compares the amplitude of the sine wave SW1 with the amplitude VR of the comparison signal at the first timing T1.

[0076] When the amplitude of the sine wave SW1 is compared with the amplitude VR of the comparison signal during the first timing T1, the amplitude of the sine wave SW1 is less than the amplitude VR of the comparison signal. Therefore, the control signal conditioner 130 adjusts the timing control signal TCS to 001.

[0077] Because the timing control signal TCS is adjusted to 001, DCDL 114 provides comparator 120 with an enable signal DQW delayed by a predetermined delay (d). As a result, comparator 120 compares the amplitude of the sine wave SW1 with the amplitude VR of the comparison signal at a second timing T2 delayed by the predetermined delay (d) from the first timing T1.

[0078] When the amplitude of the sine wave SW1 is compared with the amplitude VR of the comparison signal at the second timing T2, the amplitude of the sine wave SW1 is still less than the amplitude VR of the comparison signal. Therefore, the control signal conditioner 130 adjusts the timing control signal TCS to 010.

[0079] Because the timing control signal TCS is adjusted to 010, DCDL 114 provides comparator 120 with an enable signal DQW that is further delayed by a predetermined delay (d). As a result, comparator 120 compares the amplitude of the sine wave SW1 with the amplitude VR of the comparison signal at a third timing T3, which is delayed by a predetermined delay (d) from the second timing T2.

[0080] When the amplitude of the sine wave SW1 is compared with the amplitude VR of the comparison signal at the third timing T3, the amplitude of the sine wave SW1 is now greater than the amplitude VR of the comparison signal. Therefore, the control signal conditioner 130 adjusts the current control signal ICS to 110.

[0081] Because the current control signal ICS is adjusted to 110, the current source ISRC reduces the amplitude of the output current I. As a result, the signal generator 200 outputs a sine wave SW2 with reduced amplitude. On the other hand, because the timing control signal TCS does not change from 010, no additional delay occurs in DCDL 114. Therefore, the comparator 120 compares the amplitude of the sine wave SW2 with the amplitude VR of the comparison signal at a fourth timing T4, which has the same timing as the third timing T3.

[0082] When the amplitude of the sine wave SW2 is compared with the amplitude VR of the comparison signal at the fourth timing T4, the amplitude of the sine wave SW2 is less than the amplitude VR of the comparison signal. Therefore, the control signal conditioner 130 adjusts the timing control signal TCS to 011.

[0083] Because the timing control signal TCS is adjusted to 011, DCDL 114 provides comparator 120 with a delay enable signal DQW that is further delayed by a predetermined delay (d). As a result, comparator 120 compares the amplitude of the sine wave SW2 with the amplitude VR of the comparison signal at a fifth timing T5, which is delayed by a predetermined delay (d) from the fourth timing T4.

[0084] When the amplitude of the sine wave SW2 is compared with the amplitude VR of the comparison signal at the fifth timing T5, the amplitude of the sine wave SW2 is now greater than the amplitude VR of the comparison signal. Therefore, the control signal conditioner 130 adjusts the current control signal ICS to 101.

[0085] Because the current control signal ICS is adjusted to 101, the current source ISRC reduces the amplitude of the output current I. As a result, the signal generator 200 outputs a sine wave SW3 with reduced amplitude. On the other hand, because the timing control signal TCS does not change from 011, no additional delay occurs in DCDL 114. Therefore, the comparator 120 compares the amplitude of the sine wave SW3 with the amplitude VR of the comparison signal at a sixth timing T6, which has the same timing as the fifth timing T5.

[0086] When the amplitude of the sine wave SW3 is compared with the amplitude VR of the comparison signal at the sixth timing point T6, the amplitude of the sine wave SW3 is less than the amplitude VR of the comparison signal. Therefore, the control signal conditioner 130 adjusts the timing control signal TCS to 100.

[0087] Because the timing control signal TCS is adjusted to 100, DCDL 114 provides comparator 120 with a delay enable signal DQW that is further delayed by a predetermined delay (d). As a result, comparator 120 compares the amplitude of the sine wave SW3 with the amplitude VR of the comparison signal at a seventh timing T7, which is delayed by a predetermined delay (d) from the sixth timing T6.

[0088] When the amplitude of the sine wave SW3 is compared with the amplitude VR of the comparison signal at the seventh timing T7, the amplitude of the sine wave SW3 is less than the amplitude VR of the comparison signal. Therefore, the control signal conditioner 130 adjusts the timing control signal TCS to 101. As a result, the comparison timing of the comparator 120 now becomes the eighth timing T8.

[0089] However, the eighth timing T8 is located at the phase following π / 2 of the sine wave. In other words, because the amplitude of the sine wave SW3 decreases after this timing, further amplitude adjustment via comparison is unnecessary. Therefore, after the eighth timing T8, amplitude adjustment and comparison timing adjustment operations are no longer performed. However, through the above operations, the signal generator 200 can output an amplitude with minimal phase noise (e.g., compared to...). Figure 4 The sine wave with the amplitude of the adjacent VR.

[0090] Although the magnitude of the predetermined delay (d) has been exaggerated for ease of understanding, the actual predetermined delay (d) can have a very small value. As a result, many comparison operations may actually be performed before the sine wave phase becomes π / 2.

[0091] The semiconductor device according to this embodiment enables the signal generator 200 to output a sine wave with minimal phase noise through this relatively simple configuration and operation. In other words, optimal amplitude adjustment of the crystal oscillator can be performed at low cost.

[0092] Figure 11 This is a block diagram of a semiconductor device according to some embodiments.

[0093] In the following text, we will not provide a repeated explanation of the above embodiments, but will mainly explain the differences.

[0094] refer to Figure 11 The semiconductor chip 1000A may include a frequency divider 140. The frequency divider 140 can divide the signal DQW output from DCDL 114 and provide the divided signal as an enable signal DQWD to comparator 120. As a result, because a predetermined margin can be ensured for the comparison timing of the signal of comparator 120, the reliability of the comparison can be improved.

[0095] Figure 12 This is a block diagram of a semiconductor device according to some embodiments.

[0096] refer to Figure 12 The semiconductor chip 1000B may include a memory unit 150 and a digital-to-analog converter 160.

[0097] Storage unit 150 may store digital data VD corresponding to predetermined conditions. This digital data VD may be data related to the amplitude VR of a reference signal. In some embodiments, storage unit 150 may store the digital data VD related to the amplitude VR of the reference signal in the form of a table. For example, the table may store a reference output, such as temperature, with the amplitude VR of the reference signal as an input or index, but embodiments are not limited thereto. Storage unit 150 may be a tangible or non-transitory storage medium, such as random access memory (RAM), read-only memory (ROM), permanent mass storage devices (such as disk drives, solid-state (e.g., NAND flash memory) devices, etc.), and / or any other data storage mechanism capable of storing and recording data.

[0098] The digital-to-analog converter 160 can convert the digital data VD stored in the storage unit 150 into an analog signal to generate a reference signal. The generated reference signal can then be used for the comparison operation of the comparator 120.

[0099] Figure 13 This is a block diagram of a semiconductor device according to some embodiments.

[0100] refer to Figure 13 The semiconductor device may include a thermistor 300 (th), a temperature sensing unit 170 (TSU), and a calibration unit 180 (CLU).

[0101] Although the thermistor 300 is depicted as being external to the semiconductor chip 1000C, and the temperature sensing unit 170 and calibration unit 180 are depicted as being internal to the semiconductor chip 1000C, the embodiments are not limited thereto. For example, the thermistor 300 may be different types of temperature sensors, such as thermocouples, resistance temperature detectors, and / or thermometers.

[0102] The temperature sensing unit 170 can use the thermistor 300 to detect temperature changes. The calibration unit 180 can adjust the capacitance of variable capacitors VC1 and VC2 according to the detected temperature. When the capacitance of variable capacitors VC1 and VC2 is adjusted according to temperature in this way, the frequency of the sine wave SW can be adjusted according to the detected temperature.

[0103] Figure 14 This is a block diagram of a semiconductor device according to some embodiments.

[0104] refer to Figure 14 The semiconductor device may include a reference clock generator 400 and multiple functional modules 500-1 to 500-r (FM1 to FMr).

[0105] The reference clock generator 400 can generate a reference clock RCK. For example, the reference clock generator 400 may include a signal generator and amplitude adjustment device composed of any of the semiconductor devices according to some of the above embodiments, and a clock generator that converts a sine wave into a square wave to generate the reference clock RCK.

[0106] Multiple functional modules 500-1 to 500-r can receive a reference clock RCK from the reference clock generator 400 and use the reference clock RCK to perform predetermined operations. While examples of such functional modules may include phase-locked loops (PLLs), input / output (IO) circuits, etc., the embodiments are not limited thereto.

[0107] In summarizing the detailed description, those skilled in the art will understand that many variations and modifications can be made to the preferred embodiments without substantially departing from the principles of the inventive concept. Therefore, the preferred embodiments of the disclosed inventive concept are used only in a general and descriptive sense and not for limiting purposes.

Claims

1. A semiconductor device, comprising: A signal generator is configured to output a sine wave, the amplitude of which is adjusted depending on a current control signal supplied to the signal generator. A comparator is configured to compare the amplitude of the sine wave provided from the signal generator with the amplitude of a reference signal at a first timing corresponding to a timing control signal, and output the comparison result. as well as A control signal conditioner is configured to adjust one of a current control signal and a timing control signal based on the comparison result of the comparator. The first timing is before the sine wave reaches the π / 2 phase.

2. The semiconductor device according to claim 1, wherein, The control signal conditioner is configured to: If the amplitude of the sine wave is less than the amplitude of the reference signal at the first timing, then the timing control signal is adjusted. If the amplitude of the sine wave is greater than the amplitude of the reference signal at the first timing, then the current control signal is adjusted.

3. The semiconductor device according to claim 2, wherein, The comparator is configured to compare the amplitude of the sine wave with the amplitude of the reference signal at a second timing when the control signal conditioner adjusts the timing control signal. The second timing is different from the first timing.

4. The semiconductor device according to claim 3, wherein, The second timing is later than the first timing.

5. The semiconductor device according to claim 4, wherein, The second timing occurs before the sine wave reaches the π / 2 phase.

6. The semiconductor device according to claim 1, wherein, The current control signal includes an m-bit digital signal. The timing control signal includes an n-bit digital signal, and m and n each represent a natural number.

7. The semiconductor device according to claim 6, further comprising: The digital control delay line (DCDL) is configured to receive the timing control signal and, based on the timing control signal, provide an enable signal to the comparator. The comparator is configured to determine its comparison timing based on the enable signal, and The signal generator includes a digitally controlled current source (DCCS) configured to adjust the current amount depending on the current control signal.

8. The semiconductor device according to claim 7, further comprising: A square wave generator is configured to convert the sine wave output from the signal generator into a square wave and provide the square wave to the DCDL. The DCDL is configured to delay the square wave according to the timing control signal, and then provide the delayed square wave signal as the enable signal to the comparator.

9. The semiconductor device according to claim 1, further comprising: An enable signal generator is configured to receive the sine wave output from the signal generator, delay the sine wave according to the timing control signal, and then provide the delayed sine wave as an enable signal to the comparator. The comparator is configured to determine the comparison timing based on the enable signal.

10. The semiconductor device according to claim 9, wherein, The enable signal generator includes: A square wave generator is configured to convert the sine wave output from the signal generator into a square wave, and A digitally controlled delay line (DCDL) is configured to delay the square wave according to a timing control signal comprising an n-bit digital signal, where n represents a natural number.

11. The semiconductor device of claim 10, further comprising: A frequency divider is configured to divide the enable signal and provide it to the comparator.

12. The semiconductor device of claim 10, further comprising: The storage unit is configured to store digital data according to predetermined conditions; as well as A digital-to-analog converter is configured to generate the reference signal by converting the digital data into an analog signal.

13. A semiconductor device, comprising: The signal generator is configured to output a sine wave; as well as An amplitude adjustment device is configured to compare the amplitude of the sine wave with the amplitude of a reference signal at a first timing prior to the sine wave reaching the π / 2 phase, and to perform one of a first operation or a second operation based on the comparison result. The first operation includes adjusting the amplitude of the sine wave, and the second operation includes adjusting the timing of comparing the amplitude of the sine wave with the amplitude of the reference signal to a second timing different from the first timing, so as to compare the amplitude of the sine wave with the amplitude of the reference signal.

14. The semiconductor device according to claim 13, wherein, The first operation also includes reducing the amplitude of the sine wave.

15. The semiconductor device according to claim 13, wherein, The amplitude adjustment device is also configured to perform both the first operation and the second operation, and The second timing is later than the first timing.

16. The semiconductor device according to claim 15, wherein, The amplitude adjustment device is configured to not adjust the amplitude of the sine wave if the second timing occurs after the sine wave reaches the π / 2 phase.

17. A semiconductor device, comprising: A reference clock generator, configured to generate a reference clock, includes: A signal generator is configured to use a crystal oscillator to output a sine wave, the sine wave having a frequency. The frequency adjustment device is configured to adjust the frequency of the sine wave based on temperature changes. An amplitude adjustment device is configured to compare the amplitude of the sine wave with the amplitude of a reference signal at a predetermined comparison timing before the phase of the sine wave reaches π / 2, in order to adjust the amplitude of the sine wave. A clock generator is configured to convert the sine wave into a square wave to generate the reference clock; and The functional module is configured to receive the reference clock from the reference clock generator and use the reference clock to perform a predetermined operation.

18. The semiconductor device according to claim 17, wherein, The amplitude adjustment device is configured as follows: If the amplitude of the sine wave is greater than the amplitude of the reference signal, the amplitude of the sine wave is reduced; and if the amplitude of the sine wave is less than the amplitude of the reference signal, the timing for comparing the amplitude of the sine wave with the amplitude of the reference signal is adjusted.

19. The semiconductor device according to claim 17, wherein, The signal generator includes: A digitally controlled current source (DCCS) is configured to regulate the output current in response to a current control signal comprising an m-bit digital signal, where m is a natural number. A variable capacitor is configured to adjust the frequency of the sine wave. The amplitude adjustment device is configured to adjust the amplitude of the sine wave to control the current control signal, and The frequency adjustment device includes a temperature sensing unit configured to detect temperature, and a calibration unit configured to adjust the capacitance of the variable capacitor depending on the detected temperature.

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