Scan driver and display device including the same

Abstract

The present invention provides a scan driver and a display device including the scan driver. The scan driver includes: a first power line configured to supply a first voltage signal; a second power line configured to supply a second voltage signal having a voltage level lower than the first voltage signal; a pull-up transistor configured to output a corresponding clock signal among a plurality of clock signals as a scan signal in response to a logic state of a first node; a pull-down transistor configured to output a second voltage signal from the second power line as a scan signal in response to a logic state of a second node; and a first light shielding film overlapping with the pull-up transistor or the pull-down transistor and configured to receive the second voltage signal from the second power line and the first voltage signal from the first power line.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and the benefit of Korean Patent Application No. 10-2019-0104474, filed on August 26, 2019, the entire disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] Various embodiments of the present disclosure relate to a scan driver and a display device including the scan driver. Background Art

[0004] In recent years, the importance of display devices has increased with the development of multimedia, and therefore, flat panel display devices such as liquid crystal display devices, plasma display devices, organic light emitting display devices, etc. have been widely used.

[0005] The scan driving circuit of such a flat panel display device includes a shift register configured to sequentially supply scan pulses to a plurality of scan lines. The shift register includes a plurality of stages including a plurality of transistors and sequentially outputs gate pulses by being coupled in a cascade manner.

[0006] In recent years, a gate-in-panel (GIP) structure has been applied in liquid crystal display devices and / or organic light-emitting display devices, in which transistors forming a shift register of a gate driving circuit are in the form of thin film transistors and embedded in a substrate of a display panel.

[0007] Since transistors forming a shift register having a GIP structure are used to supply gate pulses to gate lines of a display panel, durability and electrical reliability to ensure a long service life are important. Other important factors include mobility, leakage current, etc., which are basic characteristics of transistors.

[0008] Here, the semiconductor layer of the transistor is formed of amorphous silicon or polycrystalline silicon. Amorphous silicon has the advantages of a simple film formation process and low manufacturing cost, but the problem is that electrical reliability cannot be ensured. In addition, the problem with polycrystalline silicon is that it is difficult to use in large-scale applications due to high processing temperature and because uniformity cannot be ensured depending on the crystallization method. In order to solve these problems, research is being conducted on using oxide semiconductors as semiconductor layers of transistors.

[0009] Meanwhile, a dual-gate transistor may be used to configure a shift register, but may cause a scan driver to erroneously operate due to sensitivity to characteristic variations. Summary of the invention

[0010] Various embodiments of the present disclosure are directed to a scan driver capable of reducing erroneous operations even when using dual-gate transistors.

[0011] Furthermore, various embodiments of the present disclosure are directed to a display device including the above-described scan driver.

[0012] Aspects of the present disclosure are not limited to the above, and other aspects that may not be described herein may be clearly understood by those skilled in the art from the following description.

[0013] An embodiment of the present disclosure provides a scan driver. The scan driver includes: a first power line configured to supply a first voltage signal; a second power line configured to supply a second voltage signal having a voltage level lower than the first voltage signal; a pull-up transistor configured to output a corresponding clock signal among a plurality of clock signals as a scan signal in response to a logic state of a first node; a pull-down transistor configured to output a second voltage signal from the second power line as a scan signal in response to a logic state of a second node; and a first light shielding film overlapping with the pull-up transistor or the pull-down transistor and configured to receive the second voltage signal from the second power line and the first voltage signal from the first power line.

[0014] The pull-up transistor may include a dual-gate transistor.

[0015] A first gate electrode of the pull-up transistor may be coupled to the first node, and a second gate electrode of the pull-up transistor may be directly or capacitively coupled to the first light shielding film.

[0016] The scan driver may further include a first coupling transistor configured to apply a first voltage signal from a first power line to the first light shielding film in response to a logic state of the first node.

[0017] The first coupling transistor may be configured to apply the first voltage signal to the first light shielding film only during a period in which the pull-up transistor outputs a corresponding clock signal as a scanning signal.

[0018] The scan driver may further include a second coupling transistor configured to apply a second voltage signal from a second power line to the first light shielding film in response to a logic state of the second node.

[0019] The scan driver may further include a second light shielding film overlapping the pull-down transistor, and the first light shielding film may overlap the pull-up transistor.

[0020] The scan driver may further include a third coupling transistor and a fourth coupling transistor, the third coupling transistor being configured to apply a second voltage signal from a second power line to the second light-shielding film in response to a logic state of the first node, and the fourth coupling transistor being configured to apply a first voltage signal from a first power line to the second light-shielding film in response to a logic state of the second node.

[0021] The scan driver may further include an inverter configured such that an input terminal of the inverter is coupled to the first node, an output terminal of the inverter is coupled to the second node, and a power terminal of the inverter is coupled to the first power line and the second power line.

[0022] The inverter may be configured to supply a logic state opposite to that of the first node to the second node in response to control of the first node.

[0023] The scan driver may further include a start transistor configured to supply an output or a start pulse of a previous stage to the first node in response to an output or a start pulse of a previous stage.

[0024] The scan driver may further include a reset transistor configured to supply a second voltage signal from a second power line to the first node in response to an output of a subsequent stage or a reset pulse.

[0025] The pull-down transistor may include a double-gate transistor, and a first gate electrode of the pull-down transistor may be coupled to the second node, and a second gate electrode of the pull-down transistor may be coupled or electrically coupled to the first light shielding film.

[0026] The pull-up transistor may include an oxide transistor.

[0027] The first light-shielding film may overlap with the oxide semiconductor layer of the pull-up transistor.

[0028] The first light shielding film may maintain a first voltage signal during the first portion, and may maintain a second voltage signal during the second portion.

[0029] The first part may include a period in which the pull-up transistor outputs a corresponding clock signal as a scan signal.

[0030] The first light-shielding film may overlap with a pull-up transistor, wherein the pull-up transistor includes: a first gate electrode located on the first light-shielding film; a source electrode and a drain electrode located on the first gate electrode; an oxide semiconductor layer located on the source electrode and the drain electrode; and a second gate electrode located on the oxide semiconductor layer, and wherein the first gate electrode is configured to receive a voltage signal from the first light-shielding film.

[0031] Other embodiments of the present disclosure provide a scan driver. The scan driver includes: a first power line configured to supply a first voltage signal; a second power line configured to supply a second voltage signal having a voltage level lower than the first voltage signal; a pull-up transistor configured to output a corresponding clock signal among a plurality of clock signals as a scan signal in response to a logic state of a first node; a pull-down transistor configured to output a second voltage signal from a second power line as a scan signal in response to a logic state of a second node; an inverter configured so that an input terminal of the inverter is coupled to the first node, an output terminal of the inverter is coupled to the second node, and a power terminal of the inverter is coupled to the first power line and the second power line; and a first light shielding film overlapping with the pull-up transistor or the pull-down transistor and configured to receive a second voltage signal and a corresponding clock signal from the second power line.

[0032] Still other embodiments of the present disclosure provide a display device. The display device includes: a timing controller configured to generate a scan drive control signal and a data drive control signal based on an externally supplied signal; a scan driver configured to output a scan signal to a scan line in response to the scan drive control signal; a data driver configured to output a data signal to a data line in response to the data drive control signal; and a display including pixels coupled to the scan line and the data line, wherein the scan driver includes: a first power line configured to supply a first voltage signal; a second power line configured to supply a second voltage signal having a voltage level lower than the first voltage signal; a pull-up transistor configured to output a corresponding clock signal among a plurality of clock signals as a scan signal in response to a logic state of a first node; and a pull-down transistor configured to output a corresponding clock signal among a plurality of clock signals as a scan signal in response to a logic state of a first node. The invention relates to a method for controlling the first light shielding film and a method for controlling the first light shielding film to output a second voltage signal from the second power line as a scanning signal according to the logic state of the second node; a first light shielding film overlapping with the pull-up transistor or the pull-down transistor; a first coupling transistor configured to apply the first voltage signal from the first power line to the first light shielding film in response to the logic state of the first node; and a second coupling transistor configured to apply the second voltage signal from the second power line to the first light shielding film in response to the logic state of the second node, wherein the first light shielding film is configured to receive the second voltage signal from the second power line and the first voltage signal from the first power line at different times, and wherein the pull-up transistor is configured to output a corresponding clock signal as a scanning signal during a time period included in a time period in which the first voltage signal is applied to the first light shielding film.

[0033] Additional details of various embodiments are included in the detailed description and accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] Figure 1 is a block diagram illustrating a display device according to an embodiment of the present disclosure.

[0035] Figure 2 It is used to illustrate Figure 1 Equivalent circuit diagram of a pixel.

[0036] Figure 3 It is a graphic Figure 1 FIG. 1 is a diagram of a scan driving circuit of a scan driver.

[0037] Figure 4 The diagram is based on Figure 3 FIG. 1 is a circuit diagram of one stage of an example scan driver.

[0038] Figure 5 is the diagram being applied to Figure 4 A timing diagram showing the waveforms of voltage signals of some nodes of a stage.

[0039] Figure 6 is a graph of drive current versus threshold voltage, which indicates the variable threshold voltage characteristics of the oxide transistor.

[0040] Figure 7 It is schematically shown including Figure 4 2 is a cross-sectional view of the structure of the pull-up transistor and the pull-up light shielding film shown in FIG.

[0041] Figure 8 It is a graphic Figure 7 sectional views of variations of the examples.

[0042] Fig. 9 is a circuit diagram illustrating one stage of a scan driver according to some embodiments.

[0043] Fig.10 is the diagram being applied to Fig. 9 A timing diagram showing the waveforms of voltage signals of some nodes of a stage.

[0044] Fig.11 is a circuit diagram illustrating one stage of a scan driver according to some embodiments.

[0045] Fig.12 is a circuit diagram illustrating one stage of a scan driver according to some embodiments.

[0046] Fig.13 is the diagram being applied to Fig.12 A timing diagram showing the waveforms of voltage signals of some nodes of a stage. DETAILED DESCRIPTION

[0047] By referring to the detailed description and the accompanying drawings of the embodiments, the features of the inventive concept and the methods for completing the inventive concept can be more easily understood. Hereinafter, the embodiments will be described in more detail with reference to the accompanying drawings. However, the described embodiments can be implemented in various forms and should not be construed as being limited to the embodiments illustrated herein. On the contrary, these embodiments are provided as examples so that the disclosure will be thorough and complete, and will fully convey the aspects and features of the inventive concept to those skilled in the art. Therefore, processes, elements and techniques that are unnecessary for a person of ordinary skill in the art to fully understand the aspects and features of the inventive concept may not be described.

[0048] Unless otherwise specified, the same reference numerals denote the same elements throughout the drawings and written description, and therefore, their description will not be repeated. Further, parts not related to the description of the embodiments may not be shown to make the description clear. In the drawings, the relative sizes of elements, layers, and regions may be exaggerated for clarity.

[0049] Various embodiments are described herein with reference to cross-sectional illustrations, which are schematic illustrations of embodiments and / or intermediate structures. Therefore, variations in the shapes of the illustrations, for example due to manufacturing techniques and / or tolerances, are to be expected. Further, the specific structural or functional descriptions disclosed herein are merely illustrative for the purpose of describing embodiments according to the concepts of the present disclosure. Therefore, the embodiments disclosed herein should not be interpreted as being limited to the shapes of the specific illustrations of the regions, but should include shape deviations, for example due to manufacturing.

[0050] For example, an implanted region illustrated as a rectangle typically has rounded or curved features and / or a gradient of implant concentration at its edges, rather than a binary change from an implanted region to a non-implanted region. Similarly, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation occurs. Therefore, the regions illustrated in the accompanying drawings are schematic in nature, and their shapes are not intended to illustrate the actual shape of the regions of the device, and are not intended to be limiting. In addition, as will be appreciated by those skilled in the art, the described embodiments may be modified in a variety of different ways, all without departing from the spirit or scope of the present disclosure.

[0051] In the detailed description, for the purpose of explanation, numerous specific details are set forth to provide a thorough understanding of the various embodiments. However, it is apparent that the various embodiments can be practiced without these specific details or with one or more equivalent arrangements. In other instances, well-known structures and devices are shown in block diagram form to avoid unnecessary obfuscation of the various embodiments.

[0052] It will be understood that, although the terms "first", "second", "third", etc. may be used herein to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the spirit and scope of the present disclosure, the first element, component, region, layer or part described below may be referred to as a second element, component, region, layer or part.

[0053] For ease of explanation, spatial relative terms, such as "below", "below", "below", "below", "above", "on", etc., may be used herein to describe the relationship between an element or feature and another element or feature as illustrated in the accompanying drawings. It will be understood that, in addition to the orientations depicted in the accompanying drawings, spatial relative terms are also intended to cover different orientations of the device in use or operation. For example, if the device in the accompanying drawings is turned over, the element described as "below", "below" or "below" other elements or features will be subsequently oriented to be "above" other elements or features. Therefore, the example terms "below" and "below" can cover both the above and below orientations. The device can be oriented in other ways (e.g., rotated 90 degrees or in other orientations), and the spatial relative descriptors used in this article should be interpreted accordingly. Similarly, when the first part is described as being arranged "on" the second part, this indicates that the first part is arranged on the upper or lower side of the second part, without being limited to the upper side of the second part based on the direction of gravity.

[0054] It will be understood that when an element, layer, region or component is referred to as being "on", "connected to" or "coupled to" another element, layer, region or component, it may be directly on, directly connected to or coupled to another element, layer, region or component, or there may be one or more intermediate elements, layers, regions or components. However, "direct connection / direct coupling" refers to a component directly connecting or coupling another component without intermediate components. At the same time, other expressions describing the relationship between components such as "between...", "immediately between..." or "adjacent to..." and "directly adjacent to..." can be similarly interpreted. In addition, it will also be understood that when an element or layer is referred to as being "between" two elements or layers, it may be the only element or layer between the two elements or layers, or there may also be one or more intermediate elements or layers.

[0055] For purposes of this disclosure, expressions such as "at least one of..." when following a list of elements modify the entire list of elements and do not modify the individual elements of the list. For example, "at least one of X, Y, and Z" and "at least one selected from the group consisting of X, Y, and Z" can be interpreted as any combination of only X, only Y, only Z, or two or more of X, Y, and Z, such as, for example, XYZ, XYY, YZ, and ZZ. In this article, the same number refers to the same element. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0056] The terms used herein are only for the purpose of describing specific embodiments, and are not intended to limit the present disclosure. As used herein, unless the context clearly indicates otherwise, the singular form "one" is intended to also include the plural form. It will be further understood that when the terms "comprising", "having", "including" are used in this specification, the existence of the features, integers, steps, operations, elements and / or parts is specified, but the existence or addition of one or more other features, integers, steps, operations, elements, parts and / or their groups is not excluded. As used herein, the term "and / or" includes any and all combinations of one or more associated listed items.

[0057] As used herein, the terms "substantially," "approximately," "approximately," and similar terms are used as terms of approximation rather than terms of degree, and are intended to account for the inherent deviations in measured or calculated values ​​that one of ordinary skill in the art would recognize. As used herein, "approximately" or "approximately" includes the values ​​and averages within the acceptable range of deviations of the particular values ​​determined by one of ordinary skill in the art, taking into account the measurements in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system). For example, "approximately" can mean within one or more standard deviations, or within ±30%, 20%, 10%, 5% of the value. Further, when describing embodiments of the present disclosure, the use of "may" refers to "one or more embodiments of the present disclosure."

[0058] Any suitable hardware, firmware (e.g., an application specific integrated circuit), software, or a combination of software, firmware, and hardware may be used to implement the electronic or electrical devices and / or any other related devices or components according to the embodiments of the present disclosure described herein. For example, the various components of these devices may be formed on an integrated circuit (IC) chip or on separate IC chips. Further, the various components of these devices may be implemented on a flexible printed circuit film, a tape carrier package (TCP), a printed circuit board (PCB), or formed on a substrate.

[0059] Further, the various components of these devices can be processes or threads running on one or more processors in one or more computing devices, which execute computer program instructions and interact with other system components to perform the various functions described herein. The computer program instructions are stored in a memory, which can be implemented in a computing device using a standard storage device such as a random access memory (RAM). The computer program instructions can also be stored in other non-temporary computer-readable media such as a CD-ROM, a flash drive, etc. In addition, those skilled in the art should recognize that the functions of the various computing devices can be combined or integrated into a single computing device, or the functions of a particular computing device can be distributed on one or more other computing devices without departing from the spirit and scope of the embodiments of the present disclosure.

[0060] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as those commonly understood by those skilled in the art to which the inventive concept belongs. It will also be understood that, unless explicitly defined as such herein, terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and / or this specification, and should not be interpreted in an idealized or overly formal sense.

[0061] Figure 1 is a block diagram illustrating a display device according to an embodiment of the present disclosure. Figure 2 It is used to illustrate Figure 1 An equivalent circuit diagram of a pixel is shown in FIG.

[0062] Hereinafter, an organic light emitting display device will be described as an example of a display device. However, it is not limited thereto and the embodiments may be applied to other display devices such as a liquid crystal display device, a field emission display device, an electrophoretic device, etc. unless the embodiments change the technical spirit of the present disclosure.

[0063] Reference Figure 1 and Figure 2 , the display device according to an embodiment of the present disclosure may include: a display part 100 including a plurality of pixels PX, a scan driver 210 , a data driver 220 , a sensor 230 , and a timing controller 240 .

[0064] The timing controller 240 may generate a scan driving control signal and a data driving control signal DCS based on an external input signal. The scan driving control signal and the data driving control signal DCS generated by the timing controller 240 may be supplied to the scan driver 210 and the data driver 220, respectively.

[0065] The scan driving control signal may include a plurality of clock signals CLK1 and CLK2 and a scan start signal SSP. The scan start signal SSP may control a timing of outputting the first scan signal.

[0066] The data driving control signal DCS may include a source start pulse and a clock signal. The source start pulse controls the time to start sampling data, and the clock signal may be used to control the sampling operation.

[0067] The scan driver 210 may output a scan signal to the scan lines SL1 to SLn in response to the scan drive control signal. The scan driver 210 may sequentially supply the scan signal to the scan lines SL1 to SLn. Here, the scan signal may be set to a scan-on voltage (e.g., a high-level voltage) to turn on a transistor included in the pixel PX.

[0068] The data driver 220 may output data signals to the data lines DL1 to DLm in response to the data driving control signal DCS. The data signals supplied to the data lines DL1 to DLm may be supplied to the pixels PX supplied with the scan signals. To this end, the data driver 220 may supply the data signals to the data lines DL1 to DLm so as to be synchronized with the scan signals.

[0069] The sensor 230 may supply an initialization voltage to the pixels PX supplied with the sensing signals through the sensing lines RL1 to RLm, and may measure degradation information of the pixels PX. Figure 1 2 is illustrated as a separate component, but the sensor 230 may be included in the data driver 220 .

[0070] The display portion 100 may include a plurality of pixels PX, each of which is coupled to one data line DLi among the data lines DL1 to DLm, one scan line SLj among the scan lines SL1 to SLn, and one sensing line RLi among the sensing lines RL1 to RLm.

[0071] The pixel PX may be supplied with a first voltage signal ELVDD and a second voltage signal ELVSS supplied from the outside, the first voltage signal ELVDD being a high potential voltage and the second voltage signal ELVSS being a low potential voltage.

[0072] Each of the pixels PX is driven by a plurality of thin film transistors. Amorphous silicon (a-Si) transistors, polycrystalline silicon (poly-Si) transistors, oxide transistors, organic transistors, etc. can be used as thin film transistors. Here, an example of using oxide transistors as thin film transistors will be described in the present disclosure.

[0073] In an embodiment, each of the pixels PX may include an organic light emitting element OLED coupled between a first power line and a second power line, and may also include a pixel circuit configured to drive the organic light emitting element OLED, respectively, the pixel circuit including a first switching transistor TR1 and a second switching transistor TR2, a driving transistor T1 and a storage capacitor Cst, a first voltage signal ELVDD flows in the first power line, and a second voltage signal ELVSS flows in the second power line.

[0074] The organic light emitting element OLED includes an anode coupled to the driving transistor T1 , a cathode coupled to the second power line, and a light emitting element layer between the anode and the cathode, thereby being configured to emit light in proportion to the amount of current supplied from the driving transistor T1 .

[0075] The first switching transistor TR1 is driven by responding to a scanning signal from one scanning line SLj, thereby supplying a data voltage from the corresponding data line DLi to the scanning node of the driving transistor T1, and the second switching transistor TR2 is driven by responding to a scanning signal from another scanning line SLj+1, thereby supplying an initialization voltage from the sensing line RLi to the source node of the driving transistor T1. The second switching transistor TR2 can be used as a path for outputting a current from the driving transistor T1 to the sensing line RLi in a sensing mode.

[0076] The storage capacitor Cst coupled between the scan node and the source node of the driving transistor T1 is charged with a differential voltage between a data voltage and an initialization voltage, and supplies the charged voltage as a driving voltage of the driving transistor T1. The data voltage is supplied to the scan node through the first switching transistor TR1, and the initialization voltage is supplied to the source node through the second switching transistor TR2.

[0077] The driving transistor T1 controls current supplied from the first power line according to the driving voltage supplied from the storage capacitor Cst and supplies current (the amount of which is proportional to the driving voltage) to the organic light emitting element OLED, thereby enabling the organic light emitting element OLED to emit light.

[0078] Meanwhile, in an embodiment, the scan driving circuit forming the scan driver 210 may be a gate-in-panel (GIP) type, and may be formed of oxide transistors formed on a substrate together with transistors of the pixels PX.

[0079] The scan driver 210 includes a shift register for driving the scan lines SL1 to SLn coupled to the display portion 100 in a sequential or interlaced manner, respectively, in response to a scan drive control signal from the timing controller 240. The scan driver 210 enables each of the scan lines SL1 to SLn by supplying a scan pulse having a scan-on voltage during a driving period of the corresponding scan line, and disables the corresponding scan line by supplying a scan pulse having a scan-off voltage during a remaining period. The scan drive circuit may be formed on one side of the boundary region of the display portion 100, or may be a plurality of circuits formed on opposite sides of the boundary region of the display portion 100.

[0080] Figure 3 It is a graphic Figure 1 FIG. 2 is a diagram of a scan driving circuit of a scan driver 210 .

[0081] Reference Figure 3 , the scan driver 210 according to an embodiment of the present disclosure includes a shift register 310 , a clock line part 320 , and a power line part 330 .

[0082] The shift register 310 includes a plurality of stages ST1 to STn respectively coupled to the plurality of scan lines SL1 to SLn in a one-to-one manner. Respective output terminals OUT1 to OUTn of the plurality of stages ST1 to STn may be coupled to the respective scan lines SL1 to SLn in a one-to-one manner.

[0083] Each of the plurality of stages ST1 to STn may be enabled in response to a signal output from one of the previous stages or in response to a scan start signal, and may be reset in response to a signal output from one of the subsequent stages or in response to a reset pulse. To this end, each of the plurality of stages ST1 to STn includes a plurality of oxide transistors, each of which includes an oxide semiconductor layer. Here, the oxide semiconductor layer may be made of zinc oxide (ZnO), indium zinc oxide (InZnO), indium gallium zinc oxide (InGaZnO 4 ) and so on.

[0084] The shift register 310 includes a light shielding layer LS, which is configured to absorb external light and internal light by overlapping the oxide semiconductor layer of the transistor, thereby reducing or preventing light degradation of the oxide transistor. Specifically, each of the stages ST1 to STn of the shift register 310 further includes a coupling transistor, which is configured to apply a different voltage signal to the light shielding layer LS overlapping the output transistor for each part, thereby reducing the clock load caused by the light shielding layer LS, and thereby also reducing or preventing voltage emission. Therefore, the output characteristics of the stage can be improved. In addition, the light shielding layer LS of each stage is divided into a plurality of parts and a plurality of regions, and different voltages are applied to the plurality of parts and a plurality of regions, so that the characteristics of the transistor can be adjusted for each region according to the action of the transistor.

[0085] The clock line component 320 includes a plurality of clock signal lines. Figure 1 The timing controller 240 illustrated in FIG. 1 supplies a plurality of clock signals CLK1 and CLK2 whose phases are sequentially delayed. A plurality of clock signal lines are selectively coupled to each of the plurality of stages ST1 to STn, thereby supplying at least one of the clock signals CLK1 and CLK2 to each of the plurality of stages ST1 to STn. In the present embodiment, the clock line component 320 is described as including a first clock signal line through which the first clock signal CLK1 is supplied and a second clock signal line through which the second clock signal CLK2 is supplied, but other embodiments are not limited to the number of clock signal lines.

[0086] The power line part 330 includes a third power line 331 of high potential, through which a third voltage signal VGH of high potential having a gate-on voltage level of a transistor in each of the stages ST1 to STn is supplied, and the power line part 330 also includes a fourth power line 332 of low potential, through which a fourth voltage signal VGL of low potential having a gate-off voltage level of a transistor in each of the stages ST1 to STn is supplied. Each of the third power line 331 and the fourth power line 332 is commonly coupled to the plurality of stages ST1 to STn. According to some embodiments, the third voltage signal VGH may have the same voltage level as the first voltage signal ELVDD, and the fourth voltage signal VGL may have the same voltage level as the second voltage signal ELVSS, but they are not limited thereto.

[0087] The light shielding layer LS overlaps at least one of the plurality of thin film transistors. In an embodiment, the light shielding layer LS may include a pull-up light shielding film LSu overlapping the pull-up transistor and a pull-down light shielding film LSd overlapping the pull-down transistor. A description thereof will be described later. In an embodiment, the pull-down light shielding film LSd may be omitted.

[0088] The light shielding layer LS overlaps a pull-up transistor among the plurality of transistors, the pull-up transistor outputting a clock signal as a gate pulse, thereby reducing or preventing degradation of an oxide semiconductor layer of the pull-up transistor due to light.

[0089] The light shielding layer LS can maintain different voltage levels for each portion. The light shielding layer LS according to the example is coupled to a high potential power line, a low potential power line, a clock line, a source electrode of a pull-up transistor, or an output node of the stages ST1 to STn, thereby receiving a voltage signal having a corresponding voltage level.

[0090] In some embodiments, the respective light shielding layers LS provided in the plurality of stages ST1 to STn may be coupled together through coupling lines and bridge electrodes.

[0091] Figure 4 The diagram is based on Figure 3 FIG. 1 is a circuit diagram of one stage of the scan driver 210 of an example. Figure 5 is the diagram being applied to Figure 4 A timing diagram showing the waveforms of voltage signals of some nodes of a stage. Figure 6 is a graph of drive current versus threshold voltage, which indicates the variable threshold voltage characteristics of the oxide transistor.

[0092] Reference Figure 4 and Figure 6 , a stage STi of the scan driver 210 may include a start transistor TRs controlled by a start signal Vst, a reset transistor TRr controlled by a reset signal Vrst, a pull-up transistor TRu and a pull-down transistor TRd of an output terminal OUT, an inverter INV, a first coupling transistor TRQ, and a second coupling transistor TRQb.

[0093] Figure 4 The stage structure illustrated in FIG. 1 is schematic, and the components except the pull-up transistor TRu, the pull-down transistor TRd, the first coupling transistor TRQ, and the second coupling transistor TRQb in the stage can be implemented in various known forms. For example, the reset signal Vrst can be replaced by a carry signal, and the inverter INV can be implemented in any of various known circuits.

[0094] In response to a signal output from a previous stage (for example, a signal supplied from the output terminal OUTi-1 of the previous stage) or a scan start signal, the start transistor TRs controlled by the start signal Vst supplies the signal output from the previous stage or the scan start signal to the first node Q, thereby setting the first node Q to a high logic state.

[0095] The first node Q may be configured such that a source / drain electrode of the start transistor TRs, a source / drain electrode of the reset transistor TRr, an input terminal of the inverter INV, a gate electrode of the pull-up transistor TRu, and a gate electrode of the first coupling transistor TRQ are coupled to the first node Q.

[0096] In response to an output of a subsequent stage or a reset pulse, the reset transistor TRr controlled by the reset signal Vrst supplies the fourth voltage signal VGL to the first node Q, thereby resetting the first node Q to a low logic state.

[0097] The pull-up transistor TRu coupled to the output node O outputs a corresponding clock signal (eg, the first clock signal CLK1 ) to the output terminal OUT coupled to the output node O in response to a high logic state of the first node Q. As shown in FIG.

[0098] The output node O may be configured such that the source / drain electrode of the pull-up transistor TRu and the source / drain electrode of the pull-down transistor TRd are coupled to the output node O. The output node O may output a scan signal through the output terminal OUTi. The scan signal may be supplied to the start transistor of the next stage. The output terminal OUTi+1 of the next stage may output a shifted signal.

[0099] In an embodiment, the pull-up transistor TRu may be a dual-gate transistor. A dual-gate transistor may be formed by positioning two gate electrodes on opposite sides (e.g., top and bottom sides) of a semiconductor layer. In the case of a dual-gate transistor, the mobility of the drive current may be increased by increasing the number of gate electrodes. When the pull-up transistor TRu is formed by a dual-gate transistor, the difference between the mobility of the pull-up transistor TRu and the mobility of the pull-down transistor TRd may be compensated.

[0100] The first gate of the pull-up transistor TRu may be coupled to the first node Q, and the second gate of the pull-up transistor TRu may receive a voltage signal from the pull-up light shielding film LSu. According to some embodiments, the second gate of the pull-up transistor TRu may be directly coupled to the pull-up light shielding film LSu, or may be insulated from the pull-up light shielding film LSu and capacitively coupled to the pull-up light shielding film LSu.

[0101] The inverter INV is configured such that an input terminal of the inverter INV is coupled to the first node Q, an output terminal of the inverter INV is coupled to the second node Qb, and a power supply terminal of the inverter INV is supplied with a third voltage signal VGH and a fourth voltage signal VGL by being coupled to the third power supply line 331 and the fourth power supply line 332. The inverter INV supplies the third voltage signal VGH or the fourth voltage signal VGL to the second node Qb in response to the control of the first node Q, so that the logic state of the second node Qb is opposite to the logic state of the first node Q. That is, when the first node Q is in a high logic state, the inverter INV supplies the fourth voltage signal VGL to the second node Qb, and when the first node Q is in a low logic state, the inverter INV supplies the third voltage signal VGH to the second node Qb.

[0102] In response to the high logic state of the second node Qb, the pull-down transistor TRd coupled to the output node O outputs the fourth voltage signal VGL to the output terminal OUT coupled to the output node O, and the logic state of the second node Qb is opposite to that of the first node Q.

[0103] The voltage signal supplied to the output terminal OUT, the voltage signal applied by the reset transistor TRr, and the voltage signal supplied to the inverter INV may be the same fourth voltage signal VGL.

[0104] The first coupling transistor TRQ may apply the third voltage signal VGH to the pull-up light shielding film LSu in response to the high logic state of the first node Q. The pull-up light shielding film LSu may transmit the third voltage signal VGH to the second gate electrode of the pull-up transistor TRu.

[0105] In some embodiments, the first coupling transistor TRQ may apply a high logic voltage to the pull-up light shielding film LSu only during the first clock signal (CLK1) output period during which the pull-up transistor TRu outputs a high logic scan signal, and may block the voltage applied to the pull-up light shielding film LSu during the remaining period. In the period during which the first coupling transistor TRQ blocks the voltage applied to the pull-up light shielding film LSu, another voltage signal (e.g., a fourth voltage signal VGL) may be applied to the pull-up light shielding film LSu.

[0106] When a high logic voltage is applied to the pull-up light shielding film LSu, the pull-up transistor TRu can obtain a high drive current in a manner similar to a gate synchronization (sync) or a drain synchronization structure. Therefore, the area of ​​the pull-up transistor TRu can be reduced. In addition, the dead space in the scan driver 210 can be reduced by reducing the size of the pull-up transistor TRu.

[0107] like Figure 6As shown in FIG. 1 , when the oxide transistor becomes similar to a gate synchronous or drain synchronous structure, the drive current I DS The curve of gate voltage Vg (for example, Figure 6 V TH -Gsync or V TH -Dsync) can have a larger value than the reference curve V TH -REF has a steeper slope and can be based on the reference curve V TH -REF moves to the left. That is, when the oxide transistor becomes similar to a gate synchronous or drain synchronous structure, the drive current I DS The mobility can be increased and the threshold voltage can be reduced. In addition, the driving current I DS The amount can be increased.

[0108] In contrast, when the oxide transistor becomes similar to a source synchronous structure, the drive current I DS The curve of gate voltage Vg (for example, Figure 6 V TH -Ssync) can be based on the reference curve V TH -REF moves to the right. That is, the threshold voltage can be raised as the oxide transistor becomes similar to a source synchronous structure.

[0109] The second coupling transistor TRQb can apply the fourth voltage signal VGL to the pull-up light shielding film LSu in response to the high logic state of the second node Qb. Here, the first node Q can have a low logic voltage. Therefore, the pull-up light shielding film LSu can transmit the fourth voltage signal VGL to the second gate electrode of the pull-up transistor TRu.

[0110] In this case, the fourth voltage signal VGL is applied to both gate electrodes of the pull-up transistor TRu which is a dual-gate transistor, so that an effect similar to that of the source synchronous structure can be obtained.

[0111] In the case of a dual-gate transistor, the risk of failure caused by noise occurring in the same node may increase compared to a single-gate transistor. Figure 5 As illustrated in , the noise may include coupled noise through the clock signal (eg, CLK coupling).

[0112] During a period in which the first clock signal CLK1 is output from the pull-up transistor TRu, the pull-up transistor TRu as an oxide transistor is configured similar to a gate synchronous or drain synchronous structure and is configured to have a high driving current I DS , thereby compensating for the acceleration of failure caused by the dual-gate transistor structure.

[0113] Figure 7 It is schematically shown including Figure 4sectional view of the structure of the pull-up transistor TRu and the pull-up light shielding film LSu. Figure 8 It is a graphic Figure 7 sectional view of a variation of the structure illustrated in FIG.

[0114] Reference Figure 7 , the scan driver 210 may include a substrate 201 , a pull-up light shielding film LSu located on the substrate 201 , and a pull-up transistor TRu located on the pull-up light shielding film LSu to overlap with the pull-up light shielding film LSu.

[0115] The substrate 201 may be a rigid or flexible substrate. Here, when the substrate 201 is a rigid substrate, the substrate 201 may be any one of a glass substrate, a quartz substrate, a glass ceramic substrate, and a crystallized glass substrate. When the substrate 201 is a flexible substrate, the substrate 201 may be any one of a film substrate and a plastic substrate including a polymer organic material. In addition, the substrate 201 may include glass fiber reinforced plastic (FRP). The substrate 201 may be used as a base substrate.

[0116] The buffer layer 211 may be located on the substrate 201. The buffer layer 211 plays a role in making the surface of the substrate 201 flat and reducing or preventing moisture or external air from penetrating. The buffer layer 211 may be an inorganic film. The buffer layer 211 may be a single-layer film or a multi-layer film.

[0117] The light shielding layer may be located on the buffer layer 211. In this figure, a pull-up light shielding film LSu is illustrated as a component of the light shielding layer.

[0118] The pull-up light-shielding film LSu reduces or prevents leakage current and degradation of the pull-up transistor TRu that would otherwise be caused by light by blocking light incident from the outside of the substrate 201 to the oxide semiconductor layer ACT of the pull-up transistor TRu, thereby improving the stability of the output of the pull-up transistor TRu. To this end, the pull-up light-shielding film LSu may have a larger size (or area) than the oxide semiconductor layer ACT.

[0119] The light shielding layer can be formed of an opaque metal material, a semiconductor material or a light absorbing material having conductivity. For example, any semiconductor material of silicon (Si), germanium (Ge) and silicon germanium (SiGe) as a dielectric material can be used for the light shielding layer, each of which has conductivity and a light absorption coefficient. When a semiconductor is used, the semiconductor includes a semiconductor material containing germanium (Ge) having a high light shielding rate, thereby blocking external light or internal light incident on the oxide semiconductor layer ACT.

[0120] For example, the pull-up light shielding film LSu can be formed by including amorphous silicon (a-Si). Generally, amorphous silicon (a-Si) is used to convert solar photovoltaic energy into electrical energy because it has a high light absorption rate, and the light absorption rate of amorphous silicon (a-Si) is about 100 times higher than that of crystalline silicon. This pull-up light shielding film LSu blocks light incident on the oxide semiconductor layer ACT of the pull-up transistor TRu, thereby reducing or preventing leakage current and degradation of the pull-up transistor TRu caused by light, and thereby improving the stability of the output of the pull-up transistor TRu.

[0121] The first insulating layer 212 may be located on the light shielding layer. The first insulating layer 212 may be an inorganic film. The first insulating layer 212 may be a single-layer film or a multi-layer film.

[0122] The first conductive layer may be located on the first insulating layer 212. The first conductive layer may be patterned to form a bottom gate electrode GE_B of the pull-up transistor TRu. The bottom gate electrode GE_B may correspond to the above-mentioned second gate electrode of the pull-up transistor TRu. The first conductive layer may include at least one of molybdenum (Mo), aluminum (Al), copper (Cu), and titanium (Ti). The first conductive layer may be a single-layer film or a multi-layer film.

[0123] In an embodiment, a contact hole is formed in the first insulating layer 212, and the bottom gate electrode GE_B may be coupled to the light shielding layer (eg, the pull-up light shielding film LSu) through the contact hole.

[0124] The second insulating layer 213 may be located on the first conductive layer. The second insulating layer 213 may be an inorganic film. The second insulating layer 213 may be a single-layer film or a multi-layer film.

[0125] The second conductive layer may be located on the second insulating layer 213. The second conductive layer may be patterned to form a source electrode SE and a drain electrode DE of the pull-up transistor TRu. The second conductive layer may include at least one of molybdenum (Mo), aluminum (Al), copper (Cu), and titanium (Ti).

[0126] The semiconductor layer may be located on the second conductive layer. The semiconductor layer may correspond to the above-mentioned oxide semiconductor layer ACT of the pull-up transistor TRu.

[0127] The semiconductor layer may include a channel region CH and a source region SA and a drain region DA doped with impurities at opposite sides of the channel region CH. The source region SA is coupled to the source electrode SE of the pull-up transistor TRu, and the drain region DA may be coupled to the drain electrode DE of the pull-up transistor TRu.

[0128] In other embodiments, an insulating layer may be further included between the second conductive layer and the semiconductor layer.

[0129] The third insulating layer 214 may be located on the semiconductor layer. The third insulating layer 214 may play a role in protecting the oxide semiconductor layer ACT, the source electrode SE, and the drain electrode DE of the pull-up transistor TRu from the outside. The third insulating layer 214 may be an inorganic film and / or an organic film. The third insulating layer 214 may be a single-layer film or a multi-layer film.

[0130] The third conductive layer may be located on the third insulating layer 214. The third conductive layer may be patterned to form a top gate electrode GE_T of the pull-up transistor TRu. The top gate electrode GE_T may correspond to the first gate electrode of the pull-up transistor TRu. The third conductive layer may include at least one of molybdenum (Mo), aluminum (Al), copper (Cu), and titanium (Ti). The third conductive layer may be a single-layer film or a multi-layer film.

[0131] Reference Figure 8 ,and Figure 7 Unlike the example shown in , the bottom gate electrode GE_B_1 of the pull-up transistor TRu_1 and the pull-up light shielding film LSu may be positioned to be insulated from each other. In this case, a capacitor is formed between the bottom gate electrode GE_B_1 of the pull-up transistor TRu_1 and the pull-up light shielding film LSu, so that the bottom gate electrode GE_B_1 of the pull-up transistor TRu_1 and the pull-up light shielding film LSu may be capacitively coupled to each other.

[0132] The scan driver 210 according to an embodiment will be described below. Figures 1 to 7 The same components will be described repeatedly, and the same or similar reference numerals will be used for this purpose.

[0133] Fig. 9 is a circuit diagram illustrating one stage of the scan driver 210 according to some embodiments. Fig.10 is the diagram being applied to Fig. 9 A timing diagram showing the waveforms of voltage signals of some nodes of a stage.

[0134] Reference Fig. 9 and Fig.10 According to the present example, one stage STi_1 of the scan driver 210 corresponds to Figure 4 and Figure 5 The difference of one stage STi of the embodiment is that the pull-down transistor TRd_1 is a dual-gate transistor, the second gate of the pull-down transistor TRd_1 can receive a voltage signal from the pull-down light shielding film LSd, and the third coupling transistor TRQ_1 and the fourth coupling transistor TRQb_1 replace the first coupling transistor TRQ and the second coupling transistor TRQb respectively.

[0135] Therefore, in some embodiments, the pull-down transistor TRd_1 may be a dual-gate transistor.

[0136] The first gate of the pull-down transistor TRd_1 may be coupled to the second node Qb, and the second gate of the pull-down transistor TRd_1 may receive a voltage signal from the pull-down light shielding film LSd. The second gate of the pull-down transistor TRd_1 may overlap the pull-down light shielding film LSd. According to some embodiments, the second gate of the pull-down transistor TRd_1 and the pull-down light shielding film LSd may be directly coupled to each other, or may be insulated from each other and capacitively coupled.

[0137] The third coupling transistor TRQ_1 may apply the fourth voltage signal VGL to the pull-down light shielding film LSd in response to the high logic state of the first node Q. The pull-down light shielding film LSd may transmit the fourth voltage signal VGL to the second gate electrode of the pull-down transistor TRd_1.

[0138] In some embodiments, the third coupling transistor TRQ_1 applies a low logic voltage to the pull-down light shielding film LSd only during the first clock signal (CLK1) output period, and may block the voltage applied to the pull-down light shielding film LSd during the remaining period, during which the pull-up transistor TRu_2 outputs a high logic scan signal. During the period in which the third coupling transistor TRQ_1 blocks the voltage applied to the pull-down light shielding film LSd, another voltage signal (e.g., a third voltage signal VGH) may be applied to the pull-down light shielding film LSd.

[0139] When a low logic voltage is applied to the pull-down light shielding film LSd, the threshold voltage of the pull-down transistor TRd_1 may vary similarly to the threshold voltage in the source synchronous structure.

[0140] The fourth coupling transistor TRQb_1 may apply the third voltage signal VGH to the pull-down light shielding film LSd in response to the high logic state of the second node Qb. The pull-down light shielding film LSd may transmit the third voltage signal VGH to the second gate electrode of the pull-down transistor TRd_1.

[0141] In this case, the third voltage signal VGH is applied to the gate electrode of the pull-down transistor TRd_1 which is a dual-gate transistor, so that an effect similar to that of the source synchronous structure can be obtained.

[0142] Fig.11 is a circuit diagram illustrating one stage of the scan driver 210 according to some embodiments.

[0143] Reference Fig.11 According to the present example, one stage STi_2 of the scan driver 210 is connected to Figure 4 One stage STi shown in FIG. 1 is different in that the first coupling transistor TRQ_2 transmits the first clock signal CLK1 to the pull-up light shielding film LSu.

[0144] The first coupling transistor TRQ_2 may apply the first clock signal CLK1 to the pull-up light shielding film LSu in response to a high logic state of the first node Q. The pull-up light shielding film LSu may transmit the first clock signal CLK1 to the second gate electrode of the pull-up transistor TRu.

[0145] When the embodiment is configured such that the first coupling transistor TRQ_2 applies a high potential voltage signal having a gate-on voltage level to the pull-up shielding film LSu in response to a high logic state of the first node Q, the present disclosure can be applied regardless of the type of the voltage signal applied to the pull-up shielding film LSu.

[0146] Fig.12 is a circuit diagram illustrating one stage of the scan driver 210 according to some embodiments. Fig.13 is the diagram being applied to Fig.12 A timing diagram showing the waveforms of voltage signals of some nodes of a stage.

[0147] Reference Fig.12 and Fig.13 According to the present example, one stage STi_3 of the scan driver 210 corresponds to Figure 4 and Figure 5 One stage STi is different in that the pull-down transistor TRd_1 is a dual-gate transistor and further includes a third coupling transistor TRQ_1 and a fourth coupling transistor TRQb_1 both coupled to the pull-down light shielding film LSd.

[0148] This example can correspond to Fig. 9 and Fig.10 Example combination of Figure 4 and Figure 5 .

[0149] The first coupling transistor TRQ can apply a high logic voltage to the pull-up light shielding film LSu only in the first clock signal (CLK1) output period during which the pull-up transistor TRu outputs a high logic scan signal, and the third coupling transistor TRQ_1 can apply a low logic voltage to the pull-down light shielding film LSd. In the remaining period, the first coupling transistor TRQ can block the voltage applied to the pull-up light shielding film LSu, and the third coupling transistor TRQ_1 can block the voltage applied to the pull-down light shielding film LSd.

[0150] According to the embodiments of the present disclosure, the scan driver can provide fast and stable output.

[0151] In addition, a high driving current can be obtained in the scan driver, and the dead space can be reduced by reducing the size of the transistor.

[0152] Aspects obtainable from the embodiments are not limited to the above-described aspects, and various aspects are included in the present specification.

[0153] Although the embodiments of the present disclosure have been described in detail with reference to the accompanying drawings, it will be understood by those skilled in the art that the present disclosure may be implemented in other specific forms without changing the technical spirit or essential features of the present disclosure. Therefore, it should be noted that the above embodiments are merely exemplary in all aspects and should not be interpreted as limiting the present disclosure.

Claims

1. A scanning driver, comprising: A first power line configured to supply a constant first voltage signal; a second power line configured to supply a second voltage signal having a voltage level lower than that of the first voltage signal; a pull-up transistor configured to output a corresponding clock signal among a plurality of clock signals as a scan signal in response to a logic state of the first node; a pull-down transistor configured to output the second voltage signal from the second power line as the scan signal in response to a logic state of a second node; a first light shielding film overlapping the pull-up transistor or the pull-down transistor and configured to receive the second voltage signal from the second power line and the first voltage signal from the first power line; as well as A first coupling transistor is coupled to the first power line and is configured to apply the first voltage signal from the first power line to the first light shielding film in response to the logic state of the first node.

2. The scan driver according to claim 1, wherein: The pull-up transistor comprises a dual-gate transistor.

3. The scan driver according to claim 2, wherein: A first gate electrode of the pull-up transistor is coupled to the first node, and a second gate electrode of the pull-up transistor is directly or capacitively coupled to the first light shielding film.

4. The scan driver according to claim 1, wherein: The first coupling transistor is configured to apply the first voltage signal to the first light shielding film only during a period in which the pull-up transistor outputs the corresponding clock signal as the scanning signal.

5. The scan driver according to claim 1, further comprising: A second coupling transistor is configured to apply the second voltage signal from the second power line to the first light shielding film in response to the logic state of the second node.

6. The scan driver according to claim 5, further comprising: a second light shielding film overlapping the pull-down transistor, The first light shielding film overlaps with the pull-up transistor.

7. The scan driver according to claim 6, further comprising: a third coupling transistor configured to apply the second voltage signal from the second power line to the second light shielding film in response to the logic state of the first node; and A fourth coupling transistor is configured to apply the first voltage signal from the first power line to the second light shielding film in response to the logic state of the second node.

8. The scan driver according to claim 1, further comprising: An inverter is configured such that an input terminal of the inverter is coupled to the first node, an output terminal of the inverter is coupled to the second node, and a power supply terminal of the inverter is coupled to the first power supply line and the second power supply line.

9. The scan driver according to claim 8, wherein: The inverter is configured to supply a logic state opposite to the logic state of the first node to the second node in response to control of the first node.

10. The scan driver according to claim 1, further comprising: The start transistor is configured to supply the output of the previous stage or the start pulse to the first node in response to the output of the previous stage or the start pulse.

11. The scan driver according to claim 1, further comprising: A reset transistor is configured to supply the second voltage signal from the second power supply line to the first node in response to an output of a subsequent stage or a reset pulse.

12. The scan driver according to claim 1, wherein: The pull-down transistor comprises a dual-gate transistor, and A first gate electrode of the pull-down transistor is coupled to the second node, and a second gate electrode of the pull-down transistor is coupled or electrically coupled to the first light shielding film.

13. The scan driver according to claim 1, wherein: The pull-up transistor includes an oxide transistor.

14. The scan driver according to claim 13, wherein: The first light shielding film overlaps with the oxide semiconductor layer of the pull-up transistor.

15. The scan driver according to claim 1, wherein: The first light shielding film maintains the first voltage signal during a first portion, and maintains the second voltage signal during a second portion.

16. The scan driver according to claim 15, wherein: The first portion includes a period in which the pull-up transistor outputs the corresponding clock signal as the scan signal.

17. The scan driver according to claim 1, wherein: The first light shielding film overlaps with the pull-up transistor, Wherein, the pull-up transistor comprises: A first gate electrode, located on the first light shielding film; A source electrode and a drain electrode, located on the first gate electrode; an oxide semiconductor layer located on the source electrode and the drain electrode; and a second gate electrode located on the oxide semiconductor layer, and The first gate electrode is configured to receive a voltage signal from the first light shielding film.

18. A scanning driver, comprising: A first power line configured to supply a constant first voltage signal; a second power line configured to supply a second voltage signal having a voltage level lower than that of the first voltage signal; a pull-up transistor configured to output a corresponding clock signal among a plurality of clock signals as a scan signal in response to a logic state of the first node; a pull-down transistor configured to output the second voltage signal from the second power line as the scan signal in response to a logic state of a second node; an inverter configured such that an input terminal of the inverter is coupled to the first node, an output terminal of the inverter is coupled to the second node, and a power supply terminal of the inverter is coupled to the first power supply line and the second power supply line; a first light shielding film overlapping the pull-up transistor or the pull-down transistor and configured to receive the second voltage signal and the corresponding clock signal from the second power line; as well as A coupling transistor is coupled to the second power line and is configured to apply the second voltage signal from the second power line to the first light shielding film in response to the logic state of the second node.

19. A display device comprising: a timing controller configured to generate a scan driving control signal and a data driving control signal based on an externally supplied signal; a scan driver configured to output a scan signal to a scan line in response to the scan drive control signal; a data driver configured to output a data signal to a data line in response to the data driving control signal; and a display comprising pixels coupled to the scan lines and the data lines, Wherein, the scanning driver comprises: A first power line configured to supply a first voltage signal; a second power line configured to supply a second voltage signal having a voltage level lower than that of the first voltage signal; a pull-up transistor configured to output a corresponding clock signal among a plurality of clock signals as the scan signal in response to a logic state of the first node; a pull-down transistor configured to output the second voltage signal from the second power line as the scan signal in response to a logic state of a second node; a first light shielding film overlapping the pull-up transistor or the pull-down transistor; a first coupling transistor configured to apply the first voltage signal from the first power line to the first light shielding film in response to the logic state of the first node; and a second coupling transistor configured to apply the second voltage signal from the second power line to the first light shielding film in response to the logic state of the second node, wherein the first light shielding film is configured to receive the second voltage signal from the second power line and the first voltage signal from the first power line at different times, and wherein the pull-up transistor is configured to output the corresponding clock signal as the scanning signal during a period included in a period in which the first voltage signal is applied to the first light shielding film.

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