Semiconductor chip stacking structure, semiconductor package and its manufacturing method

Abstract

A semiconductor chip stack, a semiconductor package, and a method for manufacturing the same are provided. The semiconductor chip stack includes a first semiconductor chip and a second semiconductor chip. The first chip includes: a first semiconductor substrate having an active surface and a passive surface; a first insulating layer formed on the passive surface; and a first pad formed in the first insulating layer. The second semiconductor chip includes: a second semiconductor substrate having an active surface and a passive surface; a second insulating layer formed on the active surface; a second pad formed in the second insulating layer; a polymer layer formed on the second insulating layer; an under-bump metallization (UBM) pattern embedded in the polymer layer; and embedded solder formed on the UBM pattern and embedded in the polymer layer. The lower surface of the embedded solder is coplanar with the lower surface of the polymer layer, and the embedded solder contacts the first pad at the contact surface, with the cross-sectional area of ​​the embedded solder being largest at the contact surface.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2019-0104585, filed on August 26, 2019, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] This disclosure relates to a semiconductor package and a method for manufacturing a semiconductor package. Background Technology

[0004] Over the past few decades, advancements in technology, materials, and manufacturing processes have led to rapid development in computing power and wireless communication technologies. This has enabled the direct realization of high-performance transistors, and, in accordance with Moore's Law, integration speed has roughly doubled every 18 months. Making systems lightweight, thin, short, and small, as well as improving power efficiency, has always been a goal of the semiconductor manufacturing industry. At this point in time, where economic and physical limits are being reached, 3D integrated packaging is recommended as an effective solution.

[0005] The development of three-dimensional integrated devices began with the introduction of complementary metal-oxide-semiconductor (CMOS) integrated devices in 1980 and has undergone 30 years of continuous research and development (R&D). For example, three-dimensional (3D) integration technology can be used for the integration of logic and memory circuits, sensor packaging, or heterogeneous integration of microelectromechanical systems (MEMS) and CMOS. 3D integration technology allows for high reliability, low power consumption, and low manufacturing costs, and enables a reduction in form factor.

[0006] Recently, due to the use of solder for 3D bonding and the reduction of solder pitch size, reflow processes are increasingly being replaced by thermocompression bonding (TCB) processes as a technique for bonding fine-pitch areas. Summary of the Invention

[0007] On the one hand, a method for manufacturing semiconductor package machines with improved reliability is provided.

[0008] According to one or more embodiments, a semiconductor chip stack structure is provided, including a first semiconductor chip and a second semiconductor chip, the first semiconductor chip comprising: a first semiconductor substrate having an active surface and a passive surface opposite to the active surface; a first semiconductor device layer formed on the active surface and including a circuit pattern; a first back surface insulating layer formed on the passive surface; a plurality of first back surface pads formed at the same level as the first back surface insulating layer; a first front surface insulating layer formed on the first semiconductor device layer and spaced apart from the first semiconductor substrate, the first semiconductor device layer being interposed between the first front surface insulating layer and the first semiconductor substrate; a plurality of first front surface pads formed at the same level as the first front surface insulating layer; a plurality of first through electrodes configured to pass through the first semiconductor substrate and the first semiconductor device layer and electrically connected to the plurality of first back surface pads and the plurality of first front surface pads, respectively; a first polymer layer formed on the first front surface insulating layer; a plurality of first under-bump metallization (UBM) patterns embedded in the first polymer layer; and a plurality of first... A second semiconductor chip includes: a second semiconductor substrate having an active surface and a passive surface opposite to the active surface; a second semiconductor device layer formed on the active surface of the second semiconductor substrate and including a circuit pattern; a second front surface insulating layer formed on the second semiconductor device layer and spaced apart from the second semiconductor substrate, and the second semiconductor device layer being interposed between the second front surface insulating layer and the second semiconductor substrate; a plurality of second front surface pads formed at the same level as the second front surface insulating layer; a second polymer layer formed on the second front surface insulating layer; a plurality of second UBM patterns embedded in the second polymer layer; and a plurality of second buried solders formed on the plurality of second UBM patterns and embedded in the second polymer layer, wherein the lower surfaces of the plurality of second buried solders are coplanar with the lower surface of the second polymer layer, the plurality of second buried solders respectively contact the plurality of first back surface pads on a contact surface, and the horizontal cross-sectional area of ​​each of the plurality of second buried solders is the largest on the contact surface.

[0009] According to another aspect of one or more embodiments, a semiconductor package is provided, comprising a first semiconductor chip, a second semiconductor chip, and a third semiconductor chip stacked in sequence, wherein the first semiconductor chip is different from the second and third semiconductor chips, wherein the second semiconductor chip comprises: a second semiconductor substrate; a semiconductor device layer formed on an active surface of the second semiconductor substrate and including a circuit pattern; a front surface insulating layer formed on the semiconductor device layer and spaced apart from the semiconductor substrate, and the semiconductor device layer being interposed between the front surface insulating layer and the semiconductor substrate; a plurality of front surface pads formed at the same level as the front surface insulating layer; a polymer layer formed on the front surface insulating layer; a plurality of under-bump metallization (UBM) patterns embedded in the polymer layer; and a plurality of embedded solders, each contacting the plurality of UBM patterns and embedded in the polymer layer, wherein the lower surfaces of the plurality of embedded solders are coplanar with the lower surface of the polymer layer, and the horizontal cross-sectional area of ​​each of the plurality of embedded solders increases as the distance from the first semiconductor chip decreases.

[0010] According to another aspect of one or more embodiments, a semiconductor package is provided, comprising: a package substrate; a semiconductor chip stack including a first semiconductor chip and a second semiconductor chip stacked on the package substrate; and a logic chip spaced apart from the semiconductor chip stack on the package substrate, wherein the first semiconductor chip includes: a first semiconductor substrate; a first semiconductor device layer formed on the first semiconductor substrate and including a circuit pattern; a plurality of first through electrodes configured to pass through the first semiconductor substrate and the first semiconductor device layer in a first direction perpendicular to the upper surface of the semiconductor substrate; a first polymer layer formed on the first semiconductor device layer; a plurality of first under-bump metallization (UBM) patterns configured to be embedded in the first polymer layer and electrically connected to the plurality of first through electrodes, respectively; and a plurality of first buried solders disposed on the plurality of first UBM patterns and embedded in the first polymer layer, wherein the horizontal cross-sectional area of ​​each of the plurality of first buried solders embedded in the first polymer layer increases as the distance from the package substrate decreases.

[0011] According to another aspect of one or more embodiments, a method of manufacturing a semiconductor package is provided, the method comprising: providing a first wafer including a first semiconductor device layer, a first insulating layer disposed on the first semiconductor device layer, and a first pad disposed at the same level as the first insulating layer; forming a first polymer layer on the first wafer; forming a first opening to expose the first pad; forming a first under-bump metallization (UBM) pattern in the first opening; forming a sidewall slope at a portion of the sidewall of the first opening by plasma etching of the first polymer layer; and forming a first embedded solder to fill the first opening.

[0012] According to another aspect of one or more embodiments, a semiconductor chip stack structure is provided, including a first semiconductor chip and a second semiconductor chip. The first semiconductor chip includes: a first semiconductor substrate having an active surface and a passive surface; a first insulating layer formed on the passive surface; and a plurality of first pads formed in the first insulating layer. The second semiconductor chip includes: a second semiconductor substrate having an active surface and a passive surface; a second insulating layer formed on the active surface; a plurality of second pads formed in the second insulating layer; a polymer layer formed on the second insulating layer; a plurality of UBM patterns embedded in the polymer layer; and a plurality of embedded solders formed on the plurality of UBM patterns and embedded in the polymer layer, wherein the lower surfaces of the plurality of embedded solders are coplanar with the lower surface of the polymer layer, the plurality of embedded solders contact the plurality of first pads at contact surfaces, and the horizontal cross-sectional area of ​​each of the plurality of embedded solders is maximized on the contact surfaces. Attached Figure Description

[0013] Various embodiments will become clearer from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0014] Figure 1A This is a layout diagram of a semiconductor package according to various embodiments;

[0015] Figure 1B It is along Figure 1A A cross-sectional view taken from line 1I-1I';

[0016] Figure 1C It shows Figure 1B An enlarged partial cross-sectional view of region E1;

[0017] Figure 1D This is a diagram illustrating a semiconductor package according to some other embodiments;

[0018] Figures 2A to 2Q This shows a partial cross-sectional view of a semiconductor package according to different embodiments;

[0019] Figure 3 This is a flowchart illustrating a method for manufacturing a semiconductor package according to some embodiments;

[0020] Figures 4 to 7 This is a cross-sectional view illustrating a method for manufacturing a semiconductor package according to some embodiments;

[0021] Figure 8 This is a conceptual diagram illustrating a method for manufacturing a semiconductor device according to some embodiments;

[0022] Figure 9 This is a flowchart illustrating a method for manufacturing a semiconductor package according to some embodiments;

[0023] Figure 10 and Figure 11 This is a diagram illustrating a method of manufacturing a semiconductor package according to some embodiments;

[0024] Figure 12 This shows a cross-sectional view of a semiconductor package according to some other embodiments;

[0025] Figure 13A This is a plan view of a semiconductor package according to some other embodiments;

[0026] Figure 13B It is along Figure 13A A cross-sectional view taken from line 13I-13I'; and

[0027] Figure 14 This is a block diagram illustrating a system implemented via a semiconductor package according to some embodiments. Detailed Implementation

[0028] In the following description, various embodiments will be described in detail with reference to the accompanying drawings. In this specification, the phrase "at least one of A, B and C" includes "only A", "only B", "only C", "both A and B", "both A and C", "both B and C", or "all of A, B and C".

[0029] Figure 1A This is a layout diagram showing a semiconductor chip stack structure 10 according to various embodiments. Figure 1B It is along Figure 1A The cross-sectional view taken from line 1I-1I'.

[0030] exist Figure 1AFor simplicity, only the first rear surface pad 122, the second rear surface pad 222, the third rear surface pad 322, the first under-bump metallization (UBM) pattern 141, the second UBM pattern 241, the third UBM pattern 341, the fourth UBM pattern 441, the first embedded solder 143, the second embedded solder 243, the third embedded solder 343, and the fourth embedded solder 443 are shown in the layout. As described below, the first rear surface pad 122, the second rear surface pad 222, the third rear surface pad 322, the first UBM pattern 141, the second UBM pattern 241, the third UBM pattern 341, the fourth UBM pattern 441, the first embedded solder 143, the second embedded solder 243, the third embedded solder 343, and the fourth embedded solder 443 are aligned and may overlap in the vertical direction (i.e., in the Z direction). Here, "aligned" means aligned within a specific tolerance range.

[0031] Reference Figure 1A and Figure 1B The semiconductor chip stack structure 10 may be included in the first direction (or in the direction of) Figure 1B The first semiconductor chip C1, the second semiconductor chip C2, the third semiconductor chip C3, and the fourth semiconductor chip C4, along with the molding layer 160, are stacked in the vertical direction or the Z direction.

[0032] The semiconductor chip stack structure 10 may include a circuit region CR in which circuitry is formed, and a pad region PR for electrical connections between the stacked first semiconductor chip C1, second semiconductor chip C2, third semiconductor chip C3, and fourth semiconductor chip C4. Figure 1A In the diagram, two circuit regions CR are shown spaced apart from each other, and a pad region is interposed between the two circuit regions CR. However, these are for illustrative purposes and are not intended to limit the technical spirit of this disclosure in any way.

[0033] In the pad area PR, a first through electrode 125, a second through electrode 225, a third through electrode 325, a first UBM pattern 141, a second UBM pattern 241, a third UBM pattern 341, a fourth UBM pattern 441, a first embedded solder 143, a second embedded solder 243, a third embedded solder 343, and a fourth embedded solder 443 can be formed. Figure 1A The diagram illustrates a schematic configuration of the lower surface of the semiconductor chip stack structure 10 (i.e., the lower surface of the first semiconductor chip C1), wherein a first UBM pattern 141 and a first buried solder 143 are exposed on the lower surface of the semiconductor chip stack structure 10.

[0034] The first through electrode 125, the second through electrode 225, the third through electrode 325, the first UBM pattern 141, the second UBM pattern 241, the third UBM pattern 341, the fourth UBM pattern 441, the first embedded solder 143, the second embedded solder 243, the third embedded solder 343, and the fourth embedded solder 443 can be arranged in various layouts in the pad area PR in the X and Y directions. In some embodiments, such as Figure 1A As shown, in the pad area PR, the first through electrode 125, the second through electrode 225, the third through electrode 325, the first UBM pattern 141, the second UBM pattern 241, the third UBM pattern 341, the fourth UBM pattern 441, the first embedded solder 143, the second embedded solder 243, the third embedded solder 343, and the fourth embedded solder 443 can form a matrix in the X and Y directions with a specified pitch. (Refer to...) Figure 1A When viewed from above, the first UBM pattern 141 is shown as substantially circular, but is not limited thereto. For example, in some embodiments, the plane of the first UBM pattern 141 may be approximately square. That is, the shape of the first UBM pattern 141 may be, for example, approximately square. Alternatively, in other embodiments, the shape of the first UBM pattern 141 may have other geometries.

[0035] Additionally, for convenience, in Figure 1A The example illustrates that, in the pad region PR, six first UBM patterns 141 are arranged in the X direction and two first UBM patterns 141 are arranged in the Y direction. However, the number and arrangement of the first UBM patterns 141 are not limited to... Figure 1A The quantity and arrangement are shown in the figure.

[0036] The first semiconductor chip C1, the second semiconductor chip C2, the third semiconductor chip C3, and the fourth semiconductor chip C4 can be, for example, memory semiconductor chips. Here, for example, the memory semiconductor chip can be a volatile memory semiconductor chip (such as dynamic random access memory (DRAM) or static random access memory (SRAM)) or a non-volatile memory semiconductor chip (such as phase-change random access memory (PRAM), magnetoresistive random access memory (MRAM), ferroelectric random access memory (FeRAM), or resistive random access memory (ReRAM)). In some embodiments, the first semiconductor chip C1, the second semiconductor chip C2, the third semiconductor chip C3, and the fourth semiconductor chip C4 can be DRAM semiconductor chips used to configure high-bandwidth memory (HBM).

[0037] exist Figure 1A and Figure 1BThe image exemplarily illustrates a semiconductor chip stacking structure 10 in which a first semiconductor chip C1, a second semiconductor chip C2, a third semiconductor chip C3, and a fourth semiconductor chip C4 are stacked. However, the number of semiconductor chips stacked in the semiconductor chip stacking structure 10 is not limited to this. For example, in some embodiments, two to 32 semiconductor chips may be stacked in the semiconductor chip stacking structure 10.

[0038] A first UBM pattern 141 and a first embedded solder 143 can be disposed on the lower surface of the first semiconductor chip C1. A second semiconductor chip C2 can be mounted on the upper surface of the first semiconductor chip C1. A second UBM pattern 241 and a second embedded solder 243 are interposed between the first semiconductor chip C1 and the second semiconductor chip C2, and therefore, the second semiconductor chip C2 can be electrically connected to the first semiconductor chip C1. A third semiconductor chip C3 can be mounted on the second semiconductor chip C2. A third UBM pattern 341 and a third embedded solder 343 are interposed between the second semiconductor chip C2 and the third semiconductor chip C3, and therefore, the third semiconductor chip C3 can be electrically connected to the second semiconductor chip C2. Additionally, a fourth semiconductor chip C4 can be mounted on the third semiconductor chip C3. A fourth UBM pattern 441 and a fourth embedded solder 443 are interposed between the third semiconductor chip C3 and the fourth semiconductor chip C4, and therefore, the fourth semiconductor chip C4 can be electrically connected to the third semiconductor chip C3.

[0039] The first semiconductor chip C1 may include a first semiconductor substrate 100, a first semiconductor device layer 110, a first through electrode 125, a first back surface insulating layer 121, a first back surface pad 122, a first front surface insulating layer 123, a first front surface pad 124, a first polymer layer 140, a first UBM pattern 141, and a first buried solder 143. The first semiconductor substrate 100 may include active and passive surfaces opposite each other. The first semiconductor device layer 110 may be formed on the active surface of the first semiconductor substrate 100. The first through electrode 125 may pass through the first semiconductor substrate 100 and the first semiconductor device layer 110 in the Z direction. The first back surface insulating layer 121 and the first back surface pad 122 may be formed on the passive surface of the first semiconductor substrate 100. The first back surface pad 122 may be electrically connected to the first through electrode 125. The first front surface insulating layer 123 and the first front surface pad 124 may be formed on the first semiconductor device layer 110. Therefore, the first front surface insulating layer 123 can be spaced apart from the first semiconductor substrate 100, and the first semiconductor device layer 110 is inserted between the first front surface insulating layer 123 and the first semiconductor substrate 100.

[0040] The first front surface insulating layer 123 and the first rear surface insulating layer 121 may include protective layers for protecting the first semiconductor device layer 110 and resisting wiring structures formed in the first semiconductor device layer 110 from external impacts or moisture. For example, the first front surface insulating layer 123 and the first rear surface insulating layer 121 may include inorganic insulating layers or organic insulating layers. According to some embodiments, the first front surface insulating layer 123 and the first rear surface insulating layer 121 may include at least one of silicon nitride, silicon oxide, and silicon oxynitride.

[0041] A first polymer layer 140 may be formed on a first front surface insulating layer 123. The first polymer layer 140 may include an insulating polymer. According to some embodiments, the first polymer layer 140 may be formed by processes other than underfilling. According to some embodiments, the first polymer layer 140 may omit epoxy molding compound (EMC). According to some embodiments, the first polymer layer 140 may omit reactive prepolymers and polymers containing epoxy groups. According to some embodiments, the first polymer layer 140 may exclude bisphenol A epoxy resin, phenolic varnish epoxy resin, aliphatic epoxy resin, halide epoxy resin, epoxy resin diluent, and glycidylamine epoxy resin.

[0042] The first UBM pattern 141 and the first embedded solder 143 can be disposed in the first polymer layer 140. The first UBM pattern 141 and the first embedded solder 143 can form a stacked structure. The side surfaces of the first UBM pattern 141 and the first embedded solder 143 can be covered by the first polymer layer 140. The first embedded solder 143 can be embedded in the first polymer layer 140. The upper surface of the first embedded solder 143 can be coplanar with the upper surface of the first polymer layer 140 and can be exposed to the outside. Therefore, the first embedded solder 143 can be embedded in the first polymer layer 140.

[0043] The first semiconductor substrate 100 may include, for example, silicon (Si). Alternatively, the first semiconductor substrate 100 may include semiconductor elements (such as germanium (Ge)) or compound semiconductors (such as silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs), or indium phosphide (InP)). Alternatively, the first semiconductor substrate 100 may have a silicon-on-insulator (SOI) structure. For example, the first semiconductor substrate 100 may include a buried oxide (BOX) layer. The first semiconductor substrate 100 may include conductive regions, such as impurity-doped wells or impurity-doped structures. In addition, the first semiconductor substrate 100 may have various device isolation structures, such as shallow trench isolation (STI) structures.

[0044] The first semiconductor device layer 110 may include a plurality of individual devices of various kinds and an interlayer insulating layer. The plurality of individual devices may include various microelectronic devices, such as metal-oxide-semiconductor field-effect transistors (MOSFETs) (e.g., complementary metal-insulator-semiconductor (CMOS) transistors), system-on-large-scale integrated circuits (LSI), flash memory, dynamic random access memory (DRAM), static RAM (SRAM), electrically erasable programmable read-only memory (EEPROM), programmable RAM (PRAM), magnetic RAM (MRAM) or resistive RAM (ReRAM), image sensors (e.g., CMOS imaging sensors (CIS)), microelectromechanical systems (MEMS), active devices and / or passive devices. The plurality of individual devices may be formed in the first semiconductor device layer 110 within the circuit region CR and may be electrically connected to a conductive region of the first semiconductor substrate 100. The first semiconductor device layer 110 may also include at least two of the plurality of individual devices or conductive wiring or conductive plugs for electrically connecting the plurality of individual devices to the conductive regions of the first semiconductor substrate 100. Additionally, the plurality of individual devices may be electrically isolated from other adjacent individual devices by an insulating layer.

[0045] The first semiconductor device layer 110 may include multiple wiring structures for connecting multiple individual devices to other wiring lines formed on the first semiconductor substrate 100. The multiple wiring structures may include a metal wiring pattern extending in a horizontal direction and via plugs extending in a vertical direction. The metal wiring pattern and via plugs may include a barrier layer and a conductive layer. The barrier layer may include at least one material selected from titanium (Ti), titanium nitride (TiN), tantalum (Ta), and tantalum nitride (TaN). The conductive layer may include at least one metal selected from tungsten (W), aluminum (Al), and copper (Cu). The multiple wiring structures may be a multilayer structure in which two or more metal wiring patterns and two or more via plugs are stacked. According to some embodiments, the first front surface pad 124 and the first rear surface pad 122 may also include at least one metal selected from W, Al, and Cu.

[0046] The first through electrode 125 may penetrate the first semiconductor substrate 100 and the first semiconductor device layer 110. The first through electrode 125 may be cylindrical. The first through electrode 125 may include a barrier layer defining the surface of these pillars and a buried conductive layer filling the interior of the barrier layer. The barrier layer may include at least one of Ti, TiN, Ta, TaN, rubidium (Ru), cobalt (Co), manganese (Mn), tungsten nitride (WN), nickel (Ni), and nickel boride (NiB). The buried conductive layer may include at least one of Cu, Cu alloys (such as CuSn, CuMg, CuNi, CuZn, CuPd, CuAu, CuRe, or CuW), W, W alloys, Ni, Ru, and Co. In some embodiments, the first through electrode 125 may be formed at the same level as the first semiconductor substrate 100 and the first semiconductor device layer 110, and may further include a via insulating layer covering the barrier layer. The via insulating layer may include an oxide layer, a nitride layer, a carbide layer, a polymer, or a combination of these layers.

[0047] The first UBM pattern 141 may be disposed on the first semiconductor device layer 110 and may contact the first front surface pad 124. The first UBM pattern 141 may include at least one of tin (Sn), Ti, vanadium (V), antimony (Sb), lead (Pb), W, chromium (Cr), Cu, Ni, Al, palladium (Pd), silver (Ag) and gold (Au).

[0048] The first UBM pattern 141 may be a single metal layer or a stacked structure having multiple metal layers. For example, the first UBM pattern 141 may include a first metal layer, a second metal layer, and a third metal layer stacked sequentially. The first metal layer may include a material with high adhesion to the first front surface pad 124 and the first front surface insulating layer 123. That is, the first metal layer may include an adhesive layer for improving stability during the formation of the first buried solder 143. For example, the first metal layer may include at least one of Ti, Ti-W, Cr, and Al. The second metal layer may include a barrier layer for preventing the diffusion of metal material included in the first buried solder 143 into the first semiconductor substrate 100. The second metal layer may include at least one of Cu, Ni, Cr-Cu, and Ni-V. The third metal layer may be used as a seed layer for forming the first buried solder 143 or as a wetting layer for improving the wetting properties of the first buried solder 143. The third metal layer may include at least one of Ni, Cu, and Al.

[0049] A first embedded solder 143 may be disposed on a first UBM pattern 141. The first embedded solder 143 may form, together with a first polymer layer 140, the lowermost surface of the semiconductor chip stack structure 10. According to some embodiments, the first embedded solder 143 may be a chip-to-substrate bonding solder for mounting the semiconductor chip stack structure 10 on an external substrate or through-hole. According to some embodiments, the first embedded solder 143 may be a chip-to-chip bonding solder for mounting the semiconductor chip stack structure 10 on an external surface or through-hole.

[0050] The first embedded solder 143 can be configured with a path for receiving control signals for operating the first semiconductor chip C1, the second semiconductor chip C2, the third semiconductor chip C3, and the fourth semiconductor chip C4, as well as at least one of a power supply potential or a ground potential from the outside; receiving data signals stored in the first semiconductor chip C1, the second semiconductor chip C2, the third semiconductor chip C3, and the fourth semiconductor chip C4 from the outside; and / or providing data stored in the first semiconductor chip C1, the second semiconductor chip C2, the third semiconductor chip C3, and the fourth semiconductor chip C4 to the outside.

[0051] The first embedded solder 143 may include solder material. The first embedded solder 143 may include Sn, In, bismuth (Bi), Sb, Cu, Ag, zinc (Zn), Pb and / or alloys of these metals. For example, the first embedded solder 143 may include at least one of Sn, Pb, Sn-Pb, Sn-Ag, Sn-Au, Sn-Cu, Sn-Bi, Sn-Zn, Sn-Ag-Cu, Sn-Ag-Bi, Sn-Ag-Zn, Sn-Cu-Bi, Sn-Cu-Zn, and Sn-Bi-Zn.

[0052] In some embodiments, an intermediate layer may be formed at the contact interface between the first embedded solder 143 and the first UBM pattern 141. The intermediate layer may include an intermediate compound (IMC) formed by reacting a metallic material included in the first embedded solder 143 and the first UBM pattern 141 at a high temperature. For example, when the first UBM pattern 141 includes Cu and / or Ni and the first embedded solder 143 includes Sn and / or Cu, the intermediate layer may include at least one of (Cu,Ni)6Sn5, (Cu,Ni)3Sn4, and (Cu,Ni)3Sn. However, the material or composition of the intermediate layer is not limited thereto and may vary depending on the materials of the first embedded solder 143 and the first UBM pattern 141, the soldering process time, and / or the temperature.

[0053] The second semiconductor chip C2 can be mounted on the upper surface of the first semiconductor chip C1 and can be electrically connected to the first semiconductor chip C1, and the second embedded solder 243 is located between the first semiconductor chip C1 and the second semiconductor chip C2.

[0054] The second semiconductor chip C2 may include a second semiconductor substrate 200, a second semiconductor device layer 210, a second rear surface insulating layer 221, a second rear surface pad 222, a second front surface insulating layer 223, a second front surface pad 224, a second through electrode 225, a second polymer layer 240, a second UBM pattern 241, and a second buried solder 243. The second buried solder 243 may contact the first rear surface pad 122 at a contact surface. According to some embodiments, the second semiconductor chip C2 may be the same as the first semiconductor chip C1. Since the technical features of the second semiconductor chip C2 are the same as those of the first semiconductor chip C1, a detailed description of the second semiconductor chip C2 will not be given for the sake of brevity.

[0055] The third semiconductor chip C3 may include a third semiconductor substrate 300, a third semiconductor device layer 310, a third rear surface insulating layer 321, a third rear surface pad 322, a third front surface insulating layer 323, a third front surface pad 324, a third through electrode 325, a third polymer layer 340, a third UBM pattern 341, and a third buried solder 343. According to some embodiments, since the technical features of the third semiconductor chip C3 are similar to those of the first semiconductor chip C1, for the sake of brevity, no further description of the third semiconductor chip C3 will be given.

[0056] The fourth semiconductor chip C4 may include a fourth semiconductor substrate 400, a fourth semiconductor device layer 410, a fourth front surface insulating layer 423, a fourth front surface pad 424, a fourth polymer layer 440, a fourth UBM pattern 441, and a fourth buried solder 443. Because in Figure 1A and Figure 1B In the example shown, the fourth semiconductor chip C4 is the memory chip located on the top layer of the stacked memory chips; therefore, the back surface insulating layer, back surface pads, and through electrodes can be omitted. Apart from omitting the back surface insulating layer, back surface pads, and through electrodes, since the technical features of the fourth semiconductor chip C4 are similar to those of the first semiconductor chip C1, additional descriptions of the fourth semiconductor chip C4 will be omitted for brevity.

[0057] A third embedded solder 343 can be inserted between the third UBM pattern 341 and the second rear surface pad 222. The third embedded solder 343 can contact the third UBM pattern 341 and the second rear surface pad 222. Therefore, the second semiconductor chip C2 and the third semiconductor chip C3 can be electrically connected to each other. A fourth embedded solder 443 can be inserted between the fourth UBM pattern 441 and the third rear surface pad 322. The fourth embedded solder 443 can contact the fourth UBM pattern 441 and the third rear surface pad 322. Therefore, the third semiconductor chip C3 and the fourth semiconductor chip C4 can be electrically connected to each other.

[0058] The molding layer 160 may surround the side surfaces of the second polymer layer 240, the third polymer layer 340, and the fourth polymer layer 440, as well as the side surfaces of the second semiconductor chip C2, the third semiconductor chip C3, and the fourth semiconductor chip C4. The molding layer 160 may include, for example, EMC (electromagnetic composite material). Figure 1B As shown, the width of the first semiconductor chip C1 in the horizontal direction (X direction) can be greater than the widths of the second semiconductor chip C2, the third semiconductor chip C3, and the fourth semiconductor chip C4 in the horizontal direction, and the molding layer 160 can contact the edge of the upper surface of the first semiconductor chip C1. However, the inventive concept is not limited thereto. According to some embodiments, the molding layer 160 can cover the upper surface of the fourth semiconductor chip C4. In other embodiments, with Figure 1B Unlike the previous method, the molding layer 160 is not formed on the upper surface of the fourth semiconductor chip C4, and the upper surface of the fourth semiconductor chip C4 can be exposed to the outside of the semiconductor chip stack structure 10.

[0059] Figure 1C It shows Figure 1B An enlarged partial cross-sectional view of region E1.

[0060] Reference Figure 1C The structural characteristics of the second embedded solder 243 and the second UBM pattern 241 will be described in more detail below. The first embedded solder 143, the third embedded solder 343, and the fourth embedded solder 443, as well as the first UBM pattern 141, the third UBM pattern 341, and the fourth UBM pattern 441, can be the same as those described below with reference to the second embedded solder 243 and the second UBM pattern 241. Therefore, for the sake of brevity, detailed descriptions of the first embedded solder 143, the third embedded solder 343, and the fourth embedded solder 443, as well as the first UBM pattern 141, the third UBM pattern 341, and the fourth UBM pattern 441, are omitted.

[0061] Reference Figure 1CThe second embedded solder 243 and the second UBM pattern 241 may have rotational symmetry with respect to an axis extending parallel to it in the Z direction. However, the inventive concept is not limited thereto. The second embedded solder 243 and the second UBM pattern 241 may have a generally square horizontal cross-section.

[0062] The second UBM pattern 241 can be generally cylindrical. The horizontal cross-sectional area of ​​the second UBM pattern 241 in the Z direction can be constant. Here, the horizontal cross-sectional area refers to the cross-sectional area perpendicular to the Z direction (i.e., its normal is parallel to the Z direction). The second embedded solder 243 can include a first portion 243p1 having a constant horizontal cross-sectional area and a second portion 243p2 having a varying horizontal cross-sectional area. The first portion 243p1 of the second embedded solder 243 can be generally cylindrical, and the second portion 243p2 of the second embedded solder 243 can be generally truncated cone-shaped.

[0063] The first portion 243p1 may include a vertical sidewall 243vw, and the second portion 243p2 may include an inclined sidewall 243sw. In some embodiments, the heights (i.e., the lengths in the Z direction) of the first portion 243p1 and the second portion 243p2 may be equal. However, the inventive concept is not limited thereto. For example, in some embodiments, the height of the first portion 243p1 may be greater than or less than the height of the second portion 243p2.

[0064] The second portion 243p2 can contact the first rear surface pad 122 at the contact surface CS. The second portion 243p2 can have a large horizontal cross-section facing the first rear surface pad 122. That is, the horizontal cross-section of the second portion 243p2 can increase as the distance from the first rear surface pad 122 decreases, and this horizontal cross-section can be maximized at the contact surface between the second portion 243p2 and the first rear surface pad 122. The cross-sectional profile of the inclined sidewall 243sw can be linear. The angle of the inclined sidewall 243sw in the horizontal direction can be constant. Therefore, the variation of the horizontal cross-sectional area of ​​the second portion 243p2 in the Z direction can be constant.

[0065] According to some embodiments, the pitch Pi (i.e., repeating cell length) of the second embedded solder 243, the second UBM pattern 241, the second front surface pad 224, and the first rear surface pad 122 can be from approximately 20 μm to approximately 1 μm. In other embodiments, the pitch Pi can be from approximately 15 μm to approximately 2 μm. In other embodiments, the pitch Pi can be from approximately 10 μm to approximately 3 μm.

[0066] According to some embodiments, the first width W1 (or diameter) of each of the first portion 243p1 of the second embedded solder 243 and the second UBM pattern 241 can be from about 10 μm to about 0.3 μm. In other embodiments, the first width W1 can be from about 5 μm to about 0.6 μm. In other embodiments, the first width W1 can be from about 3 μm to about 1 μm.

[0067] According to some embodiments, the second width W2, which is the maximum width of each of the second portions 243p2 of the second embedded solder 243, can be the horizontal width of each of the portions contacting the first back surface pad 122. According to some embodiments, the second width W2 can be less than or equal to the third width W3, and can be equal to or greater than the first width W1. According to some embodiments, the second width W2 can be from approximately 15 μm to approximately 0.3 μm. In other embodiments, the second width W2 can be from approximately 10 μm to approximately 0.6 μm. In other embodiments, the second width W2 can be from approximately 2 μm to approximately 1 μm.

[0068] According to some embodiments, the third width W3, which is the width of the corresponding first rear surface pad 122, can be from approximately 15 μm to approximately 0.5 μm. In other embodiments, the third width W3 can be from approximately 10 μm to approximately 1 μm. In other embodiments, the third width W3 can be from approximately 5 μm to approximately 2 μm.

[0069] According to some embodiments, as described below, since the horizontal cross-sectional area of ​​the second embedded solder 243 increases as the distance from the first rear surface pad 122 decreases, the horizontal cross-sectional area (or horizontal width) of the second polymer layer 240 can decrease as the distance from the contact surface decreases.

[0070] Recently, as the pitch of semiconductor devices has become finer, solder bumps with a pitch of no more than approximately 20 μm are required.

[0071] In embedded solder structures, because the polymer layer surrounds the embedded solder, during the subsequent thermoforming process, the embedded solder deforms or slips due to the mismatch between the underlying layer (e.g., the back surface insulating layer and the back surface pad) and the coefficient of thermal expansion (CTE). Consequently, the embedded solder moves parallel to the substrate. In this case, circuit defects may occur due to the opening between the underlying pattern and the embedded pattern.

[0072] According to the various embodiments disclosed herein, the second embedded solder 243, the third embedded solder 343, and the fourth embedded solder 443 may have increased (or maximum) cross-sectional areas on the surfaces that intersect with the first rear surface pad 122, the second rear surface pad 222, and the third rear surface pad 322, respectively. Therefore, even when the second embedded solder 243, the third embedded solder 343, and the fourth embedded solder 443, as well as the first rear surface pad 122, the second rear surface pad 222, and the third rear surface pad 322, are misaligned due to CTE mismatch, circuit defects caused by openings can be prevented.

[0073] Furthermore, the cross-sectional area (or width) of the surfaces where the second embedded solder 243, the third embedded solder 343, and the fourth embedded solder 443 intersect with the first rear surface pad 122, the second rear surface pad 222, and the third rear surface pad 322, respectively, can be smaller than the cross-sectional area (or width) of the first rear surface pad 122, the second rear surface pad 222, and the third rear surface pad 322. That is, W2 can be smaller than W3. Therefore, even when the second embedded solder 243, the third embedded solder 343, and the fourth embedded solder 443, as well as the first rear surface pad 122, the second rear surface pad 222, and the third rear surface pad 322, are not aligned due to CTE mismatch, circuit defects caused by short circuits can be prevented.

[0074] Figure 1D This is a diagram illustrating a semiconductor package according to some other embodiments.

[0075] More in detail, Figure 1D Is with Figure 1C For the sake of convenience and simplicity, the corresponding cross-sectional views have been omitted from the previous references. Figures 1A to 1C The given description, and will mainly focus on the Figures 1A to 1C and Figure 1D The different descriptions between them.

[0076] Reference Figure 1D The second insulating layer 242 can be inserted between the second front surface insulating layer 223 and the second polymer layer 240. That is, with Figure 1D Corresponding semiconductor chip stacking structure and reference Figures 1A to 1C The semiconductor chip stack structure 10 described is identical, and each semiconductor chip may further include an insulating layer interposed between the front surface insulating layer and the polymer layer.

[0077] The second insulating layer 242 may include an insulating material. According to some embodiments, the second insulating layer 242 may include a polymer different from the polymer included in the second polymer layer 240. According to some embodiments, the second insulating layer 242 may include silicon oxide, silicon nitride, and / or silicon oxynitride.

[0078] The second insulating layer 242 may be arranged at the same level as the second UBM pattern 241. According to some embodiments, the second UBM pattern 241 may be formed by a damascene process that patterns the second insulating layer 242, accumulates UBM pattern material, and planarizes the material. However, the inventive concept is not limited thereto. The second UBM pattern 241 may also be formed by an electroplating process after the second insulating layer 242 has been patterned.

[0079] Figures 2A to 2Q This shows a partial cross-sectional view of a semiconductor package according to different embodiments.

[0080] More in detail, Figures 2A to 2Q Is with Figure 1B The partial cross-sectional view corresponding to region E2 is shown, and for simplicity, only a second UBM pattern 241, a second embedded solder 243 and a first back surface pad 122 are shown.

[0081] Due to factors other than the shape of the second embedded solder 243 Figures 2A to 2Q Semiconductor packaging and Figures 1A to 1C The semiconductor chip stacking structure 10 is the same, so for the sake of brevity, the previously given description is omitted, and the structural characteristics of the second buried solder 243 will be mainly described.

[0082] Reference Figure 2A The second embedded solder 243 may include a first portion 243p1 having a constant cross-sectional area and a second portion 243p2 whose cross-sectional area increases as the distance from the first rear surface pad 122 decreases. However, compared with Figure 1C Compared to the embodiment shown, the second portion 243p2 of the second embedded solder 243 may protrude only from the first portion 243p1 to one side in the X direction, and may not protrude to the other side. Therefore, at least a portion of the second portion 243p2 of the second embedded solder 243 may have a vertical sidewall extending in the Z direction parallel to the vertical sidewall of the first portion 243p1. The horizontal cross-sectional area of ​​the second embedded solder 243 may vary constantly in the Z direction. Therefore, the center of the second embedded solder 243 may not vertically overlap with the center of the second UBM pattern 241. In other words, the second embedded solder 243 may not have rotational symmetry with respect to an axis extending parallel in the Z direction.

[0083] Reference Figure 2B A pore 243v can be formed between the second portion 243p2 of the second embedded solder 243 and the second polymer layer 240. The pore 243v can have various shapes and sizes. According to some embodiments, although the pore 243v is formed, the second embedded solder 243 can have the largest cross-sectional area on the surface intersecting with the first back surface pad 122. According to some embodiments, the variation in the horizontal cross-sectional area of ​​the second portion 243p2 of the second embedded solder 243 can vary depending on the pore 243v. More specifically, the variation in the horizontal cross-sectional area of ​​the second portion 243p2 of the second embedded solder 243 on the pore 243v can be greater than the variation in the horizontal cross-sectional area of ​​the second portion 243p2 of the second embedded solder 243 at the same level as the pore 243v. In other words, the angle β between the first rear surface pad 122 and the edge of the formed aperture 243v of the second embedded solder 243 can be greater than the angle α between the first rear surface pad 122 and the second embedded solder 243 opposite to the aperture 243v.

[0084] Reference Figure 2C The second embedded solder 243 may include an inclined sidewall 243sw, which is connected to... Figure 1C The difference is that the second embedded solder 243 may not include Figure 1C The vertical sidewall 243vw is shown in the figure. In the etching process of the second polymer layer 240 described later, the profile of the second polymer layer 240 can be controlled by controlling the average energy, energy distribution, and etching time of the plasma etching the second polymer layer 240. According to some embodiments, the horizontal cross-sectional variation of the second embedded solder 243 can be constant.

[0085] Figure 2D Implementation examples and Figure 2A The corresponding implementation. In other words, Figure 2D The embodiments shown may be Figure 2A and Figure 2C The combination of embodiments shown. The second embedded solder 243 may have a vertical sidewall on one side that extends parallel to the second embedded solder 243 in the Z direction.

[0086] Figure 2E Implementation examples and Figure 2B The corresponding implementation. In other words, Figure 2E The embodiments shown may be Figure 2B and Figure 2C The combination of embodiments shown. Aperture 243v can be formed between the second embedded solder 243 and the second polymer layer 240.

[0087] Reference Figure 2FThe second embedded solder 243 may include a first portion 243p1 with a constant horizontal cross-sectional area in the Z direction and a second portion 243p2 with a varying horizontal cross-sectional area in the Z direction. According to some embodiments, the rate of change of the horizontal cross-sectional area of ​​the second portion 243p2 of the second embedded solder 243 may vary in the Z direction. According to some embodiments, the second embedded solder 243 may have concave circular sidewalls 243rw1. Therefore, the rate of change of the horizontal cross-sectional area of ​​the second embedded solder 243 may increase with increasing distance from the first rear surface pad 122.

[0088] Figure 2G Implementation examples and Figure 2A The corresponding implementation. In other words, Figure 2G The embodiments shown may be Figure 2A and Figure 2F The combination of embodiments shown. The second embedded solder 243 may have a vertical sidewall on one side that extends parallel to the second embedded solder 243 in the Z direction.

[0089] Figure 2H Implementation examples and Figure 2B The corresponding implementation. In other words, Figure 2H The embodiments shown may be Figure 2B and Figure 2F The combination of embodiments shown. Aperture 243v can be formed between the second embedded solder 243 and the second polymer layer 240.

[0090] Reference Figure 2I The second embedded solder 243 may include a circular sidewall 243rw1. The circular sidewall 243rw1 may be concave and may extend from the lower surface of the second embedded solder 243 (i.e., the surface that contacts the first rear surface pad 122) to the upper surface of the second embedded solder 243 (i.e., the surface that contacts the second UBM pattern 241).

[0091] Figure 2J Implementation examples and Figure 2A The corresponding implementation. In other words, Figure 2J The embodiments shown may be Figure 2A and Figure 2I The combination of embodiments shown. The second embedded solder 243 may have a vertical sidewall on one side that extends parallel to the second embedded solder 243 in the Z direction.

[0092] Figure 2K Implementation examples and Figure 2B The corresponding implementation. In other words, Figure 2K The embodiments shown may be Figure 2B and Figure 2IThe combination of embodiments shown. Aperture 243v can be formed between the second embedded solder 243 and the second polymer layer 240.

[0093] Reference Figure 2L The second embedded solder 243 may include a first portion 243p1 with a constant horizontal cross-sectional area in the Z direction and a second portion 243p2 with a varying horizontal cross-sectional area in the Z direction. According to some embodiments, the rate of change of the horizontal cross-sectional area of ​​the second portion 243p2 of the second embedded solder 243 may vary in the Z direction. According to some embodiments, the second embedded solder 243 may have a convex circular sidewall 243rw2. Therefore, the rate of change of the horizontal cross-sectional area of ​​the second embedded solder 243 may decrease as the distance from the first rear surface pad 122 decreases.

[0094] Figure 2M Implementation examples and Figure 2A The corresponding implementation. In other words, Figure 2M The embodiments shown may be Figure 2A and Figure 2L The combination of embodiments shown. The second embedded solder 243 may have a vertical sidewall on one side that extends parallel to the second embedded solder 243 in the Z direction.

[0095] Figure 2N Implementation examples and Figure 2B The corresponding implementation. In other words, Figure 2N The embodiments shown may be Figure 2B and Figure 2L The combination of embodiments shown. Aperture 243v can be formed between the second embedded solder 243 and the second polymer layer 240.

[0096] Reference Figure 2O The second embedded solder 243 may include a circular sidewall 243rw2. The circular sidewall 243rw2 may be a convex surface and may extend from the lower surface of the second embedded solder 243 (i.e., the surface that contacts the first rear surface pad 122) to the upper surface of the second embedded solder 243 (i.e., the surface that contacts the second UBM pattern 241).

[0097] Figure 2P Implementation examples and Figure 2A The corresponding implementation. In other words, Figure 2P The embodiments shown may be Figure 2A and Figure 2O The combination of embodiments shown. The second embedded solder 243 may have a vertical sidewall on one side that extends parallel to the second embedded solder 243 in the Z direction.

[0098] Figure 2QImplementation examples and Figure 2B The corresponding implementation. In other words, Figure 2Q The embodiments shown can Figure 2B and Figure 2O The combination of embodiments shown. Aperture 243v can be formed between the second embedded solder 243 and the second polymer layer 240.

[0099] Figure 3 This is a flowchart illustrating a method for manufacturing a semiconductor package according to some embodiments.

[0100] Figures 4 to 7 This is a cross-sectional view illustrating a method for manufacturing a semiconductor package according to some embodiments. Here, Figures 6A to 6C It shows Figure 5 A magnified partial cross-sectional view of part E3.

[0101] Reference Figure 3 and Figure 4 In P110, a first wafer W on which a first semiconductor device layer 110 is formed can be provided.

[0102] The first wafer W may include a plurality of first semiconductor chips C1 separated from each other, and a scribe line SL is interposed between the plurality of first semiconductor chips C1. Each first semiconductor chip C1 may include a first semiconductor substrate 100, a first semiconductor device layer 110, a first through electrode 125, a first back surface insulating layer 121, a first back surface pad 122, a first front surface insulating layer 123, and a first front surface pad 124. The first semiconductor substrate 100 may include active and passive surfaces opposite each other. The first semiconductor device layer 110 may be formed on the active surface of the first semiconductor substrate 100. The first through electrode 125 may pass through the first semiconductor substrate 100 and the first semiconductor device layer 110.

[0103] The first semiconductor device layer 110 may include a system LSI, flash memory, DRAM, SRAM, EEPROM, PRAM, MRAM, or ReRAM. The first semiconductor device layer 110 may include multiple wiring structures for connecting multiple individual devices to other wiring lines formed on the first semiconductor substrate 100.

[0104] A first through electrode 125 may extend from a first upper surface 102 of the first semiconductor substrate 100 into the interior of the first semiconductor substrate 100. At least some portions of the first through electrode 125 may be columnar. In some embodiments, the first through electrode 125 may be formed of a barrier layer formed on a columnar surface and a buried conductive layer filling the interior of the barrier layer. In some embodiments, a via insulating layer may be interposed between the first semiconductor substrate 100 and the first through electrode 125. The via insulating layer may include an oxide layer, a nitride layer, a carbide layer, a polymer, or a combination of these layers.

[0105] Reference Figure 3 and Figure 5 In P120, a first polymer layer 140 and a first UBM pattern 141 can be formed.

[0106] According to some embodiments, the first polymer layer 140 may comprise various polymers. The first polymer layer 140 may be formed, for example, by spin coating. However, the inventive concept is not limited thereto. The first polymer layer 140 may be formed by processes such as atomic layer deposition (ALD), chemical vapor deposition (CVD), plasma-enhanced CVD (PECVD), metal-organic CVD (MOCVD), physical vapor deposition (PVD), reactive pulsed laser deposition, molecular beam epitaxy, or direct current (DC) magnetron sputtering.

[0107] In some embodiments, the first polymer layer 140 may include an uncured polymer. The first polymer layer 140 may be cured when it is bonded to an external substrate or chip, such as a packaging substrate, a logic chip, or an insertion substrate. According to some embodiments, the first polymer layer 140 may include a photosensitive material, and in this case, it may be patterned using a development process.

[0108] According to some embodiments, the first polymer layer 140 may include a non-photosensitive material and may be patterned using additional photoresist patterns. Patterning of the first polymer layer 140 may be performed by plasma etching, such as argon (Ar) plasma etching. However, the inventive concept is not limited thereto. Here, patterning the first polymer layer 140 means exposing the first front surface pad 124 by removing at least a portion of the first polymer layer 140.

[0109] The first UBM pattern 141 can be formed, for example, by electroplating. The first UBM pattern 141 may include at least one of Sn, Ti, vanadium (V), Sb, Pb, W, Cr, Cu, Ni, Al, Pd, Ag and Au.

[0110] Reference Figure 3 , Figure 6A and Figure 6B In P130, sidewall tilts can be formed in the first polymer layer 140.

[0111] The formation of sidewall tilts in the first polymer layer 140 can be performed using plasma etching, such as Ar plasma etching. According to some embodiments, the first UBM pattern 141 can be unaffected by plasma etching because it does not have sufficient energy to remove the metal pattern. Therefore, the upper portion of the first UBM pattern 141 can also be removed during the process of forming the tilts in the first polymer layer 140.

[0112] According to some embodiments, the sidewall tilt of the first polymer layer 140 can have various profiles by adjusting process parameters such as the process temperature and time of the plasma etching process, the average energy of the plasma, the type of plasma, and the energy distribution of the plasma. For example, Figure 1C and Figures 2A to 2Q Various sidewall tilt profiles according to the various embodiments discussed above are shown. By appropriately selecting the process parameters of the plasma etching process, it is possible to implement the... Figure 1C and Figures 2A to 2Q The sidewall tilt profile of the first polymer layer 140 is shown in the sidewall tilt profile. Figure 6B It shows Figure 1C The sloping profile of the sidewall is used as an example.

[0113] Reference Figure 3 and Figure 6C In P140, a first embedded solder 143 can be formed. The first embedded solder 143 can be formed by an inlay process. More specifically, after forming a material layer of Sn, Pb, Sn-Pb, Sn-Ag, Sn-Au, Sn-Cu, Sn-Bi, Sn-Zn, Sn-Ag-Cu, Sn-Ag-Bi, Sn-Ag-Zn, Sn-Cu-Bi, Sn-Cu-Zn and / or Sn-Bi-Zn on a first polymer layer 140 in which sidewalls are inclined, the first embedded solder 143 can be formed by performing chemical mechanical polishing (CMP) on which the upper surface of the first polymer layer 140 is the etched endpoint. The shape of the sidewalls of the first embedded solder 143 can be determined by the sidewall inclination formed in the first polymer layer 140.

[0114] Reference Figure 7 The first semiconductor chip C1 can be individualized by separating it along the scribing line SL. The first semiconductor chip C1 can be separated by a separation unit such as a scraper or a laser.

[0115] The above describes a method for manufacturing the first semiconductor chip C1. However, those skilled in the art will understand from this description that the second semiconductor chip C2, the third semiconductor chip C3, and the fourth semiconductor chip C4 shown in FIG1B can be formed using the same method described above.

[0116] Refer again Figure 1B The first semiconductor chip stack structure 10 can be formed by stacking the first semiconductor chip C1, the second semiconductor chip C2, the third semiconductor chip C3 and the fourth semiconductor chip C4.

[0117] According to some embodiments, in the thermocompression bonding (TCB) process for forming the first semiconductor chip stack structure 10, the tilt profile of one of the second polymer layer 240, the third polymer layer 340, and the fourth polymer layer 440, or the tilt profile of one of the second buried solder 243, the third buried solder 343, and the fourth buried solder 443, can vary. Therefore, the sidewall tilt of the second buried solder 243, the third buried solder 343, and the fourth buried solder 443 can be rounded, forming a aperture 243v, and / or the second buried solder 243, the third buried solder 343, and the fourth buried solder 443 can be recessed towards their center.

[0118] Figure 8 This is a conceptual diagram illustrating a method for manufacturing a semiconductor device according to some embodiments.

[0119] exist Figures 3 to 7 The text describes the situation in such a context. Figure 8 The chip-to-chip (or die-to-die) bonding of individualized semiconductor chips, as shown in (c), is performed. However, the inventive concept is not limited thereto.

[0120] Reference Figure 8 For reference, please refer to Figures 3 to 6C The description describes the formation of a first wafer Wa, a second wafer Wb, a third wafer Wc, and a fourth wafer Wd. In some embodiments, according to arrow (a), the first wafer Wa, the second wafer Wb, the third wafer Wc, and the fourth wafer Wd can be wafer-level bonded using the TCB method, and then the semiconductor chip stack structure 10 can be individualized. In other embodiments, according to arrow (c), in such... Figure 7The diagram illustrates how, after individualizing a first wafer Wa, a second wafer Wb, a third wafer Wc, and a fourth wafer Wd to form a first semiconductor chip C1, a second semiconductor chip C2, a third semiconductor chip C3, and a fourth semiconductor chip C4, a semiconductor chip stack structure 10 can be formed by bonding the first semiconductor chip C1, the second semiconductor chip C2, the third semiconductor chip C3, and the fourth semiconductor chip C4 via a TCB method. In other embodiments, according to arrow (b), the semiconductor chip stack structure 10 can be formed by wafer-to-wafer bonding of the first wafer Wa and the second wafer Wb, prior to individualizing the third wafer Wc and the fourth wafer Wd, and then by chip-level bonding of the third wafer Wc and the fourth wafer Wd. Then, after mounting the stack structure including the third semiconductor chip C3 and the fourth semiconductor chip C4 on the stack structure of the first wafer Wa and the second wafer Wb, chip-to-wafer bonding is performed to individualize the third semiconductor chip C3 and the fourth semiconductor chip C4.

[0121] Figure 9 This is a flowchart illustrating a method for manufacturing a semiconductor package according to some embodiments.

[0122] Figure 9 P210 and P220 and Figure 3 Since P110 and P120 are the same, for the sake of brevity, their various aspects have been omitted.

[0123] Figure 10 and Figure 11 This is a diagram illustrating a method of manufacturing a semiconductor package according to some embodiments. More specifically, Figure 10 and Figure 11 Is with Figures 6A to 6C The corresponding partial cross-sectional view.

[0124] Reference Figure 9 and Figure 10 In P230, the first embedded solder 143 can be formed. This can be achieved by referring to... Figure 6C The described inlay process is used to form the first embedded solder 143. Unlike in Figure 6C, in... Figure 10 In the process, before the sidewall tilt is formed in the first polymer layer 140, the first embedded solder 143 may be formed.

[0125] Then, refer to Figure 9 and Figure 11 In P240, sidewall tilts can be formed in the first polymer layer 140.

[0126] The sidewall tilt formed in the first polymer layer 140 can be compared with the reference. Figure 3 , Figure 6A and Figure 6B Since the descriptions are identical, the repeated descriptions are omitted for brevity.

[0127] When the first polymer layer 140 is etched by plasma, the upper part of the first embedded solder 143 is not removed because the first embedded solder 143 is unaffected.

[0128] In this way, it is possible to form Figure 1B The first semiconductor chip C1, the second semiconductor chip C2, the third semiconductor chip C3, and the fourth semiconductor chip C4 are described. The first semiconductor chip C1, the second semiconductor chip C2, the third semiconductor chip C3, and the fourth semiconductor chip C4 can be bonded using the TCB method. At this time, because heat and pressure are applied to the second polymer layer 240, the third polymer layer 340, and the fourth polymer layer 440, as well as the second embedded solder 243, the third embedded solder 343, and the fourth embedded solder 443, when the second embedded solder 243, the third embedded solder 343, and the fourth embedded solder 443 are bonded sequentially to the first back surface pad 122, the second back surface pad 222, and the third back surface pad 322, the vias can be omitted.

[0129] Figure 12 This is a cross-sectional view of a semiconductor package 20 according to some other embodiments.

[0130] For convenience and for brevity, previous references have been omitted. Figures 1A to 1C The given description, and the main description with Figures 1A to 1C The difference.

[0131] According to some embodiments, the semiconductor package 20 may include a first semiconductor chip C1, a second semiconductor chip C2, a third semiconductor chip C3, a fourth semiconductor chip C4, and a fifth semiconductor chip C5, as well as an external connection terminal 524. Because the first semiconductor chip C1, the second semiconductor chip C2, the third semiconductor chip C3, and the fourth semiconductor chip C4 are connected to... Figure 1B The first semiconductor chip C1, the second semiconductor chip C2, the third semiconductor chip C3, and the fourth semiconductor chip C4 are the same, so for the sake of brevity, their detailed descriptions will not be given.

[0132] According to some embodiments, the semiconductor package 20 may be a hybrid package. The first semiconductor chip C1, the second semiconductor chip C2, the third semiconductor chip C3, and the fourth semiconductor chip C4 may be a memory device or a DRAM device for implementing HBM.

[0133] According to some embodiments, the fifth semiconductor chip C5 may include a fifth semiconductor substrate 500, a fifth semiconductor device layer 510, a fifth back surface insulating layer 521, a fifth back surface pad 522, a fifth through electrode 525, a rewiring layer 523, and an external connection terminal 524.

[0134] According to some embodiments, by stacking a first semiconductor chip C1, a second semiconductor chip C2, a third semiconductor chip C3, and a fourth semiconductor chip C4 as memory chips and logic chips, this configuration is advantageous for implementing deep learning because local computation and operation processing can be performed. Deep learning operations can be performed using field-programmable gate arrays (FPGAs), graphics processing units (GPUs), and central processing units (CPUs). However, as... Figure 12 As shown, when the logic layer (i.e., the fifth semiconductor chip C5) in the semiconductor package 20 is used, the power consumption can be reduced because the amount of operation processing per watt can be increased in high memory bandwidth.

[0135] Figure 13A This is a plan view of a semiconductor package 30 according to some other embodiments.

[0136] Figure 13B It is along Figure 13A The cross-sectional view taken from line 13I-13I'.

[0137] Reference Figure 13A and Figure 13B The semiconductor package 30 may include a first analog device 1011 and a second analog device 1012, a radio frequency (RF) device 1030, a passive device 1040, a semiconductor chip stack structure 10, a logic chip 1100, a package substrate 1001, and an external connection terminal 1026.

[0138] Semiconductor chip stacking structure 10 and reference Figures 1A to 1C The descriptions are identical, and therefore, for the sake of brevity, repeated descriptions are omitted.

[0139] The packaging substrate 1001 can be, for example, a printed circuit board (PCB), a ceramic substrate, or a through-hole component. When the packaging substrate 1001 is a PCB, it can include a substrate base and upper surface pads 1022 and lower surface pads 1024 formed on the upper and lower surfaces of the substrate base, respectively. The upper surface pads 1022 and lower surface pads 1024 can be exposed by solder resist layers covering the upper and lower surfaces of the substrate base. The substrate base can be formed of at least one material selected from phenolic resin, epoxy resin, and polyimide. For example, the substrate base can include at least one material selected from FR4, tetrafunctional epoxy resin, polyphenylene ether, epoxy / polyphenylene ether, bismaleimide triazine (BT), thermosetting resin, cyanate ester, polyimide, and liquid crystal polymer. The upper surface pads 1022 and lower surface pads 1024 can be formed of Cu, Ni, stainless steel, or beryllium copper. Internal wiring lines electrically connected to the upper surface pad 1022 and the lower surface pad 1024 can be formed in the substrate. The upper surface pad 1022 and the lower surface pad 1024 can be portions of the solder mask layer exposed in the patterned circuit wiring lines after the upper and lower surfaces of the substrate are coated with Cu foil.

[0140] When the packaging substrate 1001 is a through-hole component, the packaging substrate 1001 may include a substrate formed of semiconductor material and upper surface pads 1022 and lower surface pads 1024 formed on the upper and lower surfaces of the substrate, respectively. The substrate may be formed, for example, from a silicon wafer. Internal wiring may be formed on the upper surface, the lower surface, or within the substrate. Additionally, vias electrically connecting the upper surface pads 1022 and the lower surface pads 1024 may be formed within the substrate.

[0141] External connection terminals 1026 may be attached to the lower surface of the package substrate 1001. External connection terminals 1026 may be attached to, for example, a lower surface pad 1024. External connection terminals 1026 may be, for example, solder balls or bumps. External connection terminals 1026 can electrically connect the semiconductor package 30 to an external device. For example, external connection terminals 1026 may include a UBM pattern 1027 disposed on the lower surface pad 1024 and solder balls 1028 disposed on the UBM pattern 1027. External connection terminals 1026 may also include external connection pillars disposed between the UBM pattern 1027 and the solder balls 1028. External connection pillars may include, for example, Cu.

[0142] UBM pattern 1027 may include with Figures 1A to 1CThe material is the same as that described in the first UBM pattern 141, second UBM pattern 241, third UBM pattern 341, and fourth UBM pattern 441. In an exemplary embodiment, the width and / or height of the external connection terminal 1026 may be greater than that of the first embedded solder 143, second embedded solder 243, third embedded solder 343, and fourth embedded solder 443 (see [reference]). Figure 1B The width and / or height of the external connection terminal 1026. In some embodiments, the area of ​​the external connection terminal 1026 may be greater than the areas of the first embedded solder 143, the second embedded solder 243, the third embedded solder 343, and the fourth embedded solder 443. In some embodiments, the horizontal width of the external connection terminal 1026 may be not less than approximately 20 μm. In other embodiments, the horizontal width of the external connection terminal 1026 may be not less than approximately 50 μm. In some embodiments, the vertical height (height in the Z direction) of the external connection terminal 1026 may be not less than approximately 20 μm. In other embodiments, the vertical height (height in the Z direction) of the external connection terminal 1026 may be not less than approximately 50 μm. However, the inventive concept is not limited thereto.

[0143] RF device 1030 can be an antenna device for transmitting and receiving radio frequency waves, and may include multiple filters. RF device 1030 can operate in various wireless communication environments, such as 3G, 4G and / or 5G wireless communication environments.

[0144] The passive device 1040 may include an impedance device for impedance matching or a multilayer ceramic capacitor (MLCC) for blocking noise.

[0145] In the semiconductor package 30, on the package substrate 1001, a molding component 1050 may be formed surrounding some or all of the first analog device 1011, the second analog device 1012, the RF device 1030, the passive device 1040, the semiconductor chip stack structure 10, and the logic chip 1100. The molding component 1050 may be formed by, for example, EMC.

[0146] The logic chip 1100 may include a logic substrate 1101, a logic device layer 1110, a front surface insulating layer 1023, a front surface pad 1124, a polymer layer 1140, a UBM pattern 1141, and buried solder 1143. (Except for the omitted...) Figure 12 Apart from the vias, back surface pads, and back surface insulating layer shown, the logic chip 1100 can be connected to... Figure 12 It is the same as the fifth semiconductor chip C5.

[0147] Figure 14This is a block diagram illustrating a system 1200 implemented via a semiconductor package according to an embodiment.

[0148] Reference Figure 14 System 1200 may include a controller 1210, an input / output device 1220, a storage device 1230, and an interface 1240. According to some embodiments, system 1200 may include... Figures 1A to 1C Semiconductor chip stacking structure 10 Figure 12 Semiconductor package 20 and Figure 13A and Figure 13B At least one of the semiconductor packages 30, or can be... Figures 1A to 1C Semiconductor chip stacking structure 10 Figure 12 Semiconductor package 20 and Figure 13A and Figure 13B At least one of the semiconductor packages 30 is used to implement this.

[0149] System 1200 may be a mobile system or a system for sending or receiving information. In some embodiments, the mobile system is a personal digital assistant (PDA), a portable computer, a network tablet, a cordless phone, a mobile phone, a digital music player, or a memory card.

[0150] The controller 1210 used to execute programs in the control system 1200 may include a microprocessor, digital signal processor, microcontroller, or similar device.

[0151] Input / output device 1220 can input or output data to system 1200. System 1200 can be connected to external devices (e.g., personal computers (PCs) or networks) using input / output device 1220 and can exchange data with external devices. Input / output device 1220 can be, for example, a keypad, keyboard, or monitor.

[0152] Storage device 1230 may store code and / or data used to operate controller 1210 or data processed by controller 1210.

[0153] Interface 1240 can be a data transmission path between system 1200 and another external device. Controller 1210, input / output device 1220, storage device 1230, and interface 1240 can communicate with each other via bus 1250. System 1200 can be included in a mobile phone, MP3 player, navigator, portable multimedia player (PMP), solid-state drive (SSD), or home appliance.

[0154] Although the inventive concept has been specifically shown and described with reference to various embodiments thereof, it will be understood that various changes in form and detail may be made herein without departing from the spirit and scope of the appended claims.

Claims

1. A semiconductor chip stacking structure, comprising a first semiconductor chip and a second semiconductor chip, The first semiconductor chip includes: A first semiconductor substrate having an active surface and a passive surface opposite to the active surface; A first semiconductor device layer is formed on the active surface and includes a circuit pattern; A first rear surface insulating layer is formed on the passive surface; Multiple first rear surface pads are formed at the same level as the first rear surface insulating layer; A first front surface insulating layer is formed on the first semiconductor device layer and spaced apart from the first semiconductor substrate, and the first semiconductor device layer is interposed between the first front surface insulating layer and the first semiconductor substrate. Multiple first front surface pads are formed at the same level as the first front surface insulating layer; A plurality of first through electrodes are configured to pass through the first semiconductor substrate and the first semiconductor device layer, and are electrically connected to the plurality of first rear surface pads and the plurality of first front surface pads, respectively; A first polymer layer is formed on the first front surface insulating layer; Multiple metallized patterns under the first bumps are embedded in the first polymer layer; as well as Multiple first embedded solders are respectively formed on the metallization patterns under the multiple first bumps and embedded in the first polymer layer. The second semiconductor chip includes: A second semiconductor substrate has an active surface and a passive surface opposite to the active surface; A second semiconductor device layer is formed on the active surface of the second semiconductor substrate and includes a circuit pattern. A second front surface insulating layer is formed on the second semiconductor device layer and spaced apart from the second semiconductor substrate, and the second semiconductor device layer is interposed between the second front surface insulating layer and the second semiconductor substrate. Multiple second front surface pads are formed at the same level as the second front surface insulating layer; A second polymer layer is formed on the second front surface insulating layer; Multiple second bump under-metallization patterns are embedded in the second polymer layer; and Multiple second embedded solders are respectively formed on the metallization patterns under the multiple second bumps and embedded in the second polymer layer. The lower surfaces of the plurality of second embedded solders are coplanar with the lower surface of the second polymer layer. The plurality of second embedded solders contact the plurality of first rear surface pads on the contact surface. The sidewalls of the second embedded solders have a straight shape and are inclined relative to the vertical axis. The horizontal cross-sectional area of ​​each of the plurality of second embedded solders is the largest on the contact surface.

2. The semiconductor chip stacking structure according to claim 1, wherein, Each of the plurality of second embedded solders includes a first portion and a second portion, the first portion having a constant horizontal cross-sectional area and the second portion having a variable horizontal cross-sectional area.

3. The semiconductor chip stacking structure according to claim 2, wherein, The horizontal cross-sectional area of ​​the second part increases as the distance from the contact surface decreases.

4. The semiconductor chip stacking structure according to claim 2, wherein, The rate of change of the horizontal cross-sectional area of ​​the second portion in a first direction perpendicular to the active surface of the second semiconductor substrate is constant.

5. The semiconductor chip stacking structure according to claim 2, wherein, The pitch of the plurality of second embedded solders is not greater than 20 mm and not less than 1 mm.

6. The semiconductor chip stacking structure according to claim 1, wherein, The minimum horizontal width of each of the plurality of second embedded solders is not greater than 10 mm and not less than 0.3 mm.

7. The semiconductor chip stacking structure according to claim 1, wherein, The maximum horizontal width of each of the plurality of second embedded solders is not greater than 15 mm and not less than 0.3 mm.

8. The semiconductor chip stacking structure according to claim 1, wherein, The maximum horizontal width of each of the plurality of second embedded solder pads is less than the horizontal width of each of the plurality of first rear surface pads.

9. A semiconductor package, comprising: The first semiconductor chip, the second semiconductor chip, and the third semiconductor chip are stacked sequentially. The first semiconductor chip is different from the second and third semiconductor chips. The second semiconductor chip includes: Second semiconductor substrate; A semiconductor device layer is formed on the active surface of the second semiconductor substrate and includes a circuit pattern. A front surface insulating layer is formed on the semiconductor device layer and spaced apart from the second semiconductor substrate, and the semiconductor device layer is interposed between the front surface insulating layer and the second semiconductor substrate; Multiple front surface pads are formed at the same level as the front surface insulating layer; A polymer layer is formed on the front surface insulating layer; Multiple bump-under metallized patterns are embedded in the polymer layer; and Multiple embedded solders, each contacting the rear surface pads of the first semiconductor chip at its contact surface, are embedded in the polymer layer. The lower surfaces of the plurality of embedded solders are coplanar with the lower surface of the polymer layer, and the sidewalls of the embedded solders have a straight shape and are inclined relative to the vertical axis. The horizontal cross-sectional area of ​​each of the plurality of embedded solders increases as the distance from the first semiconductor chip decreases and is maximized on the contact surface.

10. The semiconductor package according to claim 9, wherein, The first semiconductor chip includes a logic chip, and the second and third semiconductor chips include memory chips.

11. The semiconductor package of claim 9, wherein, The first semiconductor chip includes a plurality of external connection terminals, which are formed on the side of the second semiconductor chip opposite to the active surface. The width of the plurality of external connection terminals is greater than the width of the plurality of embedded solders.

12. The semiconductor package of claim 11, wherein, Each of the plurality of external connection terminals has a width of not less than 20 mm.

13. The semiconductor package according to claim 9, wherein, The pitch of the plurality of embedded solders is not greater than 20 mm and not less than 1 mm.

14. A semiconductor package, comprising: The packaging substrate includes a substrate and an upper surface pad located on the upper surface of the substrate. A semiconductor chip stack comprising a first semiconductor chip and a second semiconductor chip stacked on the packaging substrate; as well as A logic chip, spaced apart from the semiconductor chip stack on the packaging substrate. The first semiconductor chip includes: First semiconductor substrate; A first semiconductor device layer is formed on the first semiconductor substrate and includes a circuit pattern; A plurality of first through electrodes are configured to pass through the first semiconductor substrate and the first semiconductor device layer in a first direction perpendicular to the upper surface of the first semiconductor substrate; A first polymer layer is formed on the first semiconductor device layer; Multiple first bump under-metallization patterns are configured to be embedded in the first polymer layer and electrically connected to the multiple first through electrodes, respectively; and Multiple first embedded solders are arranged on the metallization pattern under the multiple first bumps and respectively contact the upper surface pads on the contact surface, and are embedded in the first polymer layer. Wherein, the horizontal cross-sectional area of ​​the first polymer layer decreases as the distance from the packaging substrate decreases, and the sidewall where the first polymer layer intersects with the first embedded solder has a straight shape and is inclined relative to the vertical axis, and the horizontal cross-sectional area of ​​the first embedded solder is the largest on the contact surface.

15. The semiconductor package of claim 14, wherein, The first polymer layer does not include epoxy molding compound.

16. The semiconductor package of claim 14, wherein, Each of the plurality of metallized patterns under the first bumps is columnar.

17. The semiconductor package of claim 14, wherein, The plurality of first embedded solders each include a plurality of first columnar portions.

18. The semiconductor package of claim 17, wherein, The plurality of first embedded solders also include a plurality of truncated conical portions, and The plurality of truncated conical portions are respectively arranged below the plurality of first columnar portions.

19. A semiconductor chip stacking structure, comprising a first semiconductor chip and a second semiconductor chip, The first semiconductor chip includes: A first semiconductor substrate having an active surface and a passive surface; A first insulating layer is formed on the passive surface; as well as Multiple first pads are formed in the first insulating layer; The second semiconductor chip includes: A second semiconductor substrate having an active surface and a passive surface; A second insulating layer is formed on the active surface of the second semiconductor substrate; Multiple second pads are formed in the second insulating layer; A polymer layer is formed on the second insulating layer; Multiple bump-under metallized patterns are embedded in the polymer layer; and Multiple embedded solders are formed on the multiple under-bump metallization patterns and embedded in the polymer layer. The lower surfaces of the plurality of embedded solders are coplanar with the lower surface of the polymer layer. The plurality of embedded solders contact the plurality of first pads on the contact surface, and the sidewall profile of the embedded solders is determined by the sidewall profile of the polymer layer, such that the horizontal cross-sectional area of ​​each of the plurality of embedded solders is maximized on the contact surface, and the sidewall of the embedded solder has a straight shape and is inclined relative to the vertical axis.

20. The semiconductor chip stacking structure according to claim 19, wherein, Each of the plurality of embedded solders includes a first portion and a second portion, the first portion having a constant horizontal cross-sectional area and the second portion having a variable horizontal cross-sectional area.

21. The semiconductor chip stacking structure according to claim 20, wherein, The horizontal cross-sectional area of ​​the second part increases as the distance from the contact surface decreases.

22. The semiconductor chip stacking structure according to claim 20, wherein, The rate of change of the horizontal cross-sectional area of ​​the second portion in a first direction perpendicular to the active surface of the second semiconductor substrate is constant.

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