Semiconductor packaging device and manufacturing method thereof

Abstract

The present disclosure provides a semiconductor packaging device and a method for manufacturing the same. By dividing the redistribution layer originally formed at the chip end or the substrate end into two parts, one part is formed at the substrate end and the other part is formed at the chip end, that is, dividing it into two working lines, the semiconductor packaging device can achieve technical effects including but not limited to the following: First, by forming the redistribution layer at the substrate end and the chip end respectively, the connection between the chip and the substrate with a 5 to 7 nanometer process is achieved. Second, by adopting the redistribution layer, the process cost is reduced compared to 2.5D and 3D packaging. Third, by forming the redistribution layer at the substrate end and the chip end respectively, the overall yield can be improved compared to forming the redistribution layer only at a single end of the substrate or only at a single end of the wafer.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor packaging technology, and more particularly to a semiconductor packaging device and a manufacturing method thereof. Background Art

[0002] As semiconductor wafer / chip manufacturing capabilities improve year by year, semiconductor substrate manufacturing capabilities must also keep pace to meet the needs of wafer-to-substrate docking. To solve this problem, the following two solutions are often used:

[0003] First, a redistribution layer is formed on one end of the wafer, and then the wafer with the redistribution layer formed is bonded and electrically connected to a common substrate (eg, a substrate with a line width and line spacing of more than 10 microns).

[0004] Second, a redistribution layer is formed on one side of the substrate, and then the chip is bonded and electrically connected to the substrate with the redistribution layer. Currently, semiconductor wafer manufacturing capabilities have reached 7nm and even 5nm processes, and the bump pitch of the final chip is less than 25 microns. The minimum pitch of ordinary semiconductor substrates is currently 130um, which is no longer suitable for chips produced by 5 to 7nm processes. After the redistribution layer is formed on the substrate side, the UBM (Under Bump Metallization) layer corresponding to the redistribution layer on the substrate has a minimum size of 25 microns. Therefore, chips produced by 5 to 7nm processes cannot be directly connected to the UBM layer of the substrate after the redistribution layer is formed. While using 2.5D packaging or 3D IC interposers can solve the above problems, their high manufacturing costs have led to significant obstacles to entering mass production.

[0005] Furthermore, in both of the above methods, if the redistribution layer formed on the wafer or substrate side typically has multiple layers of circuitry, the overall yield will be multiplied by the yield of each additional circuit layer, meaning the overall yield will decrease. Summary of the Invention

[0006] The present disclosure provides a semiconductor packaging device and a method for manufacturing the same.

[0007] In a first aspect, the present disclosure provides a semiconductor packaging device, the semiconductor packaging device comprising:

[0008] substrate;

[0009] an adhesive layer, disposed on the substrate;

[0010] A first redistribution layer is disposed on the adhesive layer;

[0011] a second redistribution layer, disposed on the first redistribution layer and electrically connected to the first redistribution layer;

[0012] At least one chip is disposed on the second redistribution layer and electrically connected to the second redistribution layer;

[0013] At least one through hole penetrates the first redistribution layer and the adhesive layer and extends to the substrate, and the first redistribution layer is electrically connected to the substrate through the at least one through hole.

[0014] In some optional embodiments, the line width and line spacing of the first redistribution layer and the second redistribution layer are between 0.5 microns and 10 microns, and the line width and line spacing of the substrate are greater than 10 microns.

[0015] In some optional embodiments, the line width and line spacing of the first redistribution layer and the second redistribution layer are between 0.5 microns and 2 microns.

[0016] In some optional embodiments, the second redistribution layer is electrically connected to the first redistribution layer via solder balls, and bottom filling glue is filled between the bottom of the second redistribution layer and the first redistribution layer.

[0017] In some optional embodiments, the at least one chip is electrically connected to the second redistribution layer via a wire; and

[0018] The semiconductor packaging device further includes:

[0019] a first package body, encapsulating the at least one chip;

[0020] The second package body covers the substrate, the adhesive layer, the first redistribution layer, the second redistribution layer and the first package body.

[0021] In some optional implementations, the first package body and the second package body are made of the same packaging material.

[0022] In some optional embodiments, the at least one chip is electrically connected to the second redistribution layer via solder balls, and an underfill is filled between the bottom of the at least one chip and the second redistribution layer; and

[0023] The semiconductor packaging device further includes:

[0024] a third package body, covering the second redistribution layer and the at least one chip;

[0025] The fourth package body covers the substrate, the adhesive layer, the first redistribution layer and the third package body.

[0026] In some optional implementations, the third package body and the fourth package body are made of the same packaging material.

[0027] In some optional embodiments, the at least one chip is electrically connected to the second redistribution layer via solder balls, an underfill is filled between the bottom of the at least one chip and the second redistribution layer, and the semiconductor package device further comprises:

[0028] The fifth package covers the substrate, the adhesive layer, the first redistribution layer, the second redistribution layer and the at least one chip.

[0029] In some optional embodiments, the line in the first redistribution layer that is closest to the second redistribution layer is a communication line, or the line in the second redistribution layer that is closest to the first redistribution layer is a communication line.

[0030] In a second aspect, the present disclosure provides a method for manufacturing a semiconductor package device, the method comprising:

[0031] providing a substrate and a first redistribution layer;

[0032] bonding the first redistribution layer to the substrate via the adhesive layer;

[0033] Drilling a hole on the surface of the first redistribution layer, penetrating the first redistribution layer and the adhesive layer and extending to the substrate to form a through hole;

[0034] Performing electroplating and conducting in the formed through-holes, so that the first redistribution layer is electrically connected to the substrate through the at least one through-hole;

[0035] providing at least one chip and a carrier;

[0036] bonding the at least one chip to a carrier;

[0037] Plastic encapsulation to form a first package, wherein the at least one chip is encapsulated;

[0038] After removing the carrier, grinding the upper and lower surfaces of the first package body so that the electrical connectors of each chip are exposed from the first package body, and the active surfaces of each chip are close to the same surface of the first package body;

[0039] forming a second redistribution layer on the surface of the active surface of each of the chips of the first package, so that each of the chips is electrically connected to the second redistribution layer;

[0040] Mounting the second redistribution layer on the first redistribution layer, and electrically connecting the second redistribution layer to the first redistribution layer;

[0041] Filling the bottom filling glue between the bottom of the second redistribution layer and the first redistribution layer;

[0042] The second package is formed by plastic packaging, wherein the second package covers the substrate, the adhesive layer, the first redistribution layer, the second redistribution layer and the first package.

[0043] In some optional embodiments, attaching the second redistribution layer to the first redistribution layer includes:

[0044] The second redistribution layer is flip-chip soldered to the first redistribution layer, or the second redistribution layer is hot-pressed soldered to the first redistribution layer.

[0045] In a third aspect, the present disclosure provides a method for manufacturing a semiconductor package device, the method comprising:

[0046] providing a substrate and a first redistribution layer;

[0047] bonding the first redistribution layer to the substrate via the adhesive layer;

[0048] Drilling a hole on the surface of the first redistribution layer, penetrating the first redistribution layer and the adhesive layer and extending to the substrate to form a through hole;

[0049] Performing electroplating and conducting in the formed through-holes, so that the first redistribution layer is electrically connected to the substrate through the at least one through-hole;

[0050] Providing a second redistribution layer and at least one chip, wherein the second redistribution layer has a first surface and a second surface opposite to the first surface;

[0051] Mounting the at least one chip on the first surface of the second redistribution layer and electrically connecting the second redistribution layer;

[0052] Filling bottom filling glue between the bottom of the at least one chip and the second redistribution layer;

[0053] Plastic encapsulation is performed to form a third package body, wherein the third package body covers the at least one chip and the second redistribution layer but does not cover the second surface of the second redistribution layer;

[0054] Mounting the third package onto the first redistribution layer and electrically connecting the second redistribution layer to the first redistribution layer;

[0055] Filling the space between the bottom of the third package and the first redistribution layer with bottom filling glue;

[0056] The fourth package is formed by plastic packaging, wherein the fourth package covers the substrate, the adhesive layer, the first redistribution layer and the third package.

[0057] In some optional embodiments, the step of attaching the at least one chip to the first surface of the second redistribution layer and electrically connecting the at least one chip to the second redistribution layer includes:

[0058] The at least one chip is flip-chip soldered to the first surface of the second redistribution layer and electrically connected to the second redistribution layer, or the at least one chip is hot-pressed soldered to the first surface of the second redistribution layer and electrically connected to the second redistribution layer.

[0059] In some optional embodiments, mounting the third package body on the first redistribution layer and electrically connecting the second redistribution layer to the first redistribution layer includes:

[0060] The third package is flip-chip soldered to the first redistribution layer and the second redistribution layer is electrically connected to the first redistribution layer, or the third package is hot-pressed soldered to the first redistribution layer and the second redistribution layer is electrically connected to the first redistribution layer.

[0061] In a fourth aspect, the present disclosure provides another method for manufacturing a semiconductor package device, the method comprising:

[0062] providing a substrate and a first redistribution layer;

[0063] bonding the first redistribution layer to the substrate via the adhesive layer;

[0064] Drilling a hole on the surface of the first redistribution layer, penetrating the first redistribution layer and the adhesive layer and extending to the substrate to form a through hole;

[0065] Performing electroplating and conducting in the formed through-holes, so that the first redistribution layer is electrically connected to the substrate through the at least one through-hole;

[0066] providing a second redistribution layer and at least one chip;

[0067] Mounting the second redistribution layer on the first redistribution layer and electrically connecting the second redistribution layer to the first redistribution layer;

[0068] Filling the bottom filling glue between the bottom of the second redistribution layer and the first redistribution layer;

[0069] Mounting the at least one chip on the second redistribution layer and electrically connecting the chip to the second redistribution layer;

[0070] Filling bottom filling glue between the bottom of the at least one chip and the second redistribution layer;

[0071] The fifth package is formed by plastic packaging, wherein the fifth package covers the substrate, the adhesive layer, the first redistribution layer, the second redistribution layer and the at least one chip.

[0072] In some optional embodiments, attaching the second redistribution layer to the first redistribution layer and electrically connecting the second redistribution layer to the first redistribution layer includes:

[0073] The second redistribution layer is flip-chip soldered to the first redistribution layer and electrically connected to the first redistribution layer, or the second redistribution layer is hot-pressed soldered to the first redistribution layer and electrically connected to the first redistribution layer.

[0074] In some optional embodiments, the step of attaching the at least one chip to the second redistribution layer and electrically connecting the chip to the second redistribution layer includes:

[0075] The at least one chip is flip-chip soldered to the second redistribution layer and electrically connected to the second redistribution layer, or the at least one chip is hot-pressed soldered to the second redistribution layer and electrically connected to the second redistribution layer.

[0076] The semiconductor packaging device and manufacturing method provided by the present disclosure divides the redistribution layer originally formed on the wafer side or the substrate side into two parts, one part formed on the substrate side and the other part formed on the wafer side, that is, divides the work into two lines. As a result, the semiconductor packaging device can achieve technical effects including but not limited to the following:

[0077] First, by forming redistribution layers on the substrate and chip ends respectively, the connection between the 5 to 7 nanometer process chip and the substrate is achieved.

[0078] Second, by using a redistribution layer, the process cost is reduced compared to 2.5D and 3D packaging.

[0079] Third, by forming the redistribution layer on the substrate side and the chip side respectively, the overall yield can be improved compared to forming the redistribution layer only on a single side of the substrate or only on a single side of the wafer. BRIEF DESCRIPTION OF THE DRAWINGS

[0080] Other features, objects and advantages of the present disclosure will become more apparent from a reading of the detailed description of non-limiting embodiments made with reference to the following drawings:

[0081] Figure 1A is a schematic structural diagram of an embodiment of a semiconductor packaging device according to the present disclosure;

[0082] Figure 1B is a schematic structural diagram of another embodiment of a semiconductor packaging device according to the present disclosure;

[0083] Figure 1C is a schematic structural diagram of another embodiment of a semiconductor packaging device according to the present disclosure;

[0084] Figure 1D is a schematic structural diagram of another embodiment of a semiconductor packaging device according to the present disclosure;

[0085] Figure 1E is a schematic structural diagram of another embodiment of a semiconductor packaging device according to the present disclosure;

[0086] Figure 2A-2J are cross-sectional views of semiconductor package devices 2a, 2b, 2c, 2d, 2e, 2f, 2g, 2h, 2i, and 2j at various stages of fabrication according to one embodiment of the present disclosure;

[0087] Figure 3A-3G are cross-sectional views of semiconductor package devices 3a, 3b, 3c, 3d, 3e, 3f, and 3g manufactured at various stages of fabrication according to yet another embodiment of the present disclosure;

[0088] Figures 4A-4E are cross-sectional views of semiconductor package devices 4 a , 4 b , 4 c , 4 d , and 4 e manufactured at various stages of fabrication according to yet another embodiment of the present disclosure.

[0089] Explanation of symbols:

[0090] 11 substrate 18 bottom filler

[0091] 12 Adhesive layer 19 First package

[0092] 13 first redistribution layer 20 second package body

[0093] 14 Second redistribution layer 21 Third package body

[0094] 14a first surface 22 fourth package body

[0095] 14b Second surface 23 Solder balls

[0096] 15 Chip 24 Underfill

[0097] 16 through hole 25 fifth package

[0098] 17 solder balls 26 carriers DETAILED DESCRIPTION

[0099] The following describes the specific embodiments of the present invention in conjunction with the accompanying drawings and examples. Those skilled in the art will readily understand the technical problems solved by the present invention and the technical effects produced by the present invention through the contents of this specification. It should be understood that the specific embodiments described herein are merely for the purpose of explaining the relevant invention and are not intended to limit the invention. Furthermore, for ease of description, only portions relevant to the relevant invention are shown in the accompanying drawings.

[0100] It should be noted that the structures, proportions, sizes, etc. illustrated in the drawings of the specification are only used to match the contents recorded in the specification for the understanding and reading of those skilled in the art, and are not used to limit the limiting conditions for the implementation of the present invention. Therefore, they have no substantial technical significance. Any modification of the structure, change in the proportional relationship or adjustment of the size should still fall within the scope of the technical content disclosed by the present invention without affecting the efficacy and purpose that can be achieved by the present invention. At the same time, terms such as "on", "first", "second" and "one" quoted in this specification are only for the convenience of description and are not used to limit the scope of the implementation of the present invention. Changes or adjustments in their relative relationships should also be regarded as the scope of the implementation of the present invention without substantially changing the technical content.

[0101] In addition, the embodiments and features of the embodiments of the present disclosure may be combined with each other without conflict. The present disclosure will be described in detail below with reference to the accompanying drawings and in conjunction with the embodiments.

[0102] refer to Figure 1A , Figure 1A FIG2 shows a cross-sectional view of a semiconductor package device 1 a according to an embodiment of the present disclosure. The semiconductor package device 1 a may include a substrate 11 , an adhesive layer 12 , a first redistribution layer 13 , a second redistribution layer 14 , at least one chip 15 , and at least one through-via 16 .

[0103] The substrate 11 may be, for example, a PCB (Printed Circuit Board), such as a paper-based copper foil laminate, a composite copper foil laminate, or a polymer-impregnated fiberglass-based copper foil laminate. The substrate 11 may also be provided with at least one of the following: a through hole, a buried via, a blind via, and a conductive trace.

[0104] The adhesive layer 12 is disposed on the substrate 11. The adhesive layer 12 may include an adhesive or an adhesive material (eg, an adhesive polymer material).

[0105] The first redistribution layer 13 is disposed on the adhesive layer 12 .

[0106] The second redistribution layer 14 is disposed on the first redistribution layer 13 and electrically connected to the first redistribution layer 13 .

[0107] The chip 15 is disposed on the second redistribution layer 14 and is electrically connected to the second redistribution layer 14. The chip 15 can be any type of bare chip (i.e., die). For example, it can include a logic chip, a memory chip, a micro-electro-mechanical system (MEMS) chip, a radio frequency chip, etc.

[0108] The through-hole 16 penetrates the first redistribution layer 13 and the adhesive layer 12 and extends to the substrate 11. The first redistribution layer 13 is electrically connected to the substrate 11 through at least one through-hole 16. The through-hole 16 can be filled with a conductive material, for example, copper, gold, indium, tin, silver, palladium, osmium, iridium, ruthenium, titanium, magnesium, aluminum, cobalt, nickel or zinc, other metals, metal alloys, or a combination of two or more thereof.

[0109] In some optional embodiments, the line width and line spacing of the first redistribution layer 13 and the second redistribution layer 14 are between 0.5 microns and 10 microns, and the line width and line spacing of the substrate 11 are greater than 10 microns.

[0110] In some optional embodiments, the line width and line spacing of the first redistribution layer 13 and the second redistribution layer 14 are between 0.5 microns and 2 microns.

[0111] Continue to refer Figure 1B , Figure 1B The semiconductor package device 1b shown in FIG. 1 is similar to Figure 1A The semiconductor package device 1a shown in the figure is different in that the second redistribution layer 14 is electrically connected to the first redistribution layer 13 through a solder ball 23, and an underfill 18 is filled between the bottom of the second redistribution layer 14 and the first redistribution layer 13.

[0112] Continue to refer Figure 1C , Figure 1C The semiconductor package device 1c shown in FIG. 1 is similar to Figure 1A The semiconductor package device 1a shown in FIG. Figure 1BThe semiconductor package device 1c shown in FIG. 1 is different in that the chip 15 is electrically connected to the second redistribution layer 14 via a wire, and the semiconductor package device 1c further includes a first package body 19 encapsulating at least one chip 15. The second package body 20 encapsulates the substrate 11, the adhesive layer 12, the first redistribution layer 13, the second redistribution layer 14, and the first package body 19. Here, the first package body 19 and the second package body 20 can use the same packaging material or different packaging materials. In some embodiments, the first package body 19 and the second package body 20 can be a black adhesive with high viscosity and high temperature cycle durability or include the above-mentioned black adhesive; in other embodiments, the first package body 19 and the second package body 20 can be different materials or can include different materials. For example, the first package body 19 and the second package body 20 can include a filler, an encapsulation material (such as an epoxy encapsulation material or other encapsulation material), polyimide, a phenolic compound or material, a material including silicone dispersed therein, or a combination thereof.

[0113] Continue to refer Figure 1D , Figure 1D The semiconductor package device 1d shown in FIG. 1 is similar to Figure 1A The semiconductor package device 1a shown in FIG. Figure 1B The semiconductor package device 1d shown in the figure is different in that: at least one chip 15 is electrically connected to the second redistribution layer 14 through a solder ball, and an underfill is filled between the bottom of the at least one chip 15 and the second redistribution layer 14. The semiconductor package device 1d also includes: a third package body 21 and a fourth package body 22. The third package body 21 covers the second redistribution layer 14 and the at least one chip 15, and the fourth package body 22 covers the substrate 11, the adhesive layer 12, the first redistribution layer 13 and the third package body 21. Here, the third package body 21 and the fourth package body 22 can use the same packaging material or different packaging materials. In some embodiments, the third package body 21 and the fourth package body 22 can be a black adhesive with high viscosity and high temperature cycle durability or contain the above-mentioned black adhesive; in other embodiments, the third package body 21 and the fourth package body 22 can be different materials or can contain different materials. For example, the third package body 21 and the fourth package body 22 may include a filler, an encapsulation material (eg, epoxy encapsulation material or other encapsulation material), polyimide, a phenolic compound or material, a material including silicone dispersed therein, or a combination thereof.

[0114] Continue to refer Figure 1E , Figure 1E The semiconductor package device 1e shown in FIG. 1 is similar to Figure 1A The semiconductor package device 1a shown in FIG. Figure 1BThe semiconductor packaging device 1e shown in the figure is different in that: at least one chip 15 is electrically connected to the second redistribution layer 14 through a solder ball 23, a bottom filling glue 24 is filled between the bottom of at least one chip 15 and the second redistribution layer 14, and the semiconductor packaging device 1e also includes: a fifth package body 25, the fifth package body 25 covers the substrate 11, the adhesive layer 12, the first redistribution layer 13, the second redistribution layer 14 and the at least one chip 15.

[0115] In practice, in order to reduce crosstalk interference, at least one power layer or ground layer must be placed between the communication line layer (or signal layer) and the communication line layer. Normally, the formation of the redistribution layer at the chip end is performed by the wafer factory, while the formation of the redistribution layer at the substrate end is performed by the substrate factory. Therefore, the redistribution layer formed at the chip end often needs to be provided with a power layer, a communication line layer, and a ground layer in sequence to avoid crosstalk interference. Similarly, the redistribution layer formed at the substrate end often needs to be provided with a power layer, a communication line layer, and a ground layer in sequence to avoid crosstalk interference. Here, in order to reduce the thickness of the semiconductor packaging device, in some embodiments, for example Figure 1A-1E In the illustrated semiconductor package devices 1a-1e, the lines in the first redistribution layer 13 closest to the second redistribution layer 14 are communication lines, or the lines in the second redistribution layer 14 closest to the first redistribution layer 13 are communication lines. As an example, the first redistribution layer 13 sequentially provides a ground layer and a communication line layer for chip 15 from chip 15 to the second redistribution layer 14, while the second redistribution layer 14 sequentially provides a ground layer, a communication line layer, and a power layer for the substrate from substrate 11 to the first redistribution layer 13. Alternatively, as an example, the first redistribution layer 13 sequentially provides a ground layer, a communication line layer, and a power layer for chip 15 from chip 15 to the second redistribution layer 14, while the second redistribution layer 14 sequentially provides a ground layer and a communication line layer for the substrate from substrate 11 to the first redistribution layer 13. In other words, the original six layers of lines required—the ground layer for chip 15 and substrate 11, the communication line layer, and the power layer—are reduced to five, thereby reducing the thickness of the semiconductor package device.

[0116] Figure 2A 、 Figure 2B 、 Figure 2C 、 Figure 2D 、 Figure 2E 、 Figure 2F 、 Figure 2G 、 Figure 2H 、 Figure 2I and Figure 2J According to some embodiments of the present disclosure (e.g., Figure 1CThe semiconductor package device 1c) is shown as a cross-sectional view of semiconductor package devices 2a, 2b, 2c, 2d, 2e, 2f, 2g, 2h, 2i and 2j at various stages of manufacture. The figures have been simplified to better understand various aspects of the present invention.

[0117] The first step is to provide a substrate and a first redistribution layer.

[0118] like Figure 2A As shown, a substrate 11 and a first redistribution layer 13 are provided.

[0119] In the second step, the first redistribution layer is bonded to the substrate through the adhesive layer.

[0120] like Figure 2B As shown, the first redistribution layer 13 is bonded to the substrate 11 via the adhesive layer 12 .

[0121] In the third step, a hole is drilled on the surface of the first redistribution layer, penetrating the first redistribution layer and the adhesive layer and extending to the substrate to form a through hole. For example, laser drilling or mechanical drilling can be used.

[0122] In the fourth step, electroplating and conducting are performed in the formed through-holes, so that the first redistribution layer is electrically connected to the substrate through at least one through-hole.

[0123] like Figure 2C As shown, a hole is drilled on the surface of the first redistribution layer 13, penetrates the first redistribution layer 13 and the adhesive layer 12, and extends to the substrate 11, forming a through hole 16. Then, electroplating and conduction are performed in the formed through hole 16, and then the through hole 16 is filled with a conductive material (for example, copper, or another metal, or a combination of metals), so that the first redistribution layer 13 is electrically connected to the substrate 11 through the through hole 16.

[0124] The fifth step is to provide at least one chip and a carrier, and to bond the at least one chip to the carrier.

[0125] Here, the carrier may comprise glass or other materials.

[0126] like Figure 2D At least one chip 15 is bonded to a carrier 26 .

[0127] The sixth step is to perform plastic packaging to form a first package body, wherein the first package body covers at least one chip.

[0128] For example, the encapsulation may be performed by compression molding, injection molding, or transfer molding. The encapsulation material used for the encapsulation may include a filler, an encapsulation material (such as an epoxy encapsulation material or other encapsulation material), polyimide, a phenolic compound or material, a material containing silicone dispersed therein, or a combination thereof.

[0129] like Figure 2E As shown, the first package 19 is formed by molding, and the first package 19 covers each chip 15 .

[0130] In the seventh step, after removing the carrier, the upper and lower surfaces of the first package body are ground so that the electrical connectors of each chip are exposed from the first package body and the active surfaces of each chip are close to the same surface of the first package body.

[0131] For example, the carrier may be removed by a thermal process, a sawing operation, laser irradiation, or other suitable process.

[0132] like Figure 2F As shown, after removing the carrier 26 , the upper and lower surfaces of the first package body 19 are ground so that the electrical connectors of each chip 15 are exposed from the first package body 19 , and the active surfaces of each chip 15 are close to the same surface of the first package body 19 .

[0133] In the eighth step, a second redistribution layer is formed on the surface of the active surface of each chip of the first package body, so that each chip is electrically connected to the second redistribution layer.

[0134] For example, a layer of photosensitive insulating material can be first coated on the active surface of each chip in the first package. Then, a photolithography machine can be used to expose and develop the photosensitive insulating material. Then, metal (e.g., copper) can be electroplated. Finally, the photoresist can be stripped and etched to obtain the first layer of circuits. Repeating these steps can obtain multiple layers of the second redistribution layer.

[0135] like Figure 2G As shown, a second redistribution layer 14 is formed on the surface of the first package body 19 where the active surface of each chip 15 is located, so that each chip 15 is electrically connected to the second redistribution layer 14 .

[0136] In the ninth step, the second redistribution layer is mounted on the first redistribution layer, and the second redistribution layer is electrically connected to the first redistribution layer.

[0137] For example, the second redistribution layer may be flip chip bonded (FCB) to the first redistribution layer, or the second redistribution layer may be thermally compressed (FCB) to the first redistribution layer.

[0138] like Figure 2H As shown, the second redistribution layer 14 is attached to the first redistribution layer 13 , and the second redistribution layer 14 is electrically connected to the first redistribution layer 13 .

[0139] In the tenth step, bottom filling glue is filled between the bottom of the second redistribution layer and the first redistribution layer.

[0140] For example, the bottom filling glue can be filled between the bottom of the second redistribution layer and the first redistribution layer through the dispensing process, so that the bottom filling glue can protect the solder balls between the second redistribution layer and the first redistribution layer, thereby enhancing the strength of the bottom welding area of ​​the second redistribution layer.

[0141] like Figure 2I As shown, an underfill 18 is filled between the bottom of the second redistribution layer 14 and the first redistribution layer 13 .

[0142] The eleventh step is to perform plastic encapsulation to form a second package body, wherein the second package body covers the substrate, the adhesive layer, the first redistribution layer, the second redistribution layer and the first package body.

[0143] like Figure 2J As shown, the second package body 20 is formed by plastic encapsulation. The second package body 20 covers the substrate 11, the adhesive layer 12, the first redistribution layer 13, the second redistribution layer 14 and the first package body 19.

[0144] The above process requires two mounting steps and two plastic encapsulation steps to form a semiconductor package device.

[0145] In yet another optional embodiment, in order to manufacture a semiconductor package device (eg, Figure 1D The semiconductor packaging device 1d) shown can be carried out as follows:

[0146] The first step is to provide a substrate and a first redistribution layer.

[0147] In the second step, the first redistribution layer is bonded to the substrate through the adhesive layer.

[0148] In the third step, a hole is drilled on the surface of the first redistribution layer, penetrating the first redistribution layer and the adhesive layer and extending to the substrate to form a through hole.

[0149] In the fourth step, electroplating and conducting are performed in the formed through-holes, so that the first redistribution layer is electrically connected to the substrate through at least one through-hole.

[0150] Here, the specific operations from the first step to the fourth step and the technical effects produced are basically the same as those from the first step to the fourth step in the above embodiment, and can be referred to Figure 2A 、 Figure 2B 、 Figure 2C and Figure 2D The relevant description will not be repeated here.

[0151] Figure 3A 、 Figure 3B 、 Figure 3C 、 Figure 3D 、 Figure 3E 、 Figure 3F and Figure 3G According to some embodiments of the present disclosure (e.g., Figure 1D The semiconductor package device 1d) is shown as a cross-sectional view of semiconductor package devices 3a, 3b, 3c, 3d, 3e, 3f and 3g manufactured in the fifth step and thereafter. The figures have been simplified for a better understanding of various aspects of the present invention.

[0152] The fifth step is to provide a second redistribution layer and at least one chip, wherein the second redistribution layer has a first surface and a second surface opposite to the first surface.

[0153] The at least one chip may include various types of bare chips (ie, dies), such as logic chips, memory chips, micro-electro-mechanical system (MEMS) chips, radio frequency chips, and the like.

[0154] Here, the second redistribution layer may be a prefabricated redistribution layer.

[0155] like Figure 3A As shown, a second redistribution layer 14 and at least one chip 15 are provided.

[0156] In a sixth step, at least one chip is mounted on the first surface of the second redistribution layer and electrically connected to the second redistribution layer.

[0157] For example, at least one chip may be flip-chip soldered to the first surface of the second redistribution layer and electrically connected to the second redistribution layer, or at least one chip may be thermocompression soldered to the first surface of the second redistribution layer and electrically connected to the second redistribution layer.

[0158] like Figure 3B As shown, at least one chip 15 is mounted on the first surface 14 a of the second redistribution layer 14 and electrically connected to the second redistribution layer 14 .

[0159] Step 7: Filling the bottom filling glue between the bottom of at least one chip and the second redistribution layer.

[0160] For example, the bottom filling glue can be filled between the bottom of at least one chip and the second redistribution layer through a dispensing process, so that the bottom filling glue can protect the solder balls between the bottom of at least one chip and the second redistribution layer, thereby enhancing the strength of the welding area at the bottom of at least one chip.

[0161] like Figure 3C As shown, an underfill 24 is filled between the bottom of at least one chip 15 and the second redistribution layer 14 .

[0162] In the eighth step, plastic packaging is performed to form a third package body, where the third package body covers at least one chip and the second redistribution layer but does not cover the second surface of the second redistribution layer.

[0163] like Figure 3D As shown, the third package body 21 is formed by plastic encapsulation. The third package body 21 covers the at least one chip 15 and the second redistribution layer 14 but does not cover the second surface 14 b of the second redistribution layer 14 .

[0164] In the ninth step, the third package is mounted on the first redistribution layer, and the second redistribution layer is electrically connected to the first redistribution layer.

[0165] For example, the third package may be flip-chip soldered to the first redistribution layer and the second redistribution layer may be electrically connected to the first redistribution layer. Alternatively, the third package may be thermocompression soldered to the first redistribution layer and the second redistribution layer may be electrically connected to the first redistribution layer.

[0166] like Figure 3E As shown, the surface where the second redistribution layer 14 of the third package body 21 is located is mounted to the first redistribution layer 13 , and the second redistribution layer 14 is electrically connected to the first redistribution layer 13 .

[0167] In the tenth step, bottom filling glue is filled between the bottom of the third package body and the first redistribution layer.

[0168] For example, the bottom filling glue can be filled between the bottom of the third package body and the first redistribution layer through the dispensing process, so that the bottom filling glue can protect the solder balls between the second redistribution layer and the first redistribution layer, thereby enhancing the strength of the bottom welding area of ​​the second redistribution layer.

[0169] like Figure 3F As shown, an underfill 18 is filled between the bottom of the third package body 21 and the first redistribution layer 13 .

[0170] In the eleventh step, plastic packaging is performed to form a fourth package body, wherein the fourth package body covers the substrate, the adhesive layer, the first redistribution layer and the third package body.

[0171] like Figure 3G As shown, the fourth package body 22 is formed by plastic packaging, and the fourth package body 22 covers the substrate 11 , the adhesive layer 12 , the first redistribution layer 13 and the third package body 21 .

[0172] The above process requires two mounting steps and two plastic encapsulation steps to form a semiconductor package device.

[0173] In yet another optional embodiment, in order to manufacture a semiconductor package device (eg, Figure 1E The semiconductor packaging device 1e) shown can be carried out as follows:

[0174] The first step is to provide a substrate and a first redistribution layer.

[0175] In the second step, the first redistribution layer is bonded to the substrate through the adhesive layer.

[0176] In the third step, a hole is drilled on the surface of the first redistribution layer, penetrating the first redistribution layer and the adhesive layer and extending to the substrate to form a through hole.

[0177] In the fourth step, electroplating and conducting are performed in the formed through-holes, so that the first redistribution layer is electrically connected to the substrate through at least one through-hole.

[0178] The fifth step is to provide a second redistribution layer and at least one chip.

[0179] Here, the specific operations of the first to fifth steps and the technical effects produced are basically the same as the first to fourth steps in the above embodiment, and can be referred to Figure 2A 、 Figure 2B 、 Figure 2C 、 Figure 2D and Figure 3A The relevant description will not be repeated here.

[0180] Figure 4A 、 Figure 4B 、 Figure 4C 、 Figure 4D and Figure 4E 1e ) are cross-sectional views of semiconductor package devices 4a, 4b, 4c, 4d, and 4e manufactured in the sixth and subsequent steps according to some embodiments of the present disclosure (eg, the semiconductor package device 1e shown in FIG. 1e ). The figures have been simplified for better understanding of various aspects of the present invention.

[0181] In the sixth step, the second redistribution layer is mounted on the first redistribution layer and electrically connected to the first redistribution layer.

[0182] For example, the second redistribution layer may be flip-chip bonded to the first redistribution layer and electrically connected to the first redistribution layer, or the second redistribution layer may be thermocompression bonded to the first redistribution layer and electrically connected to the first redistribution layer.

[0183] like Figure 4A As shown, the second redistribution layer 14 is attached to the first redistribution layer 13 and electrically connected to the first redistribution layer 13 .

[0184] Step 7: Fill the bottom filling glue between the bottom of the second redistribution layer and the first redistribution layer.

[0185] For example, the bottom filling glue can be filled between the bottom of the second redistribution layer and the first redistribution layer through the dispensing process, so that the bottom filling glue can protect the solder balls between the second redistribution layer and the first redistribution layer, thereby enhancing the strength of the bottom welding area of ​​the second redistribution layer.

[0186] like Figure 4B As shown, an underfill 18 is filled between the bottom of the second redistribution layer 14 and the first redistribution layer 13 .

[0187] In the eighth step, at least one chip is mounted on the second redistribution layer and electrically connected to the second redistribution layer.

[0188] For example, at least one chip may be flip-chip soldered to the second redistribution layer and electrically connected to the second redistribution layer, or at least one chip may be thermocompression soldered to the second redistribution layer and electrically connected to the second redistribution layer. Figure 4C As shown, at least one chip 15 is attached to the second redistribution layer 14 and electrically connected to the second redistribution layer 14 .

[0189] like Figure 4C As shown, at least one chip 15 is attached to the second redistribution layer 14 and electrically connected to the second redistribution layer 14 .

[0190] In the ninth step, an underfill glue is filled between the bottom of at least one chip and the second redistribution layer.

[0191] For example, the bottom filling glue can be filled between the bottom of at least one chip and the second redistribution layer through a dispensing process, so that the bottom filling glue can protect the solder balls between the bottom of at least one chip and the second redistribution layer, thereby enhancing the strength of the welding area at the bottom of at least one chip.

[0192] like Figure 4D As shown, an underfill 24 is filled between the bottom of at least one chip 15 and the second redistribution layer 14 .

[0193] The tenth step is to perform plastic packaging to form a fifth package body, wherein the fifth package body covers the substrate, the adhesive layer, the first redistribution layer, the second redistribution layer and at least one chip.

[0194] like Figure 4E As shown, the fifth package 25 is formed by plastic encapsulation. The fifth package 25 covers the substrate 11, the adhesive layer 12, the first redistribution layer 13, the second redistribution layer 14 and at least one chip 15.

[0195] The above process requires two mounting steps and one plastic encapsulation step to form a semiconductor package device.

[0196] Although the present disclosure has been described and illustrated with reference to specific embodiments of the present disclosure, these descriptions and illustrations do not limit the present disclosure. It will be clearly understood by those skilled in the art that various changes may be made and that equivalent elements may be substituted within the embodiments without departing from the true spirit and scope of the present disclosure as defined by the appended claims. The illustrations may not necessarily be drawn to scale. Due to variables in the manufacturing process, etc., there may be differences between the artistic reproduction in the present disclosure and the actual device. There may be other embodiments of the present disclosure that are not specifically described. The description and drawings should be regarded as illustrative, not restrictive. Modifications may be made to adapt specific circumstances, materials, compositions of matter, methods or processes to the objectives, spirit and scope of the present disclosure. All such modifications are intended to fall within the scope of the claims appended hereto. Although the methods disclosed herein have been described with reference to specific operations performed in a specific order, it should be understood that these operations may be combined, subdivided or reordered to form equivalent methods without departing from the teachings of the present disclosure. Therefore, unless specifically indicated herein, the order and grouping of operations do not limit the present disclosure.

Claims

1. A method for manufacturing a semiconductor package device, comprising: Providing a substrate and a first redistribution layer, wherein the line width and line spacing of the substrate are greater than 10 microns; bonding the first redistribution layer to the substrate via the adhesive layer; Drilling a hole on the surface of the first redistribution layer, penetrating the first redistribution layer and the adhesive layer and extending to the substrate to form a through hole; Performing electroplating and conducting in the formed through-holes, so that the first redistribution layer is electrically connected to the substrate through at least one of the through-holes; Providing at least one chip and a carrier, wherein at least one chip is a chip with a 5-nanometer to 7-nanometer process; bonding the at least one chip to a carrier; Plastic encapsulation to form a first package body, wherein the first package body covers the at least one chip; After removing the carrier, grinding the upper and lower surfaces of the first package body so that the electrical connectors of each chip are exposed from the first package body, and the active surfaces of each chip are close to the same surface of the first package body; forming a second redistribution layer on the surface of the active surface of each chip of the first package, so that each chip is electrically connected to the second redistribution layer, wherein the line width and line spacing of the first redistribution layer and the second redistribution layer are between 0.5 microns and 10 microns; Mounting the second redistribution layer on the first redistribution layer, wherein the second redistribution layer is electrically connected to the first redistribution layer; Filling bottom filling glue between the bottom of the second redistribution layer and the first redistribution layer; The second package is formed by plastic encapsulation, wherein the second package covers the substrate, the adhesive layer, the first redistribution layer, the second redistribution layer and the first package.

2. A method for manufacturing a semiconductor package device, comprising: providing a substrate and a first redistribution layer; bonding the first redistribution layer to the substrate via the adhesive layer; Drilling a hole on the surface of the first redistribution layer, penetrating the first redistribution layer and the adhesive layer and extending to the substrate to form a through hole, wherein the through hole tapers toward the substrate; Performing electroplating and conducting in the formed through-holes, so that the first redistribution layer is electrically connected to the substrate through at least one of the through-holes; Providing a second redistribution layer and at least one chip, wherein the second redistribution layer has a first surface and a second surface opposite to the first surface; Attaching the at least one chip to the first surface of the second redistribution layer and electrically connecting the second redistribution layer; Filling an underfill between the bottom of the at least one chip and the second redistribution layer; Plastic encapsulation is performed to form a third package body, wherein the third package body covers the at least one chip and the second redistribution layer but does not cover the second surface of the second redistribution layer; Mounting the third package onto the first redistribution layer and electrically connecting the second redistribution layer to the first redistribution layer; Filling bottom filling glue between the bottom of the third package body and the first redistribution layer; The fourth package body is formed by plastic encapsulation, wherein the fourth package body covers the substrate, the adhesive layer, the first redistribution layer and the third package body.

3. A method for manufacturing a semiconductor package device, comprising: providing a substrate and a first redistribution layer; bonding the first redistribution layer to the substrate via the adhesive layer; Drilling a hole on the surface of the first redistribution layer, penetrating the first redistribution layer and the adhesive layer and extending to the substrate to form a through hole; Performing electroplating and conducting in the formed through-holes, so that the first redistribution layer is electrically connected to the substrate through at least one of the through-holes; providing a second redistribution layer and at least one chip; Mounting the second redistribution layer on the first redistribution layer and electrically connecting the first redistribution layer; Filling bottom filling glue between the bottom of the second redistribution layer and the first redistribution layer; attaching the at least one chip to the second redistribution layer and electrically connecting the chip to the second redistribution layer; Filling an underfill between the bottom of the at least one chip and the second redistribution layer; The fifth package is formed by plastic packaging, wherein the fifth package covers the substrate, the adhesive layer, the first redistribution layer, the second redistribution layer and the at least one chip.

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