Analog-to-digital converter

Abstract

The present invention discloses an analog-to-digital converter, comprising: a first switched capacitor array, for receiving an input signal and sampling the input signal to generate a first sampled signal; a second switched capacitor array, for sampling the input signal to generate a second sampled signal and generate a first quantization error; a third switched capacitor array, for sampling the input signal to generate a third sampled signal and generate a second quantization error; an integrator, coupled to the second switched capacitor array and the third switched capacitor array, for receiving and integrating the first quantization error and the second quantization error in a time-interleaved manner to generate an integrated quantization error; and a quantizer, coupled to the first switched capacitor array and the integrator, for quantizing the first sampled signal by using the integrated quantization error as a reference voltage to generate a digital output signal. The implementation of the present invention can improve the operating speed of the analog-to-digital converter.

Description

Technical Field

[0001] The present disclosure relates generally to the field of electronics, and more particularly to analog-to-digital converters. Background Art

[0002] In a noise shaping analog-to-digital converter (ADC), the ADC usually requires additional stages to sample and integrate the quantization error for the next cycle. For example, after the switched capacitor array samples the input signal and the quantizer quantizes the sampled input signal to generate a digital output signal, there is a quantization error on the switched capacitor array. Then, the additional buffer and integrator of the ADC samples and integrates the quantization error to generate the integrated quantization error for the next cycle of the quantizer. In the process of generating the integrated quantization error, the switched capacitor array and the quantizer will stop working to avoid affecting the operation of the integrator, but this will reduce the operating speed of the ADC. Summary of the invention

[0003] Therefore, an object of the present invention is to provide an ADC which uses two additional switched capacitor arrays to replicate quantization errors, and the two additional switched capacitor arrays are operated alternately to increase the operating speed of the ADC, thereby solving the above problems.

[0004] The present invention provides an ADC, comprising: a first switch capacitor array, for receiving an input signal and sampling the input signal to generate a first sampling signal; a second switch capacitor array, for sampling the input signal to generate a second sampling signal and generate a first quantization error; a third switch capacitor array, for sampling the input signal to generate a third sampling signal and generate a second quantization error; an integrator, coupled to the second switch capacitor array and the third switch capacitor array, for receiving and integrating the first quantization error and the second quantization error in a time-interleaved manner to generate an integrated quantization error; and a quantizer, coupled to the first switch capacitor array and the integrator, for quantizing the first sampling signal by using the integrated quantization error as a reference voltage to generate a digital output signal.

[0005] These and other objects of the present invention will no doubt become apparent to those skilled in the art after reading the following detailed description of the preferred embodiments as illustrated in the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figure 1 is a diagram showing an ADC according to an embodiment of the present invention.

[0007] Figure 2 A timing diagram of an ADC according to an embodiment of the present invention is shown.

[0008] Figure 3 is a diagram showing a switched capacitor array according to one embodiment of the present invention. DETAILED DESCRIPTION

[0009] Certain terms are used in the following description and claims to refer to specific system components. As will be appreciated by those skilled in the art, manufacturers may refer to the same component by different names. This document is not intended to distinguish between components that differ in name but function the same. In the following discussion and claims, the terms "include" and "comprising" are used in an open-ended manner and should be interpreted to mean "including, but not limited to...". The terms "coupled" and "coupled" are intended to mean an indirect or direct electrical connection. Thus, if a first device is coupled to a second device, the connection may be through a direct electrical connection, or through an indirect electrical connection via other devices and connections.

[0010] Figure 1 FIG. 1 is a diagram illustrating an ADC 100 according to an embodiment of the present invention. Figure 1 As shown, ADC 100 is a Successive-Approximation-Register (SAR) ADC, and ADC 100 includes a first switched capacitor array Cx, a second switched capacitor array Cy, a third switched capacitor array Cz, an integrator 110, a quantizer 120, a time interleaving control circuit 130, a control circuit 140, and a switch circuit. In this embodiment, the first switched capacitor array Cx includes a plurality of capacitors and switches (in this embodiment, there are four capacitors Cx1-Cx4), and one terminal of each capacitor is connected to a top plate, and the other terminal of each capacitor is connected to a positive reference voltage +Vref or a negative reference voltage –Vref through a corresponding switch. Integrator 110 may include an operational amplifier 112 and a feedback capacitor Cint. The switching circuit includes five switches SW1-SW5, wherein the switch SW1 is coupled between the input terminal Nin of the ADC 100 and the first switch capacitor array Cx, the switch SW2 is coupled between the input terminal Nin and the second switch capacitor array Cy, the switch SW3 is coupled between the input terminal Nin and the third switch capacitor array Cz, the switch SW4 is coupled between the second switch capacitor array Cy and the integrator 110, and the switch SW5 is coupled between the third switch capacitor array Cz and the integrator 110.

[0011] In this embodiment, the second switched capacitor array Cy and the third switched capacitor array Cz can be designed to have a structure similar to the first switched capacitor array Cx (but not intended to limit the present invention). For example, the second switched capacitor array Cy can also include four capacitors, one terminal of each capacitor is connected to the plate, and the other terminal of each capacitor is connected to the positive reference voltage +Vref or the negative reference voltage -Vref through a corresponding switch.

[0012] Figure 2 FIG. 1 shows a timing diagram of the ADC 100 according to an embodiment of the present invention. Figure 1 and Figure 2 Each cycle of ADC 100 includes a sampling phase and a quantization phase. In the first sampling phase of ADC 100 (i.e., Figure 2 ), the control circuit 140 generates a control signal Φ1 to enable the switch SW1 to allow the first switch capacitor array Cx to receive the input signal Vin, thereby generating a first sampling signal on the top plate, the control circuit 140 generates a control signal ΦA to enable the switch SW2 to allow the second switch capacitor array Cy to receive the input signal Vin to generate a second sampling signal, and the control circuit 140 generates a control signal ΦB to disable the switch SW3 to disconnect the third switch capacitor array Cz from the input terminal Nin, that is, the third switch capacitor array Cz does not receive the input signal Vin. In addition, during the time period T1, the control signal ΦA enables the switch SW5 to connect the third switch capacitor array Cz to the integrator 110, that is, the feedback capacitor Cint of the integrator 110 and the third switch capacitor array Cz have a charge-sharing operation, and the quantization error in the third switch capacitor array Cz is sent to the integrator 110, and the integrator 110 integrates the received quantization error to generate an integrated quantization error. In addition, the control signal ΦB disables the switch SW4 to disconnect the second switched capacitor array Cy from the integrator 110 .

[0013] In the first sampling phase (i.e., time period T1) of the ADC 100, the first switched capacitor array Cx and the second switched capacitor array Cy simultaneously sample the input signal Vin, and the integrator 110 integrates the quantization error from the third switched capacitor array Cz. In addition, in this time period, the time interleaving control circuit 130 does not generate any control signal to control the switches in the second switched capacitor array Cy and the third switched capacitor array Cz.

[0014] In the first quantization stage of ADC 100 (ie, Figure 2In the time period T2 shown in FIG. 1 ), all switches SW1-SW5 are disabled, that is, the first switch capacitor array Cx, the second switch capacitor array Cy and the third switch capacitor array Cz do not receive and sample the input signal Vin, and the integrator 110 does not receive the quantization error from the second switch capacitor array Cy and the third switch capacitor array Cz, that is, the integrator 110 provides a stable integrated quantization error to the quantizer 120. The control circuit 140 generates a control signal Φ SAR , so that the quantizer 120 performs SAR conversion to quantize the first sampled signal generated by the first switched capacitor array Cx by using the integrated quantization error to generate a digital output signal Dout. For example, the integrated quantization error output by the integrator 110 is used as a reference voltage, and the quantizer 120 compares the first sampled signal with the reference voltage (i.e., the integrated quantization error) to generate a digital output signal Dout. In this embodiment, the quantizer 120 sequentially generates four bits used as the digital output signal Dout. The digital output signal Dout is further used to control the switches of the first switched capacitor array Cx, and after the control switch connects the capacitors Cx1-Cx4 to the positive reference voltage +Vref or the negative reference voltage -Vref, the voltage on the top plate of the first switched capacitor array Cx can be considered as a quantization error. Note that because the use of the digital output signal Dout to control the switches within the first switched capacitor array Cx is known to those skilled in the art, the embodiments of the present invention do not focus on the control within the first switched capacitor array Cx, and a detailed description of the first switched capacitor array Cx is omitted here.

[0015] In the time period T2, the time interleaving control circuit 130 generates a control signal D1 to the second switch capacitor array Cy so that the second switch capacitor array Cy generates a first quantization error, wherein the first quantization error is a duplicate of the quantization error of the first switch capacitor array Cx. For example, if the second switch capacitor array Cy has the same structure as the first switch capacitor array Cx, the digital output signal Dout can be used as the control signal D1, that is, the switches of the second switch capacitor array Cy and the first switch capacitor array Cy are controlled by the same method. In addition, in this time period, the third switch capacitor array Cz does not work, and the time interleaving control circuit 130 does not generate any control signal to the third switch capacitor array Cz.

[0016] Because the first quantization error generated by the second switched capacitor array Cy is a repetition of the quantization error of the first switched capacitor array Cx in the time period T2, the first quantization error generated by the second switched capacitor array Cy can be sent to the integrator 110 for generating an integrated quantization error in the next cycle, and the integrator 110 does not need the quantization error of the first switched capacitor array Cx. Therefore, the first switched capacitor array Cx can immediately enter the next sampling phase without wasting time sending its quantization error to the integrator 110.

[0017] In the second sampling phase of ADC 100 (ie, Figure 2 ), the control circuit 140 generates a control signal Φ1 to enable the switch SW1 to allow the first switch capacitor array Cx to receive the input signal Vin to generate a first sampling signal on the top plate, the control circuit 140 generates a control signal ΦB to enable the switch SW3 to allow the third switch capacitor array Cz to receive the input signal Vin to generate a third sampling signal, and the control circuit 140 generates a control signal ΦA to disable the switch SW2 to disconnect the second switch capacitor array Cy from the input terminal Nin, that is, the second switch capacitor array Cy does not receive the input signal Vin. In addition, during the time period T3, the control signal ΦB enables the switch SW4 to connect the second switch capacitor array Cy to the integrator 110, that is, the feedback capacitor Cint of the integrator 110 and the second switch capacitor array Cy have a charge sharing operation, and the first quantization error in the second switch capacitor array Cy is sent to the integrator 110, and the integrator 110 integrates the received quantization error to generate an integrated quantization error.

[0018] In the second sampling phase of the ADC 100 (i.e., time period T3), the first switched capacitor array Cx and the third switched capacitor array Cz simultaneously sample the input signal Vin, and the integrator 110 integrates the quantization error from the second switched capacitor array Cy. In addition, in this time period, the time interleaving control circuit 130 does not generate any control signal to control the switches in the second switched capacitor array Cy and the third switched capacitor array Cz.

[0019] In the second quantization stage of ADC 100 (ie, Figure 2 In the time period T4 shown in FIG. 1 ), all switches SW1-SW5 are disabled, that is, the first switch capacitor array Cx, the second switch capacitor array Cy and the third switch capacitor array Cz do not receive and sample the input signal Vin, and the integrator 110 does not receive the quantization error from the second switch capacitor array Cy and the third switch capacitor array Cz, that is, the integrator 110 provides a stable integrated quantization error to the quantizer 120. The control circuit 140 generates a control signal Φ SAR, so that the quantizer 120 uses the integrated quantization error to quantize the first sampled signal generated by the first switched capacitor array Cx to generate a digital output signal Dout. For example, the integrated quantization error output by the integrator 110 is used as a reference voltage, and the quantizer 120 compares the first sampled signal with the reference voltage (i.e., the integrated quantization error) to generate a digital output signal Dout. In this embodiment, the quantizer 120 sequentially generates four bits used as the digital output signal Dout. The digital output signal Dout is further used to control the switches of the first switched capacitor array Cx, and after controlling the switches to connect the capacitors Cx1-Cx4 to the positive reference voltage +Vref or the negative reference voltage –Vref, the voltage on the top plate of the first switched capacitor array Cx can be considered as a quantization error.

[0020] In the time period T4, the time interleaving control circuit 130 generates a control signal D2 to the third switch capacitor array Cz so that the third switch capacitor array Cz generates a second quantization error, wherein the second quantization error is a repetition of the quantization error of the first switch capacitor array Cx. For example, if the third switch capacitor array Cz has the same structure as the first switch capacitor array Cx, the digital output signal Dout can be used as the control signal D2, that is, the switches of the third switch capacitor array Cz and the first switch capacitor array Cx are controlled by the same method. In addition, in this time period, the second switch capacitor array Cy does not work, and the time interleaving control circuit 130 does not generate any control signal to the second switch capacitor array Cy.

[0021] Because the second quantization error generated by the third switch capacitor array Cz in the time period T4 is a repetition of the quantization error of the first switch capacitor array Cx, the second quantization error generated by the third switch capacitor array Cz can be sent to the integrator 110 for generating an integrated quantization error in the next cycle, and the integrator 110 does not need the quantization error of the first switch capacitor array Cx. Therefore, the first switch capacitor array Cx can immediately enter the next sampling phase without wasting time sending its quantization error to the integrator 110.

[0022] The above operations of the first sampling phase, the first quantization phase, the second sampling phase, and the second quantization phase may be repeatedly performed in subsequent cycles. That is, the ADC 110 may sequentially operate in the third sampling phase (e.g., Figure 2 The time period T5 shown in the figure), the third quantization stage, the fourth sampling stage and the fourth quantization stage, and the operations of the third sampling stage, the third quantization stage, the fourth sampling stage and the fourth quantization stage are respectively the same as the operations of the first sampling stage, the first quantization stage, the second sampling stage and the second quantization stage.

[0023] Referring to the above description, since one of the second switched capacitor array Cy and the third switched capacitor array Cz is used to generate repeated quantization errors, the second switched capacitor array Cy and the third switched capacitor array Cz are controlled to alternately perform sampling operations and quantization error integration operations, and the sampling operations and the quantization error integration operations are simultaneously performed during the sampling phase of the ADC. Therefore, since the quantization error of the first switched capacitor array Cx is not required for quantization error integration, the operating speed of the ADC 100 can be improved.

[0024] Note that the second switched capacitor array Cy or the third switched capacitor array Cz does not have to have the same circuit structure as the first switched capacitor array Cx. As long as the second switched capacitor array Cy and the third switched capacitor array Cz can generate a repeated quantization error of the first switched capacitor array Cx, the second switched capacitor array Cy or the third switched capacitor array Cz may have any other suitable structure, such as Figure 3 The switched capacitor array 300 shown in FIG. The switched capacitor array 300 includes capacitors C1-C3 and six switches SW6-SW11, wherein one terminal of the capacitors C1-C3 is coupled to a positive reference voltage +Vref or a negative reference voltage -Vref through switches SW6-SW8, respectively, and the other terminals of the capacitors C1-C3 are coupled to a reference voltage, such as 0V, through switches SW9-SW11, respectively, wherein the switches SW6-SW11 are controlled by control signals D1 / D2 output by the time interleaving control circuit 130.

[0025] Those skilled in the art will readily observe that various modifications and variations can be made to the apparatus and methods while maintaining the teachings of the present invention.Therefore, the above disclosure should be interpreted as being limited only by the appended claims.

Claims

1. An analog-to-digital converter, characterized in that: include: A first switched capacitor array, configured to receive an input signal and sample the input signal to generate a first sampled signal; A second switched capacitor array, used for sampling the input signal to generate a second sampled signal and a first quantization error; a third switched capacitor array, used for sampling the input signal to generate a third sampled signal and a second quantization error; an integrator, coupled to the second switched capacitor array and the third switched capacitor array, for receiving and integrating the first quantization error and the second quantization error in a time-interleaved manner to generate an integrated quantization error; and a quantizer coupled to the first switched capacitor array and the integrator, for quantizing the first sampled signal by using the integrated quantization error as a reference voltage to generate a digital output signal; The analog-to-digital converter operates alternately in a sampling phase and a quantization phase; When the analog-to-digital converter operates in the sampling phase, the first switch capacitor array samples the input signal to generate the first sampled signal, one of the second switch capacitor array and the third switch capacitor array samples the input signal to generate the second sampled signal or the third sampled signal, and the other of the second switch capacitor array and the third switch capacitor array sends the first quantization error or the second quantization error to the integrator.

2. The analog-to-digital converter according to claim 1, wherein: When the analog-to-digital converter operates in the quantization stage, the quantizer quantizes the first sampling signal by using the integrated quantization error to generate the digital output signal, and only one of the second switched capacitor array and the third switched capacitor array is controlled by the digital output signal to generate the first quantization error or the second quantization error.

3. The analog-to-digital converter according to claim 1, wherein: The analog-to-digital converter sequentially operates in a first sampling stage, a first quantization stage, a second sampling stage, and a second quantization stage; and When the analog-to-digital converter operates in the first sampling phase, the first switch capacitor array samples the input signal to generate the first sampling signal, the second switch capacitor array samples the input signal to generate the second sampling signal, and the third switch capacitor array sends the second quantization error to the integrator; When the analog-to-digital converter operates in the first quantization stage, the quantizer quantizes the first sampling signal using the integrated quantization error to generate the digital output signal, and controls the second switched capacitor array to generate the first quantization error according to the digital output signal; When the analog-to-digital converter operates in the second sampling phase, the first switch capacitor array samples the input signal to generate the first sampling signal, the third switch capacitor array samples the input signal to generate the third sampling signal, and the second switch capacitor array sends the first quantization error to the integrator; When the analog-to-digital converter operates in the second quantization stage, the quantizer quantizes the first sampling signal using the integrated quantization error to generate the digital output signal, and controls the third switched capacitor array to generate the second quantization error according to the digital output signal.

4. The analog-to-digital converter according to claim 1, wherein: Also includes: A switching circuit is configured to selectively connect the input signal to the first switched capacitor array, the second switched capacitor array, and the third switched capacitor array, and selectively connect the second switched capacitor array and the third switched capacitor array to the integrator.

5. The analog-to-digital converter according to claim 1, wherein: The switching circuit includes: a first switch coupled between the input signal and the first switched capacitor array; a second switch coupled between the input signal and the second switched capacitor array; a third switch coupled between the input signal and the third switched capacitor array; a fourth switch coupled between the second switched capacitor array and the integrator; and A fifth switch is coupled between the third switched capacitor array and the integrator.

6. The analog-to-digital converter according to claim 5, wherein: The analog-to-digital converter sequentially operates in a first sampling stage, a first quantization stage, a second sampling stage, and a second quantization stage; and When the analog-to-digital converter operates in the first sampling phase, the first switch, the second switch and the fifth switch are enabled, and the third switch and the fourth switch are disabled; When the analog-to-digital converter operates in the first quantization phase, the first switch, the second switch, the third switch, the fourth switch and the fifth switch are disabled; when the analog-to-digital converter operates in the second sampling phase, the first switch, the third switch and the fourth switch are enabled, and the second switch and the fifth switch are disabled; When the analog-to-digital converter operates in the second quantization stage, the first switch, the second switch, the third switch, the fourth switch, and the fifth switch are disabled.

7. The analog-to-digital converter according to claim 6, wherein: When the analog-to-digital converter operates in the first sampling phase, the first switch capacitor array samples the input signal to generate the first sampling signal, the second switch capacitor array samples the input signal to generate the second sampling signal, and the third switch capacitor array sends the second quantization error to the integrator; When the analog-to-digital converter operates in the first quantization stage, the quantizer quantizes the first sampling signal using an integrated quantization error to generate the digital output signal, and controls the second switched capacitor array to generate the first quantization error according to the digital output signal; When the analog-to-digital converter operates in the second sampling phase, the first switch capacitor array samples the input signal to generate the first sampling signal, the third switch capacitor array samples the input signal to generate the third sampling signal, and the second switch capacitor array sends the first quantization error to the integrator; When the analog-to-digital converter operates in the second quantization stage, the quantizer quantizes the first sampling signal using an integrated quantization error to generate the digital output signal, and controls the third switched capacitor array to generate the second quantization error according to the digital output signal.

8. The analog-to-digital converter according to claim 1, wherein: The quantization error generated in the first switched capacitor array is not sent to the integrator for generating the integrated quantization error.

9. The analog-to-digital converter according to claim 1, wherein: The analog-to-digital converter is a successive approximation register analog-to-digital converter.

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