Analog-to-digital converter with resistive digital-to-analog converter for reference voltage tuning

Abstract

The present invention relates to an analog-to-digital converter having a resistive digital-to-analog converter for reference voltage tuning, and discloses an analog-to-digital converter circuit and a method for operating the analog-to-digital converter. A resistive digital-to-analog converter (RDAC) has a first reference node coupled to a first current source, a second reference node coupled to a second current source, an input port configured to receive a first voltage, and an output port coupled to a buffer. The RDAC is configured to generate a second voltage including a first voltage offset from the first voltage, and supply the second voltage from the output port of the RDAC to the buffer.

Description

Technical Field

[0001] The present invention relates generally to circuits and, more particularly, to analog-to-digital converter circuits and methods of operating analog-to-digital converters. Background Art

[0002] Successive approximation register (SAR) analog-to-digital converters (ADCs) typically employ capacitive digital-to-analog converters (CDACs), where constituent capacitors are switched between a reference voltage and ground to set the appropriate output voltage. Although an ideal CDAC outputs a precise, linear reference voltage, real-world CDACs are affected by external factors such as temperature and are therefore prone to error. For example, when temperature changes, the reference voltage output by the CDAC may drift, thereby potentially introducing gain errors.

[0003] A time-interleaved ADC may include a time-multiplexed parallel array of n identical successive approximation register (SAR) chips to increase the net sampling rate, but each individual chip in the array actually samples at a lower rate. Each SAR chip includes a buffer, such as a source follower, which has one or more transistors to provide a voltage drop relative to a stable reference voltage provided to its input. However, the output voltage may exhibit significant temperature variations between these different SAR chips due to, for example, process variations between transistors in these different SAR chips. The result is a temperature dependency that may cause different SAR chips to output different voltages despite receiving the same reference voltage.

[0004] Currently, the voltages of these different slices cannot be independently adjusted and calibrated. Such independent adjustments are desired to provide a mechanism for compensating for gain differences due to manufacturing-related mismatches. Furthermore, these independent adjustments should be achieved without increasing temperature variations.

[0005] Therefore, there is a need for improved analog-to-digital converter circuits and methods of operating analog-to-digital converters. Summary of the invention

[0006] In one embodiment, an analog-to-digital converter circuit is provided. The circuit includes a resistor digital-to-analog converter (RDAC), the RDAC having a first reference node coupled to a first current source, a second reference node coupled to a second current source, an input port configured to receive a first voltage, and an output port coupled to a buffer. The RDAC is configured to generate a second voltage including a first voltage offset from the first voltage, and supply the second voltage from the output port of the RDAC to the buffer.

[0007] In one embodiment, a method of operating an analog-to-digital converter is provided. The method includes assigning a first voltage to an input port of a resistive digital-to-analog converter (RDAC), the RDAC being calibrated to provide a voltage offset. The method also includes generating a second voltage including the voltage offset from the first voltage by the RDAC, and supplying the second voltage to a buffer from an output port of the RDAC. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate various embodiments of the present invention and, together with the general description of the present invention given above and the detailed description of the embodiments given below, serve to explain these embodiments of the present invention. In the accompanying drawings, like reference numerals represent similar features in different views.

[0009] Figure 1 is a circuit diagram of an example receiver circuit including an analog-to-digital converter in accordance with an embodiment of the present invention.

[0010] Figure 2 is a circuit diagram of a voltage reference circuit of an analog-to-digital converter according to an embodiment of the present invention.

[0011] Figure 3 is a circuit diagram of an embodiment of a SAR chip.

[0012] Figure 3A is a circuit diagram of an alternative embodiment of the SAR chip.

[0013] Figure 4 yes Figure 3 A circuit diagram of an embodiment of a resistive digital-to-analog converter.

[0014] Figure 5 yes Figure 3 A circuit diagram of an embodiment of a capacitive digital-to-analog converter. DETAILED DESCRIPTION

[0015] Please refer to Figure 1, the receiver circuit 10 may include an analog-to-digital converter (ADC) 15 configured to sample an analog input signal and convert the analog input signal to a digital output. The ADC 15 may be configured with sufficient resolution to provide a digital output that best represents the analog input signal. For example, the ADC 15 may be configured to convert a continuous analog waveform to a discrete digital representation by a binary search through a plurality of possible quantization levels before converging on a digital output for each conversion. The ADC 15 may be configured to process sampled data at a faster rate than the operating sampling rate of each individual SAR chip by time-interleaving identical successive approximation register (SAR) chips. To this end, the ADC 15 may include a time-multiplexed parallel array of n identical SAR chips of a successive approximation register (SAR) 18 to achieve a higher net sampling rate, even though each individual SAR chip in the array is actually sampling at a lower rate. The number of SAR chips in the array may be thirty-two (32), sixty-four (64), one hundred and twenty-eight (128), etc.

[0016] like Figure 1 As shown in , an analog input signal may be provided as an input 11 from a signal source to a variable-gain amplifier (VGA) 12. The VGA 12 may provide signal conditioning at an electronically settable voltage gain. To avoid problems caused by gain temperature variations of the SAR 18, the receiver circuit 10 may compensate for gain temperature variations by varying the electronically settable voltage gain of the VGA 12 based on temperature. The receiver circuit 10 may supply the output of the VGA 12 to an equalizer circuit represented by a continuous-time linear equalizer (CTLE) 14. The CTLE 14 provides signal conditioning in the form of equalization, thereby restoring the balance between the various frequency components of the signal received from the VGA 12. The interleaver 16 may sample the output of the CTLE 14 and provide lower frequency samples to each of the n SAR slices of the SAR 18. The interleaver 16 implements time interleaving to allow the ADC 15 to process the signal received as the input 11 at a faster rate by utilizing the multiple slices of the SAR 18 in a time-sequential manner. The signal is effectively quantized and processed independently by the chips of SAR 18 , and digital circuitry (not shown) then interleaves the B-bit samples of each of the n SAR chips into a B-bit stream representing a B-bit digital code at the sampling rate of ADC 15 .

[0017] Please refer to Figure 2-4 According to an embodiment of the present invention, ADC 15 ( Figure 1) may include a global reference circuit 20 having a transistor 26, an operational amplifier 34, and a voltage divider 45. Transistor 26 may be a p-type field effect transistor having a source 28 coupled to a current source 22, a drain 32, and a gate 30. The gate 30 of transistor 26 may be coupled to the drain 32 of transistor 26 such that transistor 26 is diode-connected. In one embodiment, current source 22 may be a constant current source, such as a 1 / R bandgap current reference. Operational amplifier 34 may have a non-inverting input 36 that is coupled to a supply constant reference voltage (V REFGLOBAL ) is coupled to a constant reference voltage source 24 of a transistor 26. Operational amplifier 34 may have an inverting input 38 coupled to source 28 of transistor 26. The feedback loop of operational amplifier 34 regulates the gate voltage of transistor 26. Voltage divider 45 includes resistor 44 coupled between drain 32 of transistor 26 and ground 46. Voltage divider 45 also includes resistor 48 coupled to output 41 of operational amplifier 34 and drain 32 of transistor 26. Global reference circuit 20 is configured to generate a reference voltage (V MID ).

[0018] The output 40 of the global reference circuit 20 may be coupled in parallel to a number of successive approximation register (SAR) slices 42 (eg, n slices ( 18 ) of the SAR 18 ). Figure 1 Therefore, the reference voltage (V MID ) are distributed in parallel to each SAR chip 42 of the ADC 15. However, no voltage is provided as feedback from any SAR chip 42 to any one of the inputs 36, 38 of the operational amplifier 34.

[0019] Each SAR chip 42 may include a resistive digital-to-analog converter (RDAC) 54 and a buffer 68 coupled to the RDAC 54. The RDAC 54 includes a plurality of resistors 82 each having a fixed resistance value and arranged in a network, and a plurality of switches 86 controlled to change the resistance value of the RDAC 54. In one embodiment, the resistors 82 may have nominally equal resistance values. The RDAC 54 of each SAR chip 42 has a center tap or input port 52, which represents the input of the SAR chip 42. The input port 52 is coupled to the output 40 of the global reference circuit 20, and each SAR chip 42 receives the reference voltage (V MID). The RDAC 54 may be center-tapped at the input port 52 so that the number of resistors 82 disposed between the input port 52 and the reference node 58 in the upper half of the resistor string is nominally equal to the number of resistors 82 disposed between the input port 52 and the reference node 62 in the lower half of the resistor string. A current source 56 may be coupled to the reference node 58 of the RDAC 54 of each SAR chip 42, and another current source 60 may be coupled to the reference node 62 of the RDAC 54 of each SAR chip 42. The resistor 82 generates an ohmic (IR) voltage drop so that the current source 56 drives the upper half of the resistor string to a voltage (V TOP ) and current source 60 drives the lower half of the resistor string to a voltage (V BOT ). In one embodiment, current source 60 may be an equivalent of current source 56 so that negligible and ideally zero current flows from SAR patch 42 into input port 52. In one embodiment, current sources 56 and 60 may be constant current sources, such as 1 / R bandgap current reference sources, so that the voltage drop across each resistor 82 is stable and constant. In one embodiment, current sources 56 and 60 may be shared by all SAR patches 42, in which case the connection to current sources 56 and 60 is a common node between all SAR patches 42, similar to the connection between SAR patches 42 and global reference circuit 20.

[0020] The reference voltage (V MID ) is used as the reference voltage (V REF ) can be adjusted by the RDAC 54 before being supplied to the buffer 68. Specifically, the adjustment of the resistance of the RDAC 54 can affect the change of the voltage transmitted to the buffer 68. In addition, the current sources 56 and 60 can provide a constant current to bias each RDAC 54 to maintain a constant voltage drop across each RDAC 54, thereby adjusting the reference voltage (V MID ) produces a well-defined level offset. In one embodiment, the switch 86 of the RDAC 54 of each SAR chip 42 is configured to be independently controlled so that the output voltage of each RDAC 54 can be individually set to a specific value. The voltage offset of the RDAC 54 of each SAR chip 42 is independent of the reference voltage (V MID ) value or magnitude.

[0021] The buffer 68 of each SAR chip 42 may have an input and an output with a low output resistance, and its level is shifted to the input voltage at the output port. The buffer 68 of each parallel SAR chip 42 of the SAR 18 may generate an analog voltage at its output port based on the voltage received at its input port 52. In one embodiment, the buffer 68 may be a source follower buffer, which includes a current source 66 and a transistor 64. The transistor 64 may be a p-type field effect transistor, and the current source 66 may be coupled to the source 70 of the transistor 64, the drain 72 of the transistor 64 may be coupled to the ground 46, and the gate 74 of the transistor 64 may be coupled to the output port 76 of the RDAC 54 to receive the reference voltage (V REF ).

[0022] The reference voltage (V REF ) is provided from the output port 76 of the RDAC 54 to the input of the buffer 68. The voltage (V REFBUF ) can be higher than the reference voltage (V REF ) gate-source voltage drop. Assuming that the voltage from gate 74 to source 70 of transistor 64 may be temperature dependent due to temperature dependent factors such as threshold voltage and mobility, the V REFBUF The output 80 may have a temperature variation (e.g., typically 70 mV from -10°C to 125°C). The threshold voltage of transistor 26 in global reference circuit 20 may partially compensate for the temperature dependence of transistor 64 in each buffer 68. In particular, transistor 26 and each transistor 64 may be biased similarly so that the temperature coefficients of their output voltages are substantially the same. However, the operation of RDAC 54 may provide temperature-independent voltage regulation to allow each SAR chip 42 to use a reference voltage that is different from the global reference voltage but has the same temperature dependence. Thus, compensating for the temperature-based threshold voltage deviation of transistor 64 may be combined with the predictable delta voltage step provided by RDAC 54 (which is independent of process corners). The result is a voltage value (V REFBUF ) can remain constant over temperature and can be individually tuned to a specific voltage on a per-chip basis.

[0023] Each SAR chip 42 of the SAR 18 may also include a capacitive digital-to-analog converter (CDAC) 88 and a SAR control circuit 89 coupled to the CDAC 88. The CDAC 88 (in combination with Figure 5 Further explanation) The reference voltage (V REFBUF ).

[0024] In an alternative embodiment and Figure 3A As shown in FIG. 1 , buffer 68 may be a super source follower including another transistor 69 and another current source 67. Transistor 69 may be an n-type field effect transistor having a gate coupled to the drain of transistor 64, a source coupled to ground 46, and a drain coupled to output 80. The drain of transistor 64 is coupled to current source 67.

[0025] Best as Figure 4 As shown in FIG. 1 , the RDAC 54 may use a resistor string architecture (e.g., a string DAC) having a plurality of resistors 82 coupled in series with nodes 84 between the resistors 82. For example, a plurality of switches 86 may be connected to one or more of the resistors 82 to provide selectable resistances and associated voltages at the output port 76. The RDAC 54 has a digital input code (e.g., d0, d1, d2) and a complementary digital code (e.g., ) to provide an RDAC code that activates and controls switch 86 to switch the selected resistor 82 into connection with output port 76. These digital input codes supplied to RDAC 54 adjust switch 86 to provide a voltage above or below the reference voltage (V MID ) is a fixed and temperature-independent voltage drop. For example, when a full-scale code is applied, the top switch may be closed and the output (e.g., V REF ) can go to full scale (e.g., the full scale code of RDAC 54 can produce V TOP Similarly, when a zero-scale code is applied, the bottom switch 86 may be closed and the output (e.g., V REF ) can go to zero scale (e.g., the zero scale code of RDAC 54 can produce V BOT The output of the RDAC 54 is shown in FIG. 1 . For example, each resistor 82 along the string or chain may produce a voltage drop equal to 1 least significant bit. Moreover, each code that can be applied to the RDAC 54 may have one resistor-switch pair. Therefore, as the resolution increases, the number of resistors 82 and switches 86 in the design of the RDAC 54 may increase exponentially. Each resistor 82 may have a fixed resistance value, and therefore, each resistor 82 may produce a constant delta voltage. Accordingly, each RDAC step may be a constant voltage that deviates from the voltage at the input port 52.

[0026] Each SAR chip 42 of the SAR 18 may be calibrated by using a calibration algorithm. For example, by supplying a given RDAC code, the local RDAC 54 of each SAR chip 42 may be set to a nominal value, and then the output port 76 (e.g., V ) of each local RDAC 54 may be sensed one by one (e.g., for 1 to n parallel SAR chips 42 of the SAR 18). REF ), the reference voltage (V REFGLOBAL ), then the reference voltage (V REFGLOBAL ) is set to the average value of the output ports 76 of each local RDAC 54. Alternatively, the reference voltage (V REFGLOBAL ) is set at a nominal value and can be calibrated using a separate RDAC. This global reference voltage (V REFGLOBAL ) to center the local RDACs 54 or prevent them from being railed. REF Equal to V TOP ), the reference voltage (V REFBUF ) may reduce the least significant bit by a preset number, or the maximum and minimum values ​​of the output port 76 of each local RDAC 54 may be adjusted to output the voltage (V MID ) minimum deviation.

[0027] Please refer to Figure 5 , each chip 42 of the SAR 18 may include a capacitive digital-to-analog converter (CDAC) 88 that operates based on charge redistribution. The CDAC 88 includes capacitors C1, ..., C N-3 , C N-2 , C N-1 and C N , they are connected through switches S1, ..., S N-3 , S N-2 , S N-1 and S N At voltage (V REFBUF ) and ground. Switching capacitors C1, ..., C N-3 , C N-2 , C N-1 and C N To set the appropriate output voltage V OUT The step size of the CDAC output voltage is determined by the capacitor ratio and the reference voltage (V REFBUF ) setting. The DAC gain is defined as the slope of the curve of the analog output of CDAC relative to the digital input. N-3 , C N-2 , C N-1 and C N The charge redistribution on the positive reference voltage (VREFBUF ) is drawn or poured. Capacitors C1, ..., C N-3 , C N-2 , C N-1 and C N The capacitance of the capacitor is affected by ambient temperature, but it has little effect on the CDAC step size since it is a function of the capacitor ratio. REFBUF ) may be affected by temperature drift. Since the V REFBUF 80 may vary with temperature, so the gain of CDAC 88 may vary with V REFBUF The gain of CDAC 88 directly affects the gain of ADC 15. Therefore, the gain change experienced by ADC 15 may occur due to the change in V REFBUF Represents the voltage in an environment with temperature offset.

[0028] Terms modified by approximate language such as "about," "approximately," and "substantially" cited herein are not limited to the exact value specified. The approximate language may correspond to the precision of the instrument used to measure the value, and may represent + / -10% of the value unless otherwise dependent on the precision of the instrument.

[0029] A feature that is "connected" or "coupled" to another feature may be directly connected or coupled to the other feature, or one or more intermediate features may be present. A feature may be "directly connected" or "directly coupled" to another feature if there are no intermediate features. A feature may be "not directly connected" or "not directly coupled" to another feature if there are at least one intermediate feature. A feature that is "on" or "in contact with" another feature may be directly on or in direct contact with the other feature, or one or more intermediate features may be present. A feature may be directly "on" or "in direct contact with" another feature if there are no intermediate features. A feature may not be "directly" "on" or "not directly in contact with" another feature if there are at least one intermediate feature.

[0030] The description of various embodiments of the present invention is for illustrative purposes and is not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terms used herein are selected to best explain the principles of these embodiments, practical applications, or technical improvements over commercially known technologies, or to enable those skilled in the art to understand the embodiments disclosed herein.

Claims

1. A circuit of an analog-to-digital converter, the circuit comprising: a first current source; a second current source; The first buffer, and a first resistive digital-to-analog converter having a first reference node coupled to the first current source, a second reference node coupled to the second current source, an input port configured to receive a first voltage, and an output port coupled to the first buffer, wherein the first resistive digital-to-analog converter is configured to generate a second voltage including a first voltage offset from the first voltage, and supply the second voltage from the output port of the first resistive digital-to-analog converter to the first buffer, The first voltage offset is independent of the value of the first voltage.

2. The circuit of claim 1, wherein: The first resistive digital-to-analog converter includes a plurality of first resistors and a plurality of second resistors, and the input port of the first resistive digital-to-analog converter is a center tap between the plurality of first resistors and the plurality of second resistors.

3. The circuit of claim 2, wherein: The plurality of first resistors are arranged in a first string between the first reference node and the input port, and the plurality of second resistors are arranged in a second string between the second reference node and the input port.

4. The circuit of claim 1, wherein: The first buffer includes a transistor having a gate, and the output port of the first resistive digital-to-analog converter is coupled to the gate of the transistor.

5. The circuit of claim 1, wherein: The first resistive digital-to-analog converter includes a plurality of resistors and a plurality of switches, and the switch is configured to selectively connect one or more of the resistors to the output port to generate the first voltage offset.

6. The circuit of claim 5, wherein: The first resistive digital-to-analog converter is configured to control the switch of the first resistive digital-to-analog converter in response to an n-bit digital input signal.

7. The circuit of claim 1, further comprising: A global reference circuit includes an output coupled to the input port of the first resistive digital-to-analog converter, and the global reference circuit is configured to generate the first voltage.

8. The circuit of claim 7, wherein: The global reference circuit includes a transistor and an operational amplifier, the transistor including a drain and a gate coupled to the drain, and the operational amplifier including an inverting input coupled to a source of the transistor, and further including: a third current source; and Constant reference voltage source, The source of the transistor is coupled to the third current source, and the operational amplifier includes a non-inverting input coupled to the constant reference voltage source.

9. The circuit of claim 8, wherein: The operational amplifier has an output and also includes: The voltage divider includes a first resistor and a second resistor, wherein the first resistor is coupled between the output of the operational amplifier and the input port of the first resistive digital-to-analog converter, and the second resistor is coupled between the drain of the transistor and ground.

10. The circuit of claim 1, wherein: The first buffer and the first resistive digital-to-analog converter are included in a first successive approximation register chip.

11. The circuit of claim 10, further comprising: A second successive approximation register chip includes a second buffer and a second resistive digital-to-analog converter, wherein the second resistive digital-to-analog converter includes an input port configured to receive the first voltage and an output port coupled to the second buffer, and the second resistive digital-to-analog converter is configured to generate a third voltage including a second voltage offset from the first voltage, and supply the third voltage from the output port of the second resistive digital-to-analog converter to the second buffer.

12. The circuit of claim 11, wherein: The second resistive digital-to-analog converter includes a first reference node coupled to the first current source and a second reference node coupled to the second current source.

13. The circuit of claim 11, further comprising: a global reference circuit including an output coupled in parallel to the input port of the first resistive digital-to-analog converter and the input port of the second resistive digital-to-analog converter, The global reference circuit is configured to generate the first voltage.

14. The circuit of claim 1, wherein: The first current source and the second current source are constant current sources.

15. A method of operating an analog-to-digital converter, the method comprising: assigning a first voltage to an input port of a first resistive digital-to-analog converter, the first resistive digital-to-analog converter being calibrated to provide a first voltage offset; generating, by the first resistive digital-to-analog converter, a second voltage including an offset of the first voltage from the first voltage; as well as supplying the second voltage from the output port of the first resistive digital-to-analog converter to the first buffer, The first voltage offset is independent of the value of the first voltage.

16. The method of claim 15, wherein: The first buffer includes a first transistor, and further includes: The second voltage is provided from the output port of the first resistive digital-to-analog converter to the gate of the first transistor.

17. The method of claim 16, further comprising: The first voltage is generated by comparing a source voltage of the second transistor in the reference circuit with a constant reference voltage using an operational amplifier.

18. The method of claim 17, further comprising: The second transistor is biased to compensate for a temperature dependency of the first transistor.

19. The method of claim 15, wherein: distributing the first voltage in parallel to an input port of a second resistive digital-to-analog converter, the second resistive digital-to-analog converter being calibrated to provide a second voltage offset and further comprising: generating a third voltage including the second voltage offset from the first voltage by the second resistive digital-to-analog converter; and The third voltage is supplied from the output port of the second resistive digital-to-analog converter to the second buffer.

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