Device and method for masking write operations for an operating mode using an ECC circuit system

Abstract

This application relates to an apparatus and method for masking write operations for an operating mode using an ECC circuitry. An exemplary semiconductor device includes an input / output (I / O) circuit configured to combine data corresponding to a write command received via a data terminal with a first subset of corrected read data retrieved from a memory cell array to provide write data. The exemplary semiconductor device further includes a write driver circuit configured to mask a write operation of a first bit of the write data corresponding to bits of the first subset of the read data and perform a write operation on a second bit of the write data corresponding to the data received via the data terminal.

Description

Technical Field

[0001] This application relates to semiconductor memories and, more particularly, to devices and methods for using an ECC circuitry to mask write operations for an operation mode. Background Art

[0002] High data reliability, high-speed memory access, low power, and reduced chip size are characteristics required of semiconductor memories. In some applications, a semiconductor memory device may be designed to operate in more than one mode to accommodate different applications, such as different data bus widths. However, introducing configurability may increase design complexity, power consumption, or latency. For example, performing a write operation for a first bus width within a semiconductor memory device may be different from performing a write operation for a second bus width within the semiconductor memory device. It is desirable to mitigate some of the increased complexity resulting from implementing configurability options. Summary of the Invention

[0003] According to one aspect of the present application, there is provided a device. The device includes: an input / output (I / O) circuit configured to combine data corresponding to a write command received via a data terminal with a first subset of corrected read data retrieved from a memory cell array to provide write data; and a write driver circuit configured to mask a write operation of a first bit of the write data corresponding to bits of the first subset of the read data and perform a write operation on a second bit of the write data corresponding to the data received via the data terminal.

[0004] According to another aspect of the present application, there is provided a memory. The memory includes: a pair of main input / output (I / O) lines coupled to a memory cell array; a pull-up circuit configured to provide a first voltage to a selected first one of the pair of main I / O lines; a pull-down circuit configured to provide a second voltage to a selected second one of the pair of main I / O lines; and a write driver circuit configured to receive bits of corrected read data retrieved from the memory cell array and bits of write data, wherein the write driver circuit is configured to deactivate the pull-up and pull-down circuits in response to the bits of the corrected read data matching the bits of the write data, and wherein the write driver circuit is configured to activate the pull-up circuit to provide the first voltage to the selected first one of the pair of main I / O lines and activate the pull-down circuit to provide the second voltage to the selected second one of the pair of main I / O lines in response to the bits of the corrected read data differing from the bits of the write data.

[0005] According to another aspect of the present application, a method is provided. The method includes: receiving data corresponding to a write command received via a data terminal of a semiconductor device; combining the data corresponding to the write command with a first subset of corrected read data retrieved from a memory cell array of the semiconductor device to provide write data; masking a write operation of a first bit of the write data corresponding to bits of the first subset of the read data via a write driver circuit; and performing a write operation on a second bit of the write data corresponding to the data received via the data terminal. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figure 1 is a block diagram of a semiconductor device according to an embodiment of the present invention.

[0007] Figure 2 is a schematic block diagram of a portion of a semiconductor device according to an embodiment of the present invention.

[0008] Figure 3 is a schematic block diagram of a master input / output write driver circuit according to an embodiment of the present invention.

[0009] Figure 4 is a schematic block diagram of a portion of a master input / output write driver configured to control voltages on complementary master IO signal lines according to an embodiment of the present invention.

[0010] Figure 5 An exemplary flow chart of a second mode initial read operation according to an embodiment of the present invention is provided.

[0011] Figure 6 is an exemplary flow chart of a second mode write operation for driving a signal to a master input / output write driver circuit according to an embodiment of the present invention.

[0012] Figure 7A Exemplary ECC bit data circuitry according to embodiments of the present invention is provided.

[0013] Figure 7B Exemplary ECC control plane data circuitry according to embodiments of the present invention is provided.

[0014] Figure 7C Exemplary error locating circuitry for comparing an ERRB bit to the ERRCP bit according to an embodiment of the present invention is provided.

[0015] Figure 8 Exemplary control circuits according to embodiments of the present invention are provided. DETAILED DESCRIPTION

[0016] The following details are presented to provide a thorough understanding of embodiments of the present invention. However, it will be clear to those skilled in the art that embodiments of the present invention may be practiced without these specific details. In addition, the specific embodiments of the present invention described herein are for illustrative purposes only and should not be used to limit the scope of the present invention to these specific embodiments. In other instances, well-known circuits, control signals, timing protocols, and software operations are not shown in detail so as not to unnecessarily obscure the present invention.

[0017] Some of the materials described in the present invention include circuitry and techniques for reducing current draw during write operations in certain operating modes by masking some of the write operations. The semiconductor device is capable of operating in system implementations having different data bus widths. For example, the semiconductor device may be configured to operate in a selected one of multiple input / output (I / O) bus configurations (e.g., data bus width modes) (e.g., x4 mode (e.g., the data bus is 4 bits wide), x8 mode (e.g., the data bus is 8 bits wide), etc.). During read or write operations, data bits may be sent or received over a fixed burst length (e.g., 8, 16, 32-bit burst lengths). Thus, the number of write bits received when in the x4 mode may be different from the number of write bits received when operating in the x8 mode. For example, if the burst length is 16 bits, then 64 bits will be received in the x4 mode and 128 bits will be received in the x8 mode.

[0018] To reduce the complexity of generating an error detection code to indicate whether data read from an address of a memory cell array matches data previously written to the address of the memory cell array, the internal read / write circuitry may be configured to generate the error detection code based on a fixed number of bits independent of a selected I / O bus configuration. Thus, an error correction code (ECC) circuitry may generate an ECC for a fixed number of data bits written to the memory and then store it in the memory cell array together with the written data. In some instances, when the number of written data bits received via an I / O bus for a write operation directed to a specific address is less than the number required to generate an ECC, the semiconductor device may first perform a read operation to retrieve read data from the specific address and combine a first subset of the read data (e.g., old data) with the written data (e.g., new data) received via the I / O bus for the write operation to form a set of written data bits for writing to the array. For example, the bits in bit positions K (e.g., where K equals 127, 63, etc.) to M+1 (e.g., where M equals 63, 31, etc.) of the set of written data bits may include the written data received via the I / O bus, and the bits in bit positions M to 0 may include the first subset of the read data. As another example, the bits in bit positions K to M+1 of the set of written data bits may include the first subset of the read data, and the bits in bit positions M to 0 may include the written data received via the I / O bus. The ECC circuitry may generate an ECC code for the written data bits of the write array. In this case, the subset of the read data may be written back to the memory together with the written data received via the I / O bus and the new ECC code.

[0019] During read and write operations, a column select (CS) signal line is enabled and at least one pair of data lines (e.g., a main I / O (MIO) or a global I / O (GIO)) is driven to complementary logic voltage polarities. Typically, the CS signal line remains enabled until the read and / or write operations are completed. Additionally, the voltage difference between the data signal line pairs for a read operation is less than that for a write operation. Thus, charging the data signal line pairs during a write operation uses more current than charging the signal lines during a read operation. Additionally, when a write or read operation is completed, the data signal line pairs are equalized to prepare for a subsequent read or write operation. Thus, because the voltage difference for a write operation is higher, the current consumption for equalizing the data signal line pairs is greater than the equalization current consumption for a post-read operation equalization.

[0020] Accordingly, to save power in this scenario, the control circuitry can deactivate or cut off selected CS signal lines of a subset of the control plane corresponding to writing back old data to the memory cell array in response to indicating that the ECC circuitry has not detected an error. Additionally, the write driver circuitry can mask write operations for unchanged old data of the written data to avoid driving the data signal line pair to the write voltage polarity. Finally, during a write operation, write operations for individual bits of the new data that match the corresponding bits of a second subset of the read data overwritten by the new data can be masked. By cutting off the CS signal lines and masking write operations for at least some of the written data bits when no error is detected, current consumption during driving the CS signal lines and driving the pair of data signal lines and during equalization can be reduced.

[0021] Figure 1 is a schematic block diagram of a semiconductor device 100 according to an embodiment of the present invention. For example, the semiconductor device 100 can include a chip 135 and a ZQ resistor (RZQ) 155. The chip 135 can include a clock input circuit 105, an internal clock generator 107, a timing generator 109, an address command input circuit 115, an address decoder 120, a command decoder 125, a control circuit 126, a plurality of row decoders 130, a memory cell array 145 including sense amplifiers 150 and transfer gates 195, a plurality of column decoders 140, a plurality of read / write amplifiers 165, an input / output (I / O) circuit 170, a ZQ resistor (RZQ) 155, a ZQ calibration circuit 175, and a voltage generator 190. The semiconductor device 100 can include a plurality of external terminals, which include address and command terminals coupled to a command / address bus 110, clock terminals CK and / CK, data terminals DQ, DQS, and DM, power supply terminals VDD, VSS, VDDQ, and VSSQ, and a calibration terminal ZQ. The chip 135 can be mounted on a substrate 160 (such as a memory module substrate, a motherboard, or the like).

[0022] The memory cell array 145 includes a plurality of banks BANK0 to N, each bank BANK0 to N including a plurality of word lines WL, a plurality of bit lines BL, and a plurality of memory cells MC arranged at intersections of the plurality of word lines WL and the plurality of bit lines BL. The number of banks BANK0 to N can include 2, 4, 8, 16, or any other number of banks. Selection of the word lines WL for each bank is performed by a corresponding row decoder 130, and selection of the bit lines BL is performed by a corresponding column decoder 140. The plurality of sense amplifiers 150 are positioned for their corresponding bit lines BL and are coupled to at least one respective local I / O line via transfer gates TG 195 serving as switches, and the local I / O line is further coupled to a respective one of at least two main I / O line pairs.

[0023] The address / command input circuit 115 can receive an address signal and a bank address signal from the outside at the command / address terminal via the command / address bus 110 and transmit the address signal and the bank address signal to the address decoder 120. The address decoder 120 can decode the address signal received from the address / command input circuit 115 and provide a row address signal XADD to the row decoder 130 and a column address signal YADD to the column decoder 140. The address decoder 120 can also receive the bank address signal and provide the bank address signal BADD to the row decoder 130 and the column decoder 140.

[0024] The address / command input circuit 115 can receive a command signal from the outside (e.g., the memory controller 105 for example) at the command / address terminal via the command / address bus 110 and provide the command signal to the command decoder 125. The command decoder 125 can decode the command signal and provide various internal command signals. For example, the internal command signals can include a row command signal for selecting a word line, a column command signal such as a read command or a write command for selecting a bit line, a mode register set command MRS that can cause the mode register setting to be stored at the control circuit 126, and a ZQ calibration command ZQ_com that can activate the ZQ calibration circuit 175.

[0025] Therefore, when a read command is issued and the row address and the column address are timely supplied for the read command, the read data is read from the memory cells in the memory cell array 145 specified by the row address and the column address. The read / write amplifier 165 can receive the read data DQ and provide the read data DQ to the IO circuit 170. The IO circuit 170 can provide the read data DQ to the outside via the data terminal DQ, and provide a data strobe signal at DQS to the outside and / or provide a data mask signal at DM to the outside. Similarly, when a write command is issued and the row address and the column address are timely supplied for the write command, the input / output circuit 170 can receive write data at the data terminal DQ, receive a data strobe signal at DQS, and receive a data mask signal at DM, and provide the write data to the memory cell array 145 via the read / write amplifier 165. Therefore, the write data can be written into the memory cells specified by the row address and the column address.

[0026] During both read and write operations, the column decoder 140 may drive the column select CS signal and the main IO write driver circuit 167 may drive each respective pair of main IO lines to complementary logic voltage polarities based on the row and column addresses. The voltage difference between the respective pair of signal lines driven by the main IO write driver circuit 167 for a read operation may be less than that for a write operation. Thus, during a write operation, the current consumption for driving and equalizing the respective pair of main I / O lines to prepare for a subsequent read or write operation may be greater than the drive and equalization current consumption for a read operation.

[0027] In some examples, the semiconductor device 100 may be configured to operate the IO circuit 170 in a selected one of multiple data terminal DQ bus configurations (e.g., data bus width modes) (e.g., x4 mode (e.g., the data bus is 4 bits wide), x8 mode (e.g., the data bus is 8 bits wide), etc.). In some examples, during a read or write operation, data bits are transmitted or received via the data terminal DQ over a fixed burst length (e.g., 8, 16, 32 bit burst lengths). Thus, the number of write bits received when operating in the x4 mode may be different from the number of write bits received when operating in the x8 mode. For example, if the burst length is 16 bits, then 64 bits will be received in the x4 mode and 128 bits will be received in the x8 mode.

[0028] To reduce the complexity associated with generating error correction and detection codes for data generated for writing to the memory cell array 145, the column decoder 140, row decoder 130, read / write amplifier 165, and / or the main IO write driver circuit 167 may be configured to read a fixed number of bits from the memory cell array 145 and write a fixed number of bits to the memory cell array 145 independent of the selected data terminal DQ bus configuration. Reading and writing a fixed number of bits may simplify the operation of the ECC control circuit 166 configured to detect and correct errors in data read from the memory cell array 145. For example, the ECC control circuit 166 may generate an ECC for a fixed number of data bits written to the memory cell array 145. The ECC is written to the memory cell array 145 along with the write data bits. In some instances, when the number of bits of write data received via the data terminal DQ is less than the number of bits required to write data to the memory cell array 145, the semiconductor device 100 may first perform a read operation via the read / write amplifier 165 to retrieve read data from the row and column addresses associated with the write operation. The ECC control circuit 166 may check for errors in the read data to provide corrected read data. The read / write amplifier 165 or the IO circuit 170 may combine a first subset of the corrected read data (e.g., old data) with the write data (e.g., new data) received via the data terminal DQ for the write operation to form a set of write data to be written to the memory cell array 145. The ECC control circuit 166 may generate an ECC code for the write data bits to be written to the memory cell array 145. Thus, in this case, the old data may be written back to the memory.

[0029] However, in some instances, to reduce current, some CS signals may be cut off when no error is detected in a portion of the read data written back to the memory and some write operations can be masked (e.g., for uncorrected old data or new data that matches the old data). The control circuit 126 may provide a CS cut-off signal CSOFF to cause the column decoder 140 to cut off the corresponding CS signals and provide data masking and write enable signals DWDM / WREN to the read / write amplifier 165 based on control signals CTRL (e.g., X4 signal, column address signal CA<10>, timing signal, etc.) received from the command decoder 125, a correction signal CORRECT received from the ECC CC 166, and a DM signal from the IO circuit 170. When in x4 mode, the control circuit 126 may be configured to set the DWDM signal based on the CTRL signal (e.g., the value of the column address bit, e.g., CA<10>). Otherwise, the DWDM signal may be set based on the DM signal. The control circuit 126 may be configured to enable the CSOFF signal in response to a CORRECT signal indicating no error in the control plane (where data from a previous read operation is written back (e.g., the control plane determined based on the DWDM signal)). The timing for enabling the CSOFF signal may be determined based on the timing signal from the CTRL signal. The current consumption can be reduced by setting the CSOFF signal to cause the column decoder 140 to cut off the corresponding CS signal lines. The control circuit 126 may further be configured to enable the WREN signal according to the timing signal from the CTRL signal.

[0030] In response to the WREN signal and based on the DWDM signal, the main IO write driver circuit 167 may mask write operations for uncorrected old data to avoid driving the main I / O signal line pair to the write voltage polarity. Additionally, the main IO write driver circuit 167 may compare individual bits of the new data with the corresponding bits of a second subset of the read data and mask the write operations of the bits of the new data bits that match the corresponding bits of the second subset of the read data to avoid driving the main IO signal line pair to the write voltage polarity. The current consumption during driving the main IO signal line pair and equalization can be reduced by masking the write operations for at least some of the write data bits.

[0031] Turning to an explanation of the external terminals included in the semiconductor device 100, the clock terminals CK and / CK can receive an external clock signal and a complementary external clock signal, respectively. The external clock signal (including the complementary external clock signal) can be supplied to the clock input circuit 105. The clock input circuit 105 can receive the external clock signal and generate an internal clock signal ICLK. The clock input circuit 105 can provide the internal clock signal ICLK to the internal clock generator 107. The internal clock generator 107 can generate a phase-controlled internal clock signal LCLK based on the received internal clock signal ICLK and the clock enable signal CKE from the address / command input circuit 115. Although not limited thereto, a DLL circuit can be used as the internal clock generator 107. The internal clock generator 107 can provide the phase-controlled internal clock signal LCLK to the IO circuit 170 and the timing generator 109. The IO circuit 170 can use the phase controller internal clock signal LCLK as a timing signal for determining the output timing of the read data. The timing generator 109 can receive the internal clock signal ICLK and generate various internal clock signals.

[0032] The power supply terminals can receive power supply voltages VDD and VSS. These power supply voltages VDD and VSS can be supplied to the voltage generator circuit 190. The voltage generator circuit 190 can generate various internal voltages VPP, VOD, VARY, VPERI, and the like based on the power supply voltages VDD and VSS. The internal voltage VPP is mainly used in the row decoder 130, the internal voltages VOD and VARY are mainly used in the sense amplifiers 150 included in the memory cell array 145, and the internal voltage VPERI is used in many other circuit blocks. The power supply terminals can also receive power supply voltages VDDQ and VSSQ. The IO circuit 170 can receive the power supply voltages VDDQ and VSSQ. For example, the power supply voltages VDDQ and VSSQ can be the same voltages as the power supply voltages VDD and VSS, respectively. However, dedicated power supply voltages VDDQ and VSSQ can be used for the IO circuit 170 and the ZQ calibration circuit 175.

[0033] The calibration terminal ZQ of the semiconductor memory device 100 can be coupled to the ZQ calibration circuit 175. The ZQ calibration circuit 175 can perform a calibration operation with reference to the impedance of the ZQ resistor (RZQ) 155. In some instances, the ZQ resistor (RZQ) 155 can be mounted on a substrate coupled to the calibration terminal ZQ. For example, the ZQ resistor (RZQ) 155 can be coupled to the power supply voltage (VDDQ). The impedance code ZQCODE obtained through the calibration operation can be provided to the IO circuit 170, and thus specify the impedance of an output buffer (not shown) included in the IO circuit 170.

[0034] Figure 2FIG. 0 is a schematic block diagram of a portion of a semiconductor device 200 in accordance with an embodiment of the present invention. By way of example, semiconductor device 200 may include a control circuit 226, an ECC control circuit 266, and a main IO write driver circuit 267. Figure 1 Semiconductor device 100 may implement portions of semiconductor device 200.

[0035] ECC control circuit 266 may include a syndrome generator 232, a syndrome decoder 234, an error corrector 236, an error locator 238, a parity generator 240, and an IO circuit 270. Syndrome generator 232 may receive parity data P from a memory cell array (e.g., Figure 1 memory cell array 145) of <l:0>and read data RD <k:0>, and can be based on P <l:0>Data and RD <k:0>Data generates syndrome code data PC <n:0>。When RD <k:0>When data is stored in the memory cell array 145, it can be based on RD <k:0>Data to generate P <l:0>Data

[0036] The syndrome decoder 234 may receive the PC <n:0>data and can be based on a PC <n:0>Data generates ECC bit data ERRB <l:0>and the ECC control plane data ERRCP <n:0>。In some instances, ERRB <l:0>A first logic value (e.g., a low logic value) of a corresponding bit of the data indicates a corresponding error, and ERRB <l:0>A second logical value (e.g., a high logical value) of a corresponding bit of the data indicates no corresponding error. In some instances, ERRCP <n:0>A first logic value (e.g., a low logic value) of a corresponding bit of the data indicates a corresponding control plane error, and ERRCP <n:0>A second logical value (e.g., a high logical value) of a corresponding bit of the data indicates that there is no corresponding control plane corresponding error. Figure 7A and 7B respectively provide exemplary ECC bit data circuit system 700 and ECC control plane data circuit system 710 having 8 ERRB bits (e.g., N+1 equals 8) and 16 control planes (e.g., L+1 equals 16) according to embodiments of the present invention. In Figure 7A the ECC bit data circuit system 700 includes logic circuits 701(7) to (0), each of which is configured to receive a combination of data from PC<7:5> data (e.g., and / or the complement PCF<7:5> of the PC<7:5> data) to provide corresponding ERRB<7:0> data. Each of the logic circuits 701(7) to (0) may include a corresponding "AND" gate coupled in series with a corresponding inverter.

[0037] In Figure 7B the ECC control plane data circuit system 710 includes logic circuits 711(15) to (0), each of which is configured to receive a combination of data from PC<4:0> data (e.g., and / or the complement PCF<4:0> of the PC<4:0> data) to provide corresponding ERRCP<15:0> data. Each of the logic circuits 711(15) to (0) may include a corresponding pair of "NAND" gates, having an output coupled to a corresponding "OR" gate and an output of the corresponding "OR" gate coupled to a corresponding inverter.

[0038] Return Figure 2 , the error corrector 236 may receive RD <k:0>, ERRB <l:0>Data and ERCP <n:0>data and can be based on ERRB <l:0>and ERCP <n:0>Data provides corrected read data CRD <k:0>。The error locator 238 can receive ERRB <l:0>and ERCP <n:0>data and can be based on ERRB <l:0>and ERCP <n:0>Data determination RD <k:0>The location of any error in the data, and correction location data CORRECT can be provided at the output <n:0>。The error corrector 236 and / or the error locator 238 may use logic to decode the ERRB <l:0>and ERCP <n:0>Data for positioning RD <k:0>Error within the data. Figure 7C Provided is one ERRB for comparison according to an embodiment of the present invention <x>An exemplary error localization circuitry 720 with bits and 16 ERRCP<15:0> bits (e.g., L+1 equals 16). In Figure 7C , the error localization circuitry 720 includes logic circuits 721(15) through (0), each of which is configured to receive from ERRB <x>bits (e.g., where X is any integer from 0 to 7) and the combination of received data by ERRCP<15:0> to provide corresponding CORRECT<15:0> data. Each of the logic circuits 721(15) to (0) may include a corresponding "NOR" gate. Thus, when ERRB <x>When both the bit and the corresponding ERRCP<15:0> data bit are set to a first logical value (e.g., a low logical value), the corresponding CORRECT<15:0> data bit is set to a high logical value. Otherwise, the corresponding CORRECT<15:0> data bit is set to a second logical value (e.g., a low logical value).

[0039] Return Figure 2 , the parity generator 240 can receive the write data WD from the IO circuit 270 (e.g., Figure 1 the IO circuit system 170) <k:0>and provide write parity data WP at the output <l:0>。The IO circuit 270 can receive data DQ via the data terminal <m:0>, CRD <k:0>Data and data terminal mode signal X4. During a write operation when the X4 signal has a first value (e.g., a logic low value), the IO circuit 270 may drive DQ <m:0>Data is provided as WD <k:0>(For example, K is equal to M). During a write operation when the X4 signal has a second value (e.g., a logic high value), the IO circuit 270 may drive DQ <m:0>Data and CRD <m:0>The combination of data is provided as WD <k:0>Data (e.g., M+1 equals half of K+1). During a read operation, the IO circuit 270 may select some or all of the CRDs based on the value of the X4 signal <k:0>Data is provided to DQ <m:0>Data.

[0040] The control circuit 226 can generate data masking signals DWDM<1:0>, write enable signal WREN, and CS cut-off signals CSOFF<1:0> based on the X4 signal, address bit CA<10>, data masking signal DM (e.g., received via the DM terminal of Figure 1 ), and / or timing signal TIME. The X4 signal, CA<10> address bit, and TIME signal can correspond to the Figure 1 CTRL signal of . Each of the DWDM<1:0> signals corresponds to a different respective half of the control plane of the memory cell array. The control circuit 226 can set the DWDM<1:0> signals to a common logic value determined based on the DM signal in response to the X4 signal indicating the first mode (e.g., when the X4 signal has a value indicating the x8 mode). The control circuit 226 can set the DWDM<1:0> signals to complementary logic values determined based on the CA<10> address bit signal in response to the X4 signal indicating the second mode (e.g., when the X4 signal has a value indicating the x4 mode). Thus, in the second mode, the control circuit 226 can set one of the DWDM<1:0> to a high logic value to enable masking of the data write operation for the half of the control plane corresponding to the old data, while the control circuit 226 can set the other to a low logic value to disable masking of the write operation for the other half of the control plane corresponding to the new data.

[0041] The control circuit 226 can provide the CSOFF<1:0> signal to cause the column decoder (e.g., Figure 1 column decoder 140 of ) to cut off the corresponding CS signal at a time determined according to the TIME signal. Similar to the DWDM<1:0> signals, each of the CSOFF<1:0> signals corresponds to a different respective half of the control plane of the memory cell array. When in the x8 mode (e.g., determined based on the X4 signal), the control circuit 226 is configured to set the CSOFF<1:0> signals to a common logic value. When in the x4 mode (e.g., determined based on the X4 signal), the control circuit 226 is configured to be based on CORRECT <n:0>The signal and the DWDM <1:0> signal enable the CSOFF <1:0> signal. CORRECT <n:0>Each of them corresponds to a specific control plane of the memory cell array. Thus, when the DWDM<1> signal is enabled and according to the timing of the TIME signal, the control circuit 226 can be configured to respond to CORRECT corresponding to the control plane associated with the DWDM<1> signal indicating no error <n:0>Enable the CSOFF<1> signal for the first subset of signals. Otherwise, the CSOFF<1> signal can be deactivated. Similarly, when the DWDM<0> signal is enabled and according to the timing of the TIME signal, the control circuit 226 can be configured to respond to CORRECT corresponding to the control plane associated with the DWDM<0> signal indicating no error <n:0>Enable the CSOFF<0> signal for the second subset of signals. Otherwise, the CSOFF<0> signal can be disabled. The current consumption can be reduced by causing the column decoder to cut off the corresponding CS signal line by setting one of the CSOFF<1:> signals during a write operation. The control circuit 226 can be further configured to enable the WREN signal according to the timing of the TIME signal.

[0042] Figure 8 Provide an exemplary control circuit 826 according to an embodiment of the present invention. The control circuit 826 includes a data masking circuit 810 and a CS control circuit 820. The data masking circuit 810 can generate DWDM<1:0> signals based on the X4 signal, the CA<10> address bit, and the DM signal. The data masking circuit 810 can set the DWDM<1:0> signals to a common logic value determined based on the DM signal in response to the X4 signal indicating the first mode (e.g., when the X4 signal has a value indicating the x8 mode). The data masking circuit 810 can set the DWDM<1:0> signals to complementary logic values determined based on the CA<10> address bit signal in response to the X4 signal indicating the second mode (e.g., when the X4 signal has a value indicating the x4 mode). Thus, in the second mode, the data masking circuit 810 can set one of the DWDM<1:0> to a high logic value to enable masking of the data write operation for half of the control plane corresponding to the old data, while the data masking circuit 810 can set the other to a low logic value to disable masking of the write operation for the other half of the control plane corresponding to the new data.

[0043] At a time determined according to the time signal, the CS control circuit 820 can provide the CSOFF<1:0> signal to cause the column decoder (e.g., Figure 1 column decoder 140) to cut off the corresponding CS signal and provide the WREN signal to enable the write operation. In some instances, the CS control circuit 820 can include a state machine to determine when and how to set the CSOFF<1:0> signal and the WREN signal. When in the x8 mode (e.g., determined based on the X4 signal), the CS control circuit 820 is configured to set the CSOFF<1:0> signal to a common logic value. When in the x4 mode (e.g., determined based on the X4 signal), the CS control circuit 820 is configured to be based on CORRECT <n:0>The DWDM<1:0> signal from the signal and data masking circuit 810 enables the CSOFF<1:0> signal. Thus, when the DWDM<1> signal is enabled and according to the timing of the time signal, the CS control circuit 820 can be configured to respond to CORRECT corresponding to the control plane associated with the DWDM<1> signal indicating no error <n:0>Enable the CSOFF<1> signal for the first subset of signals. Otherwise, the CSOFF<1> signal can be disabled. Similarly, when the DWDM<0> signal is enabled and according to the timing of the TIME signal, the CS control circuit 820 can be configured to respond to CORRECT corresponding to the control plane associated with the DWDM<0> signal indicating no error <n:0>Enable the CSOFF<0> signal for the second subset of signals. Otherwise, the CSOFF<0> signal can be disabled. The control circuit 226 can be further configured to enable the WREN signal according to the timing of the TIME signal.

[0044] Return Figure 2 , the main IO write driver circuit 267 can receive CORRECT <n:0>Data, CRD <k:0>Data, WP <l:0>Data, WD <k:0>Data, DWDM<1:0> signals, X4 signals, a write enable signal WREN (e.g., via a control signal from a command decoder, e.g., a CTRL signal from Figure 1 command decoder 125). During a write operation, the host IO write driver circuit 267 may be configured to be based on CORRECT <n:0>Data, CRD <k:0>Data, WP <l:0>Data, WD <k:0>Values of data, DWDM<1:0> signals, X4 signals, WREN signals, or combinations thereof drive the master IO lines for the various control planes for the memory cell array.

[0045] In operation, the ECC control circuit 266 and the IO circuit 270 may support read operations from the memory cell array and the ECC control circuit 266, the IO circuit 270, and the control circuit 226, and the master IO write driver circuit 267 may support write operations to the memory cell array. In some instances, the semiconductor device 200 may be configured to operate the IO circuit 270 in a selected one of multiple data terminal DQ bus configurations (e.g., data bus width modes) (e.g., x4 mode (e.g., the data bus is 4 bits wide), x8 mode (e.g., the data bus is 8 bits wide), etc.). In some instances, the X4 signal will determine the selected DQ bus configuration. For example, when the X4 signal is set to a low logic value, the semiconductor device 200 may operate in a first mode (e.g., x8 data mode). When the X4 signal is set to a high logic value, the semiconductor device 200 may operate in a second mode (e.g., x4 data mode). In some instances, during a read or write operation, data bits are transmitted or received via the data terminal DQ over a fixed burst length (e.g., 8, 16, 32 bit burst lengths). Thus, the number of write bits received when in the x4 mode may be different from the number of write bits received when operating in the x8 mode. For example, if the burst length is 16 bits, then 64 bits will be received in the x4 mode and 128 bits will be received in the x8 mode.

[0046] Thus, when a read command, row address, and column address are received at the semiconductor device 200, RD may be read from the memory cell array specified by the row address and column address <k:0>Data and P <l:0>Data. The syndrome generator 232 may be configured to be based on P <l:0>Data and RD <k:0>Data generation PC <n:0>Data. The syndrome decoder 234 can decode the PC <n:0>Data to provide ERRB <l:0>Data and ERCP <n:0>Data. Error corrector 236 can decode ERRB <l:0>Data and ERCP <n:0>Data for calibration RD <k:0>Errors within to provide CRD <k:0>Data. Based on the operation mode determined by the X4 signal, the IO circuit 270 may provide some or all of the CRD <k:0>Data as DQ <m:0>Data. For example, when in the first mode (e.g., x8 mode), the IO circuit 270 can provide all of the CRD <k:0>The bit serves as DQ <m:0>Data (e.g., M equals K). When in the second mode (e.g., x4 mode), the IO circuit 270 may provide the CRD <k:0>Data (such as CRD<K:M+1> data, CRD <m:0>Data or CRD <k:0>Select the M + 1 bits of some other combinations of the M + 1 bits of the data as DQ <m:0>Data. CRD <k:0>A selected subset of the M+1 bits of data may be based on the received column and row addresses.

[0047] When a write command, a row address, and a column address are received at the semiconductor device 200, they may be received at the IO circuit 270 via DQ <m:0>Data reception writes data. When in the first mode (e.g., x8 mode), the IO circuit 270 can enable all DQ <m:0>Data as WD <k:0>Data (e.g., M equals K) is provided to the parity generator 240. The parity generator 240 may be based on WD <k:0>Data to encode WP <l:0>Data. When in the first mode, the control circuit 226 can drive the DWDM<1:0> signal based on the DM signal. Additionally, the control circuit 226 can enable the WREN signal according to the timing of the TIME signal during a write operation to enable writing to the memory cell array. The main IO write driver circuit 267 can drive the main IO line in response to the WREN signal to write WD <k:0>and WP <l:0>Data is written to a memory cell array, where some of the write operations are masked by the DWDM<1:0> signal.

[0048] When operating in a second mode (e.g., x4 mode), DQ <m:0>The count of the M+1 bits received in the data may be less than that used by the parity generator 240 to generate WP <l:0>WD of bits <k:0>Count of K + 1 bits of data. In an example, M + 1 can be half of K + 1. In a specific example, M can be equal to 64 and K can be equal to 128. Thus, the semiconductor device 200 can first perform a read operation to retrieve additional data and DQ <m:0>Data combination to provide WD <k:0>Data. The read operation may include retrieving RD from a memory cell array at a location determined by the row and column addresses received by the write command <k:0>Data and P <l:0>Data. The read operation may include a syndrome generator 232, a syndrome decoder 234, and an error corrector 236, which process the RD <k:0>Data and P <l:0>Data to provide ERRB <l:0>Data, ERCP <n:0>Data and CRD <k:0>Data. Additionally, the error locator 238 can provide CORRECT <n:0>Data

[0049] For example Figure 5 Provided is an exemplary flowchart of a second mode initial read operation in accordance with an embodiment of the present invention. As Figure 5 shown, the syndrome generator 532 may receive RP from the memory cell array <l:0>Data and RD <k:0>data and can generate a PC as a response <l:0>Data. The syndrome decoder 534 may be based on the PC <l:0>Data is used to generate ERRB <l:0>Data and ERCP <n:0>Data. The error locator 538 can determine the location of the error and by decoding the ERRB <l:0>Data and ERCP <n:0>The data will be CORRECT <n:0>Data is provided to the main IO driver circuit 567. Error correction 536 can be based on ERRB <l:0>Data and ERCP <n:0>Data is used to correct RD <k:0>Data

[0050] Return Figure 2 , the IO circuit 270 can combine the CRD <m:0>Data subset (e.g., old data) vs. DQ <m:0>Data (such as new data) to provide WD <k:0>Data. The parity generator 240 can be based on WD <k:0>Data to encode WP <l:0>Data. When in the second mode, the control circuit 226 may provide complementary values on the DWDM<1:0> signals based on the value of the CA<10> bit. For example, when the CA<10> bit has a first logic value, the control circuit 226 may provide a first logic value to the DWDM<1> signal and a second logic value to DWDM<0>. When the CA<10> bit has a second logic value, the control circuit 226 may provide a second logic value to the DWDM<1> signal and a first logic value to DWDM<0>. Additionally, according to the timing of the TIME signal, the control circuit 226 may be configured to CORRECT according to the control plane associated with the enabled one of the DWDM<1:0> signals (e.g., corresponding to writing back the old data of the memory cell array) <n:0>Enable one of the CSOFF<1:0> signals when no error is detected in the corresponding subset of signals. Thus, when the DWDM<1> signal is enabled and according to the timing of the TIME signal, the control circuit 226 can be configured to respond to CORRECT corresponding to the control plane associated with the DWDM<1> signal indicating no error <n:0>Enable the CSOFF<1> signal for the first subset of signals. Otherwise, the CSOFF<1> signal can be deactivated. Similarly, when the DWDM<0> signal is enabled and according to the timing of the TIME signal, the control circuit 226 can be configured to respond to CORRECT corresponding to the control plane associated with the DWDM<0> signal indicating no error <n:0>Enable the CSOFF<0> signal for the second subset of signals. Otherwise, the CSOFF<0> signal can be disabled. The control circuit 226 can be further configured to enable the WREN signal according to the timing of the TIME signal. The timing of enabling the WREN signal and enabling one of the CSOFF<1:0> signals can coincide or occur simultaneously. Current consumption can be reduced by enabling one of the CSOFF<1:0> signals before starting a write operation (e.g., enabling the WREN signal).

[0051] The main IO write driver circuit 267 can receive CORRECT <n:0>Data, CRD <k:0>Data, WD <k:0>Data, WP <l:0>Data, DWDM<1:0> signals, WREN signals, and X4 signals. The main IO write driver circuit 267 can drive the main IO lines based on the received signals / data to WD <k:0>Writing to a memory cell array. Figure 6 is an exemplary flowchart of a second mode write operation for driving a signal to the main IO write driver circuit 267 according to an embodiment of the present invention. As Figure 6 shown, the error corrector 636 may CORRECT <l:0>Data (e.g., to indicate which bits in the data rewritten to the memory cell array 668 have changed) and CRD <k:0>The data is provided to the main IO write driver circuit 667 to CRD <k:0>A first subset of the data is provided to comparator 670, and the CRD <k:0>The remaining subset of the data is provided to the parity generator 640. The comparator 670 can compare the CRD bit by bit <k:0>The remaining subset of the data and DQ <m:0>Data in the same data signal SD that will indicate which bits are different <m:0>Provided to the main IO write driver circuit 667. The parity generator 640 can be based on DQ <m:0>Data and CRD <k:0>The first subset of data (e.g., WD <k:0>Combination of (data) to encode WP <l:0>Data. The main IO write driver circuit 667 can drive the main IO line to WD <k:0>and WP <l:0>Write to the memory cell array 668. The main IO write driver circuit 667 can use SD <m:0>The signal is only for DQ <m:0>Data and CRD <k:0>A write operation to the memory cell array 668 is performed on different bits among a first subset of data, and CORRECT may be used <l:0>Data is only available for CRD <k:0>The bit execution of the internal correction performs a write operation on the memory cell array 668.

[0052] Return Figure 2 , based on the DWDM<1:0> signal, CORRECT <l:0>Data and CRD <k:0>Data and WD <k:0>DQ within the data <m:0>The bitwise difference between the overlapping bits, the main IO write driver circuit 267 can mask the WD for matching the previously stored data <k:0>Write operation of certain bits of data. Since a read operation is performed before the write operation in the second mode, the previously stored data is available. Thus, for WD <k:0>subset of bits (which includes uncorrected (e.g., based on CORRECT <n:0>CRD of (data) <k:0>The write operation of a direct copy of a subset of data (e.g., old data) can be masked to avoid driving the main I / O signal line pair to the write voltage polarity. Additionally, for a DQ-containing <m:0>WD of data (such as new data) <k:0>The data write operation for a subset of bits can be targeted at matching the CRD <k:0>The bits of new data corresponding to bits of data (such as old data) are masked to avoid driving the main I / O signal line pair to the write voltage polarity. The current consumption during driving the main IO signal line pair and equalization can be reduced by masking the write operations for at least some of the write data bits.

[0053] Figure 3 is a schematic block diagram of the main IO write driver circuit 367 according to an embodiment of the present invention. Figure 1 the main IO write driver circuit 167 and / or Figure 2 the main IO write driver circuit 267 of can implement parts of the main IO write driver circuit 367. The main IO write driver circuit 367 may include: individual write drivers 310(0) to (7), each of which is configured to drive a corresponding pair of control plane main IO line pairs MIO CP0 to 15; and an ECC check circuit 311, which is configured to drive a pair of ECC IO signal lines.

[0054] The main IO write driver circuit 367 may receive CORRECT<15:0> data, CRD<127:0> data, WP<7:0> data, WD<127:0> data, DWDM<1:0> signal (e.g., from Figure 1 the control circuit 126 and / or Figure 2 the control circuit 226), a write enable signal WREN (e.g., from Figure 1 the control circuit 126 and / or control Figure 2 the circuit 226) and an X4 signal (e.g., from Figure 1 the CTRL signal). During a write operation, each of the write drivers 310(0) to (7) may be configured to drive the corresponding pair of MIO CP0 to 15 signal lines to write data to the control plane of the memory cell array based on the CORRECT<15:0> data, CRD<127:0> data, WP<7:0> data, WD<127:0> data, DWDM<1:0> signal, WREN signal, or a combination thereof. The ECC check circuit 311 may be configured to drive the ECC IO signal lines to write WP <l:0>Data is written to the memory cell array.

[0055] In operation, when in the first mode (e.g., the X4 signal has a low logic value indicating the x8 mode), each of the write drivers 310(0) to (7) can drive the corresponding pairs of MIO CP0 to 15 signal lines to write the WD<127:0> data to the memory cell array, where masking is performed based on the DWDM<1:0> signal, and the ECC check circuit 311 can be configured to drive the ECCIO signal lines for WP <l:0>Data is written to the memory cell array.

[0056] When in the second mode (e.g., the X4 signal has a high logic value indicating the x4 mode), each of the write drivers 310(0) to (7) can drive the corresponding pairs of MIO CP0 to 15 signal lines to write the WD<127:0> and WP<7:0> data to the memory cell array, and the ECC check circuit 311 can be configured to drive the ECC IO signal lines to write WP <l:0>Data is written to the memory cell array. However, based on the bit difference between the DWDM<1:0> signal, the CORRECT<15:0> data, and the CRD<127:0> data and the WD<127:0> data, each of the write drivers 310(0) to (7) may mask the write operation for certain bits of the WD<127:0> data that match the previously stored data bits. Since a read operation is performed before the write operation when in the second mode, the previously stored data information is available. Therefore, the data write operation for a subset of the bits of the WD<127:0> that contains a direct copy of a subset of the CRD<127:0> data can be masked for bits that have not changed (e.g., based on the CORRECT<15:0> data) to avoid driving the primary I / O signal line pair to the write voltage polarity. Additionally, the bit masking for bits corresponding to the CRD<127:0> data (e.g., old data) can be performed for bits that contain new data (e.g. Figure 2 of DQ <m:0>Data, where M equals 64) for writing a subset of the bits of WD<127:0> to avoid driving the primary I / O signal line pair to the write voltage polarity. The current consumption during driving the primary IO signal line pair and equalization can be reduced by masking the write operations for at least some of the write data bits. Although Figure 3 depicts eight write drivers 310(0) to (7), but more or fewer than eight MIO write drivers can be included without departing from the scope of the present invention. Additionally, although Figure 3 includes 128 bits of read and write data, 16 control planes, 8 bits of write parity data, etc., other combinations of read and write data, control plane count, and parity bit data can be implemented without departing from the scope of the present invention.

[0057] Figure 4 is a schematic block diagram of a part of a write driver 400 configured to control voltages on complementary primary I / O signal lines MIOT and MIOB according to an embodiment of the present invention. Figure 1 of the primary IO write driver circuit 167, Figure 2 of the primary IO write driver circuit 267 and / or Figure 3 any of the write drivers 310(0) to (7) can implement a part of the write driver 400. The write driver 400 can include a data write data masking generator 410, a first driver circuit 420, and a second driver circuit 430.

[0058] The data write data masking generator 410 can be configured to be based on DWDM <x>(e.g., Figure 1 DWDM signal and / or from Figure 2 and 3 either or both of the DWDM <1:0> signals in <y>bit (e.g. Figure 2 or Figure 3 CRD of <k:0>CRD of data <y>bit) and WD <z>bits (e.g., Figure 2 and / or Figure 3 WDs <k:0>WD of data <z>Comparison between bits) and the X4 signal configured to indicate the x4 or x8 mode to provide the internal data write data mask signal DWDM2. In some instances, Y and Z are the same corresponding bits. The data write data mask generator 410 may include an inverter 411, a "nand" gate 412, a "nand" gate 413, a "nand" gate 414, and a "nand" gate 415. The inverter 411 may invert DWDM <x>The complementary logic values of the signal are provided to the first input of NAND gate 414 and the second input of NAND gate 415. Exclusive NOR gate 412 can be in the CRD <y>bits (such as old data) and WD <z>Perform an Exclusive NOR logic comparison between bits (such as new data) and provide the result of the Exclusive NOR comparison to the first input of NAND gate 413. Thus, the output of Exclusive NOR gate 412 can indicate whether the old data matches the new data. NAND gate 413 can perform a NAND logic comparison between the X4 signal and the output of Exclusive NOR gate 412 and provide the output based on the comparison to the second input of NAND gate 414. NAND gate 414 can perform a NAND logic comparison between the output of inverter 411 and the output of NAND gate 413 and provide the output based on the comparison to the second input of NAND gate 415. NAND gate 415 performs a NAND logic comparison between the output of inverter 411 and the output of NAND gate 414 to provide DWDM2 based on the comparison.

[0059] The first driver circuit 420 and the second driver circuit 430 are configured to control the pull-down circuit 404 and the pull-up circuit 405 to drive the MIOT and MIOB signal lines to complementary logic values (e.g., based on the VSS and VPERI voltages). The MIOT and MIOB signal lines can be implemented in any of the MIOT / B signal lines of Figure 1 and / or Figure 3 the MIO CP0 to 15 signal lines of

[0060] The first driver circuit 420 can include an inverter 421, an OR gate 422, a NAND gate 423, an OR gate 424, a NAND gate 425, and an inverter 426. The OR gate 422 can be configured to perform an operation on the CRD via the inverter 421 <y>Logical complement of the bit and CORRECT <w>Signal CORRECTF <w>the logical complement (e.g., Figure 2 and / or Figure 3 CORRECT of <n:0>perform a logical "OR" comparison between any of the complements of the signals and provide the output based on the comparison to the first input of the NAND gate 423. CORRECTF having a high logic value <w>The signal indicates no bit error (e.g., no bit to be corrected), and has a low logic indicating a unit error (e.g., a bit to be corrected). The NAND gate 423 can perform a NAND logic comparison between the output of the OR gate 422 and the DWDM2 signal and provide the output based on the comparison to the first input of the NAND gate 425. The OR gate 424 can be between the DWDM2 signal and the WD <z>Perform an "OR" logic comparison between bits and provide the output based on the comparison to the second input of NAND gate 425. NAND gate 425 can perform a "NAND" logic comparison between the output of NAND gate 423, the output of OR gate 424, and the write enable signal WREN received at the third input, and provide the output based on the comparison to the first n-type transistor of the pull-down circuit 404 and the second p-type transistor of the pull-up circuit 405 via inverter 426.

[0061] The second driver circuit 430 may include inverter 431, OR gate 432, NAND gate 433, OR gate 434, NAND gate 435, and inverter 436. OR gate 432 may be configured to be at the CRD <y>Bit and CORRECTF <w>Perform a logical "OR" comparison between signals and provide the output based on the comparison to the first input of NAND gate 433. NAND gate 433 can perform a NAND logic comparison between the output of OR gate 432 and the DWDM2 signal and provide the output based on the comparison to the first input of NAND gate 435. OR gate 434 can perform an operation between the DWDM2 signal and WD via inverter 431 <z>Performs an "OR" logic comparison between the logical complements of the bits and provides the output based on the comparison to the second input of the NAND gate 435. The NAND gate 435 can perform a NAND logic comparison between the output of the NAND gate 433, the output of the OR gate 434, and the WREN signal received at the third input, and provide the output based on the comparison to the second n-type transistor of the pull-down circuit 404 and the first p-type transistor of the pull-up circuit 405 via the inverter 436.

[0062] During a write operation (e.g., when the WREN enable signal is set to a high logic value), when in the first mode (e.g., the X4 signal has a low logic value indicating the x8 mode), one of the first driver circuit 420 or the second driver circuit 430 can enable the respective transistors of each of the pull-down circuit 404 and the pull-up circuit 405 based on DWDM <x>The SIGNAL and WREN signals drive the MIOT and MIOB signal line pairs to complementary logic voltages. Inside the data write data mask generator 410, the output of the NAND gate 413 is kept high based on the X4 signal having a low logic value, which may cause the NAND gate 415 to be based on DWDM <x>The value of the signal provides the DWDM2 signal (e.g., ignoring the CRD <y>With WD <z>value of comparison between bits).

[0063] When in the second mode (e.g., the X4 signal has a high logic value indicating the x4 mode), the first driver circuit 420 and the second driver circuit 430 can drive the corresponding pairs of MIO CP0 to 15 signal lines based on DWDM <x>Signal, CRD <y>With WD <z>Comparison between bits, CORRECTF<W signal and WREN signal will WD <k:0>and WP <l:0>Data is written into the memory cell array.

[0064] For example, within the data write data masking generator 410, when DWDM <x>When the signal has a high logic value, the NAND gate 415 can provide a DWDM2 signal with a high logic value (e.g., when WD <x>bit is the old data from a read operation). When DWDM <x>When the signal has a low logic value (e.g., when WD <x>When the bit is new data, the NAND gate 415 can be based on the value WD <x>Bit and CRD <y>Provide a DWDM2 signal with a low logic value during comparison between bits. Therefore, when WD <x>Bit and CRD <y>When the bit match occurs, the NAND gate 415 can provide the DWDM2 signal with a high logic value. When WD <x>Bits and CRD <y>When the bits have different logic values, the NAND gate 415 can provide the DWDM2 signal with a low logic value.

[0065] When the DWDM2 signal has a low logic value, the first driver circuit 420 can be at WD <z>When the bit has a high logic value, drive the MIOT signal line to a high logic value (e.g., VPERI voltage) (e.g., by enabling the second p-type transistor of the pull-up circuit 405) and drive the MIOB signal line to a low logic value (e.g., VSS voltage) (e.g., by enabling the first n-type transistor of the pull-up circuit 405). When the DWDM2 signal has a high logic value, the first driver circuit 420 can be at RD <y>The bit has a high logic value and CORRECTF <w>When the signal has a low logic value, drive the MIOT signal line to a high logic value (e.g., VPERI voltage) and drive the MIOB signal line to a low logic value (e.g., VSS voltage). Otherwise, the first driver circuit 420 can deactivate the first n-type transistor of the pull-down circuit 404 and the second p-type transistor of the pull-up circuit 405 to control the voltages of the MIOB and MIOT signal lines respectively.

[0066] When the DWDM2 signal has a low logic value, the second driver circuit 430 can be in WD <z>When the bit has a low logic value, drive the MIOB signal line to a high logic value (e.g., VPERI voltage) (e.g., by enabling the first p-type transistor of the pull-up circuit 405) and drive the MIOT signal line to a low logic value (e.g., VSS voltage) (e.g., by enabling the second n-type transistor of the pull-down circuit 404). When the DWDM2 signal has a high logic value, the second driver circuit 430 can be at RD <y>bit and CORRECTF <w>When both signals have a low logic value, drive the MIOB signal line to a high logic value (e.g., VPERI voltage) and drive the MIOT signal line to a low logic value (e.g., VSS voltage). Otherwise, the first driver circuit 420 may deactivate the first n-type transistor of the pull-down circuit 404 and the second p-type transistor of the pull-up circuit 405.

[0067] Thus, overall, during the first operation mode, the data write operation is controlled by an external masking signal. Since no read operation is performed before starting the data write operation, bitwise masking in the first mode can be restricted. However, during the second operation mode, a data read operation is first performed to make the previously stored data available. Thus, for old read data that has not been corrected (e.g., via CORRECTF with a high logic value) <w>The signal) and new data for the old data where the match is not corrected are used to mask the data writing operation in the second mode. The current consumption during driving the MIOT and MIOB signal lines and equalization can be reduced by masking the writing operation for at least some of the written data bits in the second mode.

[0068] Although the "Detailed Description" describes certain preferred embodiments and examples, those skilled in the art will understand that the scope of the present invention extends beyond the specifically disclosed embodiments to other alternative embodiments and / or uses of the embodiments and their obvious modifications and equivalents. Additionally, other modifications within the scope of the present invention will be obvious to those skilled in the art. It is also contemplated that various combinations or sub-combinations of the specific features and aspects of the embodiments can be made and still fall within the scope of the present invention. It should be understood that the various features and aspects of the disclosed embodiments can be combined with or substituted for one another to form variations of the disclosed embodiments. Therefore, it is intended that at least some of the scope of the present invention should not be limited by the specifically disclosed embodiments described above.< / w> < / w> < / y> < / z> < / w> < / y> < / z> < / y> < / x> < / y> < / x> < / y> < / x> < / x> < / x> < / x> < / x> < / z> < / y> < / x> < / z> < / y> < / x> < / x> < / z> < / w> < / y> < / z> < / w> < / w> < / w> < / y> < / z> < / y> < / x> < / z> < / z> < / y> < / y> < / x> < / x> < / x> < / x>

Claims

1. A memory device, comprising: an input / output (I / O) circuit configured to, in a first operation mode, combine data corresponding to a write command received via a data terminal with a first subset of corrected read data retrieved from a memory cell array to provide write data, and configured to provide second data corresponding to a second write command received via the data terminal as second write data; and a write driver circuit configured to, in the first operation mode, mask a write operation of a first bit of the write data corresponding to the first subset of the read data and perform a write operation on a second bit of the write data corresponding to the data received via the data terminal, wherein the write driver circuit is further configured to perform a write operation to write the second write data into the memory cell array during a second operation mode.

2. The memory device according to claim 1, further comprising an error correction code (ECC) control circuit configured to receive read data and read parity data and configured to generate the corrected read data from the read data based on the read parity data.

3. The memory device according to claim 2, wherein the ECC control circuit is configured to generate syndrome data based on the read parity data and decode the syndrome data to determine a location of an error in the read data.

4. The memory device according to claim 3, wherein the write driver circuit is configured to perform a write operation on a third bit of the write data corresponding to the location of the error in the read data.

5. The memory device according to claim 3, further comprising a control circuit configured to cause a column decoder to deactivate a column select signal in response to the ECC control circuit indicating that no error is detected in the first subset of the read data.

6. The memory device according to claim 1, wherein the write driver is configured to mask a write operation of the third bit in response to a value of the third bit of the write data corresponding to the data received via the data terminal matching a value of a corresponding bit of the corrected read data.

7. The memory device according to claim 1, wherein the data received via the data terminal contains fewer bits than the corrected read data.

8. The memory device according to claim 1, wherein the data received via the data terminal in the first operation mode contains fewer bits than the second data received via the data terminal in the second operation mode.

9. The memory device according to claim 1, further comprising: a first pair of main I / O lines, wherein the write driver is configured to deactivate a first pull-up and pull-down circuitry coupled to the first pair of main I / O lines to mask the write operation associated with the first bit; and A second pair of main I / O lines, wherein the write driver is configured to enable a second pull-up and pull-down circuit system coupled to the second pair of main I / O lines to perform the write operation associated with the second bit.

10. A memory, comprising: A pair of main input / output (I / O) lines coupled to a memory cell array; A pull-up circuit configured to provide a first voltage to a selected first one of the pair of main I / O lines; A pull-down circuit configured to provide a second voltage to a selected second one of the pair of main I / O lines; And A write driver circuit configured to receive, in a first operation mode, a bit of corrected read data retrieved from the memory cell array and a bit of write data, wherein the write driver circuit is configured to deactivate the pull-up and pull-down circuits in the first operation mode in response to the bit of the corrected read data matching the bit of the write data, wherein the write driver circuit is configured to, in the first operation mode, in response to the bit of the corrected read data being different from the bit of the write data, enable the pull-up circuit to provide the first voltage to the selected first one of the pair of main I / O lines and enable the pull-down circuit to provide the second voltage to the selected second one of the pair of main I / O lines, wherein the write driver circuit is configured to receive second write data and write the second write data into the memory cell array in a second operation mode.

11. The memory according to claim 10, wherein the write driver circuit is configured to enable the pull-up circuit to provide the first voltage to the selected first one of the pair of main I / O lines and enable the pull-down circuit to provide the second voltage to the selected second one of the pair of main I / O lines in response to a corrected signal indicating an error associated with the bit of the corrected read data.

12. The memory according to claim 10, wherein the write driver circuit is configured to deactivate the pull-up and pull-down circuits in response to a data mask signal indicating that the write of the bit of the write data is masked.

13. The memory according to claim 10, wherein the write driver circuit is further configured to compare the bit of the corrected read data with the bit of the write data during a first selected operation mode.

14. The memory according to claim 10, further comprising an error correction code (ECC) control circuit configured to generate the corrected read data from the read data based on read parity data.

15. The memory according to claim 14, further comprising a control circuit configured to cause a column decoder to deactivate a column select signal in response to the ECC control circuit indicating that no error is detected in a subset of the read data.

16. A method for operating a memory, comprising: Receiving data corresponding to a write command received via a data terminal of a semiconductor device; In a first operation mode: Combine the data corresponding to the write command with a first subset of the corrected read data retrieved from the memory cell array of the semiconductor device to provide write data; A write operation that masks a first bit of the write data corresponding to the bits of the first subset of the read data via a write driver circuit; And Perform a write operation on a second bit of the write data corresponding to the data received via the data terminal; And In a second operation mode: Provide a second data corresponding to a second write command received via the data terminal as second write data; And Write the second write data to the memory cell array.

17. The method according to claim 16, further comprising: Receive read data and read parity data from the memory cell array; And Generate the corrected read data from the read data based on the read parity data.

18. The method according to claim 17, further comprising performing a write operation on a third bit of the write data corresponding to the bits that change between the read data and the corrected read data.

19. The method according to claim 16, further comprising: A write operation that masks the third bit in response to the third bit of the write data corresponding to the data received via the data terminal matching the value of the corresponding bit of the corrected read data.

20. The method according to claim 16, wherein the data received via the data terminal contains fewer bits than the corrected read data.

21. The method according to claim 16, wherein the data corresponding to the write command received via the data terminal in the first operation mode contains fewer bits than the second data received via the data terminal in the second operation mode.

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