Semiconductor device and method of operating a semiconductor device

Abstract

Semiconductor devices and methods of operating semiconductor devices are provided. The semiconductor device includes a source layer, a plurality of channel structures, a plurality of gate electrodes, and a common source line. At least one gate electrode of the plurality of gate electrodes provides a GIDL line. During an erase operation, an erase voltage applied to the common source line reaches a target voltage, and after the erase voltage reaches the target voltage, a step increment voltage is added to the erase voltage such that a voltage level of the erase voltage is higher than a voltage level of the target voltage. After the step increment voltage has been added for a desired period of time, during a remaining operation of the erase operation, the voltage level of the erase voltage is decreased to the voltage level of the target voltage.

Description

[0001] Cross-references to related applications

[0002] This patent application claims the benefit of priority to Korean Patent Application No. 10-2019-0108759, filed on September 3, 2019, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] Various example embodiments relate to semiconductor devices, systems including semiconductor devices, and / or methods of operating semiconductor devices. Background Technology

[0004] With the increasing demand for small-size, high-capacity memory devices, memory devices with vertically stacked memory cells have been actively researched. Recently, selective epitaxial growth (SEG) processes have been omitted from memory device manufacturing processes to improve integration density and reduce manufacturing costs. Therefore, various methods have been investigated to increase the efficiency of gate-induced drain leakage (GIDL) erasure. Summary of the Invention

[0005] Various example embodiments provide a semiconductor device that can increase the generation efficiency of gate-induced drain leakage (GIDL) current without causing degradation of the insulating material between the GIDL line and the vertical channel layer.

[0006] According to at least one example embodiment, a semiconductor device may include: a source layer on a substrate; a plurality of channel structures on the substrate, each of the plurality of channel structures including a vertical insulating layer and a vertical channel layer, the plurality of channel structures extending in a first direction perpendicular to an upper surface of the substrate; a plurality of gate electrodes on the source layer and spaced apart from each other along the first direction on the sidewalls of each of the plurality of channel structures, at least one of the plurality of gate electrodes being configured to provide a gate-induced drain leakage (GIDL) line; a common source line penetrating the plurality of gate electrodes, the common source line extending along the first direction and electrically connected to the source layer; and a memory controller configured to: during an erase operation, apply an erase voltage to the common source line until the erase voltage reaches a target voltage, increase the erase voltage to a desired step-boost voltage level higher than the target voltage during a desired step-boost period after the erase voltage reaches the target voltage, and decrease the erase voltage to the target voltage after the desired step-boost period has elapsed.

[0007] According to at least one example embodiment, a semiconductor device may include: a plurality of bit lines; a common source line configured to receive an erase voltage during an erase operation; at least one memory cell string connected between one of the bit lines and the common source line, the at least one memory cell string including a plurality of memory cells; at least one string select line connected to the one bit line; a gate-sensed drain-leakage (GIDL) line electrically connected to the common source line, the GIDL line being configured to receive a GIDL voltage that increases during the erase operation while maintaining a constant potential difference with the erase voltage applied to the common source line until the erase voltage reaches a target voltage; a ground select line located on the GIDL; and a plurality of word lines located between the string select line and the ground select line. During the erase operation, after the erase voltage applied to the common source line reaches the target voltage, an overshoot occurs where a voltage higher than the target voltage is applied.

[0008] According to at least one example embodiment, a semiconductor device may include: a substrate; a source layer located on an upper surface of the substrate; a plurality of gate electrode layers, the plurality of gate electrode layers including a lowermost gate electrode layer configured to provide a gate-induced drain leakage (GIDL) line; a plurality of insulating layers, the plurality of insulating layers and the plurality of gate electrode layers being alternately stacked on the source layer; a plurality of channel structures, each of the plurality of channel structures having a vertical insulating layer and a vertical channel layer, the plurality of channel structures extending in a first direction perpendicular to the upper surface of the substrate; a common source extension region, the common source extension region including a portion of the source layer extending along the vertical channel layer, the common source extension region being formed to overlap with at least a portion of the GIDL line; and a memory controller, the memory controller being configured to provide a voltage having a high voltage level to the source layer during an erase operation, the high voltage level being greater than the voltage level of an erase voltage of the erase operation.

[0009] According to at least one example embodiment, a method of operating a semiconductor device including at least one string of memory cells, the at least one string of memory cells including a plurality of memory cells, the method may include: increasing an erase voltage to a target voltage during an erase operation of the semiconductor device, the erase voltage being applied to a common source line; after the erase voltage reaches the target voltage, increasing a step increment voltage to the erase voltage for a desired period of time such that the voltage level of the erase voltage is higher than the voltage level of the target voltage; and after increasing the step increment voltage to the erase voltage, decreasing the erase voltage to the target voltage. Attached Figure Description

[0010] The above and other aspects, features, and advantages of the various exemplary embodiments of the inventive concept will become more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0011] Figure 1 It is a block diagram of a storage device according to at least one example embodiment;

[0012] Figure 2 An array of memory cells included in a memory device according to at least one example embodiment is shown;

[0013] Figure 3 This is a schematic top view illustrating a memory cell array of a three-dimensional semiconductor device according to at least one example embodiment;

[0014] Figure 4 It is according to at least one example embodiment along Figure 3 The cross-sectional view of the three-dimensional semiconductor device shown by line I-I'.

[0015] Figure 5A and Figure 5B According to at least one example embodiment Figure 4 An enlarged cross-sectional view of region "A" in the image;

[0016] Figure 6 According to at least one example embodiment Figure 4 An enlarged cross-sectional view of region "B" in the image;

[0017] Figures 7 to 9 It is a graph showing the waveforms of the erase voltage and GIDL current according to at least one example embodiment;

[0018] Figure 10 and Figure 11 It is a graph showing the waveforms of the erase voltage and GIDL current according to at least one example embodiment;

[0019] Figure 12 According to at least one example embodiment Figure 11 A magnified view of region "D" in the image;

[0020] Figure 13 A semiconductor device according to at least one example embodiment is shown;

[0021] Figure 14 and Figure 15 It is a graph showing the waveforms of the erase voltage and channel potential according to at least one example embodiment; and

[0022] Figure 16 It is a block diagram of an electronic device including a storage device according to at least one example embodiment. Detailed Implementation

[0023] In the following description, various exemplary embodiments will be illustrated with reference to the accompanying drawings. However, these exemplary embodiments may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein; rather, these exemplary embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the exemplary embodiments of the inventive concept to those skilled in the art. In the drawings, the thickness of layers and regions has been enlarged for clarity. The same figures and / or numbers denote the same elements in the drawings, and therefore their description may be omitted.

[0024] It will be understood that when an element is referred to as “connected” or “coupled” to another element, the element may be directly connected to or coupled to that other element, or there may be intermediate elements. In contrast, when an element is referred to as “directly connected” or “directly coupled” to another element, there are no intermediate elements. Other terms used to describe relationships between elements or layers should be interpreted in the same manner (e.g., “between” vs. “directly between”, “adjacent” vs. “directly adjacent”, “on” vs. “directly on”). As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items.

[0025] It will be understood that although the terms “first,” “second,” etc., may be used herein to describe various elements, components, regions, layers, and / or portions, these elements, components, regions, layers, and / or portions should not be limited by these terms. These terms are used only to distinguish one element, component, region, layer, or portion from another element, component, region, layer, or portion. Therefore, without departing from the teachings of the exemplary embodiments, the first element, component, region, layer, or portion discussed below may be referred to as the second element, component, region, layer, or portion.

[0026] For ease of description, spatial relative terms such as “below,” “under,” “below,” “above,” and “above” may be used herein to describe the relationship of an element or feature as shown in the accompanying drawings to other elements or features. It will be understood that, in addition to the orientations depicted in the drawings, spatial relative terms are also intended to include different orientations of the device during use or operation. For example, if the device in the drawings were flipped, then an element described as “below” or “below” other elements or features would be oriented as “above” other elements or features. Therefore, the term “below” can include both “above” and “below” orientations. Devices may be oriented in other orientations (rotated 90 degrees or in other orientations), and the spatial relative descriptive terms used herein shall be interpreted accordingly.

[0027] Example embodiments are described herein with reference to cross-sectional views, which are schematic diagrams of idealized embodiments (and intermediate structures) of the example embodiments. Thus, variations in the illustrated shapes are expected, for example, due to manufacturing techniques and / or tolerances. Therefore, the example embodiments should not be construed as limited to the specific shapes of the regions shown herein, but should include, for example, shape deviations caused by manufacturing processes. For example, the edges of an implantation region illustrated as rectangular may have rounded or curved features and / or a gradient of implantation concentration, rather than a binary variation from an implantation region to a non-implantation region. Similarly, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface where implantation occurs. Therefore, the regions illustrated in the figures are purely schematic, and their shapes are not intended to show the actual shapes of the regions of the device, nor are they intended to limit the scope of the example embodiments.

[0028] Although corresponding top and / or perspective views of some cross-sectional views may not be shown, the cross-sectional views of the device structures shown herein support multiple device structures extending along two different directions as shown in the top view and / or three different directions as shown in the perspective view. The two different directions may be orthogonal to each other or may not be orthogonal to each other. The three different directions may include a third direction that may be orthogonal to the two different directions. Multiple device structures may be integrated in the same electronic device. For example, when a device structure (e.g., a memory cell structure or a transistor structure) is shown in cross-section, the electronic device may include multiple device structures (e.g., a memory cell structure or a transistor structure), as shown in the top view of the electronic device. Multiple device structures may be arranged in an array and / or two-dimensional pattern.

[0029] Figure 1 It is a block diagram of a storage device according to at least one example embodiment.

[0030] Reference Figure 1 The storage device 10 according to at least one example embodiment may include a memory cell array 20 and / or a memory controller 30, etc., but the example embodiment is not limited thereto. For example, the storage device 10 may include a greater or lesser number of constituent components. The memory cell array 20 may include a plurality of memory cells, and at least a portion of the memory cells may be interconnected to provide at least one memory cell string. The memory cell array 20 may include a plurality of memory cell strings, and the plurality of memory cell strings may be divided into a plurality of blocks (e.g., memory blocks). The memory controller 30 may include control logic 31, address decoder circuitry 32, page buffer circuitry 33, input / output circuitry 34, and / or a voltage generator 35, etc., but the example embodiment is not limited thereto.

[0031] In at least one example embodiment, the address decoder circuit 32 can be connected to the memory cell MC via word line WL, serial select line SSL, ground select line GSL, etc., and the page buffer circuit 33 can be connected to the memory cell MC via bit line BL. In at least one example embodiment, the address decoder circuit 32 can select the memory cell MC to perform storage operations such as writing data, reading data, and / or erasing data, and can receive address information for selecting the memory cell MC from the control logic 31. The voltage generator 35 is configured to generate multiple control voltages, and the address decoder circuit 32 is configured to connect the multiple control voltages to the word line in response to the received address information.

[0032] Page buffer circuit 33 can perform page operations on memory cells MC of memory cell array 20, such as writing data to memory cell MC, reading data from memory cell MC, and / or erasing data from memory cell MC, and can perform page operations (e.g., writing data, reading data, erasing data, etc.) on a page-by-page basis. Page buffer circuit 33 may include multiple page buffers, and each of the multiple page buffers may be connected to at least one bit line BL. Data to be written to memory cell array 20 by page buffer circuit 33 and / or data to be read from memory cell array 20 by page buffer circuit 33 can be input / output through input / output circuit 34. The operation of address decoder circuit 32, page buffer circuit 33, input / output circuit 34, and voltage generator 35 can be controlled by control logic 31.

[0033] The memory controller 30 may include: hardware including logic circuitry; a hardware / software combination, such as at least one processor executing software; or a combination thereof. For example, the memory controller may more specifically include, but is not limited to, a central processing unit (CPU), an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field-programmable gate array (FPGA), a system-on-a-chip (SoC), a programmable logic unit, a microprocessor, an application-specific integrated circuit (ASIC), etc.

[0034] According to at least one example embodiment, the erase operation of the memory cell array 20 can be performed using a gate-induced drain leakage (GIDL) scheme, but the example embodiment is not limited thereto. The erase voltage can be generated by the memory controller 30 (e.g., by a voltage generator 35) and applied to the common source line in the memory device 10 performing the erase operation using the GIDL scheme. When the erase voltage is applied to the common source line, a voltage higher than the target voltage can be applied for a short period after the erase voltage reaches the target voltage to intentionally cause an overshoot. Therefore, the GIDL current generation efficiency can be increased and / or improved due to the increased GIDL current.

[0035] Figure 2 An array of memory cells included in a memory device according to at least one example embodiment is shown, and Figure 3 This is a schematic top view illustrating a memory cell array of a three-dimensional semiconductor device according to at least one example embodiment.

[0036] Reference Figure 2 The storage cell array includes, but is not limited to, a common source line (CSL), multiple bit lines (BL), multiple string select lines (SSL), multiple storage cell strings (CSTR) located between the common source line (CSL) and the bit lines (BL), multiple GIDL lines (GIDL), and / or multiple ground select lines (GSL).

[0037] A memory cell array may include multiple memory cells (MCs). Each memory cell (MC) can be connected to multiple word lines (WLs) and multiple bit lines (BLs) for operation. For example, each memory cell (MC) may be connected to one word line (WL) and one bit line (BL). Multiple memory cells (MCs) may be connected in series to provide a memory cell string (CSTR), but are not limited to this.

[0038] Bit lines (BLs) can be arranged in a two-dimensional manner, and multiple memory cell strings (CSTRs) can be connected in parallel to a single bit line (BL). The common source line (CSL) can be an impurity region formed in the substrate. Multiple memory cell strings (CSTRs) can be connected together to the common source line (CSL). Multiple memory cell strings (CSTRs) can be located between multiple bit lines (BLs) and the common source line (CSL).

[0039] According to some example embodiments, a common source line (CSL) may include multiple common source lines that can be arranged in a two-dimensional manner. An electrical equivalent voltage may be applied to all common source lines (CSLs), or each common source line (CSL) may be electrically controlled individually or in groups.

[0040] Each memory cell string (CSTR) may include, but is not limited to, a GIDL transistor (GDT), a ground select transistor (GST), a string select transistor (SST), and / or multiple memory cell transistors (MCT1 to MCTn). The multiple memory cell transistors (MCT1 to MCTn) may be located between the ground select transistor (GST) and the string select transistor (SST). The string select transistor (SST) may be connected to a bit line (BL) above the memory cell (MC) in the memory cell string (CSTR).

[0041] The GIDL transistor GDT can be connected to the common source line CSL below the memory cell MC. The common source line CSL can be commonly connected to the source of the GIDL transistor GDT. According to at least one example embodiment, the GIDL transistor GDT can be connected to the bit line BL above the string select transistor SST.

[0042] The series select transistor SST, multiple memory cell transistors MCT1 to MCTn, ground select transistor GST, and GIDL transistor GDT can be connected in series.

[0043] The ground select line GSL, multiple word lines WL1 to WLn, multiple string select lines SSL, and multiple GIDL lines GIDL, located between the common source line CSL and the bit line BL, can be used as the gate electrode of the ground select transistor GST, the gate electrode of the memory cell transistors MCT1 to MCTn, the gate electrode of the string select transistor SST, and the gate electrode of the GIDL transistor GDT, respectively. Furthermore, each of the memory cell transistors MCT1 to MCTn can include a data storage element.

[0044] As an example, the GIDL line (GIDL), ground select line (GSL), word lines (WL1 to WL4), and string select line (SSL) can be sequentially formed on the substrate, and a molded insulating layer can be located below and / or above each gate electrode layer. The area of ​​each gate electrode layer can decrease with increasing distance from the substrate. The bit line (BL) can be a conductive pattern (e.g., a metal line, etc.) included on the substrate at a distance from it.

[0045] Reference Figure 2 and Figure 3 The memory cell array can be isolated by word line partitions (WLCs), but is not limited to this. Additionally, the serial select lines (SSLs) within the gate electrode layer can be isolated by select line partitions (SLCs). In some example embodiments, the word line partitions (WLCs) can be configured such that the gaps are filled with one or more insulating materials. For example, such insulating materials may include at least one of silicon oxide, silicon nitride, and silicon oxynitride.

[0046] Each channel structure in a plurality of channel structures CH can be formed to penetrate the gate electrode layer and / or insulating layer, etc. The number and location of the channel structures CH are not limited to... Figure 3 Those shown, and can be modified in various ways.

[0047] In addition, the number of memory cell strings (CSTRs), word lines (WL1 to WLn), bit lines (BLs), ground select lines (GSLs), string select lines (SSLs), and GIDL lines (GIDLs) can vary according to the example embodiment.

[0048] The memory cell array according to at least one example embodiment may include, but is not limited to, a GIDL transistor GDT that performs erase operations on the memory cell array using a GIDL scheme. The GIDL transistor GDT may be located between the ground select line GSL and the common source line CSL, and is also referred to as a "lower GIDL transistor". In some example embodiments, multiple lower GIDL transistors may also be provided (e.g., two or more GIDL transistors, etc.). In some example embodiments, at least one "upper GIDL transistor" may also be included between the string select line SSL and the bit line BL, but the example embodiments are not limited to this.

[0049] In at least one example embodiment, the lower GIDL transistor can be used as a gate electrode to generate at least one hole for an erase operation. For example, when an erase voltage is applied to the common source line CSL and a GIDL voltage is applied to the GIDL line GIDL, a high electric field can be generated in the channel region adjacent to the GIDL transistor GDT due to the voltage potential difference between the erase voltage and the GIDL voltage, and holes can be generated in the channel region by this high electric field. The holes generated in the channel region can be injected into the memory cell string to perform an erase operation on multiple memory cells.

[0050] According to at least one example embodiment, when an erase voltage is applied to the common source line, a voltage higher than the target voltage can be applied for a short period after the erase voltage reaches the target voltage to intentionally cause overshoot. Therefore, the lateral field generated by the voltage potential difference between the erase voltage and the channel region can be increased. Accordingly, the GIDL current generation efficiency can be increased due to the increased GIDL current.

[0051] Figure 4 It is according to at least one example embodiment along Figure 3 The cross-sectional view of the three-dimensional semiconductor device shown is taken along line I-I'.

[0052] Reference Figure 4The semiconductor device 100 may include: a plurality of substrates, such as substrates 101, 180, and 110; a plurality of channel structures CH, the plurality of channel structures CH being perpendicular to the upper surfaces of the plurality of substrates 101, 180, and 110; a plurality of stacked structures LS, the plurality of stacked structures LS being stacked on the plurality of substrates 101, 180, and 110 adjacent to the channel structures CH, etc. However, the example embodiment is not limited thereto, and other arrangements may be used for the semiconductor device 100. The stacked structure LS may include a plurality of insulating layers 122 and a plurality of gate electrodes 130, the plurality of insulating layers 122 and the plurality of gate electrodes 130 being alternately stacked on the plurality of substrates 101, 180, and 110.

[0053] The semiconductor device 100 according to at least one example embodiment may include, but is not limited to, a first layer 101, a second layer 180, and a third layer 110, and may include more or fewer layers. The first layer 101, the second layer 180, and the third layer 110 may each comprise polysilicon doped with impurities of a first conductivity type (e.g., p-type impurities), but are not limited thereto. For example, the first layer 101, the second layer 180, and the third layer 110 may each be doped with n-type impurities, etc. For clarity and simplicity, it is assumed that the first layer 101 may be a substrate, the second layer 180 may be a source layer, and the third layer 110 may be a supporting polysilicon layer, but the example embodiment is not limited thereto.

[0054] Multiple gate electrode layers 130 may provide GIDL lines 131 and 137, a ground select line 132, a serial select line 136, and multiple word lines 135-1 to 135-n, but are not limited thereto. GIDL lines 131 and 137, ground select line 132, and serial select line 136 may, together with the channel structure CH, provide a GIDL transistor GDT, a ground select transistor GST, and a serial select transistor SST, respectively. Multiple word lines 135-1 to 135-n may be located between the ground select line 132 and the serial select line 136, and may, together with the channel structure CH, provide and / or form multiple memory cells.

[0055] Multiple gate electrode layers 130 may be isolated by a common source line CS and an insulating layer OX surrounding the side surface of the common source line CS, but are not limited thereto. The common source line CS may be formed of a conductive material such as a metal, a metal compound, and / or polysilicon. The common source line CS may be electrically isolated from the multiple gate electrode layers 130 by the insulating layer OX. The lower portion of the common source line CS that contacts the substrate 101 may actually be exposed to the substrate 101. Therefore, the common source line CS may be electrically connected to the source layer 180 and the supporting polysilicon layer 110 formed on the substrate 101 through the substrate 101. The common source line CS and the insulating layer OX may be disposed in a word line partition region, but are not limited thereto.

[0056] According to at least one example embodiment, the plurality of insulating layers 122 may include silicon layers, silicon oxide layers, silicon carbide layers, silicon oxynitride layers, and / or silicon nitride layers, etc. The plurality of gate electrodes 130 may include, but are not limited to, metals such as polycrystalline silicon or tungsten (W) and / or conductive metal nitrides.

[0057] The stacked structure LS may include a channel via formed along a third direction Z perpendicular to the upper surface of the substrate 101. A channel structure CH may be disposed in the channel via. The channel structure CH may include a vertical channel layer 160 penetrating the stacked structure LS, a buried insulating layer 150 filling the space in the vertical channel layer 160, and a vertical insulating layer 171 located between the vertical channel layer 160 and the plurality of gate electrodes 130, etc.

[0058] The channel structure CH can penetrate (e.g., through) the stacked structure LS to be electrically connected via the substrate 101 to the source layer 180 and the supporting polysilicon layer 110 formed on the substrate 101. Multiple channel structures CH can be disposed in the stacked structure LS, and the multiple channel structures CH can be arranged in a first direction X and a second direction Y, but the example embodiment is not limited thereto. Multiple channel structures can be arranged as follows: Figure 3 The zigzag pattern shown may be arranged in other patterns.

[0059] According to at least one example embodiment, the vertical channel layer 160 may have a cylindrical or prismatic shape without the buried insulating layer 150, but the example embodiment is not limited thereto. Additionally, the channel structure CH may have sloping side surfaces that narrow in the direction toward the substrate 101, depending on (and / or based on) its aspect ratio. The vertical channel layer 160 may comprise a semiconductor material such as polycrystalline silicon or monocrystalline silicon, and the semiconductor material may be undoped, but is not limited thereto.

[0060] The vertical insulating layer 171 may include, but is not limited to, a tunnel insulating layer 171c, a charge storage layer 171b, and / or a barrier layer 171a. At least a portion of the barrier layer 171a may be formed in a shape surrounding a plurality of gate electrodes 130 to be configured as a barrier layer 172, but the example embodiment is not limited thereto.

[0061] According to at least one example embodiment, the tunnel insulating layer 171c may be located between the charge storage layer 171b and the vertical channel layer 160, and the barrier layer 171a may be located between the charge storage layer 171b and the gate electrode 130, but the example embodiment is not limited thereto. For example, the charge storage layer 171b may include at least one of a silicon nitride layer, a silicon oxynitride layer, a silicon-rich nitride layer, a nanocrystalline silicon layer, and a stacked trapping layer. The tunnel insulating layer 171c may include a material with a band gap larger than that of the charge storage layer 171b. As an example, the tunnel insulating layer 171c may be a silicon oxide layer, etc. The barrier layer 171a may include a material with a band gap larger than that of the charge storage layer 171b. As an example, the barrier layer 171a may be a silicon oxide layer, a silicon nitride layer, and / or a silicon oxynitride layer, etc.

[0062] Bit line BL may be located on stacked structure LS to span the upper surface of stacked structure LS. Bit line BL may be connected to pad PD via a first contact path 193, the pad PD being located on (and / or included in) the upper end of channel structure CH. Interlayer dielectric 191 may be disposed between bit line BL and stacked structure LS, and the first contact path 193 may be formed to penetrate interlayer dielectric 191, but the example embodiment is not limited thereto. Interlayer dielectric 191 may include: a first insulating layer 191a located on stacked structure LS to cover pad PD of channel structure CH, and a second insulating layer 191b and a third insulating layer 191c located on the first insulating layer 191a to cover channel structure CH, but the example embodiment is not limited thereto.

[0063] The common source line CS can penetrate (e.g., through) the first insulating layer 191a, and a second contact passage 195 can be formed on the upper end of the common source line CS to penetrate the second insulating layer 191b, but the example embodiment is not limited thereto. An erasing voltage can be applied to the common source line CS through a terminal 197 formed on the second insulating layer 191b.

[0064] During an erase operation, the semiconductor device 100 can apply a ground voltage to the word line and an erase voltage (e.g., a voltage corresponding to the erase operation) to the common source line CS. In this case, the word line voltage can be coupled to the vertical channel layer 160 through a vertical insulating layer 171 inserted between the word line and the vertical channel layer 160. Due to the coupling effect, the same ground voltage as the word line voltage can be applied to the vertical channel layer 160 adjacent to the word line.

[0065] The semiconductor device 100 according to at least one example embodiment can intentionally cause an overshoot (e.g., voltage overshoot) by applying a voltage higher than the target voltage for a short period after the erase voltage applied through the common source line CS reaches the target voltage. The short period of overshoot can be relative to and / or compared to the period of time the erase voltage of the erase operation of the semiconductor device and / or the voltage of other input / output operations (e.g., read operations, write operations, etc.) are applied; for example, the period of overshoot can be shorter than the period of time the erase voltage of the erase operation of the semiconductor device or the voltage of other input / output operations are applied. Therefore, the lateral electric field generated by the potential difference (e.g., voltage difference) between the erase voltage and the voltage applied to the vertical channel layer 160 can be increased. Therefore, holes migrating from the source layer 180 to the vertical channel layer 160 can migrate more quickly, and the absolute amount of holes migrating from the source layer 180 to the vertical channel layer 160 can be increased. Therefore, the GIDL current can be increased to reduce the erase voltage. Therefore, the lifespan of semiconductor devices and / or products can be increased because the electrical stress on the vertical insulating layer 171 can be reduced.

[0066] Figure 5A and Figure 5B According to at least one example embodiment Figure 4 An enlarged cross-sectional view of region "A" in the image.

[0067] Reference Figure 5A At least one common source extension region 181 (in which the source layer 180 extends along the vertical channel layer 160) may be formed in the semiconductor device. For example, the common source extension region 181 may be formed to overlap with a portion of the GIDL line 131, but is not limited thereto.

[0068] For ease of description and clarity, we will assume a GIDL voltage (e.g., V). GIDL =0V) is applied to GIDL line 131, and the erase voltage (e.g., V) is applied. ers =6V) is applied to source layer 180, but the example embodiment is not limited to this. The erase voltage V applied to source layer 180 ersIt can also be applied to the common source extension region 181. Therefore, a potential difference (e.g., a voltage difference) can occur between the GIDL line 131 and the common source extension region 181.

[0069] Reference Figure 5B A potential difference can occur in the vertical insulating layer 171 where the common source extension region 181 and the GIDL line 131 overlap. This potential difference can correspond to, but is not limited to, the potential difference that occurs between the GIDL line 131 and the common source extension region 181. Because the potential difference occurs in the vertical insulating layer 171, interband tunneling occurs at the junction surface of the vertical channel layer 160 and the common source extension region 181.

[0070] Electrons in the portion of the vertical channel layer 160 near the common source extension region 181 can migrate to the common source extension region 181 due to interband tunneling. Holes can be formed at the locations of the electrons that migrated to the common source extension region 181 in the vertical channel layer 160. Therefore, an electrically isolated region can be formed in the vertical channel layer 160 that overlaps with the GIDL line 131 to generate holes. The electrically isolated region can accumulate generated holes or release accumulated holes.

[0071] Figure 6 yes Figure 4 An enlarged cross-sectional view of region "B" in the image, and Figures 7 to 9 It is a graph showing the waveforms of the erase voltage and GIDL current according to at least one example embodiment.

[0072] Reference Figure 6 Erasure voltage V ers The source layer 180 can be applied during the erase operation of the semiconductor device, but the example embodiment is not limited thereto. For example, the erase voltage V ers The target voltage (e.g., the desired voltage) can be 15V, but is not limited to this, and can be set to any suitable voltage for performing the erase operation on the desired semiconductor device. During the erase operation of the semiconductor device, the GIDL voltage V... GIDL It can be applied to GIDL line 131. GIDL voltage V GIDL It can be used with the erase voltage V ers While maintaining a constant and / or near-constant potential difference, it is applied, but the example embodiments are not limited thereto, and according to at least one example embodiment, V GIDL With V ers The potential difference between them can vary during the step-up period. In other words, the GIDL voltage V GIDL It can have the same voltage as the erase voltage V ersThe same rate of change. During the erase operation of a semiconductor device, the word line voltage V... WL It can be applied to word line 135-1. For example, word line voltage V. WL It can be 0V, but the example implementation is not limited to this.

[0073] Reference Figure 6 and Figure 7 According to at least one example embodiment, when the erase voltage V ers Step-up voltage increase (e.g., increasing) until the erase voltage V ers When the target voltage is reached, the GIDL voltage V GIDL It can be used with the erase voltage V ers A step boost is achieved while maintaining a constant (and / or near-constant) potential difference. In other words, the GIDL voltage V GIDL It can be compared with the erase voltage V ers The erase voltage V increases at the same rate. ers The magnitude and pulse width of the second unit step voltage can be correlated with the GIDL voltage V, respectively. GIDL The magnitude of the first unit step voltage is the same as the pulse width. For example, when the erase voltage V... ers The voltage is boosted from 0V to 15V in a stepwise manner until the erase voltage V is reached. ers When the target voltage is reached, the GIDL voltage V GIDL It is possible to step up from -11V to 4V, but the example embodiment is not limited to this. Therefore, the GIDL voltage V GIDL During the erase operation of a semiconductor device, the erase voltage V can be used. ers Maintain a constant (and / or nearly constant) potential difference ΔV1.

[0074] Reference Figure 6 and Figure 8 The total erase time t of the semiconductor device ers This can include a step-up boost phase and an execution phase. The erase voltage (e.g., V) ers =0 to 15V, etc.) can be applied to the source layer 180 during the step-up phase (e.g., the period during which a step-up voltage is applied). Figure 8 As shown, the erase voltage V ers This can be a step voltage. For example, the increment of the step voltage could be 0.5V, but it is not limited to this. Semiconductor devices can make the erase voltage V... ers Step-up voltage increase (and / or increase) until the erase voltage V ers The target voltage (e.g., 15V) can be achieved from 0V, but the example embodiment is not limited to this.

[0075] return Figure 6During the step boost phase, the GIDL voltage (e.g., V) GIDL =-11V to 4V) can be applied to GIDL line 131. For example, GIDL voltage V GIDL The potential can be greater than the erasure voltage V. ers Low first voltage (e.g., 11V, etc.). For example, when the erase voltage V... ers The GIDL voltage V is increased by a step-up (e.g., by increasing) until the erase voltage reaches the target voltage. GIDL It can be used with the erase voltage V ers While maintaining a constant (and / or near-constant) potential difference (e.g., 11V), a step boost (e.g., increase) is performed. Thus, a first potential difference (e.g., 11V) can appear between the GIDL line 131 and the source layer 180, but is not limited thereto.

[0076] When a first potential difference appears between the GIDL line 131 and the source layer 180, interband tunneling can occur at the junction surface of the vertical channel layer 160 and the common source extension region "a", as shown in the reference. Figure 5B As described.

[0077] Due to the interband tunneling effect, electrons in the vertical channel layer 160 near the common source extension region "a" can migrate to the common source extension region "a". Holes (+) can be generated at the location of the electrons that migrate to the common source extension region. According to at least one example embodiment, an isolation region can be formed in the portion of the vertical channel layer 160 that overlaps with the GIDL line 131. Holes (+) can accumulate in the isolation region. As the first potential difference between the GIDL line 131 and the source layer 180 increases, the absolute amount of holes (+) accumulated in the isolation region can increase.

[0078] Word line voltage (e.g., V) WL =0V) can be applied to word line 135-1 during the step boost phase. Since the string select transistor is off, the vertical channel layer 160 can be in a floating state. In this case, the word line voltage V WL It can be coupled to the vertical channel layer 160, with the vertical insulating layer 171 inserted between the word line 135-1 and the vertical channel layer 160. Due to the coupling effect, it is related to the word line voltage V. WL The same voltage can be applied to the vertical channel layer “b” adjacent to word line 135-1. Therefore, a second potential difference (e.g., 0V to 15V) can occur between the common source extension region “a” and the vertical channel layer “b” adjacent to word line 135-1, but the example embodiment is not limited thereto.

[0079] When a second potential difference occurs between the common source extension region “a” and the vertical channel layer “b” adjacent to word line 135-1, the holes (+) accumulated in the isolation region can migrate along the vertical channel layer 160 to word line 135-1.

[0080] As an example, the erase voltage V ers The voltage can be stepped up (e.g., increased, incrementally increased, and / or gradually increased, etc.) during the step-up phase (e.g., during the voltage increase phase) until the erase voltage V. ers The target voltage (e.g., 15V) is reached from 0V. Therefore, the second potential difference that appears between the common source extension region “a” and the vertical channel layer “b” adjacent to word line 135-1 can gradually increase from the initial voltage (e.g., 0V) to the target voltage (e.g., 15V), but is not limited thereto.

[0081] The greater the second potential difference between the common source extension region “a” and the vertical channel layer “b” adjacent to word line 135-1, the faster holes can migrate from the isolation region to word line 135-1.

[0082] During the execution period, holes (+) in the vertical channel layer “b” adjacent to word line 135-1 can migrate to the charge storage layer 171b adjacent to word line 135-1. At the start of the execution period, a third potential difference may appear between the vertical channel layer “b” adjacent to word line 135-1 and the charge storage layer 171b.

[0083] Figure 9 According to at least one example embodiment Figure 8 An enlarged view of region "C" in the image.

[0084] Reference Figure 9 When the erase voltage V ers During the step-up voltage increase (e.g., from 0V to 0.5V), a second potential difference can occur between the common source extension region “a” and the vertical channel layer “b” adjacent to word line 135-1. Due to this second potential difference, holes accumulated in the isolation region can migrate along the vertical channel layer 160 toward word line 135-1.

[0085] With the emergence of a second potential difference, the channel potential P at vertical channel layer 160... CH It can increase rapidly. Then, as the holes (+) accumulated in the isolation zone migrate toward word line 135-1, the channel potential P of the vertical channel layer 160 increases. CH It can be increased slowly. Therefore, the channel potential P CH With erase voltage V ers The gap between them can gradually decrease, and the GIDL current I generated by the migration of holes... GIDLIt can increase instantly, and then decrease exponentially.

[0086] Figure 10 and Figure 11 It is a graph showing the waveforms of the erase voltage and GIDL current according to at least one example embodiment, and Figure 12 According to at least one example embodiment Figure 11 An enlarged view of region "D" in the image.

[0087] Figures 10 to 12 Erasure voltage V ers and Figures 7 to 9 Erasure voltage V ers Different. The erase voltage V applied to the source layer 180 during the step boost phase. ers Once the target voltage (e.g., 15V) is reached, overshoot can be intentionally caused by applying a voltage higher than the target voltage for a short period of time.

[0088] In this specification, the term "overshoot" can refer to the phenomenon where, during the erase voltage V... ers After reaching the target voltage (e.g., 15V), an additional unit step voltage is intentionally applied, causing the erase voltage V to... ers The erase voltage V is higher than the target voltage, and after applying an additional unit step voltage, the erase voltage V ers Intentionally step down to the target voltage.

[0089] According to at least one example embodiment, when an additional unit step voltage is intentionally applied, the erase voltage V is... ers During step-down voltage reduction, the erase voltage V after step-down voltage reduction is... ers It can be higher than the target voltage. According to at least one example embodiment, when an additional, intentionally applied unit step voltage is applied, the erase voltage V... ers During step-down voltage reduction, the erase voltage V after step-down voltage reduction is... ers It can be lower than the target voltage.

[0090] Reference Figure 10 When the erase voltage V ers The voltage is stepped up within time t1 until the erase voltage V is reached. ers When the target voltage is reached, the GIDL voltage V GIDL It can be used with the erase voltage V ers A step-up voltage increase is achieved while maintaining a constant (and / or near-constant) potential difference. Erase voltage V ers The magnitude and pulse width of the second unit step voltage can be correlated with the GIDL voltage V, respectively. GIDL The magnitude of the first unit step voltage is the same as the pulse width. For example, when the erase voltage V... ers The voltage is boosted from 0V to 15V in a step-up manner, until the erase voltage V.ers When the target voltage is reached, the GIDL voltage V GIDL It is possible to step up from -11V to 4V, but the example embodiment is not limited to this. Therefore, within time t1, the GIDL voltage V GIDL Can be used with erase voltage V ers Maintain a constant (and / or nearly constant) potential difference ΔV1.

[0091] Erasing voltage V ers During the time interval t1 to t2 after the target voltage (e.g., 15V) is reached, an additional unit step voltage OS can be intentionally applied to increase the erase voltage V. ers Higher than the target voltage. After another intentional application of a unit step voltage OS, the erase voltage V... ers It is possible to intentionally step down the voltage to the target voltage. GIDL voltage V GIDL It can be independent of the erase voltage V ers Instead of a step-up boost, the voltage can be maintained at time t1. Therefore, during the time interval from t1 to t2, the GIDL voltage V... GIDL Can be used with erase voltage V ers Maintain a constant (and / or nearly constant) potential difference ΔV2. The potential difference ΔV2 maintained during time t1 to t2 can be greater than the potential difference ΔV1 maintained during time t1.

[0092] After time t2, the erase voltage V drops step-down to the target voltage. ers The target voltage can be maintained. This is because the GIDL voltage V... GIDL The voltage can remain constant (and / or nearly constant) after time t1, therefore the GIDL voltage V GIDL It can be after time t2 and the erase voltage V ers Maintain a constant (and / or near-constant) potential difference ΔV1. During the erase operation, the upper limit and / or maximum magnitude of the required erase voltage Vers can be greater than the erase voltage V maintained after time t2. ers Size.

[0093] According to at least one example embodiment, the absolute amount of holes (+) accumulating in the isolation region can increase due to the increased potential difference maintained during time t1 to t2. Furthermore, holes (+) can accumulate in the isolation region more quickly due to the increased rate of electron migration from the vertical channel layer to the common source extension region.

[0094] Reference Figure 11 The total erase time t of the semiconductor device ers This can include a step-boost period and an execution period. During the step-boost period, the erase voltage (e.g., V) is applied. ers=0 to 15V) can be applied to the source layer. Erase voltage V ers The voltage can be stepped up until the erase voltage V is reached. ers From an initial voltage (e.g., 0V) to a target voltage (e.g., 15V).

[0095] Even at the erase voltage V ers After reaching the target voltage (e.g., 15V), the erase voltage V... ers It is also possible to additionally step up the voltage N times (N is an integer greater than or equal to 1) to have a voltage higher than the target voltage (e.g., 15V) (e.g., 15V + N*h, where h is the step increment (also known as the size of the unit step voltage)), but the example embodiment is not limited to this. At the erase voltage V ers After N additional step boosts, the erase voltage V ers It can be stepped down again to the target voltage (e.g., 15V).

[0096] According to at least one example embodiment, the semiconductor device can make the erase voltage V ers Step-up boost, until the erase voltage V ers From an initial voltage (e.g., 0V) to a target voltage (e.g., 15V). The absolute amount of holes (+) accumulated in the isolation region can be measured by the erase voltage V. ers The erase voltage increases due to overshoot after the target voltage is reached. Therefore, even when the same GIDL current is generated, the erase voltage can be reduced, and the electrical stress applied to the insulating material can be reduced. This can thus increase the lifespan of semiconductor devices and / or products.

[0097] Additionally, at the erase voltage V ers The overshoot that occurs after the target voltage is reached increases the rate at which electrons in the vertical channel layer migrate to the common source extension region. Therefore, holes (+) can accumulate in the isolation region more quickly. Consequently, even when the same erase voltage is applied (e.g., the same magnitude of erase voltage), the erase time can be reduced.

[0098] Reference Figure 11 and Figure 12 At the erase voltage V ers Once the target voltage (e.g., 15V) is reached, an additional unit step voltage can be applied to increase the erase voltage V. ers Higher than the target voltage. After applying an additional unit step voltage, the erase voltage V ers It can be stepped down again to the target voltage. When the erase voltage V ers When overshoot OS (e.g., overshoot voltage) exists, the channel potential P is greater than when there is no overshoot OS. CH It can increase more quickly. Therefore, the channel potential P CHIt can quickly follow the erase voltage V ers .

[0099] According to at least one example embodiment, the pulse width w' of the additionally applied unit step voltage OS can be related to the erase voltage V. ers The pulse width w of the unit step voltage is the same, but the example embodiments are not limited thereto. According to at least one example embodiment, the magnitude h' of the additionally applied unit step voltage OS can be the same as the erase voltage V. ers The magnitude h of the unit step voltage is the same, but the example embodiment is not limited to this.

[0100] According to at least one example embodiment, the pulse width w' of the additionally applied unit step voltage OS can be related to the erase voltage V. ers The pulse width w of the unit step voltage is different. According to at least one example embodiment, the magnitude h' of the additionally applied unit step voltage OS can be different from the erase voltage V. ers The magnitude h of the unit step voltage is different.

[0101] For example, the pulse width w' of the additional applied unit step voltage OS can be the total erase time t. ers The required percentage (e.g., 10% or less) of the target erase voltage (e.g., 15V) and the size h' of the additional applied unit step voltage OS can be a required percentage (e.g., 10% or less) of the target erase voltage (e.g., 15V), but the example embodiment is not limited thereto.

[0102] The semiconductor device according to at least one example embodiment may include being configured to apply an erase voltage V. ers An erase voltage generator is applied to the memory cell array. According to at least one example embodiment, the erase voltage generator may be included in the memory controller 30, but is not limited thereto. The semiconductor device may also include additional circuitry, such as an overshoot voltage generator, for implementing and / or generating an overshoot to apply a voltage higher than the target voltage V to the erase voltage V for a short period of time. ers According to at least one example embodiment, the overshoot voltage generator may be included in the memory controller 30, but is not limited thereto. As an example, the semiconductor device may also include a capacitor additionally connected to the erase voltage generator to provide the overshoot voltage, but is not limited thereto. As the voltage is charged and discharged in the capacitor, the erase voltage V... ers The voltage can be further stepped up N times, and then stepped down again to the target voltage. However, according to some example embodiments, the erase voltage generator can also generate and provide an overshoot voltage. Therefore, the voltage generator 35 included in the memory controller 30 may include an erase voltage generator and additional circuitry for implementing and / or generating an overshoot.

[0103] In a semiconductor device according to at least one example embodiment, when the erase voltage V ers When applied to the memory cell array, even with the erase voltage V ers After reaching the target voltage, a DC pulse can be applied for a short period of time. Therefore, the erase voltage V ers It can be further boosted N times in a step manner, and then stepped down again to the target voltage.

[0104] Figure 13 A semiconductor device according to at least one example embodiment is shown.

[0105] Reference Figure 13 The semiconductor device may include, but is not limited to, a vertical channel layer 160, a source layer 180, and / or a GIDL line 131.

[0106] The vertical channel layer 160 may contain undoped semiconductor material, etc. The source layer 180 may be a source region of a first conductivity type. For example, the first conductivity type may be N-type, but is not limited thereto. The source layer 180 may be a common source extension region in which a source region of the first conductivity type formed on the substrate extends along the vertical channel layer 160, but is not limited thereto. The GIDL line 131 may provide at least one GIDL transistor.

[0107] During the erase operation of the semiconductor device, a GIDL voltage (e.g., V) can be generated by voltage generator 35 or a separate GIDL voltage generator (not shown). GIDL = -11V to 4V), and the GIDL voltage can be applied to the GIDL line 131, and the erase voltage (e.g., V) ers A voltage (e.g., 0V to 15V) can be applied to the source layer 180. The erase operation of the semiconductor device can include a step-boost period and an execution period. The erase voltage (e.g., V) ers =0V to 15V) can be applied to the source layer 180 during the step boost period.

[0108] When the erasure voltage V ers When applied to source layer 180 during the step-boost period, overshoot operation is possible to apply a voltage higher than the target voltage (e.g., 15V) for the desired overshoot period (e.g., overshoot time and / or short time, etc.). Therefore, the erase voltage V ers The voltage can be increased to be higher than the target voltage (e.g., 15V) during the overshoot period. Therefore, the erase voltage V applied to the source layer 180 can be increased. ers The transverse electric field generated by the potential difference between the voltage (e.g., 0V) applied to the vertical channel layer 160 and the voltage applied to the vertical channel layer 160.

[0109] According to at least one example embodiment, holes (+) can accumulate in the isolation region of the vertical channel layer 160 due to a first potential difference occurring between the GIDL line 131 and the source layer 180. The absolute amount of holes (+) accumulated in the isolation region can increase when the lateral electric field between the source layer 180 and the vertical channel layer 160 is enhanced. Furthermore, holes (+) can accumulate in the isolation region more rapidly when the lateral electric field between the source layer 180 and the vertical channel layer 160 is enhanced.

[0110] The vertical electric field between the GIDL line 131 and the vertical channel layer 160 is enhanced to induce the generation of GIDL current. However, in order to enhance the vertical electric field in a conventional semiconductor device, the voltage applied to the GIDL line 131 is increased, which leads to the degradation and / or deterioration of the insulating material between the GIDL line 131 and the vertical channel layer 160.

[0111] However, the semiconductor device according to one or more example embodiments may introduce an overshoot period: during a short time, the erase voltage V applied to the source layer 180... ers Apply a voltage higher than the target voltage, then erase the voltage V. ers The voltage is then stepped down again to the target voltage. Therefore, the efficiency of GIDL current generation can be improved without deteriorating the insulation material between the GIDL line 131 and the vertical channel layer 160.

[0112] Because the erase voltage can be reduced as the GIDL current increases, the electrical stress applied to the insulating material can be reduced. Therefore, the lifespan of semiconductor devices and / or products can be increased. Additionally, even with the same erase voltage applied, the erase time (e.g., the time required to perform the erase operation) can be reduced.

[0113] Figure 14 and Figure 15 It is a graph showing the waveforms of the erase voltage and channel potential according to at least one example embodiment. Figure 14 At least one example embodiment is shown, wherein the erase voltage V ers Step boost until erase voltage V ers From an initial voltage (e.g., 0V) to a target voltage (e.g., V) target =15V). Figure 15 The erase voltage V is shown. ers Achieving the target voltage (e.g., V) without a step boost. target At least one example embodiment of (=15V).

[0114] Reference Figure 14 During the erase operation of a semiconductor device, the erase voltage V can be... ersAfter reaching the target voltage (e.g., 15V), an overshoot erase voltage with a unit step pulse width w1 and a unit step voltage magnitude h1 is applied. The overshoot erase voltage can be stepped up N times. At the erase voltage V... ers After N additional step boosts, the erase voltage V ers It can be stepped down again to the target voltage. Therefore, when the erase voltage V ers When overshoot OS exists, the channel potential P is different from that when overshoot OS does not exist. CH It can be increased more quickly.

[0115] As mentioned above, the unit step pulse width w1 of the overshoot erase voltage can be, for example, the total erase time t. ers 10% or less, and the unit step voltage magnitude h1 of the overshoot erase voltage can be, for example, the target erase voltage (e.g., V). target =10% or less of 15V, but the example embodiments are not limited to this.

[0116] Reference Figure 15 During the erase operation of a semiconductor device, an erase voltage V can be applied first. ers An overshoot erase voltage with a unit step pulse width w2 and a unit step voltage magnitude h2 is applied. The overshoot erase voltage can be stepped up N times. At the erase voltage V... ers After N additional step boosts, the erase voltage V ers It can be stepped down again to the target voltage.

[0117] As mentioned above, the unit step pulse width w2 of the overshoot erase voltage can be, for example, the total erase time t. ers 10% or less, and the unit step voltage magnitude h2 of the overshoot erase voltage can be, for example, the target erase voltage (e.g., V). target =10% or less of 15V, but the example embodiments are not limited to this.

[0118] Figure 16 It is a block diagram of an electronic device including a storage device according to at least one example embodiment.

[0119] Figure 16 The electronic device 1000 shown according to at least one example embodiment may include a display 1010, an image sensor 1020, a memory 1030, a port 1040, at least one processor 1050, etc. The electronic device 1000 may also include wired / wireless communication devices, a power supply, etc. Figure 16In the components shown, port 1040 can be a device configured for electronic device 1000 to communicate with video cards, sound cards, memory cards, Universal Serial Bus (USB) devices, etc. Electronic device 1000 can be a comprehensive concept including smartphones, tablet PCs, smart wearable devices, as well as general desktop PCs, laptop PCs, etc.

[0120] The processor 1050 can perform specific operations, commands, tasks, etc. The processor 1050 can be a central processing unit (CPU) or a microprocessor unit (MCU), and can communicate with the display 1010, the image sensor 1020, the memory 1030, and other devices connected to the port 1040 via the bus 1060.

[0121] The memory 1030 may be a non-transitory computer-readable storage medium configured to store data and / or multimedia data required for the operation of the electronic device 1000. The memory 1030 may include volatile memory such as random access memory (RAM) and / or non-volatile memory such as flash memory. Additionally, the memory 1030 may include at least one of solid-state drives (SSDs), hard disk drives (HDDs), and / or optical disc drives (ODDs) as storage devices. The memory 1030 may include, according to the above references... Figures 1 to 15 The storage device described is any of the various example embodiments described, but is not limited thereto.

[0122] As described above, according to at least one example embodiment, the generation efficiency of the GIDL current can be increased by introducing an overshoot period where the erase voltage applied to the source layer is increased to above the target voltage for a short period, and then stepped down to the target voltage. Therefore, the efficiency of the GIDL erase operation can be improved without causing degradation of the insulating material.

[0123] Although various exemplary embodiments have been shown and described above, it will be apparent to those skilled in the art that modifications and variations may be made without departing from the scope of the inventive concept as defined by the appended claims.

Claims

1. A semiconductor device comprising: a source layer on a substrate; a plurality of channel structures on the substrate, each of the plurality of channel structures including a vertical insulating layer and a vertical channel layer, the plurality of channel structures extending in a first direction perpendicular to an upper surface of the substrate; a plurality of gate electrodes on the source layer and spaced apart from each other in the first direction on sidewalls of each of the plurality of channel structures, at least one of the plurality of gate electrodes configured to provide a gate-induced drain leakage line; a common source line penetrating the plurality of gate electrodes, the common source line extending in the first direction and electrically connected to the source layer; and a storage controller configured to, during an erase operation, apply an erase voltage to the common source line until the erase voltage reaches a target voltage, increase the erase voltage to a required step-up voltage at a voltage level higher than the voltage level of the target voltage for a required step-up period after the erase voltage reaches the target voltage, and decrease the erase voltage to the target voltage after the required step-up period elapses. the voltage level of the required step-up voltage is at least two step increments higher than the voltage level of the target voltage.

2. The semiconductor device of claim 1, wherein, 3. The semiconductor device of claim 1, wherein, a portion of the source layer extends along the vertical channel layer in a common source extension region; and the common source extension region overlaps at least a portion of the gate-induced drain leakage line.

4. The semiconductor device of claim 1, further comprising: an insulating layer surrounding a side surface of the common source line, wherein the plurality of gate electrodes are electrically isolated from each other by the insulating layer. the storage controller is further configured to increase the erase voltage by stepping up the erase voltage until the erase voltage reaches the target voltage.

5. The semiconductor device of claim 1, wherein, a pulse width of the boost of the erase voltage during the required step-up period is equal to a pulse width of a unit step voltage used to step up the erase voltage.

6. The semiconductor device of claim 5, wherein, a voltage magnitude of the boost of the erase voltage during the required step-up period is equal to a voltage magnitude of a unit step voltage used to step up the erase voltage.

7. The semiconductor device of claim 5, wherein, a pulse width of the boost of the erase voltage during the required step-up period is different from a pulse width of a unit step voltage used to step up the erase voltage.

8. The semiconductor device of claim 5, wherein, a voltage magnitude of the boost of the erase voltage during the required step-up period is different from a voltage magnitude of a unit step voltage used to step up the erase voltage.

9. The semiconductor device of claim 5, wherein, a pulse width of the boost of the erase voltage during the required step-up period is 10% or less of a total duration of the erase operation.

10. The semiconductor device of claim 1, wherein, a voltage magnitude of the boost of the erase voltage during the required step-up period is 10% or less of the target voltage.

11. The semiconductor device of claim 1, wherein, the storage controller is further configured to:

12. The semiconductor device of claim 1, wherein, ​ increasing a gate-induced drain leakage voltage applied to the gate-induced drain leakage line until the erase voltage reaches the target voltage, the gate-induced drain leakage voltage being increased while maintaining a constant potential difference with the erase voltage.

13. A semiconductor device comprising: a plurality of bit lines; a common source line configured to receive an erase voltage during an erase operation; at least one string of memory cells connected between one of the plurality of bit lines and the common source line, the at least one string of memory cells including a plurality of memory cells; at least one string select line connected to the one of the plurality of bit lines; a gate-induced drain leakage line electrically connected to the common source line, the gate-induced drain leakage line configured to receive a gate-induced drain leakage voltage, the received gate-induced drain leakage voltage being increased while maintaining a constant potential difference with the erase voltage during the erase operation until the erase voltage reaches a target voltage; a ground select line on the gate-induced drain leakage line; and a plurality of word lines between the string select line and the ground select line; wherein, during the erase operation, an overshoot occurs in which the erase voltage is higher than the target voltage after the erase voltage applied to the common source line reaches the target voltage.

14. The semiconductor device of claim 13, further comprising: a string select transistor connected to the string select line, the string select transistor configured to be in an off state during the erase operation. the plurality of word lines configured to receive a ground voltage during the erase operation.

15. The semiconductor device of claim 13, wherein, the gate-induced drain leakage voltage is increased at a first unit step voltage while maintaining a constant potential difference with the erase voltage when the erase voltage is increased at a second unit step voltage until the erase voltage reaches the target voltage.

16. The semiconductor device of claim 13, wherein, 17. A semiconductor device comprising: a substrate; a source layer on an upper surface of the substrate; a plurality of gate electrode layers including a lowermost gate electrode layer configured to provide a gate-induced drain leakage line; a plurality of insulating layers stacked on the source layer alternately with the plurality of gate electrode layers; a plurality of channel structures each having a vertical insulating layer and a vertical channel layer, the plurality of channel structures extending in a first direction perpendicular to the upper surface of the substrate; a common source extension region including a portion of the source layer extending along the vertical channel layer, the common source extension region formed to overlap at least a portion of the gate-induced drain leakage line; and a memory controller configured to provide a voltage having a high voltage level to the source layer during an erase operation, the high voltage level being greater than a voltage level of an erase voltage of the erase operation. the memory controller is further configured to: ​ 18. The semiconductor device of claim 17, wherein, ​ a continuously increasing gate-induced drain leakage voltage is generated during a first period of the erase operation, the continuously increasing gate-induced drain leakage voltage maintaining a first potential difference from the erase voltage until the erase voltage reaches a target voltage, wherein a lateral electric field is generated based on the first potential difference between the gate-induced drain leakage voltage and the erase voltage; during a second period of the erase operation after the erase voltage reaches the target voltage, a voltage level of the erase voltage is increased by at least one step increment above a voltage level of the target voltage, the increasing of the voltage level of the erase voltage including establishing a second potential difference between the erase voltage and the gate-induced drain leakage voltage, the second potential difference being greater than the first potential difference, wherein the lateral electric field is enhanced by the second potential difference; after the voltage level of the erase voltage is increased, the erase voltage is decreased to the target voltage; and during a third period of the erase operation after the second period, the erase voltage is maintained at the target voltage, the maintaining of the erase voltage including maintaining the first potential difference between the erase voltage and the gate-induced drain leakage voltage.

19. The semiconductor device of claim 18, wherein, The first potential difference causes a portion of the vertical channel layer to accumulate holes as electrons of the vertical channel layer migrate toward the common source extension region.

20. The semiconductor device of claim 19, wherein, The second potential difference increases a speed at which the electrons of the vertical channel layer migrate toward the common source extension region.

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