semiconductor packages

Abstract

A semiconductor package is provided. The semiconductor package includes: a package substrate having a first surface, a second surface disposed opposite to the first surface and having a recess, and a through-hole having a side surface inclined relative to the first surface, wherein a first diameter of a first opening of the through-hole defined through the first surface is smaller than a second diameter of a second opening of the through-hole defined through the bottom surface of the recess; a plurality of first semiconductor chips disposed on the first surface; a second semiconductor chip disposed on the bottom surface; and a molding portion disposed in the through-hole and covering the plurality of first and second semiconductor chips.

Description

[0001] This application claims priority from Korean Patent Application No. 10-2019-0106026 filed on August 28, 2019, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0002] Apparatuses and methods consistent with example embodiments relate to a semiconductor package. Background Art

[0003] As the electronics industry continues to evolve, the demand for increasingly high-performance, high-speed, and compact electronic components continues to grow. In response, technologies have emerged that stack and mount semiconductor chips on a single semiconductor substrate. However, this technique results in thicker semiconductor packages with poor bonding stability. Summary of the Invention

[0004] Example embodiments provide a semiconductor package capable of reducing an overall package thickness and molding semiconductor chips mounted on both sides of a package substrate using a single process.

[0005] According to one aspect of an example embodiment, a semiconductor package includes: a package substrate having a first surface, a second surface opposite to the first surface and having a recess, and a through-hole having side surfaces inclined relative to the first surface, wherein a first diameter of a first opening of the through-hole defined through the first surface is smaller than a second diameter of a second opening of the through-hole defined through a bottom surface of the recess; a plurality of first semiconductor chips disposed on the first surface; a second semiconductor chip disposed on the bottom surface; and a molding portion disposed in the through-hole and covering the plurality of first and second semiconductor chips. Each of the plurality of first semiconductor chips includes a memory chip, and the second semiconductor chip includes an application processor.

[0006] According to one aspect of an example embodiment, a semiconductor package includes: a package base having a first surface, a second surface opposite to the first surface and having a recess, and a through hole having a side surface inclined relative to the first surface, a first diameter of a first opening of the through hole defined through the first surface being smaller than a second diameter of a second opening of the through hole defined through a bottom surface of the recess, and the bottom surface of the recess defining a groove extending from the through hole to the side surface of the recess; a plurality of first semiconductor chips arranged on the first surface; a second semiconductor chip arranged on the bottom surface; and a molding portion arranged in the through hole and the groove and covering the plurality of first and second semiconductor chips.

[0007] According to one aspect of an example embodiment, a semiconductor package includes: a package substrate having a first surface including a first region and a second region, a second surface opposite to the first surface and having a recess, and a through-hole having a side surface inclined relative to the first surface, wherein a first diameter of a first opening of the through-hole defined through the first surface is smaller than a second diameter of a second opening of the through-hole defined through a bottom surface of the recess, and the through-hole is disposed in the second region; a plurality of first semiconductor chips disposed on the first region; a second semiconductor chip disposed on the bottom surface and overlapping the through-hole; and a molding portion disposed in the through-hole and covering the plurality of first and second semiconductor chips. Each of the plurality of first semiconductor chips includes a memory chip, and the second semiconductor chip includes an application processor. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The above and other aspects, features and advantages will be more clearly understood from the following detailed description of example embodiments with reference to the accompanying drawings, in which:

[0009] Figure 1 is a side cross-sectional view of a semiconductor package according to example embodiments;

[0010] Figure 2 According to an example embodiment Figure 1 an enlarged view of part A;

[0011] Figure 3 According to an example embodiment Figure 1 a layout diagram of a top portion of a semiconductor package;

[0012] Figure 4 According to an example embodiment Figure 1 a layout diagram of a bottom portion of a semiconductor package;

[0013] Figure 5 FIG. 1 is a diagram illustrating removing the second semiconductor chip therefrom according to example embodiments. Figure 4 a view of a package substrate;

[0014] Figure 6 is a graph showing warpage of a semiconductor package;

[0015] Figures 7 to 9 A semiconductor package according to an exemplary embodiment is shown;

[0016] Figure 10 is a view illustrating a package substrate from which a second semiconductor chip is removed according to example embodiments;

[0017] Figure 11 is a side cross-sectional view of a semiconductor package according to example embodiments; and

[0018] Figure 12 According to an example embodiment Figure 11 An enlarged view of part B. DETAILED DESCRIPTION

[0019] Hereinafter, example embodiments will be described in detail with reference to the accompanying drawings.

[0020] Reference Figures 1 to 5 , a semiconductor package according to example embodiments will be described. Figure 1 is a side cross-sectional view of a semiconductor package 10 according to an example embodiment, Figure 2 yes Figure 1 An enlarged view of part A of FIG. Figure 3 yes Figure 1 The layout diagram of the top of the semiconductor package 10 is shown in FIG. Figure 4 yes Figure 1 Layout diagram of the bottom of the semiconductor package 10. Figure 5 is a diagram showing the second semiconductor chip 300 being removed therefrom. Figure 4 FIG. 1 is a view of a package substrate 100 .

[0021] Reference Figure 1 and Figure 2 , a semiconductor package 10 according to example embodiments includes a package substrate 100 , a first semiconductor chip 200 , a second semiconductor chip 300 , and a molding part 400 .

[0022] The package substrate 100 includes a first surface 101 and a second surface 102, the second surface 102 being opposite to the first surface 101 and provided with a recess 110. The package substrate 100 may be a single-layer printed circuit board. The package substrate 100 may be a multi-layer printed circuit board and may include, for example, a passive component 170 such as a capacitor. The second surface 102 may be provided with ball lands 140, and a bump 150 may be attached to each of the ball lands 140. In an example embodiment, the thickness D1 of the package substrate 100 may be at least 460 μm.

[0023] Reference Figure 1 and Figure 3The first surface 101 of the package substrate 100 may include a first region 101A and a second region 101B. The first semiconductor chip 200 may be disposed in the first region 101A. The first semiconductor chip 200 may be attached to the package substrate 100 in the first region 101A. For example, the lowermost portion of the first semiconductor chip 200 may be in contact with the package substrate 100. The through-holes 120 may pass through the first surface 101 and the second surface 102 of the second region 101B of the package substrate 100. A first connection pad 160 electrically connected to the first semiconductor chip 200 using a wire bonding method may be provided in the second region 101B. The first region 101A may overlap with the recess 110 in the region 101C.

[0024] The first semiconductor chip 200 may be a memory chip of the same type, for example, a memory chip with the same capacity. The memory chip may be a phase change random access memory (PRAM), a resistive random access memory (RRAM), a magnetic random access memory (MRAM), a dynamic random access memory (DRAM), a flash memory, or the like. The first semiconductor chip 200 may be provided as a plurality of layers stacked on the first surface 101 of the package substrate 100, and may be bonded and fixed to each other by an adhesive layer 220. In an example embodiment, the first semiconductor chip 200 may be electrically connected to the first connection pad 160, respectively, by a wiring bonding method. That is, the chip pads 210 of the first semiconductor chip 200 may be connected to the first connection pad 160, respectively, by wiring 500.

[0025] Reference Figure 1 and Figure 4 , the recess 110 may be formed in a central region of the second surface 102. However, example embodiments are not limited thereto, and the recess 110 may be provided in other locations that do not contact the side surface of the package substrate 100. Figure 4 The second semiconductor chip 300 is removed. Figure 5 , the second connection pads 130 on which the second semiconductor chip 300 is mounted may be provided on the bottom surface 111 of the recess 110. The second connection pads 130 may be electrically connected to the first connection pads 160 through internal wiring inside the package substrate 100. Ball lands 140 to which bumps 150 are attached may be provided in the periphery of the recess 110. In addition, through-holes 120 are formed through the bottom surface 111 of the recess 110.

[0026] The recess 110 may be large enough to accommodate the second semiconductor chip 300 therein. That is, the recess may have a size larger than that of the second semiconductor chip 300 so that when the second semiconductor chip 300 is disposed in the recess 110, the sidewall 112 of the recess 110 does not contact the second semiconductor chip 300 (see FIG. Figure 2In some example embodiments, the recess 110 may be formed to have a depth D2 that allows the upper surface 301 of the second semiconductor chip 300 mounted thereon to be exposed. However, example embodiments are not limited thereto, and the depth D2 of the recess 110 may be changed to a depth that allows the upper surface 301 of the second semiconductor chip 300 to protrude or be recessed.

[0027] Figure 4 It is shown that the concave portion 110 is quadrilateral, but example embodiments are not limited thereto. According to other example embodiments, the concave portion may have various polygonal shapes, such as a triangle and a pentagon.

[0028] The package substrate 100 may include a plurality of recesses 110, and a plurality of second semiconductor chips 300 may be disposed in the plurality of recesses 110. For example, the number of recesses 110 may be the same as the number of second semiconductor chips 300. In this case, each recess 110 may be large enough to allow a single second semiconductor chip 300 to be mounted thereon.

[0029] Figure 6 FIG. 1 is a diagram showing that the second semiconductor chip 300 having various thicknesses D3 is mounted on the recess 110 having a thickness D1 of 460 μm of the package substrate 100 (see FIG. 1 ). Figure 1 and Figure 2 ). The warpage occurring in each semiconductor package 10 was measured based on temperature variation and thickness D3. Temperature variation during the semiconductor package manufacturing process is shown along the horizontal axis. As the temperature varied, warpage within a range of +120 μm to -120 μm occurred in each semiconductor package 10.

[0030] As mentioned above Figures 1 to 5 As discussed, a single second semiconductor chip 300 may be disposed in a single recess 110. However, example embodiments are not limited thereto. Figures 7 to 9 Semiconductor packages according to additional example embodiments are shown. Figure 7 A semiconductor package 20 according to an example embodiment is shown. Figure 7 In some example embodiments, a plurality of second semiconductor chips 2300 may be mounted on a single recess 2110. A first region 2101A and a second region 2101B are provided in the first surface 2101 of the semiconductor package 20, and a through hole 2120 is formed in the second region 2101B. This is substantially similar to the example embodiment described previously, and thus a detailed description thereof will be omitted.

[0031] Figure 8 A semiconductor package 30 according to an example embodiment is shown. Figure 8In some example embodiments, a plurality of recesses 3110 may be provided on the second surface 3102 of the semiconductor package 30, and a second semiconductor chip 3300 may be provided in each recess 3110. In this case, the recess 3110 may be provided to connect the first semiconductor chips 3200. That is, a single recess 3110 may be provided to have an area overlapping with two first semiconductor chips 3200. Furthermore, a through-hole 3120 may be provided in each of the plurality of recesses 3110. This is substantially similar to the example embodiments described previously, and therefore a detailed description thereof will be omitted.

[0032] Reference Figure 1 and Figure 2 , the second semiconductor chip 300 can be mounted on the bottom surface 111 of the recess 110. The lower surface 302 of the second semiconductor chip 300 can be provided with a die pad 310. The die pad 310 of the second semiconductor chip 300 can be mounted on the second connection pad 130 provided on the bottom surface 111 of the recess 110. For example, the die pad 310 and the second connection pad 130 can be connected by solder 320 in a flip-chip bonding method. Therefore, the second semiconductor chip 300 can be mounted on the bottom surface 111 of the recess 110 so that the lower surface 302 of the second semiconductor chip 300 on which the die pad 310 is provided is arranged to face away from the upper surface of the semiconductor package 10. When the second semiconductor chip 300 is mounted in the flip-chip bonding method, a distance D4 of approximately 45 μm can be provided between the second semiconductor chip 300 and the bottom surface 111 of the recess 110.

[0033] In an example embodiment, the second semiconductor chip 300 may be an application processor. Thus, in an example embodiment, a memory chip is provided on the first surface 101 of the package substrate 100, and a system-in-package (SIP) structure in which the application processor is provided in the recess 110 of the second surface 102 may be provided. Thus, compared to a package-on-package (POP) structure in which each of the memory chip and the application processor is mounted on a separate package substrate and then stacked, the overall thickness of the semiconductor package 10 may be reduced, and the number of electrical paths between the memory chip and the application processor may be reduced. In an example embodiment, the thickness D3 of the second semiconductor chip 300 may be 100 μm to 200 μm.

[0034] As discussed above, the through hole 120 passing through the first surface 101 and the second surface 102 can be provided in the bottom surface 111 of the recess 110. The through hole 120 can be large enough to allow the resin solution used to form the molding part 400 to pass through the through hole 120. Therefore, in the process of molding the first semiconductor chip 200 mounted on the first surface 101, the resin solution can be injected through the through hole 120, so that the second semiconductor chip 300 provided in the recess 110 can be molded at the same time as the first semiconductor chip 200. In example embodiments, the through hole 120 is provided in the central region of the recess 110, but example embodiments are not limited thereto. Alternatively, the through hole can be provided in the peripheral region of the recess 110.

[0035] Figure 9 FIG. 4 shows a semiconductor package 40 according to an example embodiment. In some example embodiments, as shown in FIG. Figure 9 As shown in , a plurality of through holes 4120 may be provided, and the plurality of through holes 4120 may be provided along the peripheral area of ​​the recess 4110. In this case, in the process of manufacturing the semiconductor package 40 by molding the first semiconductor chip 4200 mounted on the first surface 4101, a resin solution may be injected through the peripheral area of ​​the second semiconductor chip 4300. Therefore, compared with the case where the through holes are formed in the central area of ​​the recess, the pressure applied to the mounted second semiconductor chip 4300 can be reduced during the process of injecting the resin solution. In addition, the through holes 4120 may be provided so as not to overlap with the first semiconductor chip 4200, thereby reducing the application of pressure to the first semiconductor chip 4200 during the process of injecting the resin solution.

[0036] Figure 10 is a view showing a package substrate from which a second semiconductor chip is removed according to example embodiments. Figure 10 In some example embodiments, grooves 5121 connected to the through-holes 5120 may be provided on the bottom surface 5111 of the recess 5110. In this case, during the process of forming the molding portion of the semiconductor package 50, the resin solution injected through the through-holes 5120 can be more quickly dispersed into the recess 5110 through the grooves 5121. The grooves 5121 may be formed to extend from the through-holes 5120 to the sidewalls of the recess 5110. The grooves 5121 may be provided between the second connection pads 5130 provided on the bottom surface 5111. As shown, four grooves 5121 having a linear form are provided in the periphery of the through-holes 5120, however, example embodiments are not limited thereto. Alternatively, the number and arrangement of the grooves 5121 may vary. The recess 5110 is formed in the second surface 5102, and the bumps 5150 are provided in the periphery of the recess 5110. This is substantially similar to the example embodiments described previously, and therefore a detailed description thereof will be omitted.

[0037] like Figure 1 As shown in , the molding part 400 can cover the first semiconductor chip 200 and the second semiconductor chip 300, and can fill the through hole 120. The molding part 400 can be formed by molding an epoxy resin solution. The package substrate 100 on which the first semiconductor chip 200 and the second semiconductor chip 300 are mounted can be set in a mold, and a transfer molding process of pressing the resin solution into the mold can be performed to form the molding part 400. The resin solution can be injected toward the first surface 101 of the package substrate 100, and the recess 110 formed in the second surface 102 of the package substrate 100 can be filled with the through hole 120. Therefore, the first surface 101 and the second surface 102 of the package substrate 100 can be molded simultaneously by a single molding process.

[0038] Reference Figure 11 and Figure 12 , a semiconductor package according to example embodiments will be described. Figure 11 is a side cross-sectional view of a semiconductor package 600 according to example embodiments, Figure 12 yes Figure 11 FIG6 is an enlarged view of a portion B of a semiconductor package 600. Compared to the previously described semiconductor package 10, the through hole 6120 has a different shape, and the redistribution layer 6600 is disposed on the second surface 6102 of the package substrate 6100. To avoid duplication of description, the differences will be mainly described.

[0039] In example embodiments, the through hole 6120 may be narrower along the first surface 6101 of the package substrate 6100 than along the second surface 6102 of the package substrate 6100. For example, the through hole 6120 may have an inclined side surface. That is, the side surface 6121 of the through hole 6120 may be inclined relative to the first surface 6101 and the second surface 6102. Figure 11As shown in , the side surface of the through-hole 6120 may be inclined from the second surface 6102 toward the first surface 6101 toward the center of the through-hole 6120. Therefore, the dimension W2 of the bottom surface of the through-hole 6120 exposed to the recess 6110 may be larger than the dimension W1 of the through-hole 6120 exposed to the first surface 6101. In other words, the cross-sectional area of ​​the through-hole 6120 exposed to the bottom surface of the recess 6110 may be larger than the cross-sectional area of ​​the through-hole 6120 exposed to the first surface 6101. Because the dimension W1 of the through-hole 6120 exposed to the first surface 6101 into which the resin solution is injected is smaller than the dimension W2 of the bottom surface of the through-hole 6120 exposed to the recess 6110, the pressure per unit area applied during the process of injecting the resin solution from the first surface 6101 to the second surface 6102 through the through-hole 6120 can be reduced. When forming the molded portion 6400 by transfer molding, the package substrate 6100 is placed in a mold, and a resin solution is injected into the mold under high pressure. If excessive pressure is applied to the second semiconductor chip 6300 during this process, cracks may occur in the solder 6320, and loose connection of the second semiconductor chip 6300 may occur. Due to the inclined shape of the through hole 6120, excessive pressure applied to the mounted second semiconductor chip 6300 during the process of injecting the resin solution can be reduced, and the adhesive force of the second semiconductor chip 6300 mounted on the second surface 6102 can be prevented from being weakened.

[0040] The redistribution layer 6600 is attached to the second surface 6102 of the package substrate 6100 and may cover the second semiconductor chip 6300. The redistribution layer 6600 is disposed in a lower portion of the second semiconductor chip 6300, and thus the bumps 6150 and the ball pads 6140 may also be disposed in a lower portion of the second semiconductor chip 6300.

[0041] As set forth above, according to example embodiments, the overall thickness of a semiconductor package may be reduced, and semiconductor chips mounted on both sides of a package substrate may be molded using a single process.

[0042] While example embodiments have been shown and described above, it will be apparent to those skilled in the art that modifications and variations can be made without departing from the spirit and scope of the disclosure as defined by the appended claims.

Claims

1. A semiconductor package, comprising: a package substrate having a first surface, a second surface opposite to the first surface and having a recess, and a through-hole having a side surface inclined relative to the first surface, wherein a first diameter of a first opening of the through-hole defined through the first surface is smaller than a second diameter of a second opening of the through-hole defined through a bottom surface of the recess; A plurality of first semiconductor chips are arranged on the first surface; a second semiconductor chip disposed on the bottom surface of the recess; as well as a molding part provided in the through hole and covering the plurality of first semiconductor chips and the second semiconductor chip, Each of the plurality of first semiconductor chips includes a memory chip, and the second semiconductor chip includes an application processor.

2. The semiconductor package according to claim 1 , further comprising a redistribution layer disposed on the second semiconductor chip. in, The second semiconductor chip is disposed between the redistribution layer and the first surface.

3. The semiconductor package according to claim 1, wherein The package substrate includes passive components.

4. The semiconductor package according to claim 1, wherein The recess overlaps the plurality of first semiconductor chips.

5. The semiconductor package according to claim 1, wherein The recess is one of a plurality of recesses from the second surface, The second semiconductor chip is a second semiconductor chip from a plurality of second semiconductor chips, and The plurality of second semiconductor chips are respectively arranged on the plurality of recesses. The semiconductor package according to claim 5 , wherein: Each of the plurality of recesses overlaps the plurality of first semiconductor chips.

7. The semiconductor package according to claim 1, wherein The second semiconductor chip is one second semiconductor chip from among a plurality of second semiconductor chips, and The plurality of second semiconductor chips are arranged on the concave portion.

8. The semiconductor package according to claim 1, wherein A plurality of connection pads are provided on the bottom surface, wherein the second semiconductor chip includes a plurality of chip pads electrically connected to the plurality of connection pads, and The plurality of chip pads do not overlap with the through holes.

9. The semiconductor package according to claim 1, wherein The through hole is one through hole from among a plurality of through holes provided in the package substrate, and The plurality of through holes are arranged opposite to each other in a peripheral area of ​​the bottom surface.

10. The semiconductor package according to claim 1, wherein The recess is one recess from a plurality of recesses provided in the second surface, The second semiconductor chip is a second semiconductor chip from a plurality of second semiconductor chips, and The number of the plurality of recesses corresponds to the number of the plurality of second semiconductor chips.

11. The semiconductor package according to claim 1, wherein The through hole is provided in a central area of ​​the bottom surface.

12. The semiconductor package according to claim 1, wherein The molding part covers side surfaces and upper surfaces of the plurality of first semiconductor chips and side surfaces of the second semiconductor chip.

13. The semiconductor package according to claim 12, wherein The molding part covers an upper surface of the second semiconductor chip.

14. The semiconductor package according to claim 1, wherein The bottom surface defines a groove, and the groove is filled with the molding.

15. The semiconductor package according to claim 14, wherein The groove extends from the through hole to a side surface of the recess.

16. A semiconductor package, comprising: a package substrate having a first surface, a second surface opposite to the first surface and having a recess, and a through-hole having a side surface inclined relative to the first surface, wherein a first diameter of a first opening of the through-hole defined through the first surface is smaller than a second diameter of a second opening of the through-hole defined through a bottom surface of the recess, and the bottom surface of the recess defines a groove extending from the through-hole to the side surface of the recess; A plurality of first semiconductor chips are arranged on the first surface; a second semiconductor chip disposed on the bottom surface of the recess; as well as A molding part is provided in the through hole and the groove and covers the plurality of first semiconductor chips and the second semiconductor chip.

17. The semiconductor package according to claim 16, wherein A first cross-sectional area of ​​the first opening is smaller than a second cross-sectional area of ​​the second opening.

18. The semiconductor package according to claim 16, wherein The side surface of the through hole is inclined toward a center of the through hole from the second surface toward the first surface.

19. The semiconductor package according to claim 16, wherein The through-via does not overlap with the plurality of first semiconductor chips.

20. A semiconductor package, comprising: a package substrate having a first surface including a first region and a second region, a second surface opposite to the first surface and having a recess, and a through-hole having a side surface inclined relative to the first surface, wherein a first diameter of a first opening of the through-hole defined through the first surface is smaller than a second diameter of a second opening of the through-hole defined through a bottom surface of the recess, and the through-hole is provided in the second region; a plurality of first semiconductor chips, disposed on the first region; a second semiconductor chip disposed on a bottom surface of the recess and overlapping the through hole; as well as a molding part provided in the through hole and covering the plurality of first semiconductor chips and the second semiconductor chip, Each of the plurality of first semiconductor chips includes a memory chip, and the second semiconductor chip includes an application processor.

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