A chip package

Abstract

The present invention provides a chip package, which includes a lead frame, a chip component arranged on the lead frame, and a packaging layer for packaging the chip component. The lead frame has a first surface and a second surface opposite to each other, and the chip component is arranged on the first surface of the lead frame. A pin hole is arranged on the packaging layer. It also includes a heat dissipation component arranged on the second surface of the lead frame. The heat dissipation component includes a heat sink, an adhesive layer for bonding the heat sink to the second surface of the lead frame, and an insulating block arranged between the heat sink and the second surface and used to isolate the heat sink and the second surface. The insulating block is opposite to the ejector pin. During the packaging process of the chip package, even if the ejector pin applies a large pressure to the lead frame through the ejector pin hole, the lead frame will not press through the adhesive layer, thereby preventing the lead frame from contacting the heat sink and preventing the chip from short-circuiting. Moreover, under the large pressure applied by the ejector pin to the lead frame, the lead frame can also fully contact with the adhesive layer to ensure the heat dissipation performance of the chip.

Description

Technical Field

[0001] The present invention relates to the technical field of chip packaging, and in particular to a chip packaging component. Background Art

[0002] IGBT (Insulated Gate Bipolar Transistor) module is a modular semiconductor product made by connecting multiple IGBT chips and FRD chips (Freewheeling diode) in a specific circuit bridge and packaging method. It has the advantages of compact structure, high reliability and easy installation, which helps to achieve high reliability integrated layout in high-power module applications.

[0003] Since the module integrates the IGBT chip, FRD chip and driver in one package, it ensures that the whole product has higher reliability and greatly reduces the size of the equipment. However, in order to obtain higher current handling capacity, the number of chips connected in parallel is increased, and the heat loss generated by the device during operation will be too concentrated, which will increase the difficulty of heat dissipation. Therefore, appropriate measures must be taken to suppress the heat accumulation of the module during operation. This need has spawned a new technology in the field of power semiconductors - heat dissipation technology.

[0004] refer to Figure 1 In order to fully dissipate the heat of the chip 1 inside the module, a copper insulating sheet 3 will be bonded under the lead frame 2 to which the chip 1 is welded during the packaging process. The copper insulating sheet 3 is composed of a layer of epoxy resin 4 and a layer of copper heat sink 5. The epoxy resin 4 is mainly used to isolate the lead frame 2 from contacting the copper heat sink 5 to achieve insulation isolation between the lead frame 2 and the copper heat sink 5. And under a certain pressure, the epoxy resin 4 can fully contact with the lead frame 2, which will make the heat dissipation performance of the chip 1 better. However, when the pressure is too high, the lead frame 2 will press through the epoxy resin 4, causing the lead frame 2 to contact the copper heat sink 5, resulting in a short circuit of the chip 1. During the packaging process, a ejector pin 6 will be used on one side of the lead frame 2 to press against the lead frame 2 to give the lead frame 2 a certain pressure so that the epoxy resin 4 can fully contact with the lead frame 2. However, during the packaging process, the pressure applied by the ejector pin 6 on the lead frame 2 and the depth of the lead frame 2 embedded in the epoxy resin 4 are difficult to control. If the pressure applied by the ejector pin 6 on the lead frame 2 is too great, it is easy to cause contact between the lead frame 2 and the copper heat sink 5, thereby causing a short circuit in the chip 1; if the pressure applied by the ejector pin 6 on the lead frame 2 is too small, the lead frame 2 and the epoxy resin 4 cannot be fully contacted, thereby reducing the heat dissipation performance of the chip 1. Summary of the invention

[0005] The invention provides a chip package to prevent conductive connection between a lead frame and a heat sink.

[0006] The present invention provides a chip package, which includes a lead frame, a chip component arranged on the lead frame, and a packaging layer for packaging the chip component. The lead frame has a first surface and a second surface opposite to each other, and the chip component is arranged on the first surface of the lead frame. A pin hole is arranged on the packaging layer. The chip package also includes a heat dissipation component arranged on the second surface of the lead frame. The heat dissipation component includes a heat sink, an adhesive layer for bonding the heat sink to the second surface of the lead frame, and an insulating block arranged between the heat sink and the second surface and used to isolate the heat sink and the second surface. The insulating block is opposite to the pin hole.

[0007] In the above scheme, an insulating block for isolating the heat sink from the second surface of the lead frame is provided between the second surface of the lead frame and the heat sink, and the insulating block is opposite to the ejector hole. Thus, during the packaging process of the chip package, even if the ejector applies a large pressure to the lead frame through the ejector hole, the lead frame will not press through the adhesive layer, thereby preventing the lead frame from contacting the heat sink, thereby preventing the chip from short-circuiting. Moreover, even when the ejector applies a large pressure to the lead frame, the lead frame can still fully contact the adhesive layer, thereby ensuring the heat dissipation performance of the chip.

[0008] In a specific embodiment, the insulating block is embedded in the heat sink and the adhesive layer to facilitate the arrangement of the insulating block.

[0009] In a specific embodiment, a first groove is provided on a side of the heat sink facing the adhesive layer, and a second groove is provided on a side of the adhesive layer facing the heat sink. The first groove is opposite to the second groove, and the insulating block is provided in the first groove and the second groove. In the above manner, the insulating block is conveniently embedded between the heat sink and the adhesive layer.

[0010] In a specific embodiment, the insulating block is interference-fitted in the first groove to facilitate assembly of the insulating block.

[0011] In a specific embodiment, the first groove and the second groove are both rectangular grooves, so as to facilitate the cutting of grooves on the heat sink.

[0012] In a specific embodiment, the length of the first groove is L1, and the length of the heat sink is L2, wherein L1≤1 / 5L2, so as to improve the bonding stability between the heat sink and the adhesive layer.

[0013] In a specific implementation, the depth of the first groove is D1, and the thickness of the heat sink is H1, wherein D1≤1 / 2H1, so as to prevent the heat sink from breaking due to local thinness.

[0014] In a specific implementation, the depth of the second groove is D2, and the depth of the adhesive layer is H2, wherein D2≤1 / 2H2, so as to ensure the stability of the bonding between the adhesive layer and the lead frame.

[0015] In a specific embodiment, the insulating block is made of a thermally conductive material to improve the heat dissipation performance of the chip. When the insulating block is specifically arranged, the insulating block may be made of ceramic to prevent the pressure exerted by the ejector pin on the lead frame from crushing the insulating block.

[0016] In a specific embodiment, the insulating block is in the shape of a cube to facilitate the arrangement of the insulating block.

[0017] In a specific embodiment, the heat sink is a copper heat sink to improve the heat dissipation performance of the chip and save costs.

[0018] In a specific embodiment, the material of the adhesive layer is epoxy resin to improve the bonding stability and thermal conductivity between the lead frame and the heat sink.

[0019] In a specific implementation, the lead frame is a copper frame to save cost. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 It is a schematic diagram of the structure of a chip package in the prior art;

[0021] Figure 2 A schematic structural diagram of a chip package provided by an embodiment of the present invention.

[0022] Reference numerals:

[0023] 10- lead frame 11- first surface 12- second surface

[0024] 20- chip assembly 30- packaging layer 31- ejector pin hole

[0025] 32-thrust pin 41-heat sink 411-first groove

[0026] 42-adhesive layer 421-second groove 50-insulating block DETAILED DESCRIPTION

[0027] In order to make the purpose, technical solutions and advantages of the present invention more clear, the present invention will be further described in detail below with reference to the accompanying drawings.

[0028] In order to facilitate the understanding of the chip package provided by the embodiment of the present invention, its application scenario is first explained. The chip package can be a power module package such as but not limited to an IGBT module, and can also be other types of chip packages. The chip package provided by the embodiment of the present invention is described in detail below in conjunction with the accompanying drawings.

[0029] refer to Figure 2 The chip package provided by the embodiment of the present invention includes a lead frame 10 and a chip assembly 20 arranged on the lead frame 10. The lead frame 10 is a conventional frame structure used to arrange chips in the prior art, and can be a copper frame to save costs. Figure 2 The lead frame 10 shown has a first surface 11 and a second surface 12 relative to each other. A chip assembly 20 is arranged on the first surface 11 of the lead frame 10. The chip assembly 20 may include a chip, which may specifically be an IGBT chip, or an FRD chip, or other types of chips. Two chips may also be arranged on the chip assembly 20, for example, an IGBT chip and an FRD chip may be arranged on the first surface 11 of the lead frame 10. It should be understood that the number of chips included in the chip assembly 20 is not limited to the above-mentioned method, and other methods may be used in addition to this. In addition, when the chip assembly 20 is specifically arranged on the first surface 11 of the lead frame 10, soldering may be adopted, or other methods may be adopted.

[0030] refer to Figure 2 A packaging layer 30 is further provided on the first surface 11 of the lead frame 10 and the chip assembly 20 to encapsulate the chip assembly 20. In specific configuration, the material of the packaging layer 30 can be epoxy resin, silica gel, or other materials that can encapsulate chips in the prior art.

[0031] Continue to refer Figure 2 In order to improve the heat dissipation performance of the chip, a heat dissipation component for dissipating heat from the chip component 20 is provided on the second surface 12 of the lead frame 10. Figure 2 The heat dissipation assembly shown includes a heat sink 41, which can be a copper heat sink 41, an aluminum heat sink 41, an alloy heat sink 41 or other metal sheet to improve the heat dissipation performance of the chip and save costs.

[0032] In addition, to prevent the heat sink 41 from contacting the lead frame 10, the heat sink 41 is bonded to the second surface 12 of the lead frame 10 through the bonding layer 42. In the specific configuration, the material of the bonding layer 42 can be epoxy resin, which can achieve heat conduction between the lead frame 10 and the heat sink 41, thereby improving the heat dissipation performance of the chip assembly 20, and prevent the lead frame 10 from contacting the heat sink 41, thereby causing the chip assembly 20 to short-circuit. It should be understood that the material of the bonding layer 42 is not limited to the epoxy resin shown above. In addition, other insulating materials that can bond the heat sink 41 and the lead frame 10 can also be used.

[0033] When the heat sink 41 is disposed on the second surface 12 of the lead frame 10, in order to make the lead frame 10 and the adhesive layer 42, and the adhesive layer 42 and the heat sink 41 more reliably bonded, refer to Figure 2 The ejector pin 32 is pressed against the first surface 11 of the lead frame 10, so that the lead frame 10 is subjected to downward (by Figure 2 The chip package shown is used as a reference) so that the second surface 12 of the lead frame 10, the adhesive layer 42 and the heat sink 41 are pressed together, thereby improving the stability of the bonding between the heat sink 41 and the lead frame 10. Figure 2 The packaging layer 30 has an ejector hole 31 for an ejector pin 32 to pass through. The ejector pin 32 passes through the ejector hole 31 and is pressed against the first surface 11 of the lead frame 10 .

[0034] In order to prevent the ejector pin 32 from pressing too much pressure on the lead frame 10, causing the lead frame 10 to be embedded too deeply into the adhesive layer 42, thereby causing the heat sink 41 to contact the lead frame 10, refer to Figure 2 , an insulating block 50 for isolating the heat sink 41 and the second surface 12 is provided between the heat sink 41 and the second surface 12, wherein the insulating block 50 is opposite to the ejector hole 31. By providing the insulating block 50 for isolating the heat sink 41 and the second surface 12 between the second surface 12 of the lead frame 10 and the heat sink 41, and the insulating block 50 is opposite to the ejector hole 31, in this way, during the packaging process of the chip package, even if the ejector pin applies a large pressure to the lead frame 10 through the ejector hole 31, the lead frame 10 will not press through the adhesive layer 42, thereby preventing the lead frame 10 from contacting the heat sink 41, thereby preventing the chip from short-circuiting. And under the large pressure applied by the ejector pin 32 to the lead frame 10, the lead frame 10 can also fully contact with the adhesive layer 42, thereby ensuring the heat dissipation performance of the chip.

[0035] During installation, the insulating block 50 can be embedded in the heat sink 41 and the adhesive layer 42 to facilitate the installation of the insulating block 50. Figure 2, a first groove 411 can be provided on the side of the heat sink 41 facing the adhesive layer 42, and a second groove 421 can be provided on the side of the adhesive layer 42 facing the heat sink 41. The first groove 411 and the second groove 421 are located opposite to each other, so that the insulating block 50 is arranged in the first groove 411 and the second groove 421. In the above manner, it is convenient to embed the insulating block 50 between the heat sink 41 and the adhesive layer 42. When the insulating block 50 is specifically fixed in the first groove 411 and the second groove 421, the insulating block 50 can be interference fitted in the first groove 411 to facilitate the assembly of the insulating block 50; the insulating block 50 can also be bonded in the first groove 411 and the second groove 421 by gluing to facilitate the fixing of the insulating block 50 in the first groove 411 and the second groove 421.

[0036] In addition, the first groove 411 and the second groove 421 can both be rectangular grooves, and the first groove 411 is opposite to the ejector hole 31, so as to facilitate the groove on the heat sink 41. Figure 2 , the length of the first groove 411 (in Figure 2 The left-right direction in the chip package shown is the length direction of the first groove 411 (in L1), and the length of the heat sink 41 (in Figure 2 The left-right direction in the chip package shown is the length direction of the heat sink 41) is L2. Among them, L1≤1 / 5L2, so as to prevent the length of the first groove 411 from being too long, thereby affecting the bonding area between the heat sink 41 and the adhesive layer 42, affecting the bonding stability between the heat sink 41 and the adhesive layer 42, thereby improving the bonding stability between the heat sink 41 and the adhesive layer 42. When setting specifically, the length of the first groove 411 can be set to any value not greater than 1 / 5L2, such as L1=1 / 5L2, L1=1 / 6L2, L1=1 / 7L2, L1=1 / 8L2, etc.

[0037] Continue to refer Figure 2 , the depth of the first groove 411 (in Figure 2 In the chip package shown, the height of the first groove 411 in the vertical direction is D1, and the thickness of the heat sink 41 is D2. Figure 2 The height of the heat sink 41 in the vertical direction of the chip package shown is H1 (the thickness of the heat sink 41). Among them, D1≤1 / 2H1, so as to prevent the heat sink 41 from breaking due to being locally thin. Specifically, the thickness of the first groove 411 can be set to any value not greater than 1 / 2H1, such as D1=1 / 2H1, D1=1 / 3H1, D1=1 / 4H1, D1=1 / 5H1, D1=1 / 6H1, etc.

[0038] When the second groove 421 is provided, the second groove 421 is opposite to the ejector pin hole 31 on the packaging layer 30. Figure 2 The depth of the second groove 421 is ((in Figure 2 In the chip package shown, the height of the second groove 421 in the vertical direction is D2 (the thickness of the second groove 421), and the depth of the adhesive layer 42 (the thickness of the second groove 421) is D2. Figure 2 The height of the adhesive layer 42 in the vertical direction of the chip package shown is the thickness of the adhesive layer 42) is H2. Among them, D2≤1 / 2H2, so as to ensure the stability of the bonding between the adhesive layer 42 and the lead frame 10. Specifically, the thickness of the second groove 421 can be set to any value not greater than 1 / 2H2, such as D2=1 / 2H2, D2=1 / 3H2, D2=1 / 4H2, D2=1 / 5H2, D2=1 / 6H2, etc.

[0039] When the insulating block 50 is specifically set, the shape of the insulating block 50 is a cube, so that the insulating block 50 can be set in the first groove 411 and the second groove 421. It should be understood that the shape of the insulating block 50 is not limited to the cube shown above, and correspondingly, the first groove 411 and the second groove 421 are not limited to the rectangular groove shown above. In addition, other methods can also be used. That is, as long as the insulating block 50 is relative to the ejector hole 31 and is set between the second surface 12 of the lead frame 10 and the heat sink 41, it is within the protection scope of the embodiment of the present invention. For example, the shape of the insulating block 50 can be set to be circular. At this time, the shapes of the first groove 411 and the second groove 421 are also circular, so that the first groove 411 and the second groove 421 can accommodate the insulating block 50.

[0040] In addition, the material of the insulating block 50 may be a heat-conducting material to improve the heat dissipation performance of the chip. Specifically, the material of the insulating block 50 may be ceramic to prevent the pressure exerted by the ejector pin 32 on the lead frame 10 from crushing the insulating block 50. It should be understood that the material of the insulating block 50 is not limited to ceramic, and in addition, it may be other insulating materials in the prior art that can conduct heat and withstand a certain pressure.

[0041] By setting an insulating block 50 for isolating the heat sink 41 from the second surface 12 of the lead frame 10 and the heat sink 41, and the insulating block 50 is opposite to the ejector hole 31, in this way, during the packaging process of the chip package, even if the ejector 32 applies a large pressure to the lead frame 10 through the ejector hole 31, the lead frame 10 will not press through the adhesive layer 42, thereby preventing the lead frame 10 from contacting the heat sink 41, thereby preventing the chip from short-circuiting. And under the large pressure applied by the ejector 32 to the lead frame 10, the lead frame 10 can also fully contact the adhesive layer 42, thereby ensuring the heat dissipation performance of the chip.

[0042] The above are only specific embodiments of the present invention, but the protection scope of the present invention is not limited thereto. Any person skilled in the art who is familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed by the present invention, which should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention should be based on the protection scope of the claims.

Claims

1. A chip package, characterized in that: include: A lead frame, the lead frame having a first surface and a second surface opposite to each other; A chip component disposed on the first surface; A packaging layer for packaging the chip assembly, wherein the packaging layer has a pin hole; a heat dissipation assembly disposed on the second surface, the heat dissipation assembly comprising a heat sink, an adhesive layer bonding the heat sink and the second surface, and an insulating block disposed between the heat sink and the second surface and used to isolate the heat sink and the second surface; the insulating block is opposite to the ejector pin hole; The insulating block is embedded in the heat sink and the adhesive layer; A first groove is provided on one side of the heat sink facing the adhesive layer, and a second groove is provided on one side of the adhesive layer facing the heat sink; the first groove is opposite to the second groove, and the insulating block is provided in the first groove and the second groove; The bonding layer is made of insulating material.

2. The chip package according to claim 1, wherein: The first groove and the second groove are both rectangular grooves.

3. The chip package according to claim 2, wherein: The length of the first groove is L1, and the length of the heat sink is L2; ​​wherein L1≤1 / 5L2.

4. The chip package according to claim 1, wherein: The depth of the first groove is D1, and the thickness of the heat sink is H1; wherein D1≤1 / 2H1.

5. The chip package according to claim 1, wherein: The depth of the second groove is D2, and the thickness of the adhesive layer is H2; Among them, D2≤1 / 2H2.

6. The chip package according to any one of claims 1 to 5, characterized in that: The insulating block is made of heat-conductive material.

7. The chip package according to claim 6, wherein: The insulating block is made of ceramic.

8. The chip package according to any one of claims 1 to 5, characterized in that: The insulating block is in the shape of a cube.

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