Integrated chip, integrated circuit and method for forming the same

Abstract

Various embodiments of the present disclosure relate to an integrated chip including a first substrate through-hole disposed in a semiconductor substrate. The semiconductor substrate has a front surface and a back surface respectively on opposite sides of the semiconductor substrate. The semiconductor substrate includes a first doped channel region extending from the front surface to the back surface. The first substrate through-hole is defined by at least the first doped channel region. A conductive contact overlies the back surface of the semiconductor substrate and includes a first conductive layer overlying the first substrate through-hole. The first conductive layer includes a conductive material. An upper conductive layer is located below the conductive contact. An upper surface of the upper conductive layer is aligned with the back surface of the semiconductor substrate. The upper conductive layer includes a silicide of the conductive material.

Description

Technical Field

[0001] The embodiments of the present invention relate to an integrated chip, an integrated circuit and a method for forming the same. Background Art

[0002] The semiconductor industry has been continuously improving the processing power and power consumption of integrated circuits (ICs) by reducing the minimum feature size. However, in recent years, process limitations have made it difficult to continue to reduce the minimum feature size. Stacking two-dimensional (2D) ICs into three-dimensional (3D) ICs has become a potential method to continue to improve the processing power and power consumption of ICs. Typically, through-substrate vias (TSVs) are used to electrically couple stacked 2D ICs together. Summary of the invention

[0003] An embodiment of the present invention provides an integrated chip, which includes a semiconductor substrate, a first substrate through-hole, a conductive contact, and an upper conductive layer. The semiconductor substrate has a front surface and a back surface on opposite sides of the semiconductor substrate, respectively, wherein the semiconductor substrate includes a first doped channel region extending from the front surface to the back surface. The first substrate through-hole is defined by at least the first doped channel region. The conductive contact overlies the back surface of the semiconductor substrate, wherein the conductive contact includes a first conductive layer overlying the first substrate through-hole, wherein the first conductive layer includes a conductive material. The upper conductive layer is located below the conductive contact, wherein the upper surface of the upper conductive layer is aligned with the back surface of the semiconductor substrate, and the upper conductive layer includes a silicide of the conductive material.

[0004] An embodiment of the present invention provides an integrated circuit, which includes a first integrated circuit die, a second integrated circuit die, a plurality of semiconductor devices, a first substrate through-hole, a first conductive contact, and a first upper conductive layer. The first integrated circuit die includes a first semiconductor substrate and a first internal wiring structure located below the first semiconductor substrate, wherein the first internal wiring structure includes a plurality of first conductive lines. The plurality of first conductive lines respectively include a first conductive material. The second integrated circuit die is located below the first integrated circuit die, wherein the second integrated circuit die includes a second semiconductor substrate and a second internal wiring structure overlying the second semiconductor substrate. The first integrated circuit die and the second integrated circuit die are in contact at a bonding interface between the first internal wiring structure and the second internal wiring structure. A plurality of semiconductor devices are located on the second semiconductor substrate. The first substrate through-hole is located in the first semiconductor substrate and is electrically coupled to the second internal wiring structure through the first internal wiring structure. The first substrate through-hole and the first semiconductor substrate are composed of semiconductor material. The first conductive contact overlies the first semiconductor substrate. The first conductive contact includes a second conductive material different from the first conductive material. The first upper conductive layer is arranged between the first conductive contact and the first substrate through-hole. The first upper conductive layer includes a third conductive material different from the first conductive material and the second conductive material.

[0005] An embodiment of the present invention provides a method for forming an integrated circuit, which includes: performing a first ion implantation process on a front surface of a first semiconductor substrate to form a first doped channel region extending from the front surface into the first semiconductor substrate, wherein the first semiconductor substrate includes a semiconductor material; forming a first internal connection structure along the front surface of the first semiconductor substrate; thinning the first semiconductor substrate from a back surface of the first semiconductor substrate until the first doped channel region is exposed, wherein the back surface is opposite to the front surface; forming a conductive contact on the back surface of the first semiconductor substrate that overlies and is electrically coupled to the first doped channel region, wherein the conductive contact includes a conductive material; and performing an annealing process to form an upper conductive layer in the first semiconductor substrate, wherein the upper conductive layer includes a semiconductor material and a silicide of the conductive material. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The various aspects of the present disclosure will be best understood by reading the following detailed description in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, the various features are not drawn to scale. In fact, the size of the various features may be arbitrarily increased or reduced for clarity of discussion.

[0007] Figure 1Cross-sectional views of some embodiments of a three-dimensional (3D) integrated circuit (IC) are shown, wherein the 3D integrated circuit includes a first IC die having an ionic through-substrate via (TSV) and a second IC die having a semiconductor device, wherein a conductive contact overlies the ionic TSV and an upper conductive layer is disposed between the conductive contact and the ionic TSV.

[0008] Figure 2 Show according to Figure 1 The line Figure 1 A top view of some embodiments of a 3D IC.

[0009] Figure 3A Some alternative embodiments are shown with cross-sectional views of a 3DIC including a first IC die, a second IC die, and a pixel die, wherein the first IC die includes one or more ion TSVs and the pixel die includes a plurality of photodetectors.

[0010] Figure 3B and Figure 3C Show Figure 3A Cross-sectional views of some alternative embodiments of close-up views of portions of a 3D IC.

[0011] Figure 4 Cross-sectional views of some embodiments of a 3D IC having a first IC die, a second IC die, and a pixel die are shown, wherein the first IC die includes an ion TSV extending through a first semiconductor substrate and a semiconductor device disposed within a first interconnect structure.

[0012] Figures 5 to 17 A series of cross-sectional views are shown of some embodiments of a method for forming a three-dimensional (3D) integrated circuit (IC), wherein the three-dimensional integrated circuit includes a first IC die having an ionic through substrate via (TSV) and a second IC die having a semiconductor device, wherein a conductive contact overlies the ionic TSV and an upper conductive layer is disposed between the conductive contact and the ionic TSV.

[0013] Fig.18 A block diagram illustrating some embodiments of a method for forming a 3D IC including a first IC die having ionic TSVs and a second IC die having a semiconductor device, wherein a conductive contact overlies the ionic TSVs and an upper conductive layer is disposed between the conductive contact and the ionic TSVs. DETAILED DESCRIPTION

[0014] The present disclosure provides many different embodiments or examples for implementing the different features of the present disclosure. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are only examples and are not intended to be restrictive. For example, in the following description, the formation of a first feature on or on a second feature may include an embodiment in which the first feature is formed in direct contact with the second feature, and may also include an embodiment in which an additional feature may be formed between the first feature and the second feature so that the first feature and the second feature may not be in direct contact. In addition, the present disclosure may repeat the figure numbers and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0015] Additionally, for ease of description, spatially relative terms, such as "below," "beneath," "lower," "above," "upper," etc., may be used herein to describe the relationship of one element or feature to another element or features as illustrated in the figures. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0016] A three-dimensional (3D) integrated circuit (IC) includes a first IC die and a second IC die below the first IC die. The first IC die and the second IC die are two-dimensional (2D) IC dies and include corresponding semiconductor substrates and corresponding interconnect structures. The interconnect structures are located between the semiconductor substrates. The interconnect structures include alternately stacked wiring layers (e.g., horizontal wiring) and via layers (e.g., vertical wiring). The interconnect structures are in contact at a bonding interface between the first IC die and the second IC die.

[0017] The 3D IC further includes a plurality of ion substrate through vias (TSVs), which extend through the semiconductor substrate of the first IC die from the back side of the semiconductor substrate of the first IC die to the front side of the semiconductor substrate of the first IC die. The internal connection structure of the first IC is disposed on the front side of the semiconductor substrate of the first IC die, and one or more conductive contacts are disposed directly above the 3D IC on the back side of the semiconductor substrate of the first IC die. The conductive contacts are electrically coupled to the ion TSVs correspondingly, and the ion TSVs are electrically coupled to the wiring layer (wiring layer) in the internal connection structure of the first IC die. The challenge of the above structure is that the conductive contacts include conductive materials (e.g., titanium, titanium nitride, or the like) that cannot form good electrical contact (e.g., ohmic contact) with the corresponding ion TSVs. This may be because the conductive material may have a high resistivity and is therefore unable to form a good electrical connection with p-type and / or n-type ion TSVs. The lack of a good electrical connection between the conductive contacts and the ion TSVs may reduce the performance of the semiconductor devices within the 3D IC.

[0018] It is understood that in order to achieve good electrical connection between the ion TSV and the conductive contact, the conductive contact may be composed of a low-resistivity silicide of a conductive material. For example, the low-resistivity silicide may be or include titanium silicide (e.g., TiSi2). However, in order to form the low-resistivity conductive material, a high annealing temperature (e.g., greater than 600 degrees Celsius) may be utilized during the formation of the conductive contact. The 3D IC is exposed to high temperatures after forming the first and second interconnect structures and after bonding the first IC die to the second IC die. The high annealing temperature may cause damage to devices (e.g., transistors, photodetectors, metal-insulator-metal (MIM) capacitors, and / or other semiconductor devices) and / or layers disposed within the first IC die and / or the second IC die, thereby reducing the performance of the 3D IC and / or rendering the 3D IC inoperable.

[0019] Various embodiments of the present application relate to a 3D IC including a conductive contact and / or a method for forming the conductive contact, which has a good electrical connection (e.g., ohmic contact) with an ion TSV. In some embodiments, the ion TSV is formed by forming a mask layer over a semiconductor substrate and implanting dopants (e.g., n-type and / or p-type) into the semiconductor substrate. The ion TSV extends from the front side surface of the semiconductor substrate to the opposite back side surface of the semiconductor substrate and provides electrical coupling from the front side surface of the semiconductor substrate to the opposite back side surface of the semiconductor substrate. The conductive contact is formed over the back side surface of the semiconductor substrate and overlies the ion TSV. The conductive contact can be formed by depositing one or more conductive layers over the ion TSV, so that the first conductive layer overlying and / or contacting the ion TSV can, for example, include nickel. Subsequently, one or more photodetectors are formed in the semiconductor substrate and / or in the upper semiconductor substrate overlying the ion TSV. After forming the one or more photodetectors, an annealing process is performed on the 3D IC to remove defects in the semiconductor substrate and / or the upper semiconductor substrate. The annealing process may reach a low maximum temperature (e.g., up to about 410 degrees Celsius) and may be configured to simultaneously reduce pixel and / or dark current within the 3D IC. Furthermore, the annealing process simultaneously converts at least a portion of the semiconductor substrate below the first conductive layer into an upper conductive layer comprising a low resistivity conductive material (e.g., comprising a silicide such as nickel silicide (NiSi)). This in turn results in a good electrical connection (e.g., an ohmic contact) between the conductive contact and the ionic TSV. Furthermore, because the annealing process may reach a low maximum annealing temperature (e.g., about 410 degrees Celsius), damage to semiconductor devices and / or layers disposed on / in the semiconductor substrate may be mitigated and / or reduced. Thus, the low resistivity conductive material formed at the low maximum annealing temperature mitigates damage to devices and / or layers disposed within the 3D IC while achieving a good electrical contact (e.g., an ohmic contact) between the conductive contact and the ionic TSV.

[0020] Figure 1 A cross-sectional view of some embodiments of a three-dimensional (3D) integrated circuit (IC) 100 is shown having a first IC die 102 , a second IC die 104 , and a pixel IC die 105 overlying the first IC die 102 .

[0021] The first IC die 102 overlies the second IC die 104 and includes a first semiconductor substrate 108 and a first interconnect structure 106 extending along a front side 108f of the first semiconductor substrate 108. The first interconnect structure 106 is disposed between the first semiconductor substrate 108 and the second IC die 104. One or more semiconductor devices (not shown) may be disposed within the second IC die 104 such that the first interconnect structure 106 is electrically coupled to the one or more semiconductor devices. In some embodiments, the first interconnect structure 106 includes a first interconnect dielectric structure 110, a plurality of conductive lines 114, a plurality of vias 112, and a channel control contact 116. In some embodiments, the channel control contact 116 is configured to provide control of a conductive channel within a complementary metal-oxide-semiconductor (CMOS) device, such as a transistor (not shown). In some embodiments, the first semiconductor substrate 108 may be, for example, or include a semiconductor substrate material, such as silicon. In addition, the via 112 may include a first via 112 a and a second via 112 b .

[0022] In some embodiments, the first semiconductor substrate 108 overlies the first interconnect structure 106 and may include a first doping type (e.g., p-type). A first through-substrate via (TSV) 118 and a second TSV 120 extend continuously from a back side 108b of the first semiconductor substrate 108 to a front side 108f of the first semiconductor substrate 108, respectively. The first TSV 118 and the second TSV 120 are electrically coupled to one or more semiconductor devices (not shown) disposed in the second IC die 104 through the first interconnect structure 106. In some embodiments, the first TSV 118 includes a first doped channel region 122 surrounded by an isolation structure 124. In other embodiments, an outer sidewall of the first doped channel region 122 abuts an inner sidewall of the isolation structure 124. In yet other embodiments, the first doped channel region 122 is a doped region of the first semiconductor substrate 108 that includes a second doping type (e.g., n-type) opposite to the first doping type (e.g., p-type). In some embodiments, the first doping type is p-type and the second doping type is n-type, or vice versa. Therefore, in some embodiments, the first TSV 118 may, for example, include a semiconductor substrate material (eg, substrate). In addition, the first via 112a may be located directly below the first TSV 118.

[0023] In other embodiments, the second TSV 120 includes a second doped channel region 126 surrounded by a third doped channel region 128. In some embodiments, the isolation structure 124 surrounds the second doped channel region 126 so that the outer sidewalls of the second doped channel region 126 abut the inner sidewalls of the isolation structure 124. In other embodiments, the second doped channel region 126 includes a first doping type (e.g., p-type), and the third doped channel region 128 includes a second doping type (e.g., n-type). In yet other embodiments, the second doped channel region 126 and the third doped channel region 128 are doped regions of the first semiconductor substrate 108, respectively. Therefore, in some embodiments, the second TSV 120 may, for example, include a semiconductor substrate material (e.g., silicon). In addition, the second via 112b may be located directly below the second TSV 120.

[0024] The upper dielectric structure 130 overlies the back side 108b of the first semiconductor substrate 108 and extends along the back side 108b. In some embodiments, one or more conductive contacts 134 extend through the upper dielectric structure 130 and overlie the first TSV 118 and the second TSV 120. In some embodiments, the conductive contacts 134 include a first conductive layer 136, a second conductive layer 138, and a third conductive layer 140, respectively. In yet other embodiments, the upper conductive layer 132 is disposed within the first semiconductor substrate 108 and below the conductive contacts 134. In some embodiments, the upper surface of the upper conductive layer 132 is aligned with the back side 108b of the first semiconductor substrate 108. In other embodiments, the upper conductive layer 132 directly contacts the first conductive layer 136. In yet other embodiments, the lower conductive layer 131 is disposed within the first semiconductor substrate 108 and overlies a corresponding one of the first TSV 118 and the second TSV 120.

[0025] In some embodiments, the pixel IC die 105 overlies the first IC die 102 and includes an upper interconnect structure 141 and a pixel substrate 144. The upper interconnect structure 141 is disposed between the upper dielectric structure 130 and the pixel substrate 144. In some embodiments, the upper interconnect structure 141 includes an upper interconnect dielectric structure 142, a plurality of conductive lines 146, and a plurality of vias 148. In some embodiments, the pixel substrate 144 may be, for example, or include a semiconductor substrate material (e.g., silicon) and / or may include a first doping type (e.g., p-type). A plurality of photodetectors 150 are disposed within the pixel substrate 144. In some embodiments, the plurality of photodetectors 150 may each include a second doping type (e.g., n-type) and may be configured to convert incident radiation (e.g., light) into an electrical signal. In other embodiments, one or more pixel devices (not shown) may be disposed on and / or within the pixel substrate 144 and may be configured to read out the electrical signal. One or more pixel devices may be electrically coupled to the first TSV 118 and the second TSV 120 via the upper interconnect structure 141. In other embodiments, the one or more pixel devices may be or include, for example, a transfer transistor, a source follower transistor, a row select transistor, a reset transistor, another suitable pixel device, or a combination thereof.

[0026] During the manufacture of the 3D IC 100, an annealing process is performed after forming the photodetector 150 to reduce white pixels and / or dark current within the 3D IC 100. The annealing process is configured to remove impurities from the pixel substrate 144 and reach a maximum temperature (e.g., about 410 degrees Celsius). Before forming the photodetector 150, a first conductive layer 136 is formed over the corresponding TSVs 118, 120. The first conductive layer 136 may, for example, be or include a conductive material (e.g., nickel (Ni)). The conductive material is configured to be converted into a silicide material during the annealing process. Therefore, during the annealing process, an upper conductive layer 132 may be formed within the first semiconductor substrate 108. In some embodiments, the upper conductive layer 132 may be or include a silicide of a conductive material (e.g., nickel silicide (NiSi)). The upper conductive layer 132 is configured to facilitate good electrical connection (e.g., ohmic contact) between the conductive contact 134 and the corresponding TSV 118, 120. Furthermore, since the maximum temperature (e.g., about 410 degrees Celsius) is less than the high annealing temperature (e.g., about 600 degrees Celsius), damage to semiconductor devices and / or layers disposed within the 3D IC 100 may be mitigated and / or eliminated. Thus, the upper conductive layer 132 may be formed without performing an additional set of processes, and good electrical connections (e.g., ohmic contacts) between the conductive contacts 134 and the corresponding TSVs 118, 120 may be facilitated. This in turn reduces the time and cost associated with manufacturing the 3D IC 100 while improving the performance of the semiconductor devices disposed within the 3D IC 100.

[0027] In yet other embodiments, the first via 112a and the second via 112b may each be or include a conductive material. Thus, in some embodiments, the annealing process may form a lower conductive layer 131 within the first semiconductor substrate 108. The lower conductive layer 131 may, for example, be or include a silicide of a conductive material (e.g., NiSi). This in turn promotes good electrical connection (e.g., ohmic contact) between the first via 112a and the second via 112b and the corresponding first TSV 118 or second TSV 120. In yet other embodiments, the lower conductive layer 131 may be formed simultaneously with the upper conductive layer 132 during the annealing process.

[0028] Figure 2 Show according to Figure 1 The line Figure 1 A top view 200 of some alternative embodiments of the 3D IC 100 is shown.

[0029] like Figure 2As shown in the top view 200 of , when viewed from above, the first TSV 118 and the second TSV 120 may have a rectangular shape, a square shape, or another suitable shape, respectively. For example, when viewed from above, the first doped channel region 122, the second doped channel region 126, and the third doped channel region 128 may have a rectangular shape, a square shape, or another suitable shape, respectively. In addition, when viewed from above, the conductive contact 134 may have a circular shape, an elliptical shape, or another suitable shape, respectively. In some embodiments, the first conductive layer 136 laterally surrounds the second conductive layer 138, and the second conductive layer 138 laterally surrounds the third conductive layer 140.

[0030] Figure 3A Show according to Figure 1 Cross-sectional views of some embodiments of 3D IC 300 to some alternative embodiments of 3D IC 100 .

[0031] The 3D IC 300 includes a first IC die 102, a second IC die 104, and a pixel IC die 105. The first IC die 102 is disposed between the second IC die 104 and the pixel IC die 105. In some embodiments, the second IC die 104 includes a second interconnect structure 304 and a second semiconductor substrate 302. In some embodiments, the second semiconductor substrate 302 may be, for example, or include a semiconductor substrate material (e.g., silicon), a bulk substrate (e.g., a bulk silicon substrate), a silicon-on-insulator (SOI) substrate, or some other suitable substrate and / or may include a first doping type (e.g., p-type). The second interconnect structure 304 overlies the second semiconductor substrate 302. In other embodiments, the second interconnect structure 304 includes a second interconnect dielectric structure 306, a plurality of vias 318, and a plurality of conductive lines 320. The second interconnect structure 304 may be, for example, or include one or more inter-level dielectric (ILD) layers. The one or more ILD layers may be, for example, or include an oxide (e.g., silicon dioxide), a low-k dielectric material, an ultra-low-k dielectric material, or another suitable dielectric material. In some embodiments, the plurality of vias and / or conductive lines may be, for example, or include aluminum, copper, titanium, tantalum, tungsten, a combination thereof, or another suitable conductive material.

[0032] In some embodiments, a plurality of semiconductor devices 308 are disposed above and / or within the second semiconductor substrate 302. In some embodiments, the semiconductor devices 308 may be, for example, metal-oxide-semiconductor field-effect transistors (MOSFETs), some other metal-oxide semiconductor (MOS) devices, some other insulated-gate field-effect transistors (IGFETs), some other semiconductor devices, or any combination thereof. In other embodiments, the semiconductor devices 308 may each include a source / drain region 310, a gate dielectric layer 312, a gate electrode 314, and a sidewall spacer structure 316. In yet other embodiments, the source / drain region 310 may each include a second doping type (e.g., n-type) opposite to the first doping type. In some embodiments, the first doping type is p-type and the second doping type is n-type, or vice versa.

[0033] The first IC die 102 overlies the second IC die 104. The first IC die 102 includes a first interconnect structure 106, a first semiconductor substrate 108, and an upper dielectric structure 130. In some embodiments, the first semiconductor substrate 108 may be, for example, or include a semiconductor substrate material (e.g., silicon), a bulk substrate (e.g., a bulk silicon substrate), a silicon-on-insulator (SOI) substrate, or some other suitable substrate and / or may include a first doping type (e.g., p-type). In other embodiments, the first interconnect structure 106 is located below the first semiconductor substrate 108 and includes a first interconnect dielectric structure 110, a plurality of vias 112, a plurality of conductive lines 114, and a channel control contact 116. In some embodiments, the channel control contact 116 may be, for example, or include polysilicon, doped polysilicon, metal, a combination of the foregoing, or another suitable conductive material. In other embodiments, a semiconductor device, such as a transistor (not shown), may be disposed on the first semiconductor substrate 108. In various embodiments, the channel control contact 116 may be configured to apply a bias voltage to a gate electrode of one of the transistors to control a selective conductive channel within the first semiconductor substrate 108 .

[0034] In some embodiments, the first interconnect dielectric structure 110 includes a plurality of ILD layers, which may be, for example, respectively or include silicon dioxide, a low-k dielectric material, an ultra-low-k dielectric material, a combination of the foregoing, or another suitable dielectric material. In other embodiments, the via 112 and / or the conductive line 114 may be, for example, or include aluminum, copper, titanium, tantalum, a combination of the foregoing, or another suitable conductive material. In some embodiments, the first interconnect structure 106 and the second interconnect structure 304 are bonded to each other by, for example, hybrid bonding, fusion bonding, and / or metal bonding. In other embodiments, the via 112 may include a first via 112a and a second via 112b. In some embodiments, the first via 112a and the second via 112b may be, for example, or include nickel (Ni).

[0035] In addition, the first TSV 118 and the second TSV 120 extend from the front side 108f of the first semiconductor substrate 108 to the back side 108b of the first semiconductor substrate 108, respectively. In some embodiments, the isolation structure 124 extends from the front side 108f to a point above the front side 108f. In some embodiments, the isolation structure 124 may be, for example, configured as a shallow trench isolation (STI) structure, a deep trench isolation (DTI) structure, or another suitable isolation structure, respectively. In other embodiments, the isolation structure 124 may be, for example, or include a dielectric material, such as silicon dioxide, silicon nitride, silicon carbide, silicon oxynitride, a combination of the foregoing, or another suitable dielectric material. In some embodiments, the first TSV 118 may include a first doped channel region 122 and a fourth doped channel region 322. In other embodiments, the first doped channel region 122 may include a first doping type (e.g., p-type), and the fourth doped channel region 322 may include a second doping type (e.g., n-type). In yet other embodiments, the second TSV 120 may include a second doped channel region 126 including a first doping type (eg, p-type) and a third doped channel region 128 including a second doping type (eg, n-type).

[0036] In some embodiments, depletion regions are formed at the outer regions of the first TSV 118 and the second TSV 120, respectively. The depletion regions may be formed due to the pn junction between the fourth doped channel region 322 and the first semiconductor substrate 108 and / or the pn junction between the third doped channel region 128 and the first semiconductor substrate 108. In other embodiments, the depletion region is formed at the interface between the first doped channel region 122 and the fourth doped channel region 322. In addition, the depletion region may be formed at the interface between the second doped channel region 126 and the third doped channel region 128. The first TSV 118 and the second TSV 120 provide electrical coupling between the plurality of semiconductor devices 308 and the conductive contact 134 by means of the first interconnect structure 106 and the second interconnect structure 304. This is partly because under certain operating conditions, for example, the pn junction may act as a diode, so that current flows from the P-type region to the N-type region (but current may not flow from the N-type region to the P-type region).

[0037] Because the first TSV 118 and the second TSV 120 include doped regions of the first semiconductor substrate 108, the first TSV 118 and the second TSV 120 may be laterally spaced above the semiconductor device 308 and / or laterally spaced below the photodetector 150. The semiconductor substrate material (e.g., silicon) of the first TSV 118 and the second TSV 120 mitigates mechanical stress induced on the underlying semiconductor device 308 and / or the overlying photodetector 150. This, in turn, may prevent device failure (e.g., device failure due to mechanical stress) of the semiconductor device 308 and / or the photodetector 150.

[0038] The upper dielectric structure 130 extends along the back side 108b of the first semiconductor substrate 108. In some embodiments, the upper dielectric structure 130 includes a first passivation layer 324, a second passivation layer 326, a third passivation layer 328, and an upper dielectric layer 330. In some embodiments, the first passivation layer 324 may be, for example, or include an oxide (e.g., silicon dioxide) or another suitable dielectric material. In some embodiments, the second passivation layer 326 may be, for example, or include a nitride (e.g., silicon nitride) or another suitable dielectric material. In other embodiments, the third passivation layer 328 may be, for example, or include an oxide (e.g., silicon dioxide) or another suitable dielectric material. The upper dielectric layer 330 may be, for example, or include silicon dioxide, a low-k dielectric material, or another suitable dielectric material. The conductive contacts 134 extend from the pixel IC die 105 through the upper dielectric structure 130 to the first semiconductor substrate 108, respectively. In some embodiments, the conductive contacts 134 are configured to electrically couple the first TSV 118 and the second TSV 120 to the pixel IC die 105 .

[0039] The pixel IC die 105 overlies the first IC die 102 and includes a pixel substrate 144 and an upper interconnect structure 141. In some embodiments, the pixel substrate 144 may be, for example, or include a semiconductor substrate material (e.g., silicon), a bulk semiconductor substrate (e.g., a bulk silicon substrate), an SOI substrate, or another suitable substrate and / or may include a first doping type (e.g., p-type). The upper interconnect structure 141 may include an upper interconnect dielectric structure 142, a plurality of conductive lines 146, and a plurality of vias 148. In some embodiments, the upper interconnect structure 141 may include one or more ILD layers. In other embodiments, the vias 148 and the conductive lines 146 may be, for example, or include aluminum, copper, titanium, tantalum, or another suitable conductive material, respectively. A plurality of photodetectors 150 are disposed within the pixel substrate 144. In some embodiments, the photodetectors 150 may, for example, include a second doping type (e.g., n-type) and may be configured to convert electromagnetic radiation (e.g., photons) into electrical signals (i.e., to generate electron-hole pairs from the electromagnetic radiation).

[0040] The conductive contact 134 is configured to electrically couple the first TSV 118 and the second TSV 120 to the upper interconnect structure 141. In some embodiments, the conductive contact 134 overlies directly above the corresponding one of the first TSV 118 and the second TSV 120. In yet other embodiments, the conductive contact 134 may include a first conductive layer 136, a second conductive layer 138, and a third conductive layer 140, respectively. In some embodiments, the first conductive layer 136, the second conductive layer 138, and the third conductive layer 140 include materials different from each other. In various embodiments, the first conductive layer 136 may be or include nickel (Ni), the second conductive layer 138 may be or include titanium nitride (TiN), and the third conductive layer 140 may be or include tungsten (W). In other embodiments, the second conductive layer 138 may be or include titanium, tantalum, titanium nitride, tantalum nitride, combinations thereof, or the like, for example.

[0041] The upper conductive layer 132 may be located below each of the conductive contacts 134. In some embodiments, the upper conductive layer 132 directly contacts the first TSV 118 and / or the second TSV 120. The upper conductive layer 132 is configured to facilitate good electrical connection (e.g., ohmic contact) between the first TSV 118 and / or the second TSV 120 and the corresponding conductive contact 134. In some embodiments, the first conductive layer 136 includes a conductive material (e.g., nickel), and the upper conductive layer 132 includes a silicide of the conductive material. For example, the upper conductive layer 132 may be or include nickel silicide (NiSi). In some embodiments, the resistivity of the upper conductive layer 132 is in the range of about 10 micro-ohm centimeters to 20 micro-ohm centimeters (μΩ-cm), in the range of about 10.5 μΩ-cm to 15 μΩ-cm, in the range of about 5 μΩ-cm to 25 μΩ-cm, less than about 25 μΩ-cm, or another suitable value. In some embodiments, if the resistivity of the upper conductive layer 132 exceeds about 25 μΩ-cm, the conductive contact 134 may not be able to form a good electrical connection with the corresponding one of the first TSV 118 and / or the second TSV 120. Therefore, in some embodiments, since the resistivity of the upper conductive layer 132 is less than about 25 μΩ-cm, the contact resistance between the conductive contact 134 and the corresponding one of the first TSV 118 and / or the second TSV 120 is reduced, thereby improving the performance of the device disposed in / on the 3D IC 300. In other embodiments, the lower conductive layer 131 is configured as the upper conductive layer 132, so that the lower conductive layer 131 may be, for example, or include nickel silicide (NiSi). In yet other embodiments, the resistivity of the lower conductive layer 131 is in the range of about 10 micro-ohm centimeters (μΩ-cm) to 20 micro-ohm centimeters, in the range of about 10.5 μΩ-cm to 15 μΩ-cm, in the range of about 5 μΩ-cm to 25 μΩ-cm, less than about 25 μΩ-cm, or another suitable value. This in turn promotes good electrical connection (e.g., ohmic contact) between the first and / or second vias 112a, 112b and corresponding ones of the first and / or second TSVs 118, 120.

[0042] Furthermore, in some embodiments, the upper conductive layer 132 is configured to have a Schottky barrier height with the doped regions of the first semiconductor substrate 108, which promotes efficient carrier transport, for example, promoting carrier (e.g., electron) transport between the conductive contact 134 and the corresponding one of the first TSV 118 and / or the second TSV 120. In other embodiments, if the conductive contact 134 contacts the upper conductive layer 132 located directly above the doped region of the first semiconductor substrate 108 including the second doping type (e.g., n-type), the Schottky barrier height between the upper conductive layer 132 and the doped region of the first semiconductor substrate 108 may be about 0.60 electron volts (eV), 0.65 eV, in the range of about 0.55 eV to 0.70 eV, or another suitable value. This in turn promotes good electrical connection (e.g., ohmic contact) between the conductive contact 134 and the corresponding one of the first TSV 118 and / or the second TSV 120.

[0043] In some embodiments, the first semiconductor substrate 108 includes a semiconductor substrate material (e.g., silicon) having a (100) orientation. In other embodiments, the contact resistivity between the lower conductive layer 131 and / or the upper conductive layer 132 and the corresponding first doped region of the first semiconductor substrate 108 may be about 5*10 -8 Ωcm 2 To 5*10 -7 Ωcm 2 In the range of about 5*10 -8 Ωcm 2 to 10*10 -8 Ωcm 2 In the range of about 1*10 -7 Ωcm 2 To 5*10 -7 Ωcm 2 Within the range, less than 10*10 -7 Ωcm 2 , or another suitable value. In yet other embodiments, the lower conductive layer 131 and / or the upper conductive layer 132 may be or include nickel silicide (NiSi) formed at a maximum temperature of about 350 degrees Celsius, and / or the first doped region of the first semiconductor substrate 108 may be or include, for example, a doped region having a doping temperature of about 1*10 16 Atom / cm 3 To 1*10 20 Atom / cm 3 In some embodiments, the contact resistivity between the lower conductive layer 131 and / or the upper conductive layer 132 and the corresponding second doping region of the first semiconductor substrate 108 may be about 1*10 -8 Ωcm 2 To 1*10-7 Ωcm 2 In the range of about 1*10 -8 Ωcm 2 To 5*10 -8 Ωcm 2 In the range of about 5*10 -8 Ωcm 2 to 10*10 -8 Ωcm 2 Within the range, less than 1*10 -7 Ωcm 2 , or another suitable value. In some embodiments, the lower conductive layer 131 and / or the upper conductive layer 132 may be or include nickel silicide (NiSi) formed at a maximum temperature of about 350 degrees Celsius, and / or the second doped region of the first semiconductor substrate 108 may be or include, for example, a doped region having a doping temperature of about 1*10 16 Atom / cm 3 To 1*10 20 Atom / cm 3 A second doping type (eg, n-type) having a doping concentration within a range of .

[0044] In some embodiments, an anti-reflective layer 332 directly overlies an upper surface of the pixel substrate 144. The anti-reflective layer 332 is configured to mitigate reflection of electromagnetic radiation from the pixel substrate 144. A plurality of color filters 334 (e.g., a red filter, a blue filter, a green filter, or another color filter) directly contact the anti-reflective layer 332 or are otherwise located on the anti-reflective layer 332. The color filters 334 are each configured to transmit electromagnetic radiation of a specific wavelength. In addition, a plurality of micro lenses 336 are disposed above the color filters 334. The micro lenses 336 are configured to focus electromagnetic radiation (e.g., photons) toward the photo detector 150.

[0045] Figure 3B Show according to Figure 3A The dashed box 325 Figure 3A A cross-sectional view 300 b of some embodiments of a portion of a 3D IC 300 .

[0046] The bottom surface of the conductive contact 134 is aligned with the back side 108b of the first semiconductor substrate 108. In some embodiments, the top surface of the upper conductive layer 132 is aligned with the back side 108b of the first semiconductor substrate 108. In some embodiments, the second doped channel region 126 laterally surrounds the outer periphery of the upper conductive layer 132 and cups the lower side of the upper conductive layer 132. Thus, in some embodiments, the upper conductive layer 132 directly contacts the second doped channel region 126 and directly contacts the conductive contact 134. In yet other embodiments, the upper conductive layer 132 is laterally spaced between the sidewalls of the second doped channel region 126. In some embodiments, the thickness of the first conductive layer 136 is less than the thickness of the second conductive layer 138, and the thickness of the second conductive layer 138 is less than the thickness of the third conductive layer 140.

[0047] Figure 3C Show according to Figure 3A The dashed box 325 Figure 3A Cross-sectional view 300 c of some alternative embodiments of portions of 3D IC 300 .

[0048] In some embodiments, the bottom surface of the conductive contact 134 is vertically offset by a distance d1 from the back side 108b of the first semiconductor substrate 108. In other embodiments, the distance d1 is non-zero. In still other embodiments, the upper conductive layer 132 extends continuously from the sidewall of the first conductive layer 136 to the lower surface of the first conductive layer 136. In alternative embodiments, the upper surface of the upper conductive layer 132 is vertically offset by a distance d1 from the back side 108b of the first semiconductor substrate 108.

[0049] Figure 4 Show according to Figure 3A Cross-sectional views of some embodiments of a 3D IC 400 including a first IC die 102 , a second IC die 104 , and a pixel IC die 105 are shown in FIG.

[0050] The 3D IC 400 includes a device control region 402 laterally adjacent to a photodetector region 404. In some embodiments, a plurality of semiconductor devices 308 are disposed within the device control region 402 and may be configured to control other semiconductor devices disposed within the 3D IC 400. In some embodiments, a metal-insulator-metal (MIM) capacitor 406 is disposed within the first interconnect structure 106. The MIM capacitor 406 may include a first capacitor electrode 408, a capacitor dielectric layer 410, and a second capacitor electrode 412. The capacitor dielectric layer 410 is disposed between the first capacitor electrode 408 and the second capacitor electrode 412. In some embodiments, the first capacitor electrode 408 contacts the first conductive line 114, and the second capacitor electrode 412 contacts the second conductive line 114.

[0051] In some embodiments, the plurality of TSVs 414 are disposed within the first semiconductor substrate 108. In some embodiments, the plurality of TSVs 414, the photodetector 150, and / or the MIM capacitor 406 are disposed laterally within the photodetector region 404. In other embodiments, the plurality of TSVs 414 may each be configured as Figure 1 The first TSV 118 and / or the second TSV 120 of the 3DIC 100 of the embodiment of the present invention are formed by a plurality of conductive contacts 134 disposed within the upper dielectric structure 130 and overlying the TSV 414. In some embodiments, the first capacitor electrode 408 and / or the second capacitor electrode 412 may be electrically coupled to the doped region of the first semiconductor substrate 108. In yet other embodiments, the first capacitor electrode 408 and / or the second capacitor electrode 412 may be electrically coupled to one or more of the TSVs 414 by means of the vias 112 and the conductive lines 114.

[0052] Figures 5 to 17 Cross-sectional views 500 to 1700 illustrate some embodiments of a method for forming a 3D IC including a first IC die and a second IC die, each having an ion TSV and a semiconductor device, wherein a conductive contact overlies the ion TSV. Figures 5 to 17 500 to 1700 are shown, but it should be understood that Figures 5 to 17 The structures depicted in the drawings are not limited to the methods described and can in fact be separated from the methods described. Figures 5 to 17 Described as a series of actions, it should be understood that these actions are not limited to the order of actions, can be changed in other embodiments, and the disclosed method is also applicable to other structures. In other embodiments, some actions shown and / or described can be completely or partially omitted.

[0053] like Figure 5As shown in the cross-sectional view 500 of FIG. 5 , a first semiconductor substrate 108 is provided. A first TSV 118 and a second TSV 120 are formed in the first semiconductor substrate 108. In some embodiments, the first semiconductor substrate 108 may be, for example, or include a bulk substrate (e.g., a bulk silicon substrate), a silicon-on-insulator (SOI) substrate, or some other suitable substrate. In some embodiments, a first implantation process may be performed to dope the first semiconductor substrate 108 with a first doping type (e.g., p-type) to about 1*10 15 Atom / cm 3 In some embodiments, the p-type dopant of the first doping type may be, for example, or include boron, difluoroboron (eg, BF2), indium, some other suitable p-type dopant, or any combination thereof.

[0054] In addition, if Figure 5 As shown in the cross-sectional view 500 of FIG. 1 , a second implantation process may be performed to selectively form a first doped channel region 122 and a third doped channel region 128 in the first semiconductor substrate 108, wherein the first doped channel region 122 defines the first TSV 118. In some embodiments, the first doped channel region 122 and the third doped channel region 128 may each have a second doping type (e.g., n-type) opposite to the first doping type and may each further have a doping type of about 1*10 16 Atom / cm 3 To 1*10 20 Atom / cm 3 In some embodiments, the second implantation process may include: forming a first mask layer (not shown) over the front side 108f of the first semiconductor substrate 108; selectively implanting the second doping type according to the mask layer, thereby defining the first doped channel region 122 and the third doped channel region 128; and performing a removal process to remove the mask layer. In some embodiments, the removal process may include an etching process and / or a planarization process (e.g., a chemical mechanical planarization (CMP) process). In some embodiments, the n-type dopant of the second doping type may be, for example, or include phosphorus, arsenic, antimony, some other suitable n-type dopant, or any combination of the foregoing.

[0055] In addition, if Figure 5 As shown in the cross-sectional view 500 of FIG. 1 , a third implantation process may be performed to selectively form a second doped channel region 126 in the first semiconductor substrate 108, wherein the second doped channel region 126 and the third doped channel region 128 define the second TSV 120. In some embodiments, the second doped channel region 126 includes a first doping type (e.g., p-type) and has a thickness of about 1*10 16 Atom / cm 3To 1*10 20 Atom / cm 3 In some embodiments, the second doped channel region 126 has a doping concentration within a range of . In some embodiments, the doping concentration of the second doped channel region 126 is greater than the doping concentration of the first semiconductor substrate 108. In other embodiments, the second doped channel region 126 may be formed by a counter-doping process. In yet other embodiments, the third implantation process may include: forming a second mask layer (not shown) over the front side 108f of the first semiconductor substrate 108; selectively implanting the first doping type according to the mask layer, thereby defining the second doped channel region 126; and performing a removal process to remove the mask layer. In some embodiments, the removal process may include an etching process and / or a planarization process (e.g., a CMP process).

[0056] In other embodiments, after forming the first TSV 118 and the second TSV 120, a rapid thermal annealing (RTA) process is performed on the first semiconductor substrate 108 to repair any damage to the first semiconductor substrate 108 caused by forming the first TSV 118 and / or the second TSV 120. In yet other embodiments, the RTA process may reach a temperature in a range of approximately 995 degrees Celsius to 1010 degrees Celsius.

[0057] like Figure 6 As shown in the cross-sectional view 600 of , an isolation structure 124 is formed on the front side 108f of the first semiconductor substrate 108. In some embodiments, forming the isolation structure 124 may include: forming a mask layer (not shown) over the first semiconductor substrate 108; performing an etching process according to the mask layer to define an opening in the first semiconductor substrate 108; filling the opening in the first semiconductor substrate 108 with a dielectric material (e.g., including silicon dioxide, silicon nitride, silicon carbide, a combination of the foregoing, or another suitable dielectric material); and performing a removal process to remove the mask layer and / or excess dielectric material (not shown). In yet other embodiments, before and / or after forming the first TSV 118 and / or the second TSV 120 (not shown), a plurality of semiconductor devices (e.g., transistors) (not shown) may be formed on the front side 108f of the first semiconductor substrate 108.

[0058] like Figure 7As shown in the cross-sectional view 700 of FIG. 7 , a first interconnect structure 106 is formed over the front side 108 f of the first semiconductor substrate 108. In some embodiments, the first interconnect structure 106 includes a first interconnect dielectric structure 110, a plurality of conductive lines 114, a plurality of vias 112, and a channel control contact 116. The vias 112 and the conductive lines 114 are disposed within the first interconnect dielectric structure 110. In addition, the vias 112 may include a first via 112 a and a second via 112 b. In some embodiments, the first via 112 a directly overlies the first TSV 118, and the second via 112 b directly overlies the second TSV 120. In other embodiments, the first interconnect dielectric structure 110 may include a plurality of interlayer dielectric (ILD) layers, which may, for example, be or include an oxide (e.g., silicon dioxide), a low-k dielectric material, an ultra-low-k dielectric material, a combination of the foregoing, or another suitable dielectric material. In yet other embodiments, the process for forming the first interconnect dielectric structure 110 may include performing one or more chemical vapor deposition (CVD) processes, physical vapor deposition (PVD) processes, atomic layer deposition (ALD) processes, combinations thereof, or another suitable deposition or growth process.

[0059] In some embodiments, the process for forming the first interconnect structure 106 may include forming the first via 112a and the second via 112b by a single damascene process and then forming the bottommost layer of the conductive line 114 by a single damascene process. In addition, in some embodiments, the process may further include forming the remaining layers of the via 112 and the conductive line 114 by repeatedly performing a dual damascene process. In some embodiments, the via 112 and the conductive line 114 may be, for example, respectively or include aluminum, copper, titanium, tantalum, a combination of the foregoing, or another suitable conductive material. In yet other embodiments, the first via 112a and / or the second via 112b may be, for example, respectively or include nickel, copper, a combination of the foregoing, or another suitable conductive material.

[0060] like Figure 8 As shown in the cross-sectional view 800, a second IC die 104 is provided and the Figure 7 The structure of the first IC die 106 is flipped and then bonded to the second IC die 104. The first interconnect structure 106 interfaces with the second interconnect structure 304 of the second IC die 104 at the hybrid joint. In some embodiments, the second IC die 104 is configured as Figure 3A or Figure 4In some embodiments, the first semiconductor substrate 108 has an initial thickness Ti defined between the front side 108f of the first semiconductor substrate 108 and the back side 108b of the first semiconductor substrate 108. In some embodiments, the initial thickness Ti is in the range of about 750 microns to 800 microns.

[0061] like Fig. 9 As shown in the cross-sectional view 900 of FIG. 1 , a thinning process is performed on the back side 108 b of the first semiconductor substrate 108 to expose the upper surface of the first TSV 118 and the upper surface of the second TSV 120. In some embodiments, the thinning process reduces the initial thickness Ti of the first semiconductor substrate 108 to a thickness Ts. In some embodiments, the thickness Ts may be in the range of about 1 micron to 5 microns. In some other embodiments, the thinning process may include a grinding process, an etching process, a mechanical grinding process, a planarization process (e.g., a CMP process), or a combination thereof.

[0062] like Fig.10 As shown in the cross-sectional view 1000 of , an upper dielectric structure 130 is formed over the back side 108b of the first semiconductor substrate 108. In some embodiments, the upper dielectric structure 130 includes a first passivation layer 324, a second passivation layer 326, a third passivation layer 328, and an upper dielectric layer 330. In some embodiments, the first passivation layer 324 may be, for example, or include an oxide (e.g., silicon dioxide) or another suitable dielectric material. In some embodiments, the second passivation layer 326 may be, for example, or include a nitride (e.g., silicon nitride) or another suitable dielectric material. In other embodiments, the third passivation layer 328 may be, for example, or include an oxide (e.g., silicon dioxide) or another suitable dielectric material. The upper dielectric layer 330 may be, for example, or include silicon dioxide, a low-k dielectric material, or another suitable dielectric material. In other embodiments, the layers of the upper dielectric structure 130 may be, for example, formed by one or more of a CVD process, a PVD process, or another suitable deposition process, respectively.

[0063] like Fig.11As shown in the cross-sectional view 1100 of FIG. 1 , the upper dielectric structure 130 is patterned to define a contact opening 1102 and expose the upper surfaces of the first TSV 118 and the second TSV 120. In some embodiments, the patterning process includes: forming a mask layer (not shown) over the upper dielectric structure 130; exposing an unmasked area of ​​the upper dielectric structure 130 to one or more etchants to define the contact opening 1102; and performing a removal process to remove the mask layer.

[0064] like Fig.12 As shown in the cross-sectional view 1200 of FIG. 1 , a first conductive layer 136 is formed over the upper dielectric structure 130, the first TSV 118, and the second TSV 120. The first conductive layer 136 at least partially fills the contact opening 1102. In some embodiments, the first conductive layer 136 may be, for example, or include a conductive material (e.g., nickel) that is configured to be converted into a silicide of a conductive material having a low resistivity (e.g., a resistivity of less than about 25 μΩ-cm) when exposed to an annealing process at a temperature in the range of about 320 degrees Celsius to 480 degrees Celsius. In some embodiments, the first conductive layer 136 is in direct contact with the first TSV 118 and / or the second TSV 120. For example, in some embodiments, the first conductive layer 136 may be in direct contact with the first doped channel region 122 and / or the second doped channel region 126. In yet other embodiments, the first conductive layer 136 may be formed by, for example, CVD, PVD, sputtering, electroless plating, electroplating, or another suitable growth or deposition process. In some embodiments, the first conductive layer 136 may include the same material (eg, nickel) as the first and second vias 112 a and 112 b .

[0065] like Fig.13 As shown in the cross-sectional view 1300 of FIG. 1 , a second conductive layer 138 is formed on the first conductive layer 136. The second conductive layer 138 at least partially fills the contact opening 1102. In some embodiments, the second conductive layer 138 may be, for example, or include titanium, nitride, titanium nitride, a combination of the foregoing, or another suitable conductive material. In various embodiments, the second conductive layer 138 includes a different material than the first conductive layer 136. In yet other embodiments, the second conductive layer 138 may be formed by, for example, CVD, PVD, sputtering, electroless plating, electroplating, or another suitable growth or deposition process.

[0066] like Fig.14 As shown in the cross-sectional view 1400 of FIG. 1 , a third conductive layer 140 is formed on the second conductive layer 138. In some embodiments, the third conductive layer 140 fills the contact opening ( Fig.13In some embodiments, the third conductive layer 140 may be, for example, or include tungsten or another suitable conductive material. In yet other embodiments, the third conductive layer 140 may include a material different from the first conductive layer 136 and / or the second conductive layer 138. In yet other embodiments, the third conductive layer 140 may be formed by, for example, CVD, PVD, sputtering, electroless plating, electroplating, or another suitable growth or deposition process.

[0067] like Fig.15 As shown in the cross-sectional view 1500 of FIG. 1 , a planarization process is performed on the first conductive layer 136, the second conductive layer 138, and the third conductive layer 140 until reaching the upper surface of the upper dielectric structure 130, thereby defining the conductive contacts 134 and the first IC die 102. In some embodiments, the planarization process may include performing an etching process, a planarization process (e.g., a CMP process), a combination of the foregoing, or another suitable planarization process.

[0068] like Fig.16 As shown in the cross-sectional view 1600 of FIG. 1 , a pixel substrate 144 is provided, and an upper interconnect structure 141 is formed along the front side 144f of the pixel substrate 144, thereby defining a pixel IC die 105. In some embodiments, the pixel substrate 144 may be, for example, or include a semiconductor substrate material (e.g., silicon), a bulk substrate (e.g., a bulk silicon substrate), a silicon-on-insulator (SOI) substrate, or some other suitable substrate. In some embodiments, before forming the upper interconnect structure 141, an implantation process may be performed to dope the pixel substrate 144 with a first doping type (e.g., p-type) to about 1*10 15 Atom / cm 3 In yet other embodiments, before forming the interconnect structure 141, a selective ion implantation process may be performed to form a plurality of photodetectors 150 in the pixel substrate 144, so that the photodetectors 150 include a second doping type (e.g., n-type) having a doping concentration greater than that of the pixel substrate 144. In some embodiments, the selective ion implantation process may include: forming a mask layer (not shown) on the front side 144f of the pixel substrate 144; selectively implanting dopants (e.g., n-type dopants) into the pixel substrate 144 according to the mask layer, thereby defining the photodetectors 150; and performing a removal process to remove the mask layer.

[0069] like Fig.17As shown in the cross-sectional view 1700 of , the pixel IC die 105 is bonded to the first IC die 102 so that the pixel IC die 105 and the first IC die 102 are interfaced to define a hybrid bond. In some embodiments, the hybrid bond may include a dielectric-to-dielectric bond between the upper interconnect dielectric structure 142 and the upper dielectric structure 130. In addition, the hybrid bond may include a conductor-to-conductor bond between the conductive contact 134 and the conductive layer (e.g., the conductive line 146) within the upper interconnect structure 141. In some embodiments, the process of bonding the pixel IC die 105 to the first IC die 102 may include, for example, a fusion bonding process and / or a metal bonding process. In yet other embodiments, an anti-reflective layer 332 is formed on the back side 144b of the pixel substrate 144. In addition, a plurality of color filters 334 are formed on the anti-reflective layer 332 so that the color filters 334 overlie the corresponding light detectors 150. Finally, microlenses 336 are formed on the plurality of color filters 334. In some embodiments, the anti-reflective layer 332, the color filter 334 and / or the anti-reflective layer 332 may be formed by, for example, CVD, PVD, ALD or another suitable deposition or growth process. In some embodiments, the pixel IC die 105 may be configured as Figure 1 , Figure 3A and / or Figure 4 The pixel IC die 105 is provided.

[0070] In some embodiments, after forming the photodetector 150 and / or after bonding the pixel IC die 105 to the first IC die 102, the Fig.15 or Fig.17The annealing process may be performed on the structure of the first semiconductor substrate 108. The annealing process may form an upper conductive layer 132 and a lower conductive layer 131 within the first semiconductor substrate 108. The upper conductive layer 132 may include a silicide (e.g., NiSi) of the first conductive layer 136, and the lower conductive layer 131 may include a silicide (e.g., NiSi) of the first via 112a and / or the second via 112b. In addition, the annealing process is configured to remove impurities from the first semiconductor substrate 108 and / or the pixel substrate 144, the impurities being generated, for example, due to an implantation process for forming the photodetector 150. The annealing process may be performed in a hydrogen (H2) environment at a temperature in a range of approximately 280 degrees Celsius to 410 degrees Celsius. In such embodiments, the first interconnect structure 106 and / or the conductive contact 134 are exposed to a reactive species (e.g., hydrogen (H2)) during the annealing process. In some embodiments, the first conductive layer 136 and the first and / or second vias 112a and 112b, respectively, include a conductive material (e.g., nickel) configured to form a low resistivity silicide with an adjacent semiconductor substrate material (e.g., silicon) when exposed to a temperature in a range of about 320 degrees Celsius to 480 degrees Celsius. Thus, the annealing process is configured to remove impurities from the first semiconductor substrate 108 and / or the pixel substrate 144 while forming the lower conductive layer 131 and the upper conductive layer 132. This, in part, causes the conductive contact 134 and / or the first and second vias 112a and 112b to have good electrical connections (e.g., ohmic contacts) with corresponding ones of the first and second TSVs 118 and 120. Since the annealing process has a maximum temperature of approximately 410 degrees Celsius, damage to semiconductor devices (eg, semiconductor device 308, photodetector 150, etc.) and / or layers within first IC die 102, second IC die 104, and / or pixel IC die 105 may be mitigated and / or eliminated.

[0071] In still other embodiments, a photodetector (not shown) may be formed within the first semiconductor substrate 108 in a region that is laterally offset from the first TSV 118 and / or the second TSV 120. In such embodiments, the photodetector may be formed before and / or after the first TSV 118 and the second TSV 120 are formed. In still other embodiments, the photodetector may be formed before and / or after the first TSV 118 and the second TSV 120 are formed but before the first IC die 102 is bonded to the second IC die 104. In such embodiments, an annealing process is performed after the photodetector and the conductive contacts 134 are formed and before another IC die (e.g., the pixel IC die 105) is bonded to the first IC die 102. In such embodiments, the lower conductive layer 131 and / or the upper conductive layer 132 are formed before the other IC die is bonded to the first IC die 102.

[0072] Fig.18 A block diagram of a method 1800 for forming a three-dimensional (3D) integrated circuit (IC) including a first IC die and a second IC die, each having an ion substrate through via (TSV) and a semiconductor device, wherein a conductive contact overlies the ion TSV. Although method 1800 is shown and / or described as a series of actions or events, it should be understood that the method is not limited to the order or actions shown. Therefore, in some embodiments, the actions may be performed in a different order than shown, and / or may be performed simultaneously. In addition, in some embodiments, the actions or events shown may be subdivided into multiple actions or events, which may be performed at different times or simultaneously with other actions or sub-actions. In some embodiments, some of the actions or events shown may be omitted, and other actions or events not shown may be included.

[0073] At act 1802, a through substrate via (TSV) is formed within a first semiconductor substrate. Figure 5 and Figure 6 Cross-sectional view 500 and cross-sectional view 600 are shown corresponding to some embodiments of act 1802 .

[0074] At act 1804, a first interconnect structure is formed along the front side of the first semiconductor substrate. The first interconnect structure includes a first via and a second via contacting the TSV. Figure 7 A cross-sectional view 700 corresponding to some embodiments of act 1804 is shown.

[0075] At act 1806, the first interconnect structure is bonded to the second IC die. Figure 8 A cross-sectional diagram 800 is shown corresponding to some embodiments of act 1806 .

[0076] At act 1808 , a thinning process is performed on the back side of the first semiconductor substrate until an upper surface of the TSV is exposed. Fig. 9 A cross-sectional view 900 is shown corresponding to some embodiments of act 1808 .

[0077] At act 1810 , an upper dielectric structure is formed along a backside of a first semiconductor substrate such that the upper dielectric structure contacts the TSV. Fig.10 A cross-sectional view 1000 is shown corresponding to some embodiments of act 1810 .

[0078] At act 1812, a conductive contact is formed on the corresponding TSV such that the conductive contact extends through the upper dielectric structure. The conductive contact comprises the same conductive material (eg, nickel) as the first and second vias, respectively. Figure 12 to Figure 15 Cross-sectional views 1200 through 1500 are shown corresponding to some embodiments of act 1812 .

[0079] At act 1814, a plurality of photodetectors are formed within a pixel substrate of the pixel IC die. Fig.16 Cross-sectional view 1600 is shown corresponding to some embodiments of act 1814 .

[0080] At act 1816 , the pixel IC die is bonded to the first semiconductor substrate via the upper dielectric structure. Fig.17 Cross-sectional view 1700 is shown corresponding to some embodiments of act 1816 .

[0081] At action 1818, an annealing process is performed on the photodetector and the conductive contact. The annealing process forms an upper conductive layer along the back side of the first semiconductor substrate and / or forms a lower conductive layer along the front side of the first semiconductor substrate. The lower conductive layer and the upper conductive layer each include a silicide of the same conductive material (e.g., NiSi). Fig.17 Cross-sectional view 1700 is shown corresponding to some embodiments of act 1818 .

[0082] Therefore, in some embodiments, the present disclosure is directed to an integrated circuit (IC) including an ionic through-substrate via (TSV) extending from a front side surface of a semiconductor substrate to a back side surface of the semiconductor substrate. A conductive contact overlies the ionic TSV, and an upper conductive layer is disposed between the ionic TSV and the conductive contact. The conductive contact includes a conductive material, and the ionic TSV includes a semiconductor material. The upper conductive layer includes a silicide of the conductive material and the semiconductor material.

[0083] In some embodiments, the present application provides an integrated chip including a semiconductor substrate, wherein the semiconductor substrate has a front surface and a back surface on opposite sides of the semiconductor substrate, respectively, wherein the semiconductor substrate includes: a first doped channel region extending from the front surface to the back surface; a first substrate through-hole (TSV) defined at least by the first doped channel region; a conductive contact overlying the back surface of the semiconductor substrate, wherein the conductive contact includes a first conductive layer overlying the first TSV, wherein the first conductive layer includes a conductive material; and an upper conductive layer below the conductive contact, wherein an upper surface of the upper conductive layer is aligned with the back surface of the semiconductor substrate, and wherein the upper conductive layer includes a silicide of the conductive material.

[0084] In the above integrated chip, the conductive material is nickel, and the silicide is nickel silicide.

[0085] In the above integrated chip, the upper conductive layer directly contacts the first conductive layer and directly contacts the first doped channel region.

[0086] In the above integrated chip, the first doped channel region laterally surrounds the upper conductive layer and covers the lower surface of the upper conductive layer in a cup shape.

[0087] In the above-mentioned integrated chip, the conductive contact further includes: a second conductive layer, extending along the upper surface of the first conductive layer; and a third conductive layer, extending along the upper surface of the second conductive layer, wherein the second conductive layer is arranged between the first conductive layer and the third conductive layer, and wherein the first conductive layer, the second conductive layer and the third conductive layer respectively include different materials from each other.

[0088] The above-mentioned integrated chip further includes: an internal connection structure, which is arranged along the front surface of the semiconductor substrate, wherein the internal connection structure includes a plurality of conductive wires and a plurality of conductive vias, wherein the plurality of conductive wires and the plurality of conductive vias define a conductive path to the first substrate through-hole, wherein the plurality of conductive vias include a first conductive via that is laterally separated between the side walls of the first substrate through-hole and includes the conductive material.

[0089] The above-mentioned integrated chip further includes: a lower conductive layer covering the first conductive hole, wherein the lower surface of the lower conductive layer is aligned with the front surface of the semiconductor substrate, and wherein the lower conductive layer includes the silicide of the conductive material.

[0090] In the above integrated chip, the lower conductive layer directly contacts the first doped channel region and directly contacts the first via.

[0091] In the above integrated chip, the resistivity of the upper conductive layer is in the range of about 5 microohm-cm to 25 microohm-cm.

[0092] In some embodiments, the present application provides an integrated circuit (IC), comprising: a first IC die, which includes a first semiconductor substrate and a first interconnect structure under the first semiconductor substrate, wherein the first interconnect structure includes a plurality of first conductive lines, wherein the first conductive lines respectively include a first conductive material; a second IC die under the first IC die, wherein the second IC die includes a second semiconductor substrate and a second interconnect structure overlying the second semiconductor substrate; and wherein the first IC die and the second IC die are in contact at a bonding interface between the first interconnect structure and the second interconnect structure; a plurality of semiconductor devices on the second semiconductor substrate; a first through substrate via (TSV) in the first semiconductor substrate and electrically coupled to the second interconnect structure through the first interconnect structure, wherein the first TSV and the first semiconductor substrate are composed of semiconductor material; a first conductive contact overlying the first semiconductor substrate, wherein the first conductive contact includes a second conductive material different from the first conductive material; and a first upper conductive layer disposed between the first conductive contact and the first TSV, wherein the first upper conductive layer includes a third conductive material different from the first conductive material and the second conductive material, respectively.

[0093] In the above integrated circuit, the third conductive material includes the semiconductor material and silicide of the second conductive material.

[0094] In the above integrated circuit, the first conductive material includes copper and / or aluminum, the second conductive material includes nickel, the third conductive material includes nickel silicide, and the semiconductor material includes silicon.

[0095] In the above integrated circuit, the first substrate through-hole includes an inner region surrounded by an outer region, wherein the inner region includes a first doping type and the outer region includes a second doping type opposite to the first doping type, wherein the first conductive contact is laterally disposed between opposite sidewalls of the inner region.

[0096] In the above integrated circuit, the first upper conductive layer is disposed between the opposite sidewalls of the inner region, wherein the first upper conductive layer is laterally offset from the outer region by a non-zero distance.

[0097] In the above-mentioned integrated circuit, it further includes: a pixel integrated circuit die, overlying the first integrated circuit die, wherein the pixel integrated circuit die includes a pixel substrate and an upper internal connection structure arranged along the front surface of the pixel substrate; a plurality of photodetectors, arranged in the pixel substrate, wherein the plurality of photodetectors include a first doping type; and wherein the first substrate through-hole includes a doped channel region, wherein the doped channel region extends from the bottom surface of the first semiconductor substrate to the top surface of the first semiconductor substrate, and wherein the doped channel region includes the first doping type.

[0098] In the above-mentioned integrated circuit, it further includes: a second substrate through-hole, located in the first semiconductor substrate and electrically coupled to the second internal connection structure through the first internal connection structure, wherein the second substrate through-hole includes the semiconductor material, wherein the second substrate through-hole includes a first doped channel region including a first doping type; a second conductive contact, covering the second substrate through-hole, wherein the second conductive contact includes the second conductive material; a second upper conductive layer, arranged between the second substrate through-hole and the second conductive contact, wherein the second upper conductive layer includes the third conductive material and is laterally arranged between the sidewalls of the first doped channel region; and wherein the first substrate through-hole includes an inner region laterally surrounded by an outer region, wherein the inner region includes a second doping type and the outer region includes the first doping type, wherein the first doping type is opposite to the second doping type, and wherein the first upper conductive layer is laterally spaced between the sidewalls of the inner region.

[0099] In some embodiments, the present application provides a method for forming an integrated circuit (IC), the method comprising performing a first ion implantation process on a front surface of a first semiconductor substrate to form a first doped channel region extending from the front surface into the first semiconductor substrate, wherein the first semiconductor substrate comprises a semiconductor material; forming a first internal wiring structure along the front surface of the first semiconductor substrate; thinning the first semiconductor substrate from a back surface of the first semiconductor substrate until the first doped channel region is exposed, wherein the back surface is opposite to the front surface; forming a conductive contact on the back surface of the first semiconductor substrate overlying and electrically coupled to the first doped channel region, wherein the conductive contact comprises a conductive material; and performing an annealing process to form an upper conductive layer within the first semiconductor substrate, wherein the upper conductive layer comprises a semiconductor material and a silicide of the conductive material.

[0100] In the above-mentioned method for forming an integrated circuit, forming the conductive contact comprises: forming an upper dielectric structure along the back surface of the first semiconductor substrate; etching the upper dielectric structure to define a contact opening above the first doped channel region; performing a first deposition process to define a first conductive layer above the upper dielectric structure and the first doped channel region, wherein the first conductive layer at least partially fills the contact opening, wherein the first conductive layer comprises the conductive material; performing a second deposition process to define a second conductive layer above the first conductive layer, wherein the second conductive layer at least partially fills the contact opening; performing a third deposition process to define a third conductive layer above the second conductive layer, wherein the third conductive layer fills the remaining portion of the contact opening, wherein the second conductive layer and the third conductive layer respectively comprise materials different from the conductive material; and performing a planarization process on the first conductive layer, the second conductive layer and the third conductive layer until reaching the upper dielectric structure, thereby defining the conductive contact.

[0101] In the above-mentioned method for forming an integrated circuit, it further includes: forming a plurality of photodetectors in a pixel substrate; bonding the pixel substrate to the first semiconductor substrate; and performing the annealing process after bonding the pixel substrate to the first semiconductor substrate, wherein the annealing process is performed while exposing the conductive contacts and the photodetectors to a reactive substance.

[0102] In the above method for forming an integrated circuit, the annealing process reaches a maximum temperature of about 410 degrees Celsius.

[0103] The foregoing summarizes the features of several embodiments so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art will appreciate that they can easily use the present disclosure as a basis for designing or modifying other processes and structures for achieving the same purpose and / or achieving the same advantages of the embodiments introduced herein. Those skilled in the art will also recognize that such equivalent constructions do not depart from the spirit and scope of the present invention, and that various changes, substitutions, and modifications may be made herein without departing from the spirit and scope of the present invention.

Claims

1. An integrated chip, comprising: a semiconductor substrate having a front surface and a back surface on opposite sides of the semiconductor substrate, respectively, wherein the semiconductor substrate includes a first doped channel region extending from the front surface to the back surface; a first substrate through-hole defined by at least the first doped channel region; a conductive contact overlying the backside surface of the semiconductor substrate, wherein the conductive contact comprises a first conductive layer overlying the first substrate through-hole, wherein the first conductive layer comprises a conductive material; as well as An upper conductive layer is located below the conductive contact, wherein an upper surface of the upper conductive layer is aligned with the backside surface of the semiconductor substrate, and wherein the upper conductive layer includes a silicide of the conductive material. 2 . The integrated chip according to claim 1 , wherein the conductive material is nickel, and the silicide is nickel silicide. 3 . The integrated chip of claim 1 , wherein the upper conductive layer directly contacts the first conductive layer and directly contacts the first doped channel region. 4 . The integrated chip according to claim 1 , wherein the first doped channel region laterally surrounds the upper conductive layer and covers a lower surface of the upper conductive layer in a cup shape.

5. The integrated chip according to claim 1, wherein the conductive contact further comprises: a second conductive layer extending along an upper surface of the first conductive layer; as well as The third conductive layer extends along the upper surface of the second conductive layer, wherein the second conductive layer is disposed between the first conductive layer and the third conductive layer, and wherein the first conductive layer, the second conductive layer and the third conductive layer respectively include different materials from each other.

6. The integrated chip according to claim 1, further comprising: An internal connection structure is arranged along the front side surface of the semiconductor substrate, wherein the internal connection structure includes a plurality of conductive lines and a plurality of vias, wherein the plurality of conductive lines and the plurality of vias define a conductive path to the first substrate through-hole, wherein the plurality of vias include a first via laterally spaced between sidewalls of the first substrate through-hole and including the conductive material.

7. The integrated chip according to claim 6, further comprising: A lower conductive layer overlies the first conductive via, wherein a lower surface of the lower conductive layer is aligned with the front surface of the semiconductor substrate, and wherein the lower conductive layer includes the silicide of the conductive material. 8 . The integrated chip according to claim 7 , wherein the lower conductive layer directly contacts the first doped channel region and directly contacts the first via.

9. The integrated chip according to claim 1, wherein the resistivity of the upper conductive layer is in the range of 5 microohm centimeters to 25 microohm centimeters.

10. An integrated circuit comprising: A first integrated circuit die, comprising a first semiconductor substrate and a first interconnect structure located below the first semiconductor substrate, wherein the first interconnect structure comprises a plurality of first conductive lines, wherein the plurality of first conductive lines respectively comprise a first conductive material; a second integrated circuit die located below the first integrated circuit die, wherein the second integrated circuit die comprises a second semiconductor substrate and a second interconnect structure overlying the second semiconductor substrate; and wherein the first integrated circuit die and the second integrated circuit die are in contact at a bonding interface between the first interconnect structure and the second interconnect structure; a plurality of semiconductor devices, located on the second semiconductor substrate; a first through-substrate via located in the first semiconductor substrate and electrically coupled to the second internal interconnect structure through the first internal interconnect structure, wherein the first through-substrate via and the first semiconductor substrate are formed of a semiconductor material; a first conductive contact overlying the first semiconductor substrate, wherein the first conductive contact comprises a second conductive material different from the first conductive material; as well as A first upper conductive layer is disposed between the first conductive contact and the first through-substrate via, wherein the first upper conductive layer comprises a third conductive material different from the first conductive material and the second conductive material.

11. The integrated circuit of claim 10, wherein the third conductive material comprises a silicide of the semiconductor material and the second conductive material.

12. The integrated circuit of claim 10, wherein the first conductive material comprises copper and / or aluminum, the second conductive material comprises nickel, the third conductive material comprises nickel silicide, and the semiconductor material comprises silicon.

13. The integrated circuit of claim 10, wherein the first substrate through-hole comprises an inner region surrounded by an outer region, wherein the inner region comprises a first doping type and the outer region comprises a second doping type opposite to the first doping type, wherein the first conductive contact is laterally disposed between opposite sidewalls of the inner region.

14. The integrated circuit of claim 13, wherein the first upper conductive layer is disposed between the opposing sidewalls of the inner region, wherein the first upper conductive layer is laterally offset from the outer region by a non-zero distance.

15. The integrated circuit of claim 10, further comprising: a pixel integrated circuit die overlying the first integrated circuit die, wherein the pixel integrated circuit die comprises a pixel substrate and an upper interconnect structure disposed along a front surface of the pixel substrate; a plurality of photodetectors disposed within the pixel substrate, wherein the plurality of photodetectors include a first doping type; as well as Wherein the first substrate through-hole comprises a doped channel region, wherein the doped channel region extends from a bottom surface of the first semiconductor substrate to a top surface of the first semiconductor substrate, and wherein the doped channel region comprises the first doping type.

16. The integrated circuit of claim 10, further comprising: a second through-substrate via located in the first semiconductor substrate and electrically coupled to the second interconnect structure through the first interconnect structure, wherein the second through-substrate via comprises the semiconductor material, wherein the second through-substrate via comprises a first doped channel region comprising a first doping type; a second conductive contact overlying the second substrate through-hole, wherein the second conductive contact comprises the second conductive material; a second upper conductive layer disposed between the second through-substrate via and the second conductive contact, wherein the second upper conductive layer comprises the third conductive material and is laterally disposed between sidewalls of the first doped channel region; and wherein the first substrate penetration comprises an inner region laterally surrounded by an outer region, wherein the inner region comprises a second doping type and the outer region comprises the first doping type, wherein the first doping type is opposite to the second doping type, and wherein the first upper conductive layer is laterally spaced between sidewalls of the inner region.

17. A method for forming an integrated circuit, the method comprising: performing a first ion implantation process on a front side surface of a first semiconductor substrate to form a first doped channel region extending from the front side surface into the first semiconductor substrate, wherein the first semiconductor substrate comprises a semiconductor material; forming a first interconnect structure along the front surface of the first semiconductor substrate; Thinning the first semiconductor substrate from a backside surface of the first semiconductor substrate until the first doped channel region is exposed, wherein the backside surface is opposite to the frontside surface; forming a conductive contact on the backside surface of the first semiconductor substrate overlying and electrically coupled to the first doped channel region, wherein the conductive contact comprises a conductive material; as well as An annealing process is performed to form an upper conductive layer in the first semiconductor substrate, wherein the upper conductive layer includes the semiconductor material and a silicide of the conductive material.

18. The method for forming an integrated circuit according to claim 17, wherein forming the conductive contact comprises: forming an upper dielectric structure along the backside surface of the first semiconductor substrate; etching the upper dielectric structure to define a contact opening above the first doped channel region; performing a first deposition process to define a first conductive layer over the upper dielectric structure and the first doped channel region, wherein the first conductive layer at least partially fills the contact opening, wherein the first conductive layer includes the conductive material; performing a second deposition process to define a second conductive layer over the first conductive layer, wherein the second conductive layer at least partially fills the contact opening; performing a third deposition process to define a third conductive layer over the second conductive layer, wherein the third conductive layer fills a remaining portion of the contact opening, wherein the second conductive layer and the third conductive layer respectively include a material different from the conductive material; as well as A planarization process is performed on the first conductive layer, the second conductive layer, and the third conductive layer until reaching the upper dielectric structure, thereby defining the conductive contact.

19. The method for forming an integrated circuit according to claim 17, further comprising: forming a plurality of photodetectors within a pixel substrate; bonding the pixel substrate to the first semiconductor substrate; as well as The annealing process is performed after bonding the pixel substrate to the first semiconductor substrate, and the annealing process is performed while exposing the conductive contacts and the photodetectors to a reactive species.

20. The method for forming an integrated circuit of claim 19, wherein the annealing process reaches a maximum temperature of 410 degrees Celsius.

Images