Semiconductor Device and Layout Design Methods

Abstract

A semiconductor device and layout design method are disclosed. The semiconductor device includes a first unit cell and a second unit cell. The first unit cell includes a first fin pattern extending along a first direction, a first gate pattern extending along a second direction, and a first contact disposed on one side of the first gate pattern and contacting the first fin pattern. The second unit cell includes a second fin pattern extending along the first direction, a second gate pattern extending along the second direction, and a second contact disposed on one side of the second gate pattern and contacting the second fin pattern. The first gate pattern and the second gate pattern are spaced apart and located on a first straight line extending along the second direction. The first contact and the second contact are spaced apart and located on a second straight line extending along the second direction. A first intermediate contact is disposed on the first contact and the second contact and connects the first contact and the second contact.

Description

[0001] This application claims the benefit of Korean Patent Application No. 10-2019-0108535, filed on September 3, 2019, with the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference. Technical Field

[0002] This disclosure relates to a semiconductor device and a layout design method. Background Technology

[0003] With the rapid shrinking of semiconductor components due to advancements in electronic technology, there is a growing demand for more highly integrated semiconductor devices that consume less power. To meet the requirements for higher integration and lower power consumption, the feature size of semiconductor devices continues to decrease.

[0004] However, the reduced feature size results in insufficient margin between adjacent patterns. Summary of the Invention

[0005] This disclosure provides a semiconductor device with improved margin between adjacent patterns.

[0006] This disclosure also provides a layout design method for improving the margin between adjacent patterns by performing layout correction on areas prone to process defects due to insufficient process margin.

[0007] However, the aspects of this disclosure are not limited to those set forth herein. These and other aspects of this disclosure will become more apparent to those skilled in the art upon reference to the detailed description of this disclosure given below.

[0008] According to one aspect of this disclosure, a semiconductor device is provided, the semiconductor device including a first unit cell and a second unit cell, wherein the first unit cell includes: a first fin pattern extending longitudinally along a first direction; a first gate pattern extending longitudinally along a second direction to intersect the first fin pattern; and a first contact disposed on one side of the first gate pattern to contact the first fin pattern, wherein the second unit cell includes: a second fin pattern extending longitudinally along the first direction; a second gate pattern extending longitudinally along the second direction to intersect the second fin pattern; and a second contact disposed on one side of the second gate pattern to contact the second fin pattern, and wherein the first gate pattern and the second gate pattern are spaced apart from each other and located on a first straight line extending longitudinally along the second direction, the first contact and the second contact are spaced apart from each other and located on a second straight line extending longitudinally along the second direction, and a first intermediate contact is disposed on the first contact and the second contact and connects the first contact and the second contact to each other.

[0009] According to another aspect of this disclosure, a semiconductor device is provided, the semiconductor device comprising: a first gate pattern and a second gate pattern located on a first straight line extending along a first direction and extending longitudinally along the first direction; a first contact and a second contact located on a second straight line extending along the first direction and extending longitudinally along the first direction; and an intermediate contact disposed on the first contact and the second contact and extending along the first direction to connect the first contact and the second contact to each other, wherein a first gap between the first gate pattern and the second gate pattern is smaller than a second gap between the first contact and the second contact.

[0010] According to another aspect of this disclosure, a semiconductor device is provided, the semiconductor device comprising: a first fin pattern, a second fin pattern, and a third fin pattern arranged sequentially; a first contact, a second contact, and a third contact respectively contacting the first fin pattern, the second fin pattern, and the third fin pattern; a first intermediate contact disposed on the first contact and the second contact and directly contacting the first contact and the second contact; and a second intermediate contact disposed on the third contact, formed at the same vertical level as the first intermediate contact and directly contacting the third contact, wherein the first intermediate contact is connected to a first voltage, and the second intermediate contact is connected to a second voltage higher than the first voltage.

[0011] According to another aspect of this disclosure, a layout design method is provided, the layout design method comprising: preparing an original layout, wherein the original layout includes a first SRAM unit cell and a second SRAM unit cell; searching for an original contact pattern that directly connects a first fin pattern of the first SRAM unit cell and a second fin pattern of the second SRAM unit cell; generating a first contact pattern that directly contacts the first fin pattern and a second contact pattern that directly contacts the second fin pattern by cutting the original contact pattern; generating a first target pattern and a second target pattern by reflecting etch skew in the first contact pattern and the second contact pattern; and performing optical proximity correction (OPC) on the first target pattern and the second target pattern. Attached Figure Description

[0012] Figure 1 This is a circuit diagram of a semiconductor device according to an example embodiment;

[0013] Figure 2 This is a layout diagram of a semiconductor device according to a first example embodiment;

[0014] Figure 3 yes Figure 2 A layout diagram of multiple fin patterns;

[0015] Figure 4 yes Figure 2 A layout diagram of multiple gate patterns;

[0016] Figure 5 yes Figure 2 Layout diagram of multiple contact components;

[0017] Figure 6 yes Figure 2 Layout diagram of multiple intermediate contact components;

[0018] Figure 7 yes Figure 2 Detailed layout diagram of some components (gate pattern, contacts and intermediate contacts);

[0019] Figure 8 It is along Figure 2 A sectional view taken by line AA;

[0020] Figure 9A It is along Figure 2 A sectional view taken by line BB;

[0021] Figure 9B It is along Figure 2 A sectional view taken from line DD;

[0022] Figure 10 This is a layout diagram of a semiconductor device according to a second example embodiment;

[0023] Figure 11 It is along Figure 10 A cross-sectional view taken by line CC;

[0024] Figure 12 This is a block diagram of a semiconductor device according to a third exemplary embodiment;

[0025] Figure 13 This is a cross-sectional view of a semiconductor device according to a third exemplary embodiment;

[0026] Figure 14 This is a cross-sectional view of a semiconductor device according to a fourth exemplary embodiment;

[0027] Figure 15 This is a cross-sectional view of a semiconductor device according to a fifth exemplary embodiment;

[0028] Figure 16 This is a flowchart illustrating a layout design method according to an example embodiment;

[0029] Figure 17 It is used for explanation Figure 16 A diagram of example operations; and

[0030] Figure 18 It is used for explanation Figure 16 A diagram of example operations. Detailed Implementation

[0031] In the following description, various embodiments of the present disclosure will be described with reference to the accompanying drawings. In the drawings, the dimensions and relative dimensions of layers and regions may be exaggerated for clarity. The same reference numerals always refer to the same elements. Although the different drawings illustrate variations of exemplary embodiments, these drawings are not necessarily intended to exclude each other. Rather, as will be seen from the context of the detailed description below, certain features depicted and described in different drawings may be combined with other features from other drawings to produce various embodiments when the drawings and their description are considered as a whole.

[0032] Figure 1 This is a circuit diagram of a semiconductor device according to an example embodiment.

[0033] The semiconductor device according to the example embodiments may be, but is not limited to, static random access memory (SRAM), dynamic random access memory (DRAM), mobile DRAM, flash memory, electrically erasable programmable read-only memory (EEPROM), resistive random access memory (RRAM), phase-change random access memory (PRAM), or ferroelectric random access memory (FeRAM). For ease of description, the following description will be based on SRAM.

[0034] Reference Figure 1 The SRAM unit cell includes a first inverter INV1, a second inverter INV2, a first pass element PG1, and a second pass element PG2.

[0035] The first inverter INV1 and the second inverter INV2 output data with opposite phases. Specifically, the first inverter INV1 includes a first pull-up element PU1 and a first pull-down element PD1. The first pull-up element PU1 may be, but is not limited to, a p-channel metal-oxide-semiconductor (PMOS) transistor, and the first pull-down element PD1 may be, but is not limited to, an n-channel metal-oxide-semiconductor (NMOS) transistor.

[0036] The second inverter INV2 includes a second pull-up element PU2 and a second pull-down element PD2. The second pull-up element PU2 can be, but is not limited to, a PMOS transistor, and the second pull-down element PD2 can be, but is not limited to, an NMOS transistor.

[0037] The sources of pull-down elements PD1 and PD2 are connected to a first voltage (e.g., ground voltage VSS). Additionally, the sources of pull-up elements PU1 and PU2 are connected to a second voltage higher than the first voltage (e.g., power supply voltage VDD), and the drains of pull-up elements PU1 and PU2 are connected to the drains of their respective pull-down elements PD1 and PD2. Furthermore, the input terminal of the first inverter INV1 is connected to the output terminal / node N2 of the second inverter INV2, and the input terminal of the second inverter INV2 is connected to the output terminal / node N1 of the first inverter INV1.

[0038] The first pass element PG1 has a gate connected to the word line WL, a drain connected to the bit line BL, and a source connected to the output terminal / node N1 of the first inverter INV1. The second pass element PG2 also has a gate connected to the word line WL, a drain connected to the bit line BLB, and a source connected to the output terminal / node N2 of the second inverter INV2. Here, the inverted phase line signal is transmitted to the bit line BLB.

[0039] The SRAM unit cell operates as follows. When the potential of word line WL is 1 (i.e., high level), the first pass element PG1 and the second pass element PG2 are turned on to transmit the signals of bit lines BL and BLB to the first inverter INV1 and the second inverter INV2, respectively. Therefore, a data write or read operation is performed.

[0040] Figure 2 This is a layout diagram of a semiconductor device according to the first embodiment. Figure 3 yes Figure 2 The layout diagram of multiple fin patterns F1 to F8. Figure 4 yes Figure 2 The layout diagram of multiple gate patterns G1 to G6. Figure 5 yes Figure 2 The layout diagram of the multiple contacts CA1 to CA10 and CB1 to CB4. Figure 6 yes Figure 2 Layout diagram of multiple intermediate contact parts CM1 and CM3 to CM10. Figure 7 yes Figure 2 Detailed layout diagram of some components (e.g., gate patterns G1 and G2, contacts CA1 and CA2, and intermediate contact CM1).

[0041] The semiconductor device according to the first embodiment includes fin patterns F1 to F8, gate patterns G1 to G6, contacts CA1 to CA10 and CB1 to CB4, and intermediate contacts CM1 and CM3 to CM10.

[0042] First, refer to Figure 2 and Figure 3Fin patterns F1 to F8 can be formed in the active region of the substrate. Each of the fin patterns F1 to F8 can extend longitudinally along a first direction DR1. The fin patterns F1 to F8 can be spaced apart from each other and arranged along a second direction DR2. The first direction DR1 can be perpendicular to the second direction DR2.

[0043] As shown, some fin patterns (e.g., F1, F2, F5, and F6) may include multiple sub-fin patterns. For example, the first fin pattern F1 may include at least two sub-fin patterns F11 and F12, the second fin pattern F2 may include at least two sub-fin patterns F21 and F22, the fifth fin pattern F5 may include at least two sub-fin patterns F51 and F52, and the sixth fin pattern F6 may include at least two sub-fin patterns F61 and F62. Using at least two sub-fin patterns (e.g., F11 and F12) widens the region where current can flow between the source and drain, thereby increasing the current drive capability of the transistor.

[0044] As shown, the gap between adjacent sub-fin patterns (e.g., F11 and F12) (i.e., the gap between F11 and F12 in the second direction DR2) can be smaller than the gap between adjacent fin patterns (e.g., F1 and F2) (i.e., the gap between F11 and F22 in the second direction DR2).

[0045] exist Figure 2 In the design, fin patterns F1, F2, F5, and F6, which have multiple sub-fin patterns (e.g., F11 and F12, F21 and F22, F51 and F52, and F61 and F62), can be used as the source / drain regions of NMOS transistors (i.e., pull-down elements PD1 and PD2 and through elements PG1 and PG2). Additionally, other fin patterns F3, F4, F7, and F8 can be used as the source / drain regions of PMOS transistors (i.e., pull-up elements PU1 and PU2).

[0046] N-wells (NW) can be formed in the regions of the substrate 100 where pull-up elements PU1 and PU2 are formed (i.e., the regions where fin patterns F3, F4, F7, and F8 are formed). P-wells can also be formed in the regions of the substrate 100 where pull-down elements PD1 and PD2 are formed or where elements PG1 and PG2 are formed (i.e., the regions where fin patterns F1, F2, F5, and F6 are formed). However, the embodiments are not limited to this.

[0047] Reference Figure 2 and Figure 4Gate patterns G1 to G6 can extend along the second direction DR2. Specifically, some gate patterns G1, G2, and G3 can be located on a straight line extending longitudinally along the second direction DR2. Some other gate patterns G4, G5, and G6 can be located on another straight line extending longitudinally along the second direction DR2. For example, the longitudinal axes of gate patterns G1, G2, and G3 can be aligned along the same first straight line, and the longitudinal axes of gate patterns G4, G5, and G6 can be aligned along the same second straight line. Gate patterns G1, G2, and G3 are spaced apart from gate patterns G4, G5, and G6 in the first direction DR1.

[0048] Additionally, gate patterns G1 to G6 can intersect with corresponding fin patterns F1 to F8. For example, gate pattern G1 intersects with fin patterns F1 and F3, gate pattern G2 intersects with fin patterns F2 and F4, gate pattern G3 intersects with fin pattern F5, gate pattern G4 intersects with fin patterns F1 and F2, gate pattern G5 intersects with fin patterns F5 and F7, and gate pattern G6 intersects with fin patterns F6 and F8.

[0049] Reference Figure 2 and Figure 5 Contacts CA1 to CA10 can be source / drain contacts. Some contacts CA1, CA2, CA5, CA8, and CA10 can be located on a straight line extending longitudinally along the second direction DR2. Some other contacts CA3 and CA4 can be located on another straight line extending longitudinally along the second direction DR2. Some other contacts CA6, CA7, and CA9 can be located on yet another straight line extending longitudinally along the second direction DR2. For example, the longitudinal axes of contacts CA1, CA2, CA5, CA8, and CA10 can be aligned along the same first straight line, the longitudinal axes of contacts CA3 and CA4 can be aligned along the same second straight line, and the longitudinal axes of contacts CA6, CA7, and CA9 can be aligned along the same third straight line.

[0050] Contacts CA1 and CA3 to CA9 are disposed in the first unit UC1, and contacts CA2 and CA10 are disposed in the second unit UC2.

[0051] Specifically, in the first unit cell UC1, a contact CA1 is formed on the first side of the first gate pattern G1 to contact the first fin pattern F1.

[0052] Contact CA3 is formed on the second side of the first gate pattern G1, the first side of the fifth gate pattern G5, and the first side of the fourth gate pattern G4 (i.e., between the first gate pattern G1 and the fifth gate pattern G5 and between the first gate pattern G1 and the fourth gate pattern G4) to contact the first fin pattern F1 and the third fin pattern F3.

[0053] Contact CA4 is formed on the second side of the first gate pattern G1, the second side of the third gate pattern G3, and the first side of the fifth gate pattern G5 (i.e., between the first gate pattern G1 and the fifth gate pattern G5 and between the third gate pattern G3 and the fifth gate pattern G5) to contact the fifth fin pattern F5 and the seventh fin pattern F7.

[0054] Contact CA5 is formed on the first side of the third gate pattern G3 to contact the fifth fin pattern F5. Contact CA6 is formed on the second side of the fifth gate pattern G5 to contact the fifth fin pattern F5. Contact CA7 is formed on the second side of the fourth gate pattern G4 to contact the first fin pattern F1. Contact CA8 is formed on the first side of the first gate pattern G1 to contact the third fin pattern F3. Contact CA9 is formed on the second side of the fifth gate pattern G5 to contact the seventh fin pattern F7.

[0055] Additionally, in the second unit cell UC2, contact CA2 is formed on the first side of the second gate pattern G2 to contact the second fin pattern F2. Contact CA10 is formed on the first side of the second gate pattern G2 to contact the fourth fin pattern F4.

[0056] Reference Figure 2 and Figure 5 Contacts CB1 to CB4 can be gate contacts.

[0057] Contact CB1 is disposed on the fifth gate pattern G5. Specifically, contact CB1 is also disposed on the third fin pattern F3 and contacts contact CA3. For example, the fifth gate pattern G5 is electrically connected via contacts CB1 and CA3 to a portion of the first fin pattern F1 and a portion of the third fin pattern F3 located on the second side of the first gate pattern G1. Contacts CB1 and CA3 correspond to Figure 1 Node N2. As described above, refer to Figure 1 The gate of the first pull-up element PU1, the gate of the first pull-down element PD1, the drain of the second pull-up element PU2, and the drain of the second pull-down element PD2 are connected at node N2.

[0058] Contact CB2 is disposed on the first gate pattern G1. Specifically, contact CB2 is also disposed on the seventh fin pattern F7 and contacts contact CA4. For example, the first gate pattern G1 is electrically connected via contacts CB2 and CA4 to a portion of the seventh fin pattern F7 and a portion of the fifth fin pattern F5 located on the first side of the fifth gate pattern G5. Contacts CB2 and CA4 correspond to Figure 1 Node N1. As described above, refer to Figure 1The gate of the second pull-up element PU2, the gate of the second pull-down element PD2, the drain of the first pull-up element PU1, and the drain of the first pull-down element PD1 are connected at node N1.

[0059] Contact CB3 is disposed on the fourth gate pattern G4 and electrically connected to the word line WL. Contact CB4 is disposed on the third gate pattern G3 and electrically connected to the word line WL.

[0060] Reference Figure 2 and Figure 6 Intermediate contacts CM1 and CM3 to CM10 are disposed on contacts CA1 to CA10 and CB1 to CB4. Additionally, some intermediate contacts (e.g., CM1) can directly contact corresponding contacts (e.g., CA1 and CA2) and electrically connect the corresponding contacts CA1 and CA2. For example, intermediate contacts CM1 and CM3 to CM10 are used to route electrical signals between adjacent gate contacts and / or source / drain contacts.

[0061] Intermediate contacts CM1 and CM3 through CM10 differ from the wiring structure (i.e., the wiring structure including vias and / or general wiring). Each of intermediate contacts CM1 and CM3 through CM10 can be shaped to resemble a wiring structure that does not include vias and extends longitudinally in one direction. Intermediate contacts CM1 and CM3 through CM10 can be relatively shorter in length than general wiring.

[0062] When viewed in cross-section, intermediate contact members CM1 and CM3 to CM10 can be formed at the same vertical level.

[0063] Some intermediate contacts CM1, CM5, CM8, and CM10 may be located on a straight line extending longitudinally along the second direction DR2. Some other intermediate contacts CM6, CM7, and CM9 may be located on another straight line extending longitudinally along the second direction DR2. For example, the longitudinal axes of intermediate contacts CM1, CM5, CM8, and CM10 may be aligned along the same first straight line, and the longitudinal axes of intermediate contacts CM6, CM7, and CM9 may be aligned along the same second straight line.

[0064] Intermediate contact CM1 is disposed on adjacent contacts CA1 and CA2 and connects adjacent contacts CA1 and CA2 to each other. Intermediate contact CM1 is electrically connected to a first voltage (e.g., ground voltage VSS).

[0065] Intermediate contact CM3 can be disposed on contact CB3 and electrically connected to word line WL. Intermediate contact CM4 can be disposed on contact CB4 and electrically connected to word line WL. Intermediate contact CM5 can be disposed on contact CA5 and electrically connected to bit line BL. Intermediate contact CM6 can be disposed on contact CA6 and electrically connected to a first voltage (e.g., ground voltage VSS). Intermediate contact CM7 can be disposed on contact CA7 and electrically connected to bit line BLB. Intermediate contact CM8 can be disposed on contact CA8 and electrically connected to a second voltage (e.g., power supply voltage VDD). Intermediate contact CM9 can be disposed on contact CA9 and electrically connected to a second voltage (e.g., power supply voltage VDD). Intermediate contact CM10 can be disposed on contact CA10 and electrically connected to a second voltage (e.g., power supply voltage VDD).

[0066] In addition, no intermediate contact is provided on contact CA3 and CB1, and no intermediate contact is provided on contact CA4 and CB2.

[0067] Here, refer to Figure 2 and Figure 7 The first gate pattern G1 and the second gate pattern G2 are located on a first straight line Q1 extending longitudinally along the second direction DR2. For example, the longitudinal axis of the first gate pattern G1 and the longitudinal axis of the second gate pattern G2 can be aligned on the first straight line Q1.

[0068] Contacts CA1 and CA2 are also located on a second straight line Q2 extending longitudinally along the second direction DR2. For example, the longitudinal axes of contact CA1 and contact CA2 can be aligned on the second straight line Q2. The intermediate contact CM1 extends in the second direction DR2 and electrically connects adjacent contacts CA1 and CA2.

[0069] The reason why the first fin pattern F1 on the first side of the first gate pattern G1 and the second fin pattern F2 on the first side of the second gate pattern G2 are connected by contacts CA1 and CA2 and intermediate contact CM1 is as follows.

[0070] If the first fin pattern F1 on the first side of the first gate pattern G1 and the second fin pattern F2 on the first side of the second gate pattern G2 are connected using a contact extending longitudinally in the second direction DR2 (i.e., a common contact) (instead of using the intermediate contact CM1), then the space allowance from the end GE1 of the first gate pattern G1 and the end GE2 of the second gate pattern G2 to the common contact is insufficient. In this case, the process itself is not impossible, but the insufficient process allowance can easily cause short circuits between the gate patterns G1 and G2 and the common contact (i.e., can easily cause process defects).

[0071] To prevent such process defects, separate contacts CA1 and CA2 are used instead of common contacts. When separate contacts CA1 and CA2 are used, the process margin from gate patterns G1 and G2 to the separate contacts CA1 and CA2 can be sufficiently increased. Specifically, the first gap L1 between the first gate pattern G1 and the second gate pattern G2 can be smaller than the second gap L2 between the first contact CA1 and the second contact CA2. Therefore, this sufficiently increases the distance from the end GE1 of the first gate pattern G1 to the end CAE1 of the contact CA1 and the distance from the end GE2 of the second gate pattern G2 to the end CAE2 of the contact CA2. Thus, sufficient process margin from gate patterns G1 and G2 to the separate contacts CA1 and CA2 can be ensured, thereby minimizing process defects.

[0072] Figure 8 It is along Figure 2 The sectional view taken by line AA. Figure 9A It is along Figure 2 The sectional view taken by line BB. Figure 9B It is along Figure 2 The sectional view taken by line DD.

[0073] Reference Figure 2 , Figure 8 , Figure 9A and Figure 9B The semiconductor device according to the first embodiment includes fin patterns F1 to F8, gate patterns G1 to G6, contacts CA1 to CA10 and CB1 to CB4, and intermediate contacts CM1 and CM3 to CM10.

[0074] The substrate 100 may be, for example, a bulk silicon substrate or a silicon-on-insulator (SOI) substrate. Optionally, the substrate 100 may include a group IV-VI compound semiconductor or a group III-V compound semiconductor. For example, the substrate 100 may include silicon germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide. Optionally, the substrate 100 may include a base substrate and an epitaxial layer formed on the base substrate.

[0075] Each of the fin patterns F1 to F8 may be a portion of the substrate 100 (e.g., formed by etching the substrate 100) or may be formed on the substrate 100 (e.g., including an epitaxial layer grown from the substrate 100). Optionally, each of the fin patterns F1 to F8 may be made of a group IV-VI compound semiconductor or a group III-V compound semiconductor.

[0076] A field insulating layer 105 may be formed on the substrate 100. The field insulating layer 105 is formed to fill at least a portion of the region (i.e., the trench region) between adjacent fin patterns F1 to F8 and between adjacent sub-fin patterns (e.g., between sub-fin patterns F11 and F12). The field insulating layer 105 may include, for example, an oxide layer, a nitride layer, an oxide oxynitride layer, and combinations thereof. The field insulating layer 105 may partially contact the fin patterns F1 to F8. Figure 9A As shown, at least a portion of each of the fin patterns F1 to F8 may protrude above the upper surface of the field insulation layer 105.

[0077] Gate pattern (e.g., G1) (corresponding to) Figure 9A and Figure 9B The gate pattern 130 can be formed on the field insulating layer 105. For example... Figure 9A and Figure 9B As shown, the gate pattern 130 may include two or more stacked metal layers MG1 and MG2. The first metal layer MG1 controls the work function, and the second metal layer MG2 fills the space formed by the first metal layer MG1. For example, the first metal layer MG1 may include, but is not limited to, at least one of TiN, WN, TiAl, TiAlN, TiAlC, TaN, TiC, TaC, TaCN, TaSiN, and combinations thereof. Furthermore, the second metal layer MG2 may include, but is not limited to, at least one of W, Al, Cu, Co, Ti, Ta, polycrystalline Si, SiGe, and metal alloys.

[0078] The gate pattern 130 can be formed by, but is not limited to, a replacement process (or a post-gate process).

[0079] A gate insulating layer 135 may be formed between the fin patterns (e.g., F1 and F3) and the gate pattern 130. Specifically, the gate insulating layer 135 may be formed along the contours of the fin patterns F1 to F8 that protrude above the field insulating layer 105, for example, along the contours of the first fin pattern F1 and the third fin pattern F3. Additionally, the gate insulating layer 135 may be formed between the gate pattern 130 and the field insulating layer 105. For example, the gate insulating layer 135 may be formed on the upper surface of the field insulating layer 105, and a first metal layer MG1 may be formed on the upper surface of the gate insulating layer 135.

[0080] The gate insulating layer 135 may comprise silicon oxide, silicon oxynitride, silicon nitride, or a high-k material having a dielectric constant higher than that of silicon oxide. The high-k material may comprise, for example, one or more of hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate.

[0081] In addition, such as Figure 9B As shown, spacer 140 may be formed on the sidewall of gate pattern 130. Spacer 140 may include at least one of, for example, silicon nitride (SiN), silicon oxynitride (SiON), silicon oxide (SiO2), silicon carbonitride (SiOCN), and combinations thereof.

[0082] Source / drain regions SD1 and SD2 can be formed on both sides of gate pattern 130. Source / drain regions SD1 and SD2 can also be formed within fin patterns F1 to F8. For example... Figure 9B As shown, the contacts (e.g., contacts CA1 and CA3) can directly contact the source / drain areas SD1 and SD2, respectively.

[0083] In addition, although in Figure 9B The bottom surfaces of the intermediate contacts CA1 and CA3 are at substantially the same vertical level as the bottom surface of the gate pattern 130, but the embodiment is not limited to this. For example, the contacts CA1 and CA3 may be formed deeper in the fin pattern F1, such that the bottom surfaces of the contacts CA1 and CA2 are at a vertical level lower than the level of the bottom surface of the gate pattern 130.

[0084] The first interlayer insulating film 180 may cover fin patterns F1 to F8. The first interlayer insulating film 180 may cover gate pattern 130. The first interlayer insulating film 180 may be formed on substrate 100, and more specifically, on field insulating layer 105. For example, the lower surface of the first interlayer insulating film 180 may contact the upper surface of field insulating layer 105.

[0085] A first insulating layer 181 may cover the sidewalls of the gate pattern 130. For example, the first insulating layer 181 may contact the side surface of the spacer 140, which is formed on and contacts the sidewalls of the gate pattern 130. An interlayer spacer film 182 and a second insulating layer 183 may be formed on the gate pattern 130. More specifically, the interlayer spacer film 182 may be formed along the upper surface of the gate pattern 130 and may contact the upper surface of the gate pattern 130.

[0086] The first interlayer insulating film 180 may include a first insulating layer 181, an interlayer gasket film 182, and a second insulating layer 183 sequentially formed on the field insulating layer 105. The first insulating layer 181 and the second insulating layer 183 may be separated, for example, by the interlayer gasket film 182.

[0087] Each of the first insulating layer 181 and the second insulating layer 183 may include at least one of, for example, silicon oxide, silicon nitride, silicon oxynitride, and a low-k material having a dielectric constant lower than that of silicon oxide. The low-k material may include, for example, tetraethyl orthosilicate (FTEOS), silsesquioxane (HSQ), bisbenzocyclobutene (BCB), tetramethyl orthosilicate (TMOS), octamethylcyclotetrasiloxane (OMCTS), hexamethyldisiloxane (HMDS), trimethylsilanoborate (TMSB), diacetoxydi-tert-butylsiloxane (DADBS), trimethylsilane phosphate (TMSP), polytetrafluoroethylene (PTFE), tonnen silazane (TOSZ), fluorosilicate glass (FSG), polyimide nanofoams (such as polypropylene oxide), carbon-doped silicon oxide (CDO), organosilicon glass (OSG), SiLK, amorphous fluorinated carbon, silica aerogel, silica dry gel, mesoporous silica, or combinations thereof.

[0088] The interlayer gasket film 182 may include a material different from, for example, the material of the first insulating layer 181 and the second insulating layer 183. The interlayer gasket film 182 may include, for example, silicon nitride (SiN).

[0089] Contacts CA1 to CA10 and CB1 to CB4 may be formed in the first interlayer insulating film 180. Contacts CA1 to CA10 and CB1 to CB4 may pass through, for example, the second insulating layer 183, the interlayer gasket film 182, and the first insulating layer 181.

[0090] Each of contacts CA1 to CA10 and CB1 to CB4 may include a first barrier layer 161 and a first filler layer 162. The first barrier layer 161 may be formed along a contact hole formed in the first interlayer insulating film 180. The first filler layer 162 may fill the contact hole in which the first barrier layer 161 is formed. The first filler layer 162 may be formed on the first barrier layer 161. The upper surfaces of the first barrier layer 161 and the upper surfaces of the first filler layer 162 may be coplanar with each other and coplanar with the upper surface of the second insulating layer 183.

[0091] The second interlayer insulating film 190 includes a first etch stop layer 191 and a third insulating layer 192.

[0092] The first etch stop layer 191 may be formed on the second insulating layer 183 and may contact the upper surface of the second insulating layer 183. The first etch stop layer 191 may include at least one of silicon nitride (SiN), silicon oxynitride (SiON), silicon carbonitride (SiCN), and silicon carbon oxynitride (SiCO).

[0093] The third insulating layer 192 may be disposed on the first etch stop layer 191 and may contact the upper surface of the first etch stop layer 191. The third insulating layer 192 may include at least one of, for example, silicon oxide, silicon nitride, silicon oxynitride, and low-k materials.

[0094] Each of the intermediate contacts CM1 and CM3 through CM10 includes a second barrier layer 171 and a second filler layer 172. The second barrier layer 171 may be formed along a contact hole formed in the second interlayer insulating film 190. The second filler layer 172 may fill the contact hole in which the second barrier layer 171 is formed. The second filler layer 172 may be formed on the second barrier layer 171. The upper surfaces of the second barrier layer 171 and the second filler layer 172 may be coplanar with each other and coplanar with the upper surface of the third insulating layer 192.

[0095] Each of the first barrier layer 161 and the second barrier layer 171 may include at least one of, for example, tantalum (Ta), tantalum nitride (TaN), titanium (Ti), titanium nitride (TiN), ruthenium (Ru), cobalt (Co), nickel (Ni), nickel boride (NiB), tungsten (W), tungsten nitride (WN), tungsten carbonitride (WCN), zirconium (Zr), zirconium nitride (ZrN), vanadium (V), vanadium nitride (VN), niobium (Nb), niobium nitride (NbN), platinum (Pt), iridium (Ir), and rhodium (Rh).

[0096] Each of the first filler layer 162 and the second filler layer 172 may include at least one of, for example, aluminum (Al), copper (Cu), tungsten (W), cobalt (Co), ruthenium (Ru), and molybdenum (Mo).

[0097] Specifically, such as Figure 8 As shown, the first fin pattern F1 contacts contact CA1, and the second fin pattern F2 contacts contact CA2. An intermediate contact CM1 is disposed on adjacent contacts CA1 and CA2 and connects adjacent contacts CA1 and CA2 to each other. The intermediate contact CM1, as well as contacts CA1 and CA2, are electrically connected to a first voltage (e.g., ground voltage VSS).

[0098] Intermediate contacts (e.g., intermediate contacts CM1, CM8, and CM10) differ from the wiring structure (i.e., the wiring structure including vias and / or general wiring). Each of intermediate contacts CM1 and CM8 through CM10 can be shaped to resemble a wiring that does not include vias and extends in one direction. Intermediate contacts CM1 and CM8 through CM10 can be relatively shorter in length than general wiring.

[0099] Intermediate contacts (e.g., intermediate contacts CM1, CM8, and CM10) also differ from other contacts (e.g., contacts CA1, CA2, CA8, and CA10). Intermediate contacts CM1, CM8, and CM10 are used to route adjacent gate contacts and / or source / drain contacts to each other. In cross-section, the height H1 of each of the contacts (e.g., contacts CA1 and CA2) is greater than the height H2 of the intermediate contact (e.g., intermediate contact CM1).

[0100] Figure 10 This is a layout diagram of a semiconductor device according to a second example embodiment. Figure 11 It is along Figure 10 The cross-sectional view is taken by line CC. For ease of description, the main description will be referenced above. Figures 1 to 9B The differences described in the semiconductor devices.

[0101] Reference Figure 2 , Figure 3 and Figure 8 In the semiconductor device according to the first embodiment, some fin patterns F1, F2, F5, and F6 include n sub-fin patterns, where n is a natural number of 2 or greater. On the other hand, referring to... Figure 10 and Figure 11 In the semiconductor device according to the second embodiment, some fin patterns F101, F102, F105 and F106 may include m sub-fin patterns, where m is a natural number less than n.

[0102] For example, as shown, in the semiconductor device according to the first embodiment, some fin patterns F1, F2, F5, and F6 may include two sub-fin patterns. In the semiconductor device according to the second embodiment, some fin patterns F101, F102, F105, and F106 may include one sub-fin pattern.

[0103] In the semiconductor device according to the first embodiment, the transistors formed in the fin patterns F1, F2, F5, and F6 can have relatively high current driving capability. On the other hand, in the semiconductor device according to the second embodiment, the transistors formed in the fin patterns F101, F102, F105, and F106 can have relatively high integration density.

[0104] Reference Figure 10 and Figure 11In the third unit UC3, contact CA101 is formed on the first side of the first gate pattern G1 to contact the fin pattern F101. Contact CA105 is formed on the first side of the third gate pattern G3 to contact the fin pattern F105. Contact CA106 is formed on the second side of the fifth gate pattern G5 to contact the fin pattern F105. Contact CA107 is formed on the second side of the fourth gate pattern G4 to contact the fin pattern F101. Contact CA108 is formed on the first side of the first gate pattern G1 to contact the fin pattern F3. Contact CA109 is formed on the second side of the fifth gate pattern G5 to contact the fin pattern F7.

[0105] In the fourth unit cell UC4, contact CA102 is formed on the first side of the second gate pattern G2 to contact fin pattern F102. Contact CA110 is formed on the first side of the second gate pattern G2 to contact fin pattern F4.

[0106] Intermediate contact CM101 is disposed on adjacent contacts CA101 and CA102 to connect adjacent contacts CA101 and CA102 to each other. Intermediate contact CM101 is electrically connected to a first voltage (e.g., ground voltage VSS).

[0107] Intermediate contact CM105 can be disposed on contact CA105 and electrically connected to bit line BL. Intermediate contact CM106 can be disposed on contact CA106 and connected to a first voltage (e.g., ground voltage VSS). Intermediate contact CM107 can be disposed on contact CA107 and electrically connected to bit line BLB. Intermediate contact CM108 can be disposed on contact CA108 and electrically connected to power supply voltage VDD. Intermediate contact CM109 can be disposed on contact CA109 and electrically connected to power supply voltage VDD. Intermediate contact CM110 can be disposed on contact CA110 and electrically connected to power supply voltage VDD.

[0108] In the cross section, the height H1 of each of the contacts (e.g., contacts CA101, CA102, CA108 and CA110) is greater than the height H2 of each of the intermediate contacts (e.g., intermediate contacts CM101, CM108 and CM110).

[0109] Figure 12 This is a block diagram of a semiconductor device according to a third example embodiment. Figure 13 This is a cross-sectional view of a semiconductor device according to a third example embodiment.

[0110] Reference Figure 12 and Figure 13The semiconductor device according to the third embodiment includes a first region RG1 and a second region RG2 that are different from each other.

[0111] The above reference Figures 2 to 9B The described SRAM device can be located in the first region RG1, and referenced above. Figure 10 and Figure 11 The described SRAM device can be located in the second region RG2.

[0112] Specifically, a first unit cell UC1 and a second unit cell UC2 are formed in a first region RG1. The first unit cell UC1 includes a first fin pattern F1 extending longitudinally along a first direction DR1, a first gate pattern G1 extending longitudinally along a second direction DR2 to intersect with the first fin pattern F1, and a contact CA1 disposed on a first side of the first gate pattern G1 to contact the first fin pattern F1.

[0113] In addition, the second unit UC2 includes a second fin pattern F2 extending longitudinally along the first direction DR1, a second gate pattern G2 extending longitudinally along the second direction DR2 to intersect with the second fin pattern F2, and a contact CA2 disposed on the first side of the second gate pattern G2 to contact the second fin pattern F2.

[0114] Here, the first gate pattern G1 and the second gate pattern G2 are spaced apart from each other and located on a first straight line Q1 extending longitudinally along the second direction DR2. For example, the longitudinal axes of the first gate pattern G1 and the second gate pattern G2 can be aligned on the first straight line Q1. Contacts CA1 and CA2 are spaced apart from each other and located on a second straight line Q2 extending longitudinally along the second direction DR2. For example, the longitudinal axes of contacts CA1 and CA2 can be aligned on the second straight line Q2. An intermediate contact CM1 is disposed on adjacent contacts CA1 and CA2 and connects adjacent contacts CA1 and CA2 to each other. In addition, the intermediate contact CM1 and the adjacent contacts CA1 and CA2 can be connected to a first voltage (e.g., ground voltage VSS).

[0115] On the other hand, the third unit UC3 and the fourth unit UC4 are formed in the second region RG2.

[0116] The third unit cell UC3 includes a fin pattern (e.g., fin pattern F101) extending longitudinally along the third direction DR3 and a gate pattern G1 extending longitudinally along the fourth direction DR4 to intersect the fin pattern F101.

[0117] The fourth unit cell UC4 includes a fin pattern (e.g., fin pattern F102) extending longitudinally along the third direction DR3 and a gate pattern G2 extending longitudinally along the fourth direction DR4 to intersect the fin pattern F102.

[0118] Additionally, contact CA101 has a contact fin pattern F101, and contact CA102 has a contact fin pattern F102. An intermediate contact CM101 is disposed on adjacent contacts CA101 and CA102, connecting the adjacent contacts CA101 and CA102 to each other. Furthermore, the intermediate contact CM101 and the adjacent contacts CA101 and CA102 can be connected to a first voltage (e.g., ground voltage VSS).

[0119] As shown, the intermediate contact CM1 of the first region RG1 and the intermediate contact CM101 of the second region RG2 can be positioned at the same vertical level. In the cross-section, the height H1 of each of the contacts (e.g., contacts CA1, CA2, CA101 and CA102) is greater than the height H2 of each of the intermediate contacts (e.g., intermediate contacts CM1 and CM101).

[0120] As shown, the fin patterns of the first region RG1 (e.g., fin patterns F1 and F2) may include n sub-fin patterns, and the fin patterns of the second region RG2 (e.g., fin patterns F101 and F102) may include m sub-fin patterns, where n is a natural number of 2 or greater, and m is a natural number less than n. For example, as shown, each of fin patterns F1 and F2 may include two sub-fin patterns, and each of fin patterns F101 and F102 may include one sub-fin pattern.

[0121] Figure 14 This is a cross-sectional view of a semiconductor device according to the fourth exemplary embodiment. For ease of description, the main description will be consistent with the above reference. Figure 12 and Figure 13 The differences described in the semiconductor devices.

[0122] Reference Figure 14 The third unit cell UC3 and the fourth unit cell UC4 are formed in the second region RG2. Specifically, the common contact CA101a can be formed on the fin pattern F101 of the third unit cell UC3 and the fin pattern F102 of the fourth unit cell UC4, and can directly contact the fin patterns F101 and F102. The intermediate contact CM101 can be located on the common contact CA101a. That is, when process defects (e.g., short circuits between the gate pattern and the contact) are not likely to occur, a relatively large common contact CA101a can be used (for some regions).

[0123] The common contact CA101a of the second region RG2 can be positioned at the same vertical level as the contacts CA1 and CA2 of the first region RG1. The intermediate contact CM101 of the second region RG2 can be positioned at the same vertical level as the intermediate contact CM1 of the first region RG1. In the cross-section, the height H1 of each of the contacts (e.g., contacts CA1, CA2, and CA101a) is greater than the height H2 of each of the intermediate contacts (e.g., intermediate contacts CM1 and CM101).

[0124] Figure 15 This is a cross-sectional view of a semiconductor device according to the fifth exemplary embodiment. For ease of description, the main description will be consistent with the above reference. Figures 1 to 9B The differences described in the semiconductor devices.

[0125] Reference Figure 15 In the semiconductor device according to the fifth exemplary embodiment, wiring structures INT1, INT2, and INT3 are further disposed on intermediate contacts (e.g., intermediate contacts CM101, CM108, and CM110). The connection relationship between intermediate contacts CM101, CM108, and CM110 and wiring structures INT1, INT2, and INT3 is shown by way of example, but the embodiment is not limited to this connection relationship.

[0126] Specifically, the third interlayer insulating film 210 includes a second etch stop layer 211 and a fourth insulating layer 212.

[0127] The second etch stop layer 211 may be formed on the third insulating layer 192. The second etch stop layer 211 may include at least one of silicon nitride (SiN), silicon oxynitride (SiON), silicon carbonitride (SiCN), and silicon carbon oxynitride (SiCO).

[0128] The fourth insulating layer 212 may be disposed on the second etch stop layer 211. The fourth insulating layer 212 may include at least one of, for example, silicon oxide, silicon nitride, silicon oxynitride, and low-k materials.

[0129] Each of the wiring structures INT1, INT2, and INT3 (or referred to as "220") may include a third barrier layer 221 and a third fill layer 222. The third barrier layer 221 may be formed along a contact hole formed in the third interlayer insulating film 210. The third barrier layer 221 may contact the upper surface of an intermediate contact (e.g., intermediate contacts CM101, CM108, and CM110) disposed thereon. The third fill layer 222 may be formed on the third barrier layer 221 to fill the contact hole in which the third barrier layer 221 is formed.

[0130] The third barrier layer 221 may include at least one of, for example, tantalum (Ta), tantalum nitride (TaN), titanium (Ti), titanium nitride (TiN), ruthenium (Ru), cobalt (Co), nickel (Ni), nickel boride (NiB), tungsten (W), tungsten nitride (WN), tungsten carbonitride (WCN), zirconium (Zr), zirconium nitride (ZrN), vanadium (V), vanadium nitride (VN), niobium (Nb), niobium nitride (NbN), platinum (Pt), iridium (Ir), and rhodium (Rh).

[0131] The third filler layer 222 may include at least one of, for example, copper (Cu), aluminum (Al), tungsten (W), cobalt (Co), ruthenium (Ru), and molybdenum (Mo).

[0132] Although each of the wiring structures INT1, INT2, and INT3 in the figure includes vias, the embodiment is not limited to this. That is, each of the wiring structures INT1, INT2, and INT3 may also include general-purpose wiring without vias, and the general-purpose wiring may be directly connected to each of the intermediate contacts CM101, CM108, and CM110.

[0133] Now refer to Figure 16 and Figure 17 Describes a layout design method according to an embodiment.

[0134] Figure 16 This is a flowchart illustrating a layout design method according to an example embodiment. Figure 17 It is used for explanation Figure 16 The diagrams for operations S320, S330, and S340. Figure 18 It is used for explanation Figure 16 The diagram shows the operation of S320.

[0135] Reference Figure 16 Designers create / prepare the original layout (or full-chip layout) (operation S310).

[0136] A primitive layout is a set of patterns that a designer expects to ultimately implement on a chip (hereinafter referred to as the primitive layout). For example, the layout can be a data format such as the Open Art System Exchange Standard (OASIS) or Graphics Data System II (GDS2). A primitive layout may include first SRAM units and second SRAM units. For example, as... Figure 1 As discussed herein, each of the first SRAM unit cell and the second SRAM unit cell may include a first inverter INV1, a second inverter INV2, a first pass element PG1, and a second pass element PG2.

[0137] Next, perform Table-Driven Layer Operations (TDLO) (operations S320, S330, and S340).

[0138] TDLO stands for Pre-Optical Proximity Correction (Pre-OPC) operation. In TDLO, a target pattern (or pre-OPC target pattern) is generated based on the original pattern. For example, considering factors such as etching skew, the target pattern can be generated by pushing or pulling the edges of the original pattern. For instance, considering etching skew, a 5×50 original pattern can be transformed into a 5×70 target pattern. Additionally, to accurately replicate the original pattern, a virtual pattern can be added to blank areas (i.e., a virtual target pattern can be generated). Layers are defined by calculating the original pattern and the generated target pattern (e.g., by performing addition or subtraction or finding complementary sets).

[0139] Specifically, in the TDLO layout design method according to the example embodiment, although the process itself is not impossible, layout correction can be performed on areas that are prone to process defects due to insufficient process margin.

[0140] Specifically, refer to Figures 16 to 18 Search for the original contact pattern POR_CA that directly connects the first fin pattern F1 of the first SRAM unit cell and the second fin pattern F2 of the second SRAM unit cell (see...). Figure 18 (Operation S320).

[0141] As shown, assuming the original layout includes an original contact pattern POR_CA, which is disposed on a first side of a first gate pattern G1 to directly contact a first fin pattern F1 of a first SRAM unit cell and on a first side of a second gate pattern G2 of a second SRAM unit cell to directly contact a second fin pattern F2 and directly connects the first fin pattern F1 and the second fin pattern F2. The original contact pattern POR_CA is a region in the SRAM semiconductor device prone to process defects. That is, due to insufficient space margin from the ends of the first gate pattern G1 and the second gate pattern G2 to the original contact pattern POR_CA, process defects are likely to occur.

[0142] Reference Figure 16 and Figure 17 The original contact pattern POR_CA, which was searched and found in operation S320, is cut to generate a first contact pattern ACA1 that directly contacts the first fin pattern F1 and a second contact pattern ACA2 that directly contacts the second fin pattern F2 (operation S330).

[0143] Here, the original contact pattern POR_CA is cut with the Post-Development Inspection (ADI) critical dimension (CD) in mind. As a result, the gap L10 between the first contact pattern ACA1 and the second contact pattern ACA2 can be equal to or greater than the ADI CD.

[0144] Reference Figure 16 and Figure 17 The first target pattern BCA1 and the second target pattern BCA2 are generated by reflecting the etching bias in the first contact pattern ACA1 and the second contact pattern ACA2 (operation S340).

[0145] As shown, since the first target pattern BCA1 and the second target pattern BCA2 reflect the etching skew, the edges of the first target pattern BCA1 and the second target pattern BCA2 are not used for the edges of the first contact pattern ACA1 and the second contact pattern ACA2 (from the edges of the first contact pattern ACA1 and the second contact pattern ACA2 being pushed or pulled).

[0146] Next, refer to Figure 16 OPC (operation S350) is performed on the first target pattern BCA1 and the second target pattern BCA2. In the OPC, optical phenomena that may occur during the exposure process of the layer defined in the TDLO are compensated for. For example, the OPC may include optimization of the defocus stage (DS) position, optimal focus (BF) position, etc., in the exposure process. Furthermore, the OPC may include optimization of light diffraction or the optical state of the exposure equipment itself. However, the generation of the OPC model is not limited to the above description. In some embodiments, the first target pattern BCA1 and the second target pattern BCA2 can be used to generate, for example... Figure 2 The contacts CA1 and CA2 are shown in the diagram.

[0147] In concluding this detailed description, those skilled in the art will understand that many variations and modifications can be made to the preferred embodiments without substantially departing from the principles of the inventive concept. Therefore, the preferred embodiments disclosed in this inventive concept are used only in a general and descriptive sense and not for limiting purposes.

Claims

1. A semiconductor device comprising: a first unit cell; and a second unit cell, wherein the first unit cell includes: a first fin pattern extending longitudinally along a first direction; a first gate pattern extending longitudinally along a second direction to cross the first fin pattern; and a first contact provided on one side of the first gate pattern to contact the first fin pattern, wherein the second unit cell includes: a second fin pattern extending longitudinally along the first direction; a second gate pattern extending longitudinally along the second direction to cross the second fin pattern; and a second contact provided on one side of the second gate pattern to contact the second fin pattern, and wherein the first gate pattern and the second gate pattern are spaced apart from each other and located on a first straight line extending longitudinally along the second direction, the first contact and the second contact are spaced apart from each other and located on a second straight line extending longitudinally along the second direction, and a first intermediate contact is provided on and connects the first contact and the second contact to each other, wherein a width of a top surface of the first intermediate contact in the second direction is greater than a width of a bottom surface of the first intermediate contact in the second direction, wherein a width of a top surface of the first contact in the second direction is smaller than the width of the bottom surface of the first intermediate contact in the second direction, and wherein the bottom surface of the first intermediate contact is in contact with the top surface of the first contact.

2. The semiconductor device according to claim 1, wherein The first contact, the second contact, and the first intermediate contact are connected to a ground voltage.

3. The semiconductor device according to claim 1, wherein A height of the first contact is greater than a height of the first intermediate contact.

4. The semiconductor device according to claim 1, wherein The first gate pattern and the second gate pattern are spaced apart by a first gap, the first contact and the second contact are spaced apart by a second gap, and the first gap is smaller than the second gap.

5. The semiconductor device according to any one of claims 1 to 4, wherein The first unit cell further includes: a third fin pattern extending longitudinally along the first direction to cross the first gate pattern; and a third contact provided on the one side of the first gate pattern to contact the third fin pattern and located on the second straight line, and a second intermediate contact is provided on the third contact and the second straight line and formed at a same vertical height as a vertical height of the first intermediate contact.

6. The semiconductor device according to claim 5, wherein The third contact and the second intermediate contact are connected to a power supply voltage.

7. The semiconductor device according to claim 5, wherein The first unit cell further includes a fourth contact provided on another side of the first gate pattern to contact the first fin pattern and the third fin pattern, and the fourth contact is formed at a same vertical height as a vertical height of the first contact.

8. The semiconductor device according to claim 5, wherein The first fin pattern includes n sub-fin patterns, and the third fin pattern includes m sub-fin patterns, where n is a natural number of 2 or more, and m is a natural number smaller than n.

9. The semiconductor device according to claim 1, wherein The first unit cell is a static random access memory unit cell, and the second unit cell is a static random access memory unit cell.

10. The semiconductor device according to claim 1, comprising: a first region; and a second region, wherein the first unit cell and the second unit cell are formed in the first region, and a third unit cell and a fourth unit cell are formed in the second region, and wherein the third unit cell includes a fourth fin pattern extending longitudinally along a third direction and a third gate pattern extending longitudinally along a fourth direction to cross the fourth fin pattern, the fourth unit cell includes a fifth fin pattern extending longitudinally along the third direction and a fourth gate pattern extending longitudinally along the fourth direction to cross the fifth fin pattern, and a common contact is disposed on one side of the third gate pattern to contact the fourth fin pattern and on one side of the fourth gate pattern to contact the fifth fin pattern. 11.The semiconductor device according to claim 10, further comprising a third intermediate contact formed on the common contact and at a same vertical height as a vertical height of the first intermediate contact. 12.A semiconductor device comprising: a first gate pattern and a second gate pattern on a first straight line extending along a first direction and longitudinally extending along the first direction; a first contact and a second contact on a second straight line extending along the first direction and longitudinally extending along the first direction; and an intermediate contact disposed on the first contact and the second contact and extending along the first direction to connect the first contact and the second contact to each other, wherein a first gap between the first gate pattern and the second gate pattern is smaller than a second gap between the first contact and the second contact, wherein a width of a top surface of the intermediate contact in the first direction is greater than a width of a bottom surface of the intermediate contact in the first direction, wherein a width of a top surface of the first contact in the first direction is smaller than the width of the bottom surface of the intermediate contact in the first direction, and wherein the bottom surface of the intermediate contact is in contact with the top surface of the first contact. 13.The semiconductor device according to claim 12, further comprising a wiring structure disposed on the intermediate contact to contact the intermediate contact. The first contact, the second contact, and the intermediate contact are connected to a ground voltage.

14. The semiconductor device according to claim 12, wherein 15.A semiconductor device comprising: a first fin pattern, a second fin pattern, and a third fin pattern arranged sequentially; a first contact, a second contact, and a third contact extending along a first direction and contacting the first fin pattern, the second fin pattern, and the third fin pattern, respectively; a first intermediate contact disposed on and directly contacting the first contact and the second contact; and a second intermediate contact disposed on the third contact, formed at a same vertical height as a vertical height of the first intermediate contact, and directly contacting the third contact, wherein the first intermediate contact is connected to a first voltage, and the second intermediate contact is connected to a second voltage higher than the first voltage, wherein a width of a top surface of the first intermediate contact in the first direction is greater than a width of a bottom surface of the first intermediate contact in the first direction, wherein a width of a top surface of the first contact in the first direction is smaller than the width of the bottom surface of the first intermediate contact in the first direction, and wherein the bottom surface of the first intermediate contact is in contact with the top surface of the first contact. ​ 16. The semiconductor device according to claim 15, wherein The first fin pattern belongs to a first static random access memory unit cell, and the second fin pattern and the third fin pattern belong to a second static random access memory unit cell.

17. The semiconductor device according to claim 15, wherein The first voltage is a ground voltage, and the second voltage is a power supply voltage.

18. The semiconductor device according to claim 15, wherein The height of the first contact is greater than the height of the first intermediate contact.

19. The semiconductor device according to claim 15, wherein Each of the first fin pattern and the second fin pattern includes n sub-fin patterns, and the third fin pattern includes m sub-fin patterns, where n is a natural number of 2 or more, and m is a natural number smaller than n.

Images