Vertical memory device and method of manufacturing the same

Abstract

A vertical memory device includes channels extending vertically on a substrate. Charge storage structures are disposed on sidewalls of the channels. Gate electrodes are vertically spaced apart from one another and surround the charge storage structures. A first insulating pattern includes air gaps between the gate electrodes. The charge storage structures include tunnel insulating layers, charge trapping patterns, and first blocking patterns that are horizontally sequentially stacked. The charge storage structures include the charge trapping patterns that are vertically spaced apart from one another. Each of the charge trapping patterns horizontally faces one of the gate electrodes. An outer sidewall of each of the charge trapping patterns facing the first blocking pattern has a length in a first direction that is less than a length of an inner sidewall thereof facing the tunnel insulating layer in the first direction.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2019-0108612, filed on September 3, 2019, with the Korean Intellectual Property Office (KIPO), the contents of which are incorporated herein by reference in their entirety. Technical Field

[0003] This disclosure relates to a memory device, and more specifically, to a vertical memory device and a method of manufacturing the same. Background Technology

[0004] In VNAND flash memory devices, the charge trapping layer on the outer wall of the vertical channel can extend vertically, and therefore, the charge trapped in the charge trapping layer can travel vertically along multiple gate electrodes arranged at multiple different levels. As a result, the retention characteristics of the VNAND flash memory device are degraded, which leads to reliability issues in storing and retrieving data from the VNAND flash memory device. Summary of the Invention

[0005] A vertical memory device includes a channel disposed on a substrate. A charge storage structure is disposed on the outer wall of the channel. The vertical memory device also includes a gate electrode and a first insulating pattern disposed between the gate electrodes. The channel extends in a first direction perpendicular to the upper surface of the substrate. The charge storage structure includes a tunnel insulating layer, a charge trapping pattern, and a first blocking pattern sequentially stacked in a horizontal direction parallel to the upper surface of the substrate. The gate electrodes are spaced apart from each other in the first direction, each gate electrode surrounding the charge storage structure. The first insulating pattern includes an air gap therein. The charge storage structure includes charge trapping patterns spaced apart from each other in the first direction. Each of the charge trapping patterns faces one of the gate electrodes in the horizontal direction. The length of the outer wall of each charge trapping pattern facing the first blocking pattern in the first direction is less than the length of the inner wall of each charge trapping pattern facing the tunnel insulating layer in the first direction.

[0006] A vertical memory device includes a channel disposed on a substrate. A charge storage structure is disposed on the outer wall of the channel. The vertical memory device includes: a gate electrode; an insulating pattern disposed between the gate electrodes; and an etch stop layer disposed on a lower surface and an upper surface of the insulating pattern. The channel extends in a first direction perpendicular to the upper surface of the substrate. The charge storage structure includes a tunnel insulating layer, a charge trapping pattern, and a first blocking pattern sequentially stacked in a horizontal direction parallel to the upper surface of the substrate. The gate electrodes are spaced apart from each other in the first direction, each gate electrode surrounding the charge storage structure. The insulating pattern includes an air gap therein. The charge storage structure includes charge trapping patterns spaced apart from each other in the first direction. Each of the charge trapping patterns faces one of the gate electrodes in the horizontal direction.

[0007] A vertical memory device includes a channel disposed on a substrate. A charge storage structure is disposed on the outer sidewall of the channel. The vertical memory device also includes gate electrodes, an insulating pattern disposed between the gate electrodes, a protective layer, and a second barrier pattern. The channel extends in a first direction perpendicular to the upper surface of the substrate. The charge storage structure includes a tunnel insulating layer, a charge trapping pattern, and a first barrier pattern sequentially stacked in a horizontal direction parallel to the upper surface of the substrate. The gate electrodes are spaced apart from each other in the first direction. Each of the gate electrodes extends in a second direction parallel to the upper surface of the substrate to surround the charge storage structure. The insulating pattern includes an air gap therein. The protective layer covers the sidewall of the third direction end of each of the gate electrodes. The third direction is parallel to the upper surface of the substrate and intersects the second direction. The second barrier pattern covers the lower and upper surfaces of each of the gate electrodes, the sidewall facing the charge storage structure, and the lower and upper surfaces of the protective layer. The charge storage structure includes charge trapping patterns spaced apart from each other in the first direction. Each of the charge trapping patterns faces one of the gate electrodes in the horizontal direction.

[0008] A vertical memory device includes a channel on a substrate, a charge storage structure on the outer wall of the channel, gate electrodes, an insulating pattern between the gate electrodes, and a second barrier pattern. The channel extends in a first direction perpendicular to the upper surface of the substrate. The charge storage structure includes a tunnel insulating layer, a charge trapping pattern, and a first barrier pattern sequentially stacked in a horizontal direction parallel to the upper surface of the substrate. The gate electrodes are spaced apart from each other in the first direction. Each of the gate electrodes extends in a second direction parallel to the upper surface of the substrate to surround the charge storage structure. The insulating pattern includes an air gap therein. The second barrier pattern covers the lower and upper surfaces of each of the gate electrodes, the sidewalls facing the charge storage structure, and the sidewalls of the ends of each of the gate electrodes in the third direction. The third direction is parallel to the upper surface of the substrate and intersects the second direction. The charge storage structure includes charge trapping patterns spaced apart from each other in the first direction. Each of the charge trapping patterns faces one of the gate electrodes in the horizontal direction.

[0009] A vertical memory device includes a first pillar structure disposed on a substrate. A second pillar structure is disposed on the substrate. The vertical memory device also includes gate electrodes, an insulating pattern disposed between the gate electrodes, and a second blocking pattern. The first pillar structure extends in a first direction perpendicular to the upper surface of the substrate and includes a channel having a cup shape, a charge storage structure located on the outer sidewall of the channel, and a filling pattern. The charge storage structure includes a tunnel insulating layer, a charge trapping pattern, and a first blocking pattern sequentially stacked in a horizontal direction parallel to the upper surface of the substrate. The filling pattern fills the internal space formed by the channel. The second pillar structure extends in the first direction and includes an insulating material. The gate electrodes are spaced apart from each other in the first direction. Each of the gate electrodes extends in a second direction parallel to the upper surface of the substrate to surround the first pillar structure and the second pillar structure. The second blocking pattern covers the lower and upper surfaces of each of the gate electrodes, the sidewalls facing the charge storage structure, and the sidewalls of the ends of each of the gate electrodes in the third direction. The third direction is parallel to the upper surface of the substrate and intersects the second direction. The second blocking pattern covers the sidewalls of the insulating pattern facing the second pillar structure and extends in the first direction between the second pillar structure and the first pillar structure.

[0010] A vertical memory device includes a channel disposed on a substrate. A charge storage structure is disposed on the outer wall of the channel. The vertical memory device also includes gate electrodes, a first insulating pattern disposed between the gate electrodes, a common-source pattern (CSP), and a bit line. The channel extends in a first direction perpendicular to the upper surface of the substrate. The charge storage structure includes a tunnel insulating layer, a charge trapping pattern, and a first blocking pattern sequentially stacked in a horizontal direction parallel to the upper surface of the substrate. The gate electrodes are spaced apart from each other in the first direction. Each of the gate electrodes extends in a second direction parallel to the upper surface of the substrate to surround the charge storage structure. The CSP extends on the substrate in the second direction and is adjacent to an end of the gate electrode in a third direction, which is parallel to the upper surface of the substrate and intersects the second direction. The bit line extends on the gate electrode in a third direction to electrically connect to the channel. The charge storage structure includes charge trapping patterns spaced apart from each other in the first direction. Each of the charge trapping patterns faces one of the gate electrodes in the horizontal direction. The length of the outer wall of each of the charge trapping patterns facing the first blocking pattern in the first direction is less than the length of the inner wall of each of the charge trapping patterns facing the tunnel insulation layer in the first direction.

[0011] A method of manufacturing a vertical memory device includes forming a molding on a substrate to include alternating and repeating stacked first and second sacrificial layer structures. A channel and a charge storage structure are formed on the substrate. The channel extends through the molding. The charge storage structure is disposed on the outer wall of the channel to include a tunnel insulating layer, a charge trapping layer, and a first barrier layer sequentially stacked in a horizontal direction parallel to the upper surface of the substrate. A first opening is formed through the molding to expose the upper surface of the substrate, such that the first and second sacrificial layer structures transform into a first sacrificial pattern and a second sacrificial structure. The first sacrificial pattern is replaced by a third sacrificial pattern through the first opening. The third sacrificial pattern comprises a material different from that of the first sacrificial pattern. A portion of the second sacrificial structure and the first barrier layer is removed to form a second opening, such that the first barrier layer is divided into first barrier patterns spaced apart from each other in a vertical direction perpendicular to the upper surface of the substrate. A portion of the charge trapping layer is removed to form a third opening connected to the second opening, such that the charge trapping layer is divided into charge trapping patterns spaced apart from each other in a vertical direction. An insulating pattern is formed to fill the second and third openings. The insulating pattern includes air gaps located therein. Replace the third sacrificial pattern with a gate electrode.

[0012] A method for manufacturing a vertical memory device includes forming a molding on a substrate to include alternating and repeating stacked first and second sacrificial layer structures in a first direction perpendicular to the upper surface of the substrate. A channel and a charge storage structure are formed on the substrate. The channel extends through the molding. The charge storage structure is located on the outer wall of the channel to include a tunnel insulating layer, a charge trapping layer, and a first barrier layer sequentially stacked in a horizontal direction parallel to the upper surface of the substrate. A first opening is formed through the molding to expose the upper surface of the substrate, such that the first and second sacrificial layer structures transform into a first sacrificial pattern and a second sacrificial structure. The first opening extends in a second direction parallel to the upper surface of the substrate. The first sacrificial pattern is replaced with a gate electrode. A protective layer is formed to cover the sidewalls of the gate electrode at a third-direction end, said third direction being parallel to the upper surface of the substrate and intersecting the second direction. A portion of the second sacrificial structure and the first barrier layer is removed to form a second opening, such that the first barrier layer is divided into first barrier patterns spaced apart from each other in the first direction. A portion of the charge-trapping layer is removed to form a third opening connected to the second opening, such that the charge-trapping layer is divided into charge-trapping patterns spaced apart from each other in a first direction. An insulating pattern is formed to fill the second and third openings to include the air gap located therein.

[0013] A method of manufacturing a vertical memory device includes forming a molding on a substrate to include alternating and repeating stacked first and second sacrificial layer structures. A channel and a charge storage structure are formed on the substrate. The channel extends through the molding. The charge storage structure is disposed on the outer sidewall of the channel and includes a tunnel insulating layer, a charge trapping layer, and a first barrier layer sequentially stacked in a horizontal direction parallel to the upper surface of the substrate. A first opening is formed through the molding to expose the upper surface of the substrate, such that the first and second sacrificial layer structures are transformed into a first sacrificial pattern and a second sacrificial structure, respectively. The first sacrificial pattern is replaced by a third sacrificial pattern through the first opening. The third sacrificial pattern comprises a material different from that of the first sacrificial pattern. A portion of the second sacrificial structure and the first barrier layer is removed to form a second opening, such that the first barrier layer is divided into first barrier patterns spaced apart from each other in a vertical direction perpendicular to the upper surface of the substrate. The portion of the charge trapping layer exposed by the second opening is oxidized to form a dividing layer, such that the charge trapping layer is divided into charge trapping patterns spaced apart from each other in a vertical direction. An insulating pattern is formed to fill the second and third openings to include an air gap therein. Replace the third sacrificial pattern with a gate electrode.

[0014] A method of manufacturing a vertical memory device includes forming a molding on a substrate to include alternating and repeatingly stacked first and second sacrificial layer structures. A channel, a first charge storage structure, and a second charge storage structure are formed on the substrate. The channel extends through the molding. Each of the first and second charge storage structures is disposed on an outer wall of the channel and includes a tunnel insulating layer, a charge trapping layer, and a first barrier layer sequentially stacked in a horizontal direction parallel to the upper surface of the substrate. A first opening is formed through the molding to expose the upper surface of the substrate, such that the first and second sacrificial layer structures are transformed into a first sacrificial pattern and a second sacrificial structure, respectively. The first sacrificial pattern is replaced by a third sacrificial pattern through the first opening. The third sacrificial pattern comprises a material different from that of the first sacrificial pattern. Each of the second charge storage structures is removed to form a second opening. A portion of the second sacrificial structure and the first barrier layer is removed to form a third opening, such that the first barrier layer is divided into first barrier patterns spaced apart from each other in a first direction perpendicular to the upper surface of the substrate. A portion of the charge trapping layer is removed to form a fourth opening connected to the third opening, such that the charge trapping layer is divided into charge trapping patterns spaced apart from each other in the first direction. The first insulating pattern is formed to fill the third and fourth openings to include the air gap therein. The third sacrificial pattern is replaced with a gate electrode. Attached Figure Description

[0015] A more complete understanding of this disclosure and its many accompanying aspects will readily arise when considered in conjunction with the accompanying drawings, and will be readily available through reference to the following detailed description, in which:

[0016] Figures 1 to 21 These are plan views and cross-sectional views illustrating a method of manufacturing a vertical memory device according to exemplary embodiments of the present disclosure;

[0017] Figures 22 to 27 This is a cross-sectional view taken along line C-C' of a corresponding plan view, illustrating a method of manufacturing a vertical memory device according to an exemplary embodiment of the present disclosure;

[0018] Figure 28 and Figure 29 This is a cross-sectional view taken along line C-C' of a corresponding plan view, illustrating a method of manufacturing a vertical memory device according to an exemplary embodiment of the present disclosure;

[0019] Figures 30 to 41 These are plan views and cross-sectional views illustrating a method for manufacturing a vertical memory device according to exemplary embodiments of the present disclosure; and

[0020] Figure 42 This is a cross-sectional view showing a vertical memory device according to an exemplary embodiment of the present disclosure, taken along line C-C' of a corresponding plan view. Detailed Implementation

[0021] The above and other aspects and features of the vertical memory device and its manufacturing method according to exemplary embodiments of the present disclosure will become more readily understood from the following detailed description with reference to the accompanying drawings. In the following description, a direction substantially perpendicular to the upper surface of the substrate may be defined as a first direction, and two directions substantially parallel to the upper surface of the substrate and intersecting each other may be defined as a second direction and a third direction, respectively. In exemplary embodiments of the present disclosure, the second direction and the third direction may be substantially perpendicular to each other.

[0022] It will be understood that although the terms “first,” “second,” and / or “third” may be used herein to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not necessarily be limited by these terms. These terms are used to distinguish one element, component, area, layer, and / or portion from another element, component, area, layer, and / or portion. Therefore, without departing from the teachings of the inventive concept, the first element, component, area, layer, and / or portion discussed below may be referred to as the second or third element, component, area, layer, and / or portion.

[0023] Figures 1 to 21 These are plan and cross-sectional views illustrating a method for manufacturing a vertical memory device according to exemplary embodiments of the present disclosure.

[0024] Specifically, Figure 1 , Figure 4 , Figure 6 and Figure 8 It is a floor plan, and Figure 2 , Figure 3 , Figure 5 , Figure 7 and Figures 9 to 21 It is a cross-sectional view. Figure 2 , Figure 3 and Figure 5 These are cross-sectional views taken along line A-A' of the corresponding plan view. Figure 7 It is a cross-sectional view taken along line B-B' of the corresponding plan view. Figure 9 and Figures 10 to 21 These are cross-sectional views taken along line C-C' of the corresponding plan view. Figures 10 to 19 yes Figure 9 Enlarged cross-sectional view of region X.

[0025] Reference Figure 1 and Figure 2 A molding layer including a first insulating layer 110, a first sacrificial layer 120, and a second sacrificial layer structure 190 can be formed on the substrate 100.

[0026] Substrate 100 may include silicon, germanium, silicon-germanium, or III-V compounds such as GaP, GaAs, and GaSb. In some exemplary embodiments of this disclosure, substrate 100 may be a silicon-on-insulator (SOI) substrate or a germanium-on-insulator (GOI) substrate. For example, n-type impurities may be doped into substrate 100.

[0027] The substrate 100 may include a first region I and a second region II that at least partially surrounds the first region I. The first region I may be a cell array region in which memory cells can be formed, and the second region II may be an extension region or a stepped region in which contact plugs for transmitting electrical signals to memory cells can be formed.

[0028] In an exemplary embodiment of this disclosure, the molding layer may include a first insulating layer 110, a first sacrificial layer 120 and a first insulating layer 110 sequentially stacked on a substrate 100, and may also include a first sacrificial layer 120 and a second sacrificial layer structure 190 alternately and repeatedly stacked on the first insulating layer 110, and a first insulating layer 110 located on the uppermost one of the first sacrificial layers 120.

[0029] The first insulating layer 110 may include an oxide, such as silicon oxide, and the first sacrificial layer 120 may include a material that has etch selectivity relative to the first insulating layer 110, such as a nitride, such as silicon nitride.

[0030] In an exemplary embodiment of this disclosure, the second sacrificial layer structure 190 may include a second sacrificial layer 160, a third sacrificial layer 170, and a fourth sacrificial layer 180 sequentially stacked in a first direction. Each of the second sacrificial layer 160 and the fourth sacrificial layer 180 may include an oxide, for example, silicon oxide, and the third sacrificial layer 170 may include a nitride, for example, silicon nitride.

[0031] In an exemplary embodiment of this disclosure, the thickness of the second sacrificial layer structure 190 in the first direction may be equal to or less than the thickness of the first sacrificial layer 120 in the first direction. Therefore, the thickness of the third sacrificial layer 170 included in the second sacrificial layer structure 190 in the first direction may be less than the thickness of the first sacrificial layer 120 in the first direction.

[0032] Reference Figure 3 An etching process using a photoresist pattern as an etching mask can be performed to pattern the molding layer, and a trimming process can be performed to reduce the area of ​​the photoresist pattern. The etching and trimming processes can be performed alternately and repeatedly to form a molded part with a stepped shape having multiple stepped layers disposed on the substrate 100.

[0033] In the following text, "step layer" can be used to refer to layers at the same level, which includes not only the exposed portion but also the unexposed portion; only the exposed portion of a step layer that is not covered by the step layers above can be referred to as a "step". In exemplary embodiments of this disclosure, as shown in the accompanying drawings, these steps can be arranged in a second direction. However, the inventive concept is not limited to this, and these steps can also be arranged in a third direction.

[0034] In an exemplary embodiment of this disclosure, each of the step layers may include a first sacrificial layer 120, a second sacrificial layer 160 located on the first sacrificial layer 120, and a third sacrificial layer 170 and a fourth sacrificial layer 180 sequentially stacked below the first sacrificial layer 120. The upper surface of the end of the second sacrificial layer 160 (e.g., the end in the second direction) may form the upper surface of each of the steps.

[0035] Reference Figure 4 and Figure 5 A first interlayer insulating layer 220 may be formed on the substrate 100 to cover the molded part, and the first pillar structure may be formed to penetrate the first interlayer insulating layer 220 and the molded part to contact the upper surface of the substrate 100.

[0036] The first pillar structure can be formed by performing, for example, a dry etching process to form channel holes through the first interlayer insulating layer 220 and the molding, thereby exposing the upper surface of the substrate 100 and filling the channel holes. In an exemplary embodiment of this disclosure, the dry etching process can be performed until the channel holes can expose the upper surface of the substrate 100, and the channel holes can also extend through the upper portion of the substrate 100. In an exemplary embodiment of this disclosure, a plurality of channel holes can be formed in each of the second and third directions, thereby defining an array of channel holes.

[0037] The exposed upper surface of substrate 100 can be used as a seed to perform a selective epitaxial growth (SEG) process to form a semiconductor pattern 130 that fills the lower portion of the channel via. The semiconductor pattern 130 may include, for example, crystalline silicon. In an exemplary embodiment of this disclosure, the upper surface of the semiconductor pattern 130 may be higher than and lower than the lower surface of a first insulating layer 110 located at a second level in a first direction from the upper surface of substrate 100.

[0038] A first barrier layer 230, a charge trapping layer 240, a tunnel insulating layer 250, and a first spacer layer can be sequentially formed on the sidewalls of the channel via, the upper surface of the semiconductor pattern 130, and the upper surface of the first interlayer insulating layer 220. The first spacer layer can be anisotropically etched to form a first spacer on the sidewalls of the channel via. The first spacer can be used as an etching mask to etch the tunnel insulating layer 250, the charge trapping layer 240, and the first barrier layer 230, such that each of the tunnel insulating layer 250, the charge trapping layer 240, and the first barrier layer 230 can have a cup-shaped shape with its bottom open on the upper surface of the semiconductor pattern 130 and the sidewalls of the channel via. The upper portion of the semiconductor pattern 130 can also be partially removed. The first barrier layer 230, the charge trapping layer 240, and the tunnel insulating layer 250 sequentially stacked on the upper surface of the semiconductor pattern 130 and the sidewalls of the channel via can form a charge storage layer structure 260.

[0039] After removing the first spacer, a channel layer can be formed on the charge storage layer structure 260 and the first interlayer insulating layer 220, and a fill layer can be formed on the channel layer to fill the remaining portion of the channel hole. The fill layer and the channel layer can be planarized until the upper surface of the first interlayer insulating layer 220 can be exposed, such that a columnar fill pattern 280 can be formed to fill the remaining portion of the channel hole, and the channel layer can be transformed into a cup-shaped channel 270 having sidewalls and a bottom surface covering the fill pattern 280. Therefore, the charge storage layer structure 260, the channel 270, and the fill pattern 280 can be sequentially stacked on the semiconductor pattern 130.

[0040] Since the channel holes, each having a channel 270, can define a channel hole array, the channels 270 in each channel hole can also define a channel array. In an exemplary embodiment of this disclosure, the channel array may include: a first channel column 270a, which includes a first channel disposed in a second direction; and a second channel column 270b, which includes a second channel disposed in the second direction and spaced apart from the first channel column 270a in a third direction. The first channel included in the first channel column 270a may form an acute angle with the second channel included in the second channel column 270b relative to the second or third direction. Therefore, the first channel and the second channel may be arranged in a zigzag pattern.

[0041] The first channel column 270a and the second channel column 270b can be alternately and repeatedly arranged in the third direction. In an exemplary embodiment of this disclosure, five first channel columns 270a and four second channel columns 270b can be alternately arranged in the third direction to form a channel block. The channel array may include a plurality of channel blocks spaced apart from each other in the third direction.

[0042] The number of channel columns included in a channel block is not limited to this. In the following text, the four channel columns in a channel block arranged in the third direction can be referred to in this order as the first channel column 270a, the second channel column 270b, the third channel column 270c, and the fourth channel column 270d, respectively. The channel column located at the center position in the third direction of the channel block can be referred to as the fifth channel column 270e. The other four channel columns in the third direction of the channel block can again be referred to in this order as the first channel column 270a, the second channel column 270b, the third channel column 270c, and the fourth channel column 270d, respectively.

[0043] The upper portion of the fill pattern 280, the channel 270, and the charge storage layer structure 260 can be removed to form the first recess. A capping layer can be formed on the first interlayer insulating layer 220 to fill the first recess. The capping layer can be planarized until the upper surface of the first interlayer insulating layer 220 can be exposed to form a capping pattern 290. The capping pattern 290 may include, for example, doped or undoped polysilicon.

[0044] The semiconductor pattern 130, charge storage layer structure 260, channel 270, filling pattern 280 and cover pattern 290 in the channel hole can together form the first pillar structure.

[0045] Reference Figure 6 and Figure 7 The first dividing layer 300 can be formed to pass through some portions of the first insulating layer 110, the first sacrificial layer 120 and the second sacrificial layer structure 190.

[0046] The first dividing layer 300 can be formed by the following steps: forming an etching mask on the first interlayer insulating layer 220, partially etching the first interlayer insulating layer 220, the first insulating layer 110, the first sacrificial layer 120, the second sacrificial layer structure 190, and the first pillar structure to form a second recess, and filling the second recess. The first dividing layer 300 may include, for example, an oxide of silicon oxide.

[0047] In an exemplary embodiment of this disclosure, the partition layer 300 may extend in a second direction at the center portion of each channel block in the third direction and may extend through the upper portion of the channel 270 included in the fifth channel column 270e. Therefore, the channel 270 included in the fifth channel column 270e can be used as a dummy channel.

[0048] In an exemplary embodiment of this disclosure, the first dividing layer 300 extends not only through the upper portion of the channel 270, but also through the first interlayer insulation layer 220, the uppermost of the first insulation layers 110, the first sacrificial layers 120 located at the upper two horizontal levels, and the uppermost of the second sacrificial layer structure 190, and can extend partially through the second sacrificial layer structure 190 located at the second horizontal level from above. The first dividing layer 300 can extend through the upper two stepped layers of the molded part in a second direction, and therefore, the first sacrificial layers 120 located at the upper two horizontal levels can be divided by the first dividing layer 300 in a third direction.

[0049] Reference Figure 8 and Figure 9 A second interlayer insulating layer 310 can be formed on the first interlayer insulating layer 220 and the overlay pattern 290. A dry etching process can be performed to form a first opening 320 through the first interlayer insulating layer 220 and the second interlayer insulating layer 310 and the molded part.

[0050] In an exemplary embodiment of this disclosure, a dry etching process may be performed until the upper surface of the substrate 100 can be exposed by the first opening 320, and the first opening 320 may extend through the upper portion of the substrate 100. When the first opening 320 is formed, the first insulating layer 110, the first sacrificial layer 120, and the second sacrificial layer structure 190 included in the molding may be exposed.

[0051] In an exemplary embodiment of this disclosure, the first opening 320 may extend between adjacent channel blocks in a second direction, and a plurality of first openings 320 may be formed in a third direction. When the first opening 320 is formed, the first insulating layer 110, the first sacrificial layer 120, and the second sacrificial layer structure 190 may be transformed into a first insulating pattern 115, a first sacrificial pattern 125, and a second sacrificial structure 195, respectively. The second sacrificial structure 195 may include a second sacrificial pattern 165, a third sacrificial pattern 175, and a fourth sacrificial pattern 185 sequentially stacked in a first direction.

[0052] Impurities can be implanted into the upper portion of the substrate 100 exposed by the first opening 320 to form an impurity region 105.

[0053] Reference Figure 10 The first sacrificial pattern 125 and the third sacrificial pattern 175 exposed by the first opening 320 can be partially removed to form the third recess 330 and the fourth recess 335, respectively, thereby reducing the length of each of the first sacrificial pattern 125 and the third sacrificial pattern 175 in the third direction.

[0054] In an exemplary embodiment of this disclosure, the first sacrificial pattern 125 and the third sacrificial pattern 175 can be partially removed by a wet etching process using phosphoric acid (H3PO4) as an etchant. The thickness of the third sacrificial pattern 175 can be less than the thickness of the first sacrificial pattern 125, so the amount of the third sacrificial pattern 175 removed in the wet etching process can be less than the amount of the first sacrificial pattern 125 removed in the wet etching process. Therefore, the depth of the fourth recess 335 in the third direction can be less than the depth of the third recess 330 in the third direction.

[0055] When the third recess 330 and the fourth recess 335 are formed, the surfaces of the second sacrificial pattern 165 and the fourth sacrificial pattern 185 included in the second sacrificial structure 195 at their third-direction ends can be exposed.

[0056] Reference Figure 11 A fifth sacrificial layer can be conformally formed on the inner walls of the third recess 330 and the fourth recess 335, as well as on the sidewalls at the ends of the second sacrificial pattern 165 and the fourth sacrificial pattern 185. This fifth sacrificial layer can be partially removed by a finishing process to form a fifth sacrificial pattern 340 in the fourth recess 335. Therefore, the sidewalls at the ends of the third sacrificial pattern 175, which has a reduced length in the third direction, can be at least partially covered by the fifth sacrificial pattern 340.

[0057] The fifth sacrificial pattern 340 may include a material that is etch-selective relative to the third sacrificial pattern 175, such as an oxide like silicon oxide. Therefore, in some cases, the fifth sacrificial pattern 340 may be incorporated into the second sacrificial pattern 165 and the fourth sacrificial pattern 185. The finishing process can be performed by a wet etching process using hydrofluoric acid (HF) as the etchant.

[0058] Reference Figure 12 The remaining portion of the first sacrificial pattern 125 can be removed to expand the third recess 330 in a third-direction upward direction and expose the sidewalls of the first barrier layer 230. A sixth sacrificial pattern 350 can be formed in the expanded third recess 330.

[0059] The first sacrificial pattern 125 can be removed by a wet etching process using phosphoric acid (H3PO4) as an etchant, and during the wet etching process, the third sacrificial pattern 175 can be at least partially covered by the second sacrificial pattern 165, the fourth sacrificial pattern 185 and the fifth sacrificial pattern 340 to prevent it from being removed.

[0060] The sixth sacrificial pattern 350 can be formed by the following steps: forming a sixth sacrificial layer on the substrate 100 to fill the third recess 330, and partially removing the sixth sacrificial layer by, for example, an etch-back process until the second sacrificial pattern 165 and the fourth sacrificial pattern 185 can be exposed at their third-direction ends.

[0061] The sixth sacrificial pattern 350 may include a material, such as polysilicon, that has etch selectivity relative to the second sacrificial pattern 165, the fourth sacrificial pattern 185, and the fifth sacrificial pattern 340.

[0062] Reference Figure 13 The fifth sacrificial pattern 340 can be removed to form a second opening 360 that exposes the third sacrificial pattern 175 at the third-direction end.

[0063] The fifth sacrificial pattern 340 can be removed by using a wet etching process, for example, with hydrofluoric acid (HF), and the portions of the second sacrificial pattern 165 and the fourth sacrificial pattern 185 adjacent to the fifth sacrificial pattern 340 in the first direction can also be removed. When the second opening 360 is formed, the lower and upper surfaces of the third-direction end of the sixth sacrificial pattern 350 can be exposed.

[0064] Reference Figure 14 The exposed lower and upper surfaces and sidewalls of the end of the sixth sacrificial pattern 350 can be oxidized by wet oxidation or dry oxidation to form the first etch stop layer 370, and the third sacrificial pattern 175 can be removed to form the third opening 380 that exposes the sidewalls of the first barrier layer 230.

[0065] The first etch stop layer 370 may include, for example, silicon oxide, and the third sacrificial pattern 175 may be removed by using a wet etching process with, for example, phosphoric acid (H3PO4). During the wet etching process, the sixth sacrificial pattern 350 may be at least partially covered by the first etch stop layer 370, as well as the second sacrificial pattern 165 and the fourth sacrificial pattern 185, to prevent removal.

[0066] Reference Figure 15 The second sacrificial pattern 165 and the fourth sacrificial pattern 185 can be removed to enlarge the third opening 380 in the first direction, and the portion of the first barrier layer 230 exposed by the enlarged third opening 380 can be removed, such that the first barrier layer 230 extending in the first direction can be divided into a plurality of first barrier patterns 235 spaced apart from each other in the first direction.

[0067] The second sacrificial pattern 165 and the fourth sacrificial pattern 185, as well as the exposed portions of the first barrier layer 230, can be removed using a wet etching process, such as hydrofluoric acid (HF), and the first etch stop layer 370 can also be removed. When the exposed portions of the first barrier layer 230 are removed, a fourth opening 390 can be formed that connects to the third opening 380 and exposes the sidewalls of the charge trapping layer 240.

[0068] In an exemplary embodiment of this disclosure, the wet etching process may be an isotropic etching process, so the width of the fourth opening 390 in the first direction may have a maximum value at the entrance connected to the third opening 380, and may gradually decrease toward the charge trapping layer 240 in the third direction.

[0069] In an exemplary embodiment of this disclosure, the first length L1 of the first blocking pattern 235 between adjacent fourth openings 390 in a first direction can have a minimum value at the outer sidewall of the first blocking pattern 235 facing the sixth sacrificial pattern 350, and a maximum value at the inner sidewall of the first blocking pattern 235 facing the charge trapping layer 240. For example, the first length L1 of the first blocking pattern 235 can gradually increase from the sixth sacrificial pattern 350 toward the charge trapping layer 240 in a horizontal direction substantially parallel to the upper surface of the substrate 100, and the absolute value of the slope of each of the lower and upper surfaces of the first blocking pattern 235 relative to the upper surface of the substrate 100 can gradually increase in the horizontal direction from the sixth sacrificial pattern 350 toward the charge trapping layer 240.

[0070] When the second sacrificial pattern 165 and the fourth sacrificial pattern 185 and the first etch stop layer 370 are removed, the sidewalls, lower surface and upper surface of the sixth sacrificial pattern 350 can be exposed.

[0071] Reference Figure 16 The exposed sidewalls, lower and upper surfaces of the sixth sacrificial pattern 350 can be oxidized by wet oxidation or dry oxidation processes to form a second etch stop layer 400 including, for example, silicon oxide, and the portion of the charge trapping layer 240 exposed by the fourth opening 390 can be removed.

[0072] Therefore, the charge trapping layer 240 extending in the first direction can be divided into a plurality of charge trapping patterns 245 spaced apart from each other in the first direction. Hereinafter, the tunnel insulating layer 250 extending in the first direction, the charge trapping patterns 245 spaced apart from each other in the first direction, and the first blocking pattern 235 spaced apart from each other in the first direction can be collectively referred to as the charge storage structure 265.

[0073] The exposed portion of the charge trapping layer 240 can be removed by a wet etching process using, for example, phosphoric acid (H3PO4) as an etchant, and a fifth opening 410 can be formed that connects to the fourth opening 390 and partially exposes the sidewalls of the tunnel insulation layer 250.

[0074] In an exemplary embodiment of this disclosure, the wet etching process may be an isotropic etching process, so the width of the fifth opening 410 in the first direction may have a maximum value at the entrance connected to the fourth opening 390, and may gradually decrease toward the tunnel insulation layer 250 in the third direction.

[0075] In an exemplary embodiment of this disclosure, the second length L2 of the charge trapping pattern 245 between adjacent fifth openings 410 in a first direction can have a minimum value at the outer wall of the charge trapping pattern 245 facing the first blocking pattern 235, and a maximum value at the inner wall of the charge trapping pattern 245 facing the tunnel insulating layer 250. For example, the second length L2 of the charge trapping layer 235 can gradually increase in the horizontal direction from the first blocking pattern 235 toward the tunnel insulating layer 250, and the absolute value of the slope of each of the lower and upper surfaces of the charge trapping pattern 245 relative to the upper surface of the substrate 100 can gradually increase in the horizontal direction from the first blocking pattern 235 toward the tunnel insulating layer 250.

[0076] Reference Figure 17 The second insulating layer 420 can be formed by a deposition process through the first opening 320 to fill the third opening 380, the fourth opening 390 and the fifth opening 410, and an air gap 430 can be formed between adjacent sixth sacrificial patterns 350 in the first direction in the sixth sacrificial pattern 350.

[0077] The second insulating layer 420 may include, for example, an oxide of silicon oxide. The second insulating layer 420 may or may not be incorporated with the second etch stop layer 400 on the sidewalls, lower surface, and upper surface of the sixth sacrificial pattern 350.

[0078] The shape, position, and size of the air gap 430 can vary depending on the conditions of the deposition process of the second insulating layer 420. In an exemplary embodiment of this disclosure, the air gap 430 may not expose the sidewalls of the tunnel insulating layer 250, but may be formed at the end of the air gap 430 between adjacent charge trapping patterns 245 in a first direction.

[0079] Reference Figure 18The second insulating layer 420 and the second etch stop layer 400 can be partially removed until the sidewalls of the sixth sacrificial pattern 350 at the third-side-up end are exposed, in the third opening 380, the fourth opening 390 and the fifth opening 410 (see...). Figure 16 A second insulating pattern 425 may be formed in the first insulating pattern 115 and / or the first interlayer insulating layer 220 and the second interlayer insulating layer 310, and a third insulating pattern 427 may be formed on the sidewalls of the third-direction ends (see [link]). Figure 20 However, in some cases, the third insulating pattern 427 may be incorporated into the first insulating pattern 115 and / or the first interlayer insulation layer 220 and the second interlayer insulation layer 310.

[0080] The second insulating layer 420 and the second etch stop layer 400 can be partially removed by a wet etching process using, for example, hydrofluoric acid (HF) as an etchant. Through the wet etching process, the second etch stop layer 400 can at least partially cover the lower and upper surfaces of the sixth sacrificial pattern 350, and can expose the sidewalls of the third-direction upward end of the sixth sacrificial pattern 350.

[0081] The exposed sixth sacrificial pattern 350 can be removed by a wet etching process using, for example, phosphoric acid (H3PO4) as an etchant, to form a sixth opening 440 that exposes the outer wall of the first blocking pattern 235.

[0082] Reference Figure 19 A second barrier layer 450 may be formed on the sidewall of the sixth opening 440, the exposed outer sidewall of the first barrier pattern 235, and the sidewall of the second insulating pattern 425 and the second etch stop layer 400 at the third-direction upward end, and a gate electrode 460 may be formed in the sixth opening 440.

[0083] Reference Figure 20 A second barrier layer 450 may also be formed on the sidewalls of the third insulating pattern 427, the first interlayer insulating layer 220, and the second interlayer insulating layer 310, the upper surface of the second interlayer insulating layer 310, and the upper surface of the substrate 100 exposed by the first opening 320. The second barrier layer 450 may include a metal oxide having a high dielectric constant, such as aluminum oxide, hafnium oxide, etc.

[0084] The gate electrode 460 can be formed by the following steps: forming a gate electrode layer on the second barrier layer 450 to fill the remaining portion of the sixth opening 440, and partially removing the gate electrode layer by, for example, a wet etching process. The gate electrode layer may include a gate barrier layer and a gate conductive layer sequentially stacked, thus the gate electrode 460 may include a gate conductive pattern and a gate barrier pattern covering the lower and upper surfaces and sidewalls of the gate conductive pattern. The gate conductive pattern may include a metal with low resistance, such as tungsten, titanium, tantalum, platinum, etc., and the gate barrier pattern may include a metal nitride, such as titanium nitride, tantalum nitride, etc.

[0085] In an exemplary embodiment of this disclosure, the gate electrode 460 may extend in a second direction, and a plurality of gate electrodes 460 may be formed in a first direction. Furthermore, a plurality of gate electrodes 460 may be formed in a third direction. For example, gate electrodes 460, each extending in the second direction, may be spaced apart from each other through a first opening 320. The gate electrodes 460 may include a first gate electrode 472, a second gate electrode 474, and a third gate electrode 476 sequentially stacked in the first direction.

[0086] Reference Figure 20 A second spacer layer can be formed on the second barrier layer 450, and the second spacer layer can be anisotropically etched to form a second spacer 480 on the sidewall of the first opening 320.

[0087] The second spacer 480 may include, for example, an oxide of silicon oxide.

[0088] A conductive layer may be formed on the substrate 100 (e.g., the upper surface of the impurity region 105), the second spacer 480, and the second barrier layer 450, and the conductive layer may be planarized until the upper surface of the second interlayer insulating layer 310 is exposed to form a common source pattern (CSP) 490. A portion of the second barrier layer 450 located on the upper surface of the second interlayer insulating layer 310 may also be removed.

[0089] CSP 490 may extend in a second direction, and multiple CSP 490s may be spaced apart from each other in a third direction. CSP 490 may include metal, metal nitride, metal silicide, etc., and in some cases, CSP 490 may not be formed. CSP 490 and second spacers 480 covering each of the opposing sidewalls of CSP 490 in the third direction may form a dividing structure.

[0090] Reference Figure 21A third interlayer insulation layer 500 can be formed on the second interlayer insulation layer 310, the dividing structure, and the second barrier layer 450. The contact plug 510 can be formed to penetrate the second interlayer insulation layer 310 and the third interlayer insulation layer 500 to contact the upper surface of the cover pattern 290.

[0091] Bit lines 520 can be formed to contact the upper surface of contact plugs 510, enabling the fabrication of a vertical memory device. In exemplary embodiments of this disclosure, bit lines 520 can be formed in a third direction, and multiple bit lines 520 can be spaced apart from each other in a second direction.

[0092] As shown above, a second sacrificial layer structure 190 can be formed between the first sacrificial layers 120 used to form the gate electrode 460. The second sacrificial layer structure 190 has a second sacrificial layer 160 and a fourth sacrificial layer 180 comprising the same material as the first barrier layer 230, and a third sacrificial layer comprising the same material as the charge trapping layer 240. When the second sacrificial layer structure 190 is removed to form the third opening 380, the first barrier layer 230 and the charge trapping layer 240 can be partially removed, such that each of the first barrier layer 230 and the charge trapping layer 240 can be divided into a plurality of segments spaced apart from each other in a first direction. Furthermore, the second insulating layer 420 can be formed to fill the third opening 380, such that an air gap 430 can be formed in the second insulating layer 420.

[0093] Therefore, a second insulating pattern 425, including an air gap 430, can be formed between the gate electrodes 460 that replace the first sacrificial layer 120. Thus, even if different voltages are applied to adjacent gate electrodes 460 in the first direction, the breakdown of the insulating properties of the second insulating pattern 425 between the gate electrodes 460 can be reduced. As a result, the second insulating pattern 425 can be relatively thin in the first direction, and even if the gate electrodes 460 have a large number of stacks in the first direction, an increase in the height of the vertical memory device including the second insulating pattern 425 can be prevented.

[0094] Furthermore, multiple charge trapping patterns 245 may be adjacent to multiple gate electrodes 460 respectively, rather than the charge trapping layer 240 extending in the first direction being adjacent to multiple gate electrodes 460 together. Therefore, the degradation of the retention characteristics of the vertical memory device due to the movement of charge in the first direction through the gate electrodes 460 at different levels can be prevented.

[0095] Refer again Figure 8 , Figure 19 and Figure 21The vertical memory device may include: a first pillar structure extending in a first direction on a substrate 100; a gate electrode structure including gate electrodes 460, each of the gate electrodes 460 being permissible around the first pillar structure and spaced apart from each other in the first direction on the substrate 100; a second insulating pattern 425 including an air gap 430 located between the gate electrodes 460; a second barrier layer 450 covering the lower and upper surfaces of each of the gate electrodes 460 and a sidewall facing the first pillar structure; a partition structure extending in the second direction on the substrate 100 and contacting the third-direction end of the gate electrode structure; and a bit line 520 extending in the third-direction on the gate electrode structure and electrically connected to a channel 270. The vertical memory device may also include a second etch stop layer 400, a first insulating pattern 115, a third insulating pattern 427, a first partition layer 300, a first interlayer insulating layer 220, a second interlayer insulating layer 310, a third interlayer insulating layer 500, and a contact plug 510.

[0096] The first pillar structure may include: a semiconductor pattern 130 located on the substrate 100; a channel 270 having a cup shape and located on the semiconductor pattern 130; a charge storage structure 265 covering the outer wall of the channel 270; a filling pattern 280 filling the internal space formed by the channel 270; and a cover pattern 290 located on the channel 270, the charge storage structure 265, and the filling pattern 280. The charge storage structure 265 may include a first blocking pattern 235, a charge trapping pattern 245, and a tunnel insulating layer 250 sequentially stacked between the outer wall of the channel 270 and each of the gate electrodes 460.

[0097] In an exemplary embodiment of this disclosure, a plurality of first blocking patterns 235 may each face the gate electrode 460 in a horizontal direction and be spaced apart from each other in a first direction. The first length L1 of each of the first blocking patterns 235 in the first direction may be smaller at its outer sidewall facing the gate electrode 460 than at its inner sidewall facing the charge trapping pattern 245. In an exemplary embodiment of this disclosure, the first length L1 of each of the first blocking patterns 235 may gradually increase in the horizontal direction from the gate electrode 460 toward the charge trapping pattern 245, and the absolute values ​​of the slopes of the lower and upper surfaces of each of the first blocking patterns 235 relative to the upper surface of the substrate 100 may gradually increase in the horizontal direction.

[0098] In an exemplary embodiment of this disclosure, a plurality of charge trapping patterns 245 may each face the gate electrode 460 and be spaced apart from each other in a first direction. The second length L2 of each of the charge trapping patterns 245 in the first direction may be minimum at its outer sidewall facing the first blocking pattern 235 and maximum at its inner sidewall facing the tunnel insulating layer 250. For example, the second length L2 of each of the charge trapping patterns 245 may gradually increase in the horizontal direction from the first blocking pattern 235 toward the tunnel insulating layer 250, and the absolute values ​​of the slopes of the lower and upper surfaces of each of the charge trapping patterns 245 relative to the upper surface of the substrate 100 may gradually increase in the horizontal direction.

[0099] In an exemplary embodiment of this disclosure, a plurality of first pillar structures may be formed in each of the second and third directions to define an array of first pillar structures, and the array of first pillar structures may be formed by an array of channels including channels 270 in each of the first pillar structures.

[0100] The gate electrode structure may include a first gate electrode 472, a second gate electrode 474, and a third gate electrode 476 at multiple horizontal locations in a first direction, and each of the first gate electrode 472, the second gate electrode 474, and the third gate electrode 476 may extend in a second direction.

[0101] In an exemplary embodiment of this disclosure, the gate electrode structure may include at least one first gate electrode 472, a plurality of second gate electrodes 474, and at least one third gate electrode 476 sequentially stacked in a first direction on the upper surface of the substrate 100. The first gate electrode 472 may be used as a ground select line (GSL), each of the second gate electrodes 474 may be used as a word line, and the third gate electrode 476 may be used as a string select line (SSL).

[0102] In an exemplary embodiment of this disclosure, a second insulating pattern 425 may be formed between the second gate electrode 474 and between the second gate electrode 474 and the third gate electrode 476, and the second insulating pattern 425 may include an air gap 430 therein. A first insulating pattern 115 without an air gap may be formed between the first gate electrode 472 and the second gate electrode 474 and between the substrate 100 and the first gate electrode 472.

[0103] Multiple gate electrode structures can be spaced apart from each other in a third direction by a partition structure. In an exemplary embodiment of this disclosure, the gate electrode structures can form a stepped structure, the length of which in a second direction can decrease from the lowest level to the highest level in a first direction.

[0104] The partition structure may include a CSP 490 extending on the substrate 100 in a second direction and a second spacer 480 covering each of the opposing sidewalls of the CSP 490 in a third direction.

[0105] The second barrier layer 450 may at least partially cover the sidewall of the third-direction end of the second insulating pattern 425, and thus may extend in the first direction to be adjacent to the dividing structure.

[0106] The second etch stop layer 400 may at least partially cover the lower and upper surfaces of the second insulating pattern 425, but may not cover the lower and upper surfaces of the portion of the second insulating pattern 425 located between the charge trapping patterns 245. The second etch stop layer 400 may be incorporated into the second insulating pattern 425, or may be distinct from the second insulating pattern 425.

[0107] Figures 22 to 27 This is a cross-sectional view showing a method of manufacturing a vertical memory device according to an exemplary embodiment of the present disclosure. Figures 22 to 27 These can be cross-sectional views taken along line C-C' of the corresponding plan view. Figures 22 to 26 yes Figure 9 Enlarged cross-sectional view of region X.

[0108] This method may include references Figures 1 to 22 The processes shown are substantially the same or similar, and further explanations of these processes are omitted here.

[0109] Reference Figure 22 It can be executed and referenced. Figures 1 to 11 The processes shown are substantially the same or similar, and can be performed as in the reference process. Figure 19 The processes shown are essentially the same or similar.

[0110] Specifically, the first sacrificial pattern 125 can be removed to enlarge the third recess 330 in the third direction, a second blocking pattern 455 can be formed on each of the opposite sidewalls of the enlarged third recess 330 in the first direction and on the exposed outer sidewall of the first blocking layer 230, and a gate electrode 460 can be formed in the third recess 330.

[0111] In an exemplary embodiment of this disclosure, the second barrier pattern 455 and the gate electrode 460 can be formed by the following steps: forming a second barrier layer 450 on the sidewall of the third recess 330 in the first direction, on the exposed outer sidewall of the first barrier layer 230, and on the sidewall of the second sacrificial pattern 165, the fourth sacrificial pattern 185, and the fifth sacrificial pattern 340 at the third-direction end; forming a gate electrode layer on the second barrier layer 450 to fill the third recess 330; partially removing the gate electrode layer to expose a portion of the second barrier layer 450; removing the exposed portion of the second barrier layer 450 (e.g., the portion of the second barrier layer 450 located on the sidewall, lower surface, and upper surface of the second sacrificial pattern 165, the fourth sacrificial pattern 185, and the fifth sacrificial pattern 340 at the third-direction end); and partially removing the gate electrode layer to further expose a portion of the second barrier layer 450.

[0112] Therefore, the length of the portion of the second blocking pattern 455 located on the lower surface of the second sacrificial pattern 165 or on the upper surface of the fourth sacrificial pattern 185 in the third direction can be less than the length of the third sacrificial pattern 175 between the second sacrificial pattern 165 and the fourth sacrificial pattern 185 in the third direction, but can be greater than the length of the gate electrode 460 in the third direction.

[0113] Reference Figure 23 A protective layer 550 can be formed on the substrate 100 to fill the remaining portion of the third recess 330. The second sacrificial pattern 165, the fourth sacrificial pattern 185, the fifth sacrificial pattern 340 and the protective layer 550 can be partially removed until the sidewall of the third sacrificial pattern 175 at the third-direction end is exposed.

[0114] The protective layer 550 may include, for example, an oxide of silicon oxide, and thus in some cases, the protective layer 550 may be incorporated into the second sacrificial pattern 165 and the fourth sacrificial pattern 185.

[0115] Reference Figure 24 It can be executed and referenced. Figure 14 and Figure 15 The processes shown are substantially the same or similar, such that the second sacrificial structure 195 can be removed to form the third opening 380 and the fourth opening 390, and the first barrier layer 230 can be divided into the first barrier pattern 235.

[0116] When the second sacrificial structure 195 is removed, the sixth sacrificial pattern 350, which includes polysilicon, has not yet been formed, so the first etch stop layer 370 can be left unformed.

[0117] When removing the second sacrificial pattern 165 and the fourth sacrificial pattern 185, the protective layer 550 may not be completely removed; instead, it may be partially retained. Specifically, a portion of the protective layer 550 from the sidewall of the third-direction end of the gate electrode 460 to the third-direction end of the second blocking pattern 455 may be retained. Thus, the protective layer 550 may at least partially cover the gate electrode 460.

[0118] Reference Figure 25 It can be executed and referenced. Figure 16 The processes shown are substantially the same or similar, which allows the charge trapping layer 240 to be partially etched to form the fifth opening 410, and allows the charge trapping layer 240 to be divided into charge trapping patterns 245.

[0119] In exemplary embodiments of this disclosure, when the second barrier pattern 455 comprises, for example, alumina, the etching process can be performed using a dry etching process employing an etching gas with etching selectivity between alumina and nitrides. Alternatively, when the second barrier pattern 455 comprises, for example, hafnium oxide, the etching process can be performed using a wet etching process employing an etchant with etching selectivity between hafnium oxide and nitrides (e.g., phosphoric acid (H3PO4) or hydrofluoric acid (HF)). Therefore, even if the second barrier pattern 455 is exposed, it may not be removed during the etching process.

[0120] Reference Figure 26 It can be executed and referenced. Figure 17 The processes shown are substantially the same or similar, which allows a second insulating layer 420 to be formed to fill the third opening 380, the fourth opening 390 and the fifth opening 410, and allows an air gap 430 to be formed between adjacent gate electrodes 460 in the first direction in the gate electrodes 460.

[0121] The second insulating layer 420 may include, for example, an oxide of silicon oxide, and therefore may or may not be incorporated into the protective layer 550.

[0122] Reference Figure 27 It can be executed and referenced. Figure 20 and Figure 21 The processes shown are substantially the same or similar to those used to manufacture vertical memory devices.

[0123] As shown above, compared with the reference Figures 1 to 21The method of manufacturing the vertical memory device shown differs from the method described above. The process of replacing the first sacrificial pattern 125 with the sixth sacrificial pattern 350 can be skipped, and the first sacrificial pattern 125 can be directly replaced by the gate electrode 460, thus simplifying the entire process. Furthermore, a second insulating pattern 425 can be easily formed, comprising an air gap 430 between charge trapping patterns 245 spaced apart in the first direction and between gate electrodes 460 spaced apart in the first direction.

[0124] and Figure 8 , Figure 19 and Figure 21 Unlike traditional vertical memory devices, this vertical memory device may have the following structural features.

[0125] Specifically, a protective layer 550 may be formed on the sidewall of each of the gate electrodes 460 at its third-direction-oriented end, and a second etch stop layer 400 may not be formed on the lower and upper surfaces of the second insulating pattern 425 (see [link]). Figure 21 ).

[0126] The second blocking pattern 455 may at least partially cover the lower and upper surfaces of each of the gate electrodes 460, the sidewalls facing the charge storage structure 265, and the lower and upper surfaces of the protective layer 550. In an exemplary embodiment of this disclosure, the ends of the second insulating pattern 425, the protective layer 550, and the second blocking pattern 455 in a third direction may be aligned with each other in a first direction.

[0127] Figure 28 and Figure 29 This is a cross-sectional view showing a method of manufacturing a vertical memory device according to an exemplary embodiment of the present disclosure, specifically, Figure 28 and Figure 29 These are cross-sectional views taken along line C-C' of the corresponding plan view. Figure 28 yes Figure 9 Enlarged cross-sectional view of region X.

[0128] This method may include references Figures 1 to 21 The processes shown are substantially the same or similar, and further explanations regarding them are omitted here.

[0129] Reference Figure 28 It can be executed and referenced. Figures 1 to 15 The process shown is substantially the same or similar, and the portion of the charge trapping layer 240 exposed by the fourth opening 390 can be oxidized instead of forming the fifth opening 410.

[0130] Therefore, the portion of the charge trapping layer 240 adjacent to the fourth opening 390 can be converted into a second dividing layer 415, and the charge trapping layer 240 extending in the first direction can be divided into charge trapping patterns 245 spaced apart from each other in the first direction.

[0131] The oxidation process may include a dry oxidation process or a wet oxidation process, and the second dividing layer 415 formed by the oxidation process may include, for example, silicon oxide or silicon oxynitride. In an exemplary embodiment of this disclosure, the width of the second dividing layer 415 in a first direction may be maximum at the entrance adjacent to the fourth opening 390, and may gradually decrease toward the tunnel insulation layer 250 in a third direction.

[0132] Reference Figure 29 It can be executed and referenced. Figures 17 to 21 The processes shown are substantially the same or similar to those used to manufacture vertical memory devices.

[0133] The vertical memory device may have the feature that the charge trapping patterns 245 are spaced apart from each other in the first direction not by the second insulating pattern 425, but by the second dividing layer 415, which may differ from the reference. Figures 1 to 21 The vertical memory device shown.

[0134] This method can also be applied to references Figures 22 to 27 The vertical memory device shown.

[0135] Figures 30 to 41 These are plan views and cross-sectional views illustrating a method of manufacturing a vertical memory device according to exemplary embodiments of the present disclosure. Specifically, Figure 30 and Figure 33 It's a floor plan. Figure 31 , Figure 32 and Figures 34 to 41 It is a cross-sectional view. Figure 31 , Figure 34 , Figure 38 and Figure 40 These are cross-sectional views taken along line B-B' of the corresponding plan view. Figure 32 , Figures 35 to 37 , Figure 39 and Figure 41 These are cross-sectional views taken along line C-C' of the corresponding plan view. Figures 35 to 37 yes Figure 34 Enlarged cross-sectional view of region Y.

[0136] This method may include references Figures 1 to 21 The processes shown are substantially the same or similar, and further explanations thereof are omitted here. To some extent, some elements are not described below; it may be assumed that these elements are at least similar to their corresponding counterparts already described herein.

[0137] Reference Figures 30 to 32 It can be executed and referenced. Figures 1 to 12 The processes shown are essentially the same or similar. However, the references can be skipped. Figure 6 and Figure 7 The process shown is (e.g., the process for forming the first dividing layer 300).

[0138] After the fourth insulating pattern 600 is formed to fill the first opening 320, the first interlayer insulating layer 220, the second interlayer insulating layer 310, the cover pattern 290 and the upper portion of the fill pattern 280 can be etched by using an etching process with an etching mask, so that the seventh opening 610 can be formed to expose the fill pattern 280, and a third etch stop layer 620 can be formed on the sidewall of the seventh opening 610 and on the second interlayer insulating layer 310.

[0139] The fourth insulating pattern 600 may include, for example, an oxide of silicon oxide, and the third etch stop layer 620 may include a material having etch selectivity relative to the fill pattern 280, such as polysilicon.

[0140] Reference Figure 33 and Figure 34 The filling pattern 280, channel 270, semiconductor pattern 130 and charge storage layer structure 260 exposed by the seventh opening 610 can be removed by, for example, a wet etching process to form an eighth opening 630 that exposes the upper surface of the substrate 100.

[0141] During the wet etching process, the third etch stop layer 620 and the overlay pattern 290 can be completely or partially removed. If they are partially retained, additional processes for their removal can also be performed.

[0142] Reference Figure 35 It can be executed and referenced. Figure 14 The processes shown are substantially the same or similar. However, the third sacrificial pattern 175 can be removed by the eighth opening 630 instead of the first opening 320, thus forming a third opening 380 that exposes the sidewalls of the first barrier layer 230.

[0143] A first etch stop layer 370 can also be formed on the sidewall of the sixth sacrificial pattern 350 adjacent to the eighth opening 630.

[0144] Reference Figure 36 It can be executed and referenced. Figure 15The illustrated processes are substantially the same or similar, allowing the removal of the second sacrificial pattern 165 and the fourth sacrificial pattern 185 to enlarge the third opening 380 in the first direction, and allowing the removal of the portion of the first barrier layer 230 exposed by the enlarged third opening 380 to form the fourth opening 390. Thus, the first barrier layer 230 extending in the first direction can be divided into first barrier patterns 235 spaced apart from each other in the first direction.

[0145] Reference Figures 37 to 39 It can be executed and referenced. Figures 16 to 19 The processes shown are essentially the same or similar.

[0146] Therefore, the charge trapping layer 240 extending in the first direction can be divided into charge trapping patterns 245 spaced apart from each other in the first direction, the sixth sacrificial pattern 350 can be replaced by a gate electrode 460, and a second insulating pattern 425 including an air gap 430 located therein can be formed between adjacent gate electrodes 460 in the first direction.

[0147] A second etch stop layer 400 can be formed on the lower and upper surfaces of the second insulating pattern 425, and a second barrier layer 450 can be formed on the surface of the second etch stop layer 400 and on the sidewalls of the second etch stop layer 400 and the second insulating pattern 425 adjacent to the eighth opening 630. The second barrier layer 450 can also be formed on the sidewalls of the first interlayer insulating layer 220 and the second interlayer insulating layer 310, on the sidewalls of the uppermost and lowermost first insulating patterns 115 adjacent to the eighth opening 630, and on the upper surface of the substrate 100 exposed by the eighth opening 630. Furthermore, the second barrier layer 450 can at least partially cover the sidewalls of each of the gate electrodes 460 at its third-direction end, and thereby contact the sidewalls of the fourth insulating pattern 600.

[0148] Reference Figure 40 and Figure 41 A fifth insulating layer can be formed on the second barrier layer 450 to fill the eighth opening 630, and the fifth insulating layer can be planarized until the upper surface of the second interlayer insulating layer 310 can be exposed.

[0149] Therefore, a fifth insulating pattern 640 can be formed in the eighth opening 630, which can form the second pillar structure. During the planarization process, a portion of the second barrier layer 450 located on the upper surface of the second interlayer insulating layer 310 can also be removed. The fifth insulating pattern 640 may include, for example, an oxide of silicon oxide.

[0150] Executable and referenced Figure 6 and Figure 7 The illustrated processes are substantially the same or similar, such that the first dividing layer 300 can be formed to extend at least partially through the first insulating pattern 115, the second insulating pattern 425, the fifth insulating pattern 640, the first interlayer insulating layer 220 and the second interlayer insulating layer 310, the third gate electrode 476, the second barrier layer 450, and the second etch stop layer 400. Therefore, each of the third gate electrodes 476 can be divided in a third-order direction by the first dividing layer 300.

[0151] Executable and referenced Figure 20 and Figure 21 The processes shown are substantially the same or similar to those used to manufacture vertical memory devices.

[0152] As shown above, compared with the reference Figures 1 to 21 The differences shown are that, in this method of manufacturing a vertical memory device, the charge trapping layer 240 can be divided or a second insulating pattern 425 including an air gap 430 can be formed via an eighth opening 630 instead of a first opening 320 extending in the second direction. The eighth opening 630 can be formed by removing a first pillar structure, which includes channels 270 included in the fifth channel row 270e that serve as dummy channels. A process of replacing the first sacrificial pattern 125 with a sixth sacrificial pattern 350 can be performed via the first opening 320; however, a process of replacing the sixth sacrificial pattern 350 with a gate electrode 460 can be performed via the eighth opening 630.

[0153] and Figure 8 , Figure 19 and Figure 21 Unlike traditional vertical memory devices, this vertical memory device may have the following structural features.

[0154] Specifically, unlike the first pillar structure including the channel 270, a second pillar structure including an insulating material (e.g., a fifth insulating pattern 640) can be formed, and the first and second pillar structures can be arranged on the substrate 100 in each of a second and a third direction. In an exemplary embodiment of this disclosure, the second pillar structure can be formed by replacing the first pillar structure having the channel 270 included in the fifth channel column 270e with the fifth insulating pattern 640. Therefore, the second pillar structures can be arranged in the second direction to be spaced apart from each other.

[0155] In an exemplary embodiment of this disclosure, the portion of the sidewall of the second pillar structure facing each of the second insulating patterns 425 may protrude in the horizontal direction compared to the portion of the sidewall of the second pillar structure facing each of the second insulating patterns 425. Therefore, the second pillar structure may have uneven sidewalls.

[0156] In an exemplary embodiment of this disclosure, the second barrier layer 450 may at least partially cover the lower and upper surfaces of each of the gate electrodes 460, the sidewall of each of the gate electrodes 460 facing the first pillar structure, and the sidewall of the third-direction end of each of the gate electrodes 460. Furthermore, the second barrier layer 450 may at least partially cover the sidewall of the second insulating pattern 425 facing the second pillar structure, and thereby may extend between the second pillar structure and the first pillar structure in a first direction.

[0157] Figure 42 This is a cross-sectional view showing a vertical memory device according to an exemplary embodiment of the present disclosure, specifically, Figure 42 It is a cross-sectional view taken along line C-C' of the corresponding plan view.

[0158] Apart from some components, this vertical memory device can be used with Figure 21 The vertical memory devices are substantially the same or similar. Therefore, the same reference numerals may refer to the same elements, and detailed descriptions thereof are omitted here. To some extent, the omission of certain elements below may be assumed to be at least similar to their corresponding counterparts already described herein.

[0159] Reference Figure 42 It can execute with Figure 28 and Figure 29 The processes are essentially the same or similar. Therefore, the portion of the charge trapping layer 240 exposed by the fourth opening 390 can be oxidized instead of forming the fifth opening 410, so that the charge trapping layer 240 can be divided into charge trapping patterns 245 spaced apart from each other in the first direction.

[0160] Although exemplary embodiments of this disclosure have been specifically shown and described, those skilled in the art will understand that changes in form and detail may be made herein without departing from the spirit and scope of the claims.

Claims

1. A vertical memory device, comprising: A channel disposed on a substrate, the channel extending primarily in a first direction perpendicular to the upper surface of the substrate; A charge storage structure disposed on the outer wall of the channel, the charge storage structure comprising a tunnel insulating layer, a charge trapping pattern and a first blocking pattern sequentially stacked in a horizontal direction parallel to the upper surface of the substrate; A plurality of gate electrodes spaced apart from each other in the first direction, each of the plurality of gate electrodes at least partially surrounding the charge storage structure; as well as A first insulating pattern is disposed between adjacent gate electrodes among the plurality of gate electrodes, the first insulating pattern including an air gap disposed therein. The charge storage structure includes charge trapping patterns spaced apart from each other in the first direction, each of the charge trapping patterns facing one of the plurality of gate electrodes in the horizontal direction. Wherein, the length of the outer sidewall of each of the charge trapping patterns facing the first blocking pattern in the first direction is less than the length of the inner sidewall of each of the charge trapping patterns facing the tunnel insulation layer in the first direction, and The vertical memory device further includes an etch stop layer, which is disposed only on the lower and upper surfaces of the first insulating pattern and not on the lower and upper surfaces of the portion of the first insulating pattern located between the charge trapping patterns. The etch stop layer comprises silicon oxide.

2. The vertical storage device according to claim 1, wherein, The first insulating pattern is further disposed between the charge trapping patterns.

3. The vertical memory device according to claim 1 further includes a partitioning layer disposed between the charge trapping patterns.

4. The vertical storage device according to claim 1, wherein, The length of each of the charge trapping patterns in the first direction gradually increases from the outer wall of the charge trapping pattern toward the inner wall of the charge trapping pattern.

5. The vertical memory device according to claim 4, wherein, The absolute value of the slope of the upper or lower surface of each of the charge trapping patterns relative to the upper surface of the substrate gradually increases from the outer sidewall of the charge trapping pattern toward the inner sidewall of the charge trapping pattern.

6. The vertical storage device according to claim 1, wherein, The charge storage structure includes first barrier patterns spaced apart from each other in the first direction, each of the first barrier patterns facing one of the plurality of gate electrodes in the horizontal direction, and a first insulating pattern disposed between the first barrier patterns. Wherein, the length of the outer sidewall of each of the first blocking patterns facing one of the plurality of gate electrodes in the first direction is less than the length of the inner sidewall of each of the first blocking patterns facing one of the charge trapping patterns in the first direction.

7. The vertical memory device of claim 1, further comprising a second barrier layer, the second barrier layer at least partially covering the lower and upper surfaces of each of the plurality of gate electrodes and the sidewall facing the charge storage structure, the second barrier layer comprising a metal oxide.

8. The vertical memory device according to claim 7, wherein, The second barrier layer extends primarily in the first direction and at least partially covers the lower and upper surfaces of each of the plurality of gate electrodes, the sidewalls facing the charge storage structure, and the sidewalls of the first insulating pattern adjacent to each of the plurality of gate electrodes.

9. The vertical storage device according to claim 1, wherein, Each of the plurality of gate electrodes extends in a second direction parallel to the upper surface of the substrate, and Wherein, the thickness of the end of the first insulating pattern in the third direction in the first direction is greater than the thickness of the other parts of the first insulating pattern in the first direction, the third direction being parallel to the upper surface of the substrate and intersecting the second direction.

10. A vertical memory device, comprising: A channel disposed on a substrate, the channel extending primarily in a first direction perpendicular to the upper surface of the substrate; A charge storage structure disposed on the outer wall of the channel, the charge storage structure comprising a tunnel insulating layer, a charge trapping pattern and a first blocking pattern sequentially stacked in a horizontal direction parallel to the upper surface of the substrate; A plurality of gate electrodes spaced apart from each other in the first direction, each of the plurality of gate electrodes at least partially surrounding the charge storage structure; An insulating pattern is disposed between adjacent gate electrodes in the plurality of gate electrodes, the insulating pattern including an air gap disposed therein; as well as An etch stop layer is formed only on the lower and upper surfaces of the insulating pattern. The charge storage structure includes charge trapping patterns spaced apart from each other in the first direction, each of the charge trapping patterns facing one of the plurality of gate electrodes in the horizontal direction. The etch stop layer is not disposed on the lower and upper surfaces of the portion of the insulating pattern located between the charge trapping patterns, and the etch stop layer comprises silicon oxide.

11. The vertical memory device according to claim 10, wherein, The etch stop layer is a layer separate from the insulating pattern.

12. The vertical memory device according to claim 10, wherein, The insulating pattern is also formed between the charge trapping patterns.

13. The vertical memory device of claim 10, further comprising a partitioning layer disposed between the charge trapping patterns.

14. A vertical memory device, comprising: A channel disposed on a substrate, the channel extending primarily in a first direction perpendicular to the upper surface of the substrate; A charge storage structure disposed on the outer wall of the channel, the charge storage structure comprising a tunnel insulating layer, a charge trapping pattern and a first blocking pattern sequentially stacked in a horizontal direction parallel to the upper surface of the substrate; A plurality of gate electrodes, the plurality of gate electrodes being spaced apart from each other in a first direction, each of the plurality of gate electrodes extending primarily in a second direction parallel to the upper surface of the substrate, so as to at least partially surround the charge storage structure; An insulating pattern is disposed between adjacent gate electrodes in the plurality of gate electrodes, the insulating pattern including an air gap disposed therein; A protective layer that at least partially covers the sidewall of each of the plurality of gate electrodes at its third-direction end, the third-direction being parallel to the upper surface of the substrate and intersecting the second direction; as well as The second blocking pattern at least partially covers the lower and upper surfaces of each of the plurality of gate electrodes, the sidewalls facing the charge storage structure, and the lower and upper surfaces of the protective layer. The protective layer includes silicon oxide. The charge storage structure includes charge trapping patterns spaced apart from each other in the first direction, each of the charge trapping patterns facing one of the plurality of gate electrodes in the horizontal direction. The insulating pattern, the protective layer, and the second blocking pattern are aligned with each other in the first direction at their third-direction ends.

15. The vertical memory device according to claim 14, wherein, The second blocking pattern comprises a metal oxide.

16. The vertical memory device according to claim 15, wherein, The second blocking pattern includes aluminum oxide or hafnium oxide.

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