Semiconductor device and method of manufacturing the same

Abstract

A semiconductor device and a method for manufacturing the same. In one embodiment, a device includes: a semiconductor substrate having a channel region; a gate stack above the channel region; and an epitaxial source / drain region adjacent to the gate stack, the epitaxial source / drain region including: a main portion in the semiconductor substrate, the main portion including a gallium-doped semiconductor material, a first concentration of gallium in the main portion being less than the solid solubility of gallium in the semiconductor material; and a terminal portion on the main portion, the terminal portion being doped with gallium, a second concentration of gallium in the terminal portion being greater than the solid solubility of gallium in the semiconductor material.

Description

Technical Field

[0001] This disclosure relates to a semiconductor device and a method for manufacturing the same. Background Art

[0002] Semiconductor devices are applied to various electronic products, such as personal computers, mobile phones, digital cameras, and other various electronic products. The method for manufacturing a semiconductor device generally deposits materials of an insulating layer or a dielectric layer, a conductive layer, and a semiconductor layer on a semiconductor substrate in sequence, and then uses a lithography technique to pattern each material layer to form electronic components and circuits on the material layers.

[0003] The semiconductor industry continuously improves the integration density of various electronic components (such as transistors, diodes, resistors, capacitors, etc.) by reducing the minimum feature size, so that more components can be integrated within a specified range. However, with the reduction of the feature size, the breakthrough of the performance of electronic components has also become a subject of great concern. Summary of the Invention

[0004] According to an embodiment of this disclosure, a semiconductor device includes a semiconductor substrate, a gate stack, and an epitaxial source / drain region. The semiconductor substrate has a channel region; the gate stack is located above the channel region; and the epitaxial source / drain region is adjacent to the gate stack. The epitaxial source / drain region includes: a main portion located in the semiconductor substrate, the main portion including a semiconductor material doped with gallium, and a first concentration of gallium in the main portion being less than the solid solubility of gallium in the semiconductor material; and a terminal portion located above the main portion, the terminal portion being doped with gallium, and a second concentration of gallium in the terminal portion being greater than the solid solubility of gallium in the semiconductor material.

[0005] According to an embodiment of this disclosure, a method for manufacturing a semiconductor device includes: forming a gate stack on a fin; etching the fin to form a recess adjacent to the gate stack in the fin; continuously dispensing an epitaxial precursor in a first growth stage to form a first portion of the epitaxial source / drain region in the recess, the epitaxial precursor including a semiconductor material precursor and a gallium precursor, and continuously dispensing the gallium precursor at a first flow rate in the first growth stage; and continuously dispensing the epitaxial precursor in a second growth stage to form a second portion above the first portion of the epitaxial source / drain region, and continuously dispensing the gallium precursor at a second flow rate in the second growth stage, the second flow rate being greater than the first flow rate.

[0006] According to an embodiment of the present disclosure, a method for manufacturing a semiconductor device includes: forming a gate stack on a fin; etching the fin to form a recess in the fin adjacent to the gate stack; dispensing a plurality of semiconductor material precursors to form a first epitaxial layer in the recess; after dispensing the semiconductor material precursors, dispensing a dopant precursor to form an impurity layer over the first epitaxial layer; after dispensing the dopant precursor, re-dispensing the semiconductor material precursors to form a second epitaxial layer over the impurity layer; and performing annealing to diffuse at least a portion of the impurity layer into the first and second epitaxial layers. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] One embodiment of the present disclosure is best understood from the following detailed description when read in conjunction with the accompanying drawings. It is emphasized that, in accordance with industry standard practice, the various features are not drawn to scale and are for illustrative purposes only. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

[0008] Figure 1 A perspective view of a fin field-effect transistor (FinFET) showing some embodiments;

[0009] Figure 2 and Figure 3 A perspective view of a FinFET in an intermediate stage of manufacturing showing some embodiments;

[0010] Figures 4A to 4C A cross-sectional view of a FinFET in a further intermediate stage of manufacturing showing some embodiments;

[0011] Figure 5A to FIG Figure 5F A cross-sectional view of a source / drain region showing various embodiments;

[0012] Figures 6A to 12B A cross-sectional view of a FinFET in a further intermediate stage of manufacturing showing some embodiments.

[0013] SYMBOL DESCRIPTION

[0014] 5: Region

[0015] 50: Substrate

[0016] 50N, 50P: Region

[0017] 52: Fin

[0018] 52R: Recess

[0019] 56: Shallow trench isolation region

[0020] 58: Channel region

[0021] 60: Pseudo gate dielectric

[0022] 62: Pseudo gate

[0023] 64: Mask

[0024] 66: Gate spacer

[0025] 68: Lightly doped source / drain (LDD) region

[0026] 70: Source / drain region

[0027] 72: Main layer

[0028] 74: Terminal layer

[0029] 76: Layer

[0030] 78M: Main layer

[0031] 78F: Terminal layer

[0032] 80: Impurity layer

[0033] 82: Terminal layer

[0034] 84, 84 A , 84 B : Superlattice structure, superlattice layer

[0035] 86, 86 A , 86 B : Terminal layer

[0036] 100: Contact etch stop layer (CESL)

[0037] 102: Interlayer dielectric layer, first interlayer dielectric (ILD) layer

[0038] 110: Metal gate

[0039] 112: Gate dielectric

[0040] 114: Gate

[0041] 120: Contact opening

[0042] 122: Silicide

[0043] 124: Lower source / drain contact

[0044] 130: Second interlayer dielectric (ILD) layer

[0045] 132: Gate mask

[0046] 134: Gate contact

[0047] 136: Upper source / drain contact

[0048] A - A: Cross - section

[0049] B / C - B / C: Cross - section Detailed implementation manners

[0050] The following disclosed embodiment content provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of elements and arrangements are described below to simplify the present case. Of course, these examples are only examples and are not intended to be limiting. For example, the form in which the first feature is above or on top of the second feature in the following description may include embodiments in which the first feature is in direct contact with the second feature, and may also include embodiments in which additional features may be formed between the first feature and the second feature so that the first feature and the second feature are not in direct contact. In addition, the present case may repeat element symbols and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself specify the relationship between the various embodiments and / or configurations discussed.

[0051] In addition, spatial relative terms such as "below", "beneath", "lower", "above", "upper", etc. may be used herein for the purpose of facilitating description to describe the relationship between one element or feature and another element or feature as shown in the drawings. Spatial relative terms are intended to cover different orientations of the device in use or operation in addition to the orientation shown in the drawings. The device may be oriented in other ways (rotated 90 degrees or in other orientations) and the spatial relative descriptive words used herein may be interpreted accordingly.

[0052] In some embodiments of the present disclosure, the epitaxial source / drain regions are doped with gallium impurities. It should be noted that in one embodiment of the present disclosure, the source and the drain can be used interchangeably and their structures are substantially the same. The source / drain regions have terminal portions in the main part. The terminal portions are doped with a higher concentration of gallium than the main part, and gallium segregation on the surface of the source / drain regions is avoided. Doping gallium in the terminal portions of the source / drain regions can reduce the impedance of the source / drain regions. Avoiding gallium segregation on the surface of the source / drain regions helps to avoid the removal of gallium in subsequent etching processes. In addition, doping gallium in the terminal portions of the source / drain regions can increase the amount of holes in the source / drain regions, which is particularly beneficial for specific types of source / drain regions, such as P - type source / drain regions. The performance of the source / drain regions can thus be improved.

[0053] Figure 1A simplified schematic diagram of a fin field-effect transistor (FinFET) is illustrated according to an embodiment of the present disclosure. Some other features of the FinFET are omitted for clarity of illustration (discussed below). The illustrated FinFET can be electrically connected or coupled in some manner for operation, such as a single transistor or multiple transistors (e.g., two transistors).

[0054] The fin field-effect transistor includes fins 52 extending from a substrate 50. Shallow trench isolation regions 56 are disposed on the substrate 50, and the fins 52 protrude above or between adjacent shallow trench isolation regions 56. Although the shallow trench isolation regions 56 are described / illustrated as being separated from the substrate 50, as used herein, the "substrate" can be used to refer to only a semiconductor substrate or a semiconductor substrate including isolation regions. Additionally, although the fins 52 are shown as being a single continuous material of the substrate 50, the fins 52 and / or the substrate 50 can include a single material or multiple materials. In this document, the fins 52 refer to the portions extending between adjacent shallow trench isolation regions 56.

[0055] A gate dielectric 112 is along the sidewalls and above the upper surface of the fins 52, and a gate 114 is above the gate dielectric 112. Source / drain regions 70 are disposed on opposite sides of the fins 52 relative to the gate 114 and the gate dielectric 112. Gate spacers 66 separate the source / drain regions 70 from the gate dielectric 112 and the gate 114. An interlayer dielectric layer 102 is disposed above the source / drain regions 70 and the shallow trench isolation regions 56. In an embodiment of forming multiple transistors, the source / drain regions 70 can be shared between the transistors. In an embodiment where one transistor is formed by multiple fins 52, adjacent source / drain regions 70 can be electrically connected to each other, such as by epitaxial growth to bond the source / drain regions 70, or through contacts to couple the source / drain regions 70 to the same source / drain.

[0056] Figure 1 Several reference cross-sections are further illustrated. Cross-section A-A is along the longitudinal axis direction of the fins 52, for example, the current flow direction of the FinFET between the source / drain regions 70. Cross-sections B / C-B / C are perpendicular to cross-section A-A and extend through the source / drain regions 70 of the FinFET. For clear illustration, subsequent figures all refer to these reference cross-sections.

[0057] Some embodiments discussed herein are FinFETs formed under a back-gate process. In other embodiments, a front-gate process can also be used. Moreover, some embodiments contemplate the use in planar devices, such as planar field-effect transistors (Planar FETs).

[0058] Figures 2 to 12B are various views at an intermediate stage of manufacturing a FinFET according to some embodiments of the present disclosure. Figure 2and Figure 3 are schematic diagrams. Figure 4A , Figure 6A , Figure 7A , Figure 8A , Figure 9A , Figure 10A , Figure 11A and Figure 12A are cross-sectional views taken along the reference section A-A in Figure 1 , except for the multiple fins / FinFETs. Figure 4B , Figure 4C , Figure 6B , Figure 7B , Figure 8B , Figure 9B , Figure 10B , Figure 11B and Figure 12B are cross-sectional views taken along the reference section B / C-B / C in Figure 1 , except for the multiple fins / FinFETs.

[0059] Figure 2 shows the substrate 50. The substrate 50 can be a semiconductor substrate such as a bulk semiconductor, a Semiconductor-on-insulator (SOI) substrate, or others, which can be doped (with P-type or N-type dopants) or undoped. The substrate 50 can be a wafer, such as a silicon wafer. Generally, an SOI substrate is a layer of semiconductor material formed on an insulating layer. The insulating layer can be a buried oxide (BOX) layer, a silicon oxide layer, and the like. The insulating layer is usually disposed on a silicon or glass substrate. Other types of substrates such as multi-layer substrates or sloped substrates are also used. In some embodiments, the semiconductor material of the substrate 50 can include silicon, germanium; compound semiconductors, including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors, including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; or combinations thereof. For example, when a P-type device is formed, the substrate 50 can be a strained material such as silicon germanium alloy (Si x Ge 1-x , where x is a value in the range from 0 to 1), which contains a germanium concentration in the range of about 0% to about 40% to form a FinFET with a p-type fully strained channel (PFSC).

[0060] The substrate 50 includes a region 50N and a region 50P. The region 50N can be used to form N-type components, such as NMOS transistors. The region 50P can be used to form P-type devices, such as PMOS transistors, such as P-type FinFETs. The region 50N can be physically separated from the region 50P, and any number of device features (e.g., other active devices, doped regions, isolation structures, etc.) can be disposed between the region 50N and the region 50P.

[0061] The fin 52 extends from the substrate 50. The fin 52 is a semiconductor strip. In some embodiments, the fin 52 can be formed by etching trenches in the substrate 50. The etching can be any suitable etching process, such as reactive ion etch (RIE), neutral beam etch (NBE), and the like, or a combination thereof. The etching can be anisotropic. After formation, the fin 52 has a width W1, and the fins 52 in the same region 50N / 50P are spaced apart by a pitch P1. The width W1 can be in the range of about 3 nm to about 30 nm. The pitch P1 can be in the range of about 20 nm to about 100 nm.

[0062] The fins can be formed in any suitable manner. For example, one or more photolithography processes can be used, including double patterning processes or multiple patterning processes. Generally, double patterning processes or multiple patterning processes combined with photolithography and self-alignment are more capable of patterning, such as achieving a pitch smaller than that obtained using a single direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over the substrate and patterned using a photolithography process. A spacer is formed adjacent to the patterned sacrificial layer using a self-alignment process. Then the sacrificial layer is removed, and the remaining spacer can be used to pattern the fins.

[0063] A shallow trench isolation (STI) region 56 is formed above the substrate 50 and between adjacent fins 52. An insulating material is formed over the intermediate structure as an example of the STI region 56. The insulating material can be an oxide such as silicon oxide, nitride, and the like or a combination thereof, and can be formed by high density plasma chemical vapor deposition (HDP-CVD) and flowable chemical vapor deposition (FCVD). (For example, CVD-based material deposition is performed in a remote plasma system and post-cured to transform it into another material such as an oxide) and the like or a combination thereof. Other insulating materials generated by any suitable method can be used. In the illustrated embodiment, the insulating material is silicon oxide formed by an FCVD process. Once the insulating material is formed, an annealing process can be performed. In one embodiment, the insulating material is such that excess insulating material covers the fins 52. Some embodiments can utilize multiple layers. For example, in some embodiments, a liner (not shown) can be formed first along the surfaces of the substrate 50 and the fins 52. Then, a filling material as described above is formed over the liner. A removal process is performed on the insulating material to remove the excess insulating material above the fins 52. In some embodiments, a planarization process such as chemical mechanical polishing (CMP), an etch-back process, and the like and combinations thereof can be utilized. The planarization process exposes the fins 52 such that the upper surfaces of the fins 52 and the insulating material are horizontal after the planarization process is completed. Then, the insulating material is recessed, and the remaining portion of the insulating material forms the STI region 56. The recessing of the insulating material causes the upper portions of the fins 52 in regions 50N and 50P to protrude from between adjacent STI regions 56. After the recessing, the exposed portions of the fins 52 extend a height H1 above the upper surface of the STI region 56. The height H1 is greater than about 40 nm, for example, in the range of about 50 nm to about 80 nm. The exposed portions of the fins 52 include portions that will become the channel regions of the resulting FinFETs.

[0064] In addition, the upper surface of the STI region 56 can have a flat surface, a convex surface, a concave surface (such as a recess) as shown, or a combination thereof. The upper surface of the STI region 56 can be formed flat, convex, and / or concave by appropriate etching. The STI region 56 can be made recessed using an acceptable etching process, such as an etching process selective to the material of the insulating material (e.g., etching the material of the insulating material at a faster rate than the material of the fins 52). For example, acids such as dilute hydrofluoric acid (dHF) can be used to remove chemical oxides through an appropriate etching process.

[0065] The above process is merely an example of how the fin 52 is formed. In some embodiments, the fin can be generated by an epitaxial growth process. For example, a dielectric layer can be formed over the upper surface of the substrate 50, and trenches can be etched through the dielectric layer to expose the underlying substrate 50. A homoepitaxial structure can be epitaxially grown in the trenches, and the dielectric layer can be recessed to cause the homoepitaxial structure to protrude from the dielectric layer to generate the fin. Additionally, in some embodiments, a heteroepitaxial structure can be used for the fin 52. For example, after planarizing the insulating material of the STI region 56 using the fin 52, the fin 52 can be recessed, and a material different from the fin 52 can be epitaxially grown on the recessed fin 52. In these embodiments, the fin 52 includes the recessed material and the epitaxially grown material disposed above the recessed material. In another embodiment, a dielectric layer can be formed over the upper surface of the substrate 50, and trenches can be etched through the dielectric layer. Then, a heteroepitaxial structure can be epitaxially grown in the trenches using a material different from the substrate 50, and the dielectric layer can be recessed such that the heteroepitaxial structure protrudes from the dielectric layer to form the fin 52. In some embodiments of homoepitaxial or heteroepitaxial structure epitaxial growth, although in-situ and implant doping can be used together, the epitaxially grown material can be in-situ doped during growth, which can eliminate prior and subsequent implants.

[0066] Further, it may be advantageous to epitaxially grow a material different from that in the region 50P (e.g., PMOS region) in the region 50N (e.g., NMOS region). In various embodiments, the upper portion of the fin 52 can be generated from silicon germanium (Si x Ge 1-x , where x can range from 0 to 1), silicon carbide, pure or substantially pure germanium, III-V compound semiconductors, II-VI compound semiconductors, or the like. For example, available materials for generating III-V compound semiconductors include, but are not limited to, InAs, AlAs, GaAs, InP, GaN, InGaAs, InAlAs, GaSb, AlSb, AlP, GaP, and the like.

[0067] Moreover, appropriate wells (not shown) can be formed in the fin 52 and / or the substrate 50. In some embodiments, a P well can be formed in the region 50N, and an N well can be formed in the region 50P. In some embodiments, a P well or an N well is formed in both the region 50N and the region 50P.

[0068] In embodiments having different well types, a photoresist or other photomask (not shown) may be used to implement different implantation steps for regions 50N and 50P. For example, a photoresist may be formed over fins 52 and STI region 56 in region 50N. The photoresist is patterned to expose region 50P of substrate 50, such as a PMOS region. The photoresist may be formed by using a spin-on technique, and the photoresist may be patterned using acceptable photolithography techniques. Once the photoresist is patterned, an n-type impurity implantation is performed in region 50P, and the photoresist may be used as a mask to substantially prevent the n-type impurity from being implanted into region 50N such as an NMOS region. The n-type impurity may be phosphorus, arsenic, antimony, and the like implanted into the region, and its concentration is equal to or less than 10 18 cm -3 , for example, between about 10 17 cm -3 and about 10 18 cm -3 . After implantation, the photoresist is removed, for example, by a suitable ashing process.

[0069] After implanting region 50P, a photoresist is formed over fins 52 and STI region 56 in region 50P. The photoresist is patterned to expose region 50N of substrate 50, such as an NMOS region. The photoresist may be generated by a spin-on technique and patterned using suitable photolithography techniques. Once the photoresist is patterned, a p-type impurity implantation may be performed in region 50N, and the photoresist may be used as a photomask to substantially prevent the p-type impurity from being implanted into region 50P such as a PMOS region. The p-type impurity may be boron, BF2, indium, or the like implanted into the region, and its concentration is equal to or less than 10 18 cm -3 , for example, between about 10 17 cm -3 and about 10 18 cm -3 . After implantation, the photoresist may be removed by a suitable ashing process such as.

[0070] After implantation of regions 50N and 50P, annealing may be performed to activate the implanted p-type and / or n-type impurities. In some embodiments, the growth material of the epitaxial fins may be in-situ doped during growth, which may eliminate the implantation, even though in-situ and implantation doping may be used together.

[0071] In Figure 3In [the figure], a dummy gate dielectric 60 is formed above the fin 52, and a dummy gate 62 is formed above the dummy gate dielectric 60. The dummy gate dielectric 60 and the dummy gate 62 can be collectively referred to as a "dummy gate stack", each is called a "dummy gate stack", and each dummy gate stack includes the dummy gate dielectric 60 and the dummy gate 62. The dummy gate stack extends along the sidewalls of the fin 52. Although only one dummy gate stack is shown, it should be understood that multiple dummy gate stacks are formed simultaneously, and each fin 52 can have multiple dummy gate stacks formed thereon.

[0072] As an example of forming the dummy gate dielectric 60 and the dummy gate 62, a dummy dielectric layer is formed on the fin 52. The dummy dielectric layer can be, for example, silicon oxide, silicon nitride, and their combinations or the like, and can be deposited or thermally grown according to suitable techniques. A dummy gate layer is formed above the dummy dielectric layer, and a mask layer is formed above the dummy gate layer. The dummy gate layer can be deposited above the dummy dielectric layer and then planarized, for example, by chemical mechanical polish (CMP). The mask layer can be deposited above the dummy gate layer. The dummy gate layer can be a conductor material or a non-conductor material and can be selected from amorphous silicon, polysilicon, poly-SiGe, metal nitride, metal silicide, metal oxide, and metal. The dummy gate layer can be deposited by physical vapor deposition (PVD), CVD, sputtering deposition, or other techniques known in the art and used for depositing conductive materials. The dummy gate layer can be made of other materials that have a high etch selectivity for etching the isolation region. The mask layer can include, for example, silicon nitride, silicon oxynitride, or the like. In this example, a single dummy gate layer and a single mask layer are formed on the regions 50N and 50P. It should be noted that the shown dummy dielectric layer only covers the fin 52 and is for illustrative purposes only. In some embodiments, the dummy dielectric layer can be deposited such that the dummy dielectric layer covers the STI region 56, which extends between the dummy gate layer and the STI region 56. Then, the mask layer is patterned using suitable lithography and etching techniques to form a mask 64. Next, the pattern of the mask 64 is transferred to the dummy gate layer by suitable etching techniques to form the dummy gate 62. The pattern of the mask 64 is further transferred to the dummy dielectric layer to form the dummy gate dielectric 60. The dummy gate 62 covers the respective channel regions 58 of the fin 52. The pattern of the mask 64 can be used to physically separate each dummy gate 62 from adjacent dummy gates. The dummy gate 62 can also have a length direction that is generally perpendicular to the length direction of the respective fins 52.

[0073] In Figure 4A and Figure 4BIn this case, a gate spacer 66 is formed on the exposed surfaces of the dummy gate 62, the mask 64, and / or the fin 52. The gate spacer 66 can be formed by conformally depositing an insulating material and then etching the insulating material. The insulating material of the gate spacer 66 can be silicon nitride, silicon oxide, silicon carbonitride, silicon oxycarbide, and combinations thereof, etc. In some embodiments (not shown), the gate spacer 66 is formed of a multi-layer insulating material and includes multiple layers. For example, the gate spacer 66 can include a silicon oxide layer disposed between two layers of silicon nitride, or can include multiple layers of silicon oxycarbide nitride. After etching, the gate spacer 66 can have a curved sidewall (as Figure 4A shown) or can have a straight sidewall (not shown).

[0074] Before or between the formation of the gate spacer 66, implantation for the lightly doped source / drain (LDD) region 68 can be performed. In embodiments with different device types, similar to the implantations discussed, a mask, such as a photoresist, can be formed over the region 50N while exposing the region 50P, and an appropriate type (e.g., p-type) of impurity can be implanted into the exposed fins 52 in the region 50P. Subsequently, the mask can be removed. Then, a mask, such as a photoresist, can be formed over the region 50P while exposing the region 50N, and an appropriate type of impurity (e.g., n-type) can be implanted into the exposed fins 52 in the region 50N. Subsequently, the mask can be removed. The n-type impurity can be any of the n-type impurities discussed previously, and the p-type impurity can be any of the p-type impurities discussed previously. The LDD region 68 can have an impurity concentration of about 10 15 cm -3 to about 10 16 cm -3 . Annealing can be used to activate the implanted impurities. The LDD region 68 is adjacent to the channel region 58.

[0075] Then, an epitaxial source / drain region 70 is formed in the fin 52 to apply stress in the channel region 58, thereby improving performance. In some embodiments, the epitaxial source / drain region 70 can extend into the LDD region 68 and / or the fin 52 and can also penetrate the LDD region 68 and / or the fin 52. In some embodiments, the gate spacer 66 is used to separate the epitaxial source / drain region 70 from the dummy gate 62 by an appropriate lateral distance such that the epitaxial source / drain region 70 does not short-circuit the gate of the subsequently formed FinFET.

[0076] The epitaxial source / drain region 70 in region 50N (such as an NMOS region) can be formed by covering region 50P (such as a PMOS region), and etching the source / drain region of fin 52 in region 50N to form a recess 52R in fin 52. Then, the epitaxial source / drain region 70 in region 50N is epitaxially grown in recess 52R. The epitaxial source / drain region 70 can include any suitable material, such as being suitable for an n-type FinFET. For example, if fin 52 is silicon, the epitaxial source / drain region 70 in region 50N can include a material that applies tensile strain in channel region 58, such as silicon, silicon carbide, phosphorus-doped silicon carbide, silicon phosphide, or silicon and the like. The epitaxial source / drain region 70 in region 50N can have a surface that protrudes from the corresponding surface of fin 52 and can have facets.

[0077] The epitaxial source / drain region 70 in region 50N (such as a PMOS region) can be formed by covering region 50P (such as a PMOS region), and etching the source / drain region of fin 52 in region 50N to form a recess 52R in fin 52. Then, the epitaxial source / drain region 70 in region 50N is epitaxially grown in recess 52R. The epitaxial source / drain region 70 can include any suitable material, such as being suitable for a p-type FinFET. For example, if fin 52 is silicon, the epitaxial source / drain region 70 in region 50P can include a material that applies compressive strain in channel region 58, such as silicon germanium, germanium, germanium tin, and the like. The epitaxial source / drain region 70 in region 50P can have a surface that protrudes from the corresponding surface of fin 52 and can have facets.

[0078] The epitaxial source / drain region 70 and / or fin 52 can be doped with impurities to form the source / drain region, similar to the process for forming a lightly doped source / drain region discussed previously. The impurity concentration of the source / drain region can be between approximately 10 19 cm -3 and approximately 10 21 cm -3 . The n-type and / or p-type impurities for the source / drain region can be any of the impurities discussed previously. During growth, the epitaxial source / drain region 70 is doped in-situ. Doping during growth instead of by implantation can avoid stress relaxation in channel region 58 during dopant implantation. Thereby, the performance of the resulting FinFET can be improved.

[0079] In some embodiments, the epitaxial source / drain region 70 is doped with an impurity, which helps to reduce the contact resistance with the epitaxial source / drain region 70. In some embodiments, the impurity is gallium. In some examples, gallium can have advantageous aspects. For example, the solid solubility of gallium in germanium is higher than that of other impurities such as boron. Therefore, when the germanium content in the epitaxial source / drain region 70 is high, such as when forming a p-type epitaxial source / drain region 70, gallium can have a higher dopant activation, and thus, compared with other dopants, gallium contributes more holes. This helps to reduce the contact resistance when gallium is concentrated near the contact region of the epitaxial source / drain region 70.

[0080] The bond energy between gallium and germanium is low, and thus, gallium is prone to segregate to the surface of the epitaxial source / drain region 70 containing germanium. According to some embodiments, the epitaxial source / drain region 70 is grown in a manner that reduces the amount of gallium segregation and / or mitigates the effect of gallium segregation. After formation, the epitaxial source / drain region 70 has a large dopant concentration near the surface of the epitaxial source / drain region 70, but the dopants are not completely segregated to the surface of the epitaxial source / drain region 70. As further discussed below, a region extending from about 2 nm to about 12 nm below the upper surface of the epitaxial source / drain region 70 can be highly doped with gallium. In addition, as further discussed below, the epitaxial source / drain region 70 can be co-doped with multiple impurities, such as gallium and boron.

[0081] As a result of the epitaxial process for forming the epitaxial source / drain region 70 in the regions 50N and 50P, the upper surface of the epitaxial source / drain region 70 has facets that extend laterally outward beyond the sidewalls of the fin 52. In some embodiments, these facets cause adjacent epitaxial source / drain regions 70 of the same FinFET to merge, as Figure 4B shown. In other embodiments, as Figure 4C shown, after the epitaxial process is completed, the adjacent epitaxial source / drain regions 70 remain separated. The segregation of dopants can depend on the epitaxial growth direction of the epitaxial source / drain region 70. Dopant segregation can occur at different rates along different crystal directions, depending on the dopant and the substrate semiconductor material. For example, when growing silicon germanium doped with gallium, gallium has a greater segregation driving force and a greater activation energy along the <111> direction compared with along the <100> direction. As Figure 4B and Figure 4CAs shown, forming the epitaxial source / drain region 70 with a faceted surface can help reduce gallium segregation at the surface of the epitaxial source / drain region 70. During epitaxial growth, growth conditions can be selected to favor growth along the <111> direction and promote the formation of the epitaxial source / drain region 70 with multiple faceted facets. For example, growth along the <111> direction can be promoted by growing at a high temperature such as at least about 550 °C and by growing at a low pressure, like a low pressure in the range of about 10 Torr to about 300 Torr.

[0082] In Figure 4B and Figure 4C In the illustrated embodiment, a gate spacer 66 is formed that covers a portion of the sidewall of the fin 52 that extends over the STI region 56, thereby preventing epitaxial growth. In some other embodiments, the spacer etch used to form the gate spacer 66 can be adjusted to remove spacer material to allow the region for epitaxial growth to extend to the surface of the STI region 56.

[0083] Figures 5A to 5F Epitaxial source / drain regions 70 according to various embodiments are shown. Specifically, region 5 from Figure 4A is shown in more detail. Figures 5A to 5F Each of

[0084] Figure 5A illustrates an epitaxial source / drain region 70 according to one embodiment. However, it should be understood that the FinFET can be formed with some, all, or none of the features from the illustrated embodiments. The illustrated epitaxial source / drain regions 70 are formed of a material suitable for a p-type FinFET as described above and can be formed in the region 50P. Each of the illustrated epitaxial source / drain regions 70 has a main portion and a terminal portion above the main portion, and the terminal portion is highly doped.

[0085] ​From the upper surface to the lower surface of the main layer 72, the main layer 72 has a constant dopant concentration. The dopant concentration in the main layer 72 is low. Specifically, the dopant concentration in the main layer 72 is less than the solid solubility of the dopant in the base semiconductor material of the epitaxial source / drain region 70. The solid solubility of gallium in silicon-germanium depends on temperature and the exact ratio of silicon to germanium, but is typically in the range of about 3×10 20 cm -3 to about 5×10 20 cm -3 Therefore, when the epitaxial source / drain region 70 is gallium-doped silicon-germanium, the gallium concentration in the main layer 72 can be in the range of about 2×10 20 cm -3 to about 3×10 20 cm -3 For example, when the solid solubility of gallium in the base semiconductor material of the epitaxial source / drain region 70 is about 3×10 20 cm -3 the gallium concentration in the main layer 72 can be about 2×10 20 cm -3 . The main layer 72 can have a relatively large thickness, for example, a thickness in the range of about 14 nm to about 16 nm. Forming the main layer 72 with a dopant concentration less than the solid solubility of the dopant helps to reduce the segregation of the dopant to the surface of the epitaxial source / drain region 70, especially when the main layer 72 has a relatively large thickness.

[0086] The terminal layer 74 has a constant dopant concentration from the upper surface to the lower surface of the terminal layer 74. The dopant concentration in the terminal layer 74 is high. Specifically, the dopant concentration in the terminal layer 74 is greater than the solid solubility of the dopant in the base semiconductor material of the epitaxial source / drain region 70. When the epitaxial source / drain region 70 is gallium-doped silicon-germanium, the gallium concentration in the doped region can be in the range of about 5×10 20 cm -3 to about 6×10 20 cm -3 For example, when the solid solubility of gallium in the base semiconductor material of the epitaxial source / drain region 70 is about 3×10 20 cm -3 and the gallium concentration in the main layer 72 is about 2×10 20 cm -3 the gallium concentration in the terminal layer 74 can be about 6×10 20 cm -3。The terminal layer 74 can have a small thickness, such as a thickness in the range of about 2 nm to about 12 nm. Specifically, the thickness of the terminal layer 74 is less than the thickness of the main layer 72. Forming the terminal layer 74 with a smaller thickness helps to reduce the segregation of dopants to the surface of the epitaxial source / drain region 70, especially when the terminal layer 74 has a high dopant concentration. Forming the terminal layer 74 with a smaller thickness can also help to reduce the effect of dopant segregation. For example, when the terminal layer 74 is very thin, the segregated dopants can still be close enough to the bulk of the terminal layer 74 so that they contribute to the doping of the terminal layer 74.

[0087] By forming the epitaxial source / drain region 70 with the main layer 72 and the terminal layer 74, the resulting epitaxial source / drain region 70 has a large dopant concentration near the surface of the epitaxial source / drain region 70, but the dopants are not segregated to the surface of the epitaxial source / drain region 70. In this way, even after an etching process such as a contact opening etching process (discussed further below) is performed on the epitaxial source / drain region 70, the epitaxial source / drain region 70 can still have a large dopant concentration near the surface of the epitaxial source / drain region 70.

[0088] As an example of forming the main layer 72 and the terminal layer 74, an epitaxial growth process can be performed in which the intermediate structure is exposed to several precursors. The precursors include precursors of various semiconductor materials and one or more dopant precursors. The semiconductor material precursors are precursors for depositing the substrate semiconductor material, such as silicon germanium, germanium, germanium tin, and the like. For example, in an embodiment where the substrate semiconductor material is silicon germanium, the semiconductor material precursors can include a silicon precursor (such as silane (SiH4), trisilane (Si3H8), etc.) and a germanium precursor (such as germane (GeH4), etc.). The dopant precursors are any precursors of the desired dopants, such as gallium, boron, or a combination thereof. In an embodiment where the epitaxial source / drain region 70 is doped with gallium, the dopant precursors can include trimethylgallium (Ga(CH3)3), triethylgallium (Ga(C2H5)3), gallium chloride (such as GaCl, GaCl3, etc.), or the like. The precursors of gallium can include carbon or be carbon-free. In an embodiment where the epitaxial source / drain region 70 is also doped with boron, the dopant precursors can further include diborane (B2H6) or the like. During the epitaxial growth process, the intermediate structure is simultaneously exposed to the semiconductor material precursors and the dopant precursors. When growing the main layer 72 and the terminal layer 74, the flow rate ratio of the precursors can be adjusted. Specifically, when growing the main layer 72, the dopant precursors can flow at a low flow rate, while when growing the terminal layer 74, they can flow at a high flow rate. For example, when growing the main layer 72, the silicon precursor can flow at a rate ranging from about 20 sccm to about 100 sccm, the germanium precursor can flow at a rate ranging from about 50 sccm to about 500 sccm, and the gallium precursor can flow at a rate ranging from about 20 sccm to about 100 sccm. Similarly, when growing the terminal layer 74, the silicon precursor can flow at a rate ranging from about 20 sccm to about 100 sccm, the germanium precursor can flow at a rate ranging from about 50 sccm to about 500 sccm, and the gallium precursor can flow at a rate ranging from about 20 sccm to about 100 sccm. The main layer 72 and the terminal layer 74 can be formed in situ in the same processing chamber, for example, without breaking the vacuum, and the flow rates of various precursors can be adjusted during growth to produce the desired regions.

[0089] Figure 5BShows an epitaxial source / drain region 70 including a single layer 76. The layer 76 is formed of a substrate semiconductor material such as silicon germanium, germanium, germanium tin, etc. The layer 76 also has a graded impurity concentration. Specifically, the dopant concentration of the layer 76 continuously increases along the direction D1, for example, in the direction extending from the lower surface of the layer 76 to the upper surface of the layer 76. At the lower surface of the layer 76, the dopant concentration is less than the solid solubility of the dopant in the substrate semiconductor material (as described above). At the upper surface of the layer 76, the dopant concentration is greater than the solid solubility of the dopant in the substrate semiconductor material. Continuing with the example where the epitaxial source / drain region 70 is gallium-doped silicon germanium, the dopant concentration at the lower surface of the layer 76 can be in the range of about 3×10 20 cm -3 to about 5×10 20 cm -3 and the dopant concentration at the upper surface of the layer 76 can be in the range of about 5×10 20 cm -3 to about 6×10 20 cm -3 range.

[0090] As an example of generating the layer 76, an epitaxial growth process can be performed, in which the intermediate structure is exposed to several precursors. The precursors include a variety of semiconductor material precursors and one or more dopant precursors. The semiconductor material precursor is a precursor for depositing the substrate semiconductor material, such as silicon germanium, germanium, germanium tin, or the like, and can be a semiconductor material precursor similar to the above. The dopant precursor is any precursor of the desired dopant and can be a dopant precursor similar to those discussed above. During the epitaxial growth process, the intermediate structure is simultaneously exposed to the semiconductor material precursor and the dopant precursor. When growing the layer 76, the flow rate ratio of the precursors can be adjusted. Specifically, when forming the lower part of the layer 76, the dopant precursor can flow at a low flow rate, and when forming the upper part of the layer 76, it can flow at a high flow rate. For example, the gallium precursor can flow at a rate in the range of about 20 sccm to about 100 sccm at the start of growth and can continuously increase to flow at a higher rate in the range of about 20 sccm to about 100 sccm, 100 sccm at the end of growth. The flow rates of various precursors can be continuously adjusted during growth to form the layer 76 with a desired doping concentration.

[0091] Figure 5CThe epitaxial source / drain region 70 is illustrated, which includes a main layer 78M, a terminal layer 78F, and an impurity layer 80. Both the main layer 78M and the terminal layer 78F are formed of a base semiconductor material such as silicon germanium, germanium, germanium tin, etc., and are doped to the same impurity concentration. The impurity layer 80 can be a substantially pure impurity layer, and both the main layer 78M and the terminal layer 78F are doped with impurities. Continuing with the above example, the main layer 78M and the terminal layer 78F can each be gallium-doped silicon germanium, and the impurity layer 80 can be a substantially pure gallium layer.

[0092] The main layer 78M and the terminal layer 78F are formed to have the same low dopant concentration. Specifically, the dopant concentration in the main layer 78M and the terminal layer 78F is less than the solid solubility of the dopant in the base semiconductor material of the epitaxial source / drain region 70 (as described above). For example, when the epitaxial source / drain region 70 is gallium-doped silicon germanium, the gallium concentration in the main layer 78M and the terminal layer 78F can be in the range of about 2×10 20 cm -3 to about 3×10 20 cm -3 The main layer 78M can have a relatively large thickness, for example, a thickness in the range of about 14 nm to about 16 nm. The terminal layer 78F can have a small thickness, for example, a thickness in the range of about 1 nm to about 2 nm.

[0093] The impurity layer 80 is a layer with substantially pure dopants, such as gallium. The epitaxial source / drain region 70 includes alternating layers of the impurity layer 80 and the terminal layer 78F. For example, the epitaxial source / drain region 70 can include three terminal layers 78F and three impurity layers 80. The impurity layer 80 can be very thin. In some embodiments, the impurity layer 80 is one monolayer thick.

[0094] As an example of forming each layer, multiple epitaxial growth processes can be performed to form the main layer 78M and the terminal layer 78F, where the intermediate structure is exposed to several precursors. Between each epitaxial growth process, a deposition process is performed to form the impurity layer 80. The main layer 78M and the terminal layer 78F can be formed by an epitaxial growth process using precursors similar to those discussed above with respect to Figure 5A Each impurity layer 80 can be formed on the exposed surface of the corresponding underlying layer (e.g., the main layer 78M or the terminal layer 78F) by a delta-type impurity doping process. The delta-type impurity doping can be achieved, for example, by flowing the dopant precursor without flowing the semiconductor material precursor after stopping the flow of the semiconductor material precursor. In some embodiments, the dopant precursor is, for example, gallium chloride (GaCl3). Gallium chloride can form a self-limiting gallium monolayer on the exposed surface of the corresponding underlying layer. The gallium monolayer ends with chlorine. The delta-type impurity doping can be performed to the desired surface concentration. In some embodiments, for about 10 13 cm-2 Perform Delta-type impurity doping with a surface concentration of an order of magnitude. Then, a reducing agent such as silane (SiH4) or germane (GeH4) can be flowed to remove chlorine, and then an epitaxial growth process similar to the above can be performed to form the next terminal layer 78F. In some embodiments, the reduction step and the subsequent epitaxial growth can be combined. For example, the reducing agent can flow as part of the epitaxial growth process for forming the next terminal layer 78F.

[0095] After forming the various layers discussed above, annealing can be selectively performed. The resulting annealed structure is as Figure 5D shown. Annealing diffuses some or all of the impurity layer 80 into the top of the surrounding terminal layer 78F and main layer 78M, thereby forming a doped terminal layer 82. Each doped terminal layer 82 can have the same dopant concentration, which can be greater than the solid solubility of the dopant in the substrate semiconductor material of the epitaxial source / drain region 70. Thus, the upper part of the epitaxial source / drain region 70 has a large dopant concentration near the surface of the epitaxial source / drain region 70 without segregating the dopant to the surface of the epitaxial source / drain region 70. After annealing, each doped terminal layer 82 can have the same crystal structure.

[0096] Figure 5E Illustrates an epitaxial source / drain region 70 similar to the embodiment of Figure 5A , except that the terminal layer 74 is replaced with an equivalent superlattice structure 84. The superlattice structure 84 can be similar to the terminal layer 74 in terms of electrical function and have the same energy band structure as the terminal layer 74. However, instead of a single continuous layer, the superlattice structure 84 is formed by multiple alternating superlattice layers 84 A and 84 B . The main layer 72 and the superlattice layers 84 A and 84 B are formed by an epitaxial growth process using precursors similar to those discussed above with respect to Figure 5A , but the main layer 72 and the superlattice layers 84 A and 84 B can be formed from different substrate semiconductor materials doped with the same impurity. The main layer 72 and the superlattice layers 84 A and 84 B are doped to different impurity concentrations. Specifically, the dopant concentration of each superlattice layer 84 A and 84 B is greater than the dopant concentration of the main layer 72.

[0097] The superlattice layers 84 A and 84 B include semiconductor materials having different bandgaps. Continuing with the example of the epitaxial source / drain region 70 being silicon germanium doped with gallium, the superlattice layer 84A It can be silicon doped with gallium, and the superlattice layer 84 B can be germanium doped with gallium. The dopant concentration in each of the superlattice layers 84 A and 84 B is large. Specifically, the dopant concentration in each superlattice layer 84 A and 84 B is greater than the solid solubility of the dopant in the substrate semiconductor material of the main layer 72 (as described above). In this way, when the epitaxial source / drain region 70 is silicon germanium doped with gallium, the gallium concentration in the superlattice layers 84 A and 84 B can be in the range of about 5×10 20 cm -3 to about 6×10 20 cm -3 . The superlattice layers 84 A and 84 B can have a small thickness, for example, a thickness in the range of about 1 nm to about 2 nm.

[0098] Forming the superlattice layers 84 A and 84 B from alternating substrate semiconductor materials can help reduce the segregation of dopants to the surface of the epitaxial source / drain region 70. In some embodiments, the superlattice layer 84 A is formed of a semiconductor material having a high bonding energy for the dopant, and the superlattice layer 84 B is formed of a semiconductor material having a low bonding energy for the dopant. For example, the binding energy of gallium with silicon (about 4.56 eV) is greater than the binding energy of gallium with germanium (about 2.56 eV). When the superlattice layer 84 A is silicon doped with gallium and the superlattice layer 84 B is germanium doped with gallium, the superlattice layer 84 A serves as an isolation stop layer, thereby preventing gallium that attempts to segregate to the surface of the epitaxial source / drain region 70. Therefore, the superlattice layer 84 A can be doped to a higher concentration than the superlattice layer 84 B , and gallium segregation from the superlattice layer 84 A can be avoided.

[0099] Figure 5F Shows an epitaxial source / drain region 70 similar to the embodiment of Figure 5A , except that the terminal layer 74 is replaced by a plurality of alternating terminal layers 84 A and 84 B . The main layer 72 and the terminal layers 86 A and 86 BFormed from the same base semiconductor material, such as silicon germanium, germanium, germanium tin, etc. However, the main layer 72 and the terminal layer 86 A and 86 B Are doped to different impurity concentrations. Specifically, the terminal layer 86 A and 86 B Has a higher dopant concentration than the main layer 72.

[0100] The terminal layer 86 A and 86 B Comprise the same semiconductor material and are doped to the same impurity concentration. Continuing with the example where the epitaxial source / drain region 70 is gallium-doped silicon germanium, the terminal layer 86 A and 86 B Can each be gallium-doped silicon germanium. The dopant concentration in each of the terminal layers 86 A and 86 B Is high. Specifically, the dopant concentration in each terminal layer 86 A and 86 B Is greater than the solid solubility of the dopants in the base semiconductor material of the epitaxial source / drain region 70 (as described above). In this way, when the epitaxial source / drain region 70 is gallium-doped silicon germanium, the gallium concentration in the terminal layers 86 A and 86 B Can be in the range of about 5×10 20 cm -3 To about 6×10 20 cm -3 The terminal layers 86 A and 86 B Can have a small thickness, such as a thickness in the range of about 1 nm to about 2 nm.

[0101] The main layer 72 and the terminal layers 86 Figure 5A Can be formed by an epitaxial growth process using precursors similar to those discussed above with respect to A and 86 B . However, for the terminal layers 86 A and 86 B , the epitaxial growth rate can be different. The epitaxial growth rate of the terminal layers 86 A and 86 B Affects the amount of dopant segregation during growth and also affects the quality of the epitaxial growth. Growing the terminal layer 86 A At a high epitaxial growth rate helps to reduce the segregation of dopants to the surface of the epitaxial source / drain region 70. In this way, the terminal layer 86 B Can have fewer crystal defects than the terminal layer 86 A , and the terminal layers 86 A and 86B It can have different crystal structures.

[0102] The growth rate of the terminal layer 86 can be controlled by controlling the environmental conditions in the epitaxial growth process. A and 86 B Specifically, the temperature during the epitaxial growth process affects the epitaxial growth rate, and a lower temperature results in a higher growth rate. Thus, in some embodiments, the terminal layer 86 A is grown at a low temperature, and the terminal layer 86 B is grown at a high temperature. For example, the terminal layer 86 A can be grown in a temperature range of about 300 °C to about 420 °C, and the terminal layer 86 B can be grown in a temperature range of about 500 °C to about 800 °C. Growing the terminal layer 86 B at a temperature lower than that of the terminal layer 86 A results in the terminal layer 86 A having a higher activation energy than the terminal layer 86 B , which creates a high potential barrier and thus reduces dopant segregation in the terminal layer 86 A . When the terminal layer 86 A has a high activation energy, the finishing layer 86 A serves as a segregation stop layer, thereby preventing gallium from segregating toward the surface of the epitaxial source / drain region 70.

[0103] Regarding Figures 5A to 5F the epitaxial source / drain region 70 described is described as having gallium impurities. In some embodiments, the epitaxial source / drain region 70 is co-doped with multiple impurities. Specifically, in addition to gallium, the epitaxial source / drain region 70 can be further doped with boron. For example, the main layer 72 and the terminal layer 74 (see Figure 5A ), the layer 76 (see Figure 5B ), the main layer 78M and the terminal layer 78F (see Figure 5C ), the main layer 72, and the superlattice layers 86 A and 84 B (see Figure 5E ), and / or the main layer 72 and the terminal layers 86 A and 86 B (see Figure 5F ) can be further doped with boron. The layer can be boron-doped to about 2×10 20 cm -3 to about 1×10 21 cm -3Concentration. The co-doped epitaxial source / drain region 70 can help ensure sufficient doping throughout the epitaxial source / drain region 70, even in the event of some gallium segregation. In some embodiments, the concentration of gallium is less than the boron concentration in the main layer 72 (see Figure 5A and Figure 5E and Figure 5F ) and / or the main layer 78M (see Figure 5C and Figure 5D ), and the concentration of gallium is greater than the boron concentration in the terminal layer 74 (see Figure 5A ), the terminal layer 82 (see Figure 5D ), the superlattice layers 84 A and 84 B (see Figure 5E ) and the terminal layer 86 A and 86 B (see Figure 5F ).

[0104] In Figure 6A and Figure 6B , a first ILD (Inter-layer dielectric) layer 102 is deposited over the intermediate structure. The first ILD layer 102 can be formed of a dielectric material and can be deposited by any suitable method such as CVD, plasma enhanced CVD (PECVD) or FCVD. The dielectric material can include phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG) or the like. Other insulating materials can be formed using any suitable process. In some embodiments, a contact etch stop layer (CESL) 100 is disposed between the first ILD layer 102 and the epitaxial source / drain region 70, the mask 64 and the gate spacer 66. The CESL 100 can include a dielectric material having an etch rate different from that of the material of the first ILD layer 102, such as silicon nitride, silicon oxide, silicon oxynitride or the like.

[0105] In Figure 7A and Figure 7B , a planarization process such as CMP can be performed to planarize the upper surface of the first ILD layer 102 with the upper surface of the dummy gate 62 or the mask 64. The planarization process can also remove the mask 64 on the dummy gate 62 and a portion of the gate spacer 66 along the sidewalls of the mask 64. After the planarization process, the upper surfaces of the dummy gate 62, the gate spacer 66 and the first ILD layer 102 are horizontal. Accordingly, the upper surface of the dummy gate 62 is exposed through the first ILD layer 102. In some embodiments, the mask 64 can be retained, in which case the planarization process levels the upper surface of the first ILD layer 102 with the upper surface of the mask 64.

[0106] InFigure 8A and Figure 8BIn [the figure], the dummy gate 62 is removed and replaced by a metal gate 110. The metal gate 110 includes a gate dielectric 112 and a gate 114. As an example of forming the metal gate 110, the dummy gate 62 and the photomask 64 (if any) are removed in one or more etching steps, thereby forming a recess. The portion of the dummy gate dielectric 60 in the recess may also be removed. In some embodiments, only the dummy gate 62 is removed and the dummy gate dielectric 60 is retained and exposed by the recess. In some embodiments, the dummy gate dielectric 60 is removed from the recess in the first region (e.g., the core logic region) of the die and retained in the recess in the second region (e.g., the input / output region) of the die. In some embodiments, the dummy gate 62 is removed by an anisotropic dry etching process. For example, the etching process may include a dry etching process using a reactive gas that selectively etches the dummy gate 62 without etching the first ILD layer 102 or the gate spacer 66. The recess exposes the fins 52. Specifically, the channel region 58 is exposed by the recess. Each channel region 58 is disposed between adjacent pairs of the epitaxial source / drain regions 70. During the removal, the dummy gate dielectric 60 may be used as an etch stop layer when etching the dummy gate 62. The dummy gate dielectric 60 may then be selectively removed after removing the dummy gate 62. After the removal, the gate dielectric 112 is conformally deposited in the recess, such as on the top surface and sidewalls of the fins 52 and on the sidewalls of the gate spacer 66. The gate dielectric 112 may also be formed over the top surface of the first ILD layer 102. According to some embodiments, the gate dielectric 112 includes silicon oxide, silicon nitride, or a multi-layer thereof. In some embodiments, the gate dielectric 112 includes a high-k dielectric material, and in these embodiments, the gate dielectric 112 may have a k value greater than about 7.0 and may include a metal oxide or a silicate of Hf, Al, Zr, La, Mg, Ba, Ti, Pb, and combinations thereof. The method of forming the gate dielectric 112 may include molecular beam deposition (MBD), atomic layer deposition (ALD), PECVD, and the like. In embodiments where a portion of the dummy gate dielectric 60 remains in the recess, the gate dielectric 112 includes the material of the dummy gate dielectric 60 (e.g., SiO2). The gate 114 is deposited on the gate dielectric 112 respectively and fills the remaining portion of the recess. The gate 114 may include a metal-containing material such as TiN, TiO, TaN, TaC, Co, Ru, Al, W, and combinations thereof or a multi-layer thereof. For example, although a single-layer gate 114 is shown, each gate 114 may include any number of liner layers, any number of work function adjustment layers, and fill materials. After filling the gate 114, a planarization process such as CMP may be performed to remove the excess portions of the gate dielectric 112 and the material of the gate 114 that are above the top surface of the first ILD layer 102.The excess portions of the materials of the gate 114 and the gate dielectric 112 thus form the replacement gate of the resulting FinFET. The metal gate 110 may also be referred to as a "gate stack" or a "replacement gate stack". The metal gate 110 may extend along the sidewalls of the channel region 58 of the fin 52.

[0107] The formation of the gate dielectric 112 in the regions 50N and 50P may occur simultaneously such that the gate dielectric 112 in each region is formed of the same material, and the formation of the gate 114 may occur simultaneously such that the gate 114 in each region is formed of the same material. In some embodiments, the gate dielectric 112 in each region may be formed by different processes such that the gate dielectric 112 may be different materials, and / or the gate 114 in each region may be formed by different processes such that the gate 114 may be different materials. When different processes are used, various masking steps may be used to mask and expose appropriate regions.

[0108] In Figure 9A and Figure 9B a contact opening 120 is formed through the first ILD layer 102 and the CESL 100, thereby exposing the epitaxial source / drain region 70. Suitable lithography and etching techniques may be used to form the contact opening 120. In some embodiments, some loss of the epitaxial source / drain region 70 may be achieved due to, for example, over-etching to etch the contact opening 120. However, although the epitaxial source / drain regions 70 according to various embodiments have a large dopant concentration near the surfaces of the epitaxial source / drain regions 70, the dopants do not segregate to the surfaces of the epitaxial source / drain regions 70. Thus, even if some of the epitaxial source / drain region 70 is lost, a high doping concentration can still be achieved, which can reduce the contact resistance to the epitaxial source / drain region 70.

[0109] Then, a silicide 122 is formed on the portions of the epitaxial source / drain region 70 exposed by the contact opening 120 and in the contact opening 120. The silicide 122 may be formed by depositing a metal in the contact opening 120 and annealing. The metal may be, for example, titanium or cobalt, which may form the silicide 122 of TiSi2 or CoSi2, respectively. Since the epitaxial source / drain regions 70 have a large dopant concentration near their respective surfaces, the silicide 122 includes one or more dopants (e.g., gallium and boron when present) of the epitaxial source / drain region 70. The silicide 122 physically and electrically couples to the epitaxial source / drain region 70.

[0110] In some embodiments, a silicide pre-clean of the epitaxial source / drain region 70 may be performed before forming the silicide 122. For example, when etching the contact opening 120, a native oxide may form on the surface of the epitaxial source / drain region 70. The pre-silicide clean may be, for example, a wet clean to remove fluoride and native oxide from the surface of the epitaxial source / drain region 70. Gallium-rich native oxides (e.g., Ga2O3) and fluorides (e.g., GaF3) are not volatile and are difficult to remove. By avoiding dopant segregation to the surface of the epitaxial source / drain region 70, the formation of gallium-rich native oxides on the surface of the epitaxial source / drain region 70 can be avoided, and the native oxides on the epitaxial source / drain region 70 and the native oxides on the epitaxial source / drain region 70 can be more easily removed.

[0111] In Figure 10A and Figure 10B , the lower source / drain contact 124 is formed in the contact opening 120. A liner layer (e.g., a diffusion barrier layer, an adhesion layer, etc.) and a conductive material are formed in the contact opening 120, on the silicide 122. The liner may include titanium, titanium nitride, tantalum, tantalum nitride, or the like. The conductive material may be copper, a copper alloy, silver, gold, tungsten, cobalt, aluminum, nickel, or the like. A planarization process such as CMP may be performed to remove excess material from the surface of the first ILD layer 102. The remaining liner and conductive material form the lower source / drain contact 124 in the contact opening 120. The lower source / drain contact 124 is physically and electrically coupled to the epitaxial source / drain region 70.

[0112] In Figure 11A and Figure 11B , a second ILD layer 130 is deposited over the first ILD layer 102 and the lower source / drain contact 124. In some embodiments, the second ILD layer 130 is a flowable film formed by a flowable CVD method. In some embodiments, the second ILD layer 130 is formed of a dielectric material such as PSG, BSG, BPSG, USG, or the like, and may be deposited by any suitable method such as CVD and PECVD. According to some embodiments, before forming the second ILD layer 130, the metal gate 110 may be recessed such that a recess is formed between directly above the metal gate 110 and the opposing portions of the gate spacers 66. The recess is filled with a gate mask 132 including one or more layers of dielectric material (e.g., silicon nitride, silicon oxynitride, or the like), and then a planarization process is performed to remove the excess dielectric material extending over the first ILD layer 102.

[0113] In Figure 12A and Figure 12BIn [description], the gate contact 134 and the upper source / drain contact 136 are formed through the second ILD layer 130. Openings for the gate contact 134 and the upper source / drain contact 136 are formed through the second ILD layer 130. Suitable lithography and etching techniques can be used to form the openings. Liners such as diffusion barrier layers, adhesion layers or the like and conductive materials are formed in the openings. The liner may include titanium, titanium nitride, tantalum, tantalum nitride or the like. The conductive material can be copper, copper alloy, silver, gold, tungsten, cobalt, aluminum, nickel or the like. A planarization process such as CMP can be performed to remove the excess material from the surface of the second ILD layer 130. The remaining liner and conductive material form the gate contact 134 and the upper source / drain contact 136 in the openings. The upper source / drain contact 136 is physically and electrically coupled to the lower source / drain contact 124, and the gate contact 134 is physically and electrically coupled to the metal gate 110. The gate contact 134 can penetrate the gate photomask 132 (if present). The gate contact 134 and the upper source / drain contact 136 can be formed by different processes, or can be formed by the same process. Each of the gate contact 134 and the upper source / drain contact 136 can be formed with a different cross-section, which can avoid short circuits of the contacts.

[0114] Embodiments can achieve advantages. Doping the epitaxial source / drain region 70 with an impurity such as gallium can increase the number of holes in the source / drain region, which may be particularly advantageous for certain types of source / drain regions such as p-type source / drain regions. Forming the epitaxial source / drain region 70 using the epitaxial growth process described herein can help the epitaxial source / drain region 70 have a large dopant concentration near the surface of the epitaxial source / drain region 70 without completely segregating the dopant onto the surface of the epitaxial source / drain region 70. Thus, gallium can be avoided from being removed during the etching process for forming the contact opening 120, and the contact resistance with the epitaxial source / drain region 70 can be reduced by forming the silicide 122 in the gallium-rich region. In addition, doping the epitaxial source / drain region 70 during growth rather than by implantation can avoid stress relaxation in the channel region 58 during dopant implantation. Thereby, the performance of the resulting FinFET can be improved.

[0115] In one embodiment, a structure includes: a semiconductor substrate having a channel region; and a semiconductor substrate having a channel region. A gate stack above the channel region; and an epitaxial source / drain region adjacent to the gate stack, the epitaxial source / drain region including: a main portion in the semiconductor substrate, the main portion including a semiconductor material doped with gallium, a first concentration of gallium in the main portion being less than the solid solubility of gallium in the semiconductor material; a terminal portion on the main portion, the terminal portion being doped with gallium, a second concentration of gallium in the terminal portion being greater than the solid solubility of gallium in the semiconductor material.

[0116] In some embodiments of the structure, the main portion has a first thickness, the terminal portion has a second thickness, and the second thickness is less than the first thickness. In some embodiments of the structure, the main portion includes a first layer of silicon germanium doped with gallium to a first concentration, and the terminal portion includes a second layer of silicon germanium doped with a second concentration of gallium. In some embodiments of the structure, the main portion includes a first layer of silicon germanium doped with gallium to a first concentration, and the terminal portion includes a plurality of second layers of silicon germanium doped with a second concentration of gallium. In some embodiments of the structure, each of the plurality of second layers has the same crystal structure. In some embodiments of the structure, each of the plurality of second layers alternates between having a first crystal structure or a second crystal structure, the first crystal structure being different from the second crystal structure. In some embodiments of the structure, the main portion includes a layer of silicon germanium doped with gallium, and the terminal portion includes alternating layers of silicon doped with gallium and germanium doped with gallium, the silicon layer being doped with more gallium than the germanium layer. In some embodiments of the structure, the epitaxial source / drain region has a facet that laterally extends beyond the sidewall of the semiconductor substrate. In some embodiments, the structure further includes: an interlayer dielectric (ILD) layer over the epitaxial source / drain region; and a source / drain contact extending through the ILD layer; a silicide disposed between the source / drain contact and the terminal portion, the silicide including gallium.

[0117] In one embodiment, a method includes: forming a gate stack on a fin; etching the fin to form a recess in the fin adjacent to the gate stack; dispensing an epitaxial precursor during a first growth stage to form a first portion of an epitaxial source / drain region in the recess, the epitaxial precursor including a semiconductor material precursor and a gallium precursor, dispensing the gallium precursor at a first flow rate during the first growth stage; dispensing the epitaxial precursor during a second growth stage to form a second portion of the epitaxial source / drain region over the first portion of the epitaxial source / drain region, dispensing the gallium precursor at a second flow rate during the second growth stage, the second flow rate being greater than the first flow rate.

[0118] In some embodiments of the method, the first portion includes a first layer of semiconductor material doped with gallium to a first concentration, and the second portion includes a second layer of semiconductor material doped with gallium to a second concentration, the first concentration being less than the solid solubility of gallium in the semiconductor material and the second concentration being greater than the solid solubility of gallium in the semiconductor material. In some embodiments of the method, the first portion includes a first layer of semiconductor material doped with gallium to a first concentration, and during the second growth stage, the epitaxial precursor dispensing includes: dispensing the epitaxial precursor during the second growth stage to form a plurality of second layers on the first layer. In some embodiments, the method further includes: growing a first subset of the plurality of second layers at a first temperature during the second growth stage; growing a second subset of the plurality of second layers at a second temperature during the second growth stage, the second temperature being greater than the first temperature. In some embodiments of the method, the first layer includes silicon germanium doped with gallium to the first concentration, wherein the first subset of the plurality of second layers includes germanium doped with gallium to the second concentration, and wherein the plurality of second layers includes silicon doped with gallium to a third concentration, the third concentration being greater than the second concentration and the second concentration being greater than the first concentration. In some embodiments of the method, the epitaxial precursor further includes a boron precursor. In some embodiments, the method further includes: depositing an interlayer dielectric (ILD) layer over the epitaxial source / drain regions; etching an opening in the ILD layer that exposes a second portion of the epitaxial source / drain regions; forming a silicide including gallium in the opening and the second portion of the epitaxial source / drain regions; and forming source / drain contacts over the opening and the silicide.

[0119] In one embodiment, a method includes: forming a gate stack over a fin; etching the fin to form a recess in the fin between adjacent gate stacks; dispensing a semiconductor material precursor to form a first epitaxial layer in the recess; after dispensing the semiconductor material precursor, dispensing a dopant precursor to form an impurity layer over the first epitaxial layer; after dispensing the dopant precursor, redispensing the semiconductor material precursor to form a second epitaxial layer over the impurity layer; and annealing to diffuse at least a portion of the impurity layer into the first epitaxial layer and the second epitaxial layer.

[0120] In some embodiments of the method, the semiconductor material precursor includes germane, the dopant precursor is gallium chloride, and after dispensing the dopant precursor, the impurity layer includes a gallium monolayer terminated with chlorine. In some embodiments, the method further includes: dispensing a reducing agent over the impurity layer after dispensing the dopant precursor and before resuming dispensing of the semiconductor material precursor, the reducing agent removing chlorine from the gallium monolayer. In some embodiments of the method, resuming dispensing of the semiconductor material precursor includes dispensing the reducing agent and the semiconductor material precursor simultaneously, the reducing agent removing chlorine from the gallium monolayer.

[0121] The foregoing has outlined the features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they can readily use the present disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or achieve the same advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructs do not depart from the spirit and scope of the present disclosure, and that various changes, substitutions, and alterations can be made herein without departing from the spirit and scope of the present disclosure.

Claims

1. A semiconductor device, characterized in that, Comprising: A semiconductor substrate having a channel region; A gate stack located over the channel region; And An epitaxial source / drain region adjacent to the gate stack, the epitaxial source / drain region comprising: A main portion located in the semiconductor substrate, the main portion comprising a semiconductor material doped with gallium, a first concentration of gallium in the main portion being less than the solid solubility of gallium in the semiconductor material, wherein the main portion is further doped with boron to a third concentration, the first concentration being less than the third concentration; and A terminal portion located above the main portion, the terminal portion being doped with gallium, a second concentration of gallium in the terminal portion being greater than the solid solubility of gallium in the semiconductor material, wherein the main portion has a first thickness, the terminal portion has a second thickness, and the second thickness of the terminal portion is less than the first thickness of the main portion, and wherein a top surface of the terminal portion is directly above a top surface of the main portion.

2. The semiconductor device according to claim 1, wherein, The second thickness of the terminal portion is in the range of 2 nm to 12 nm.

3. The semiconductor element according to claim 1, wherein, Wherein the main portion comprises a first layer of silicon germanium doped with gallium to the first concentration and doped with boron to the third concentration, and wherein the terminal portion comprises a second layer of silicon germanium doped with gallium to the second concentration.

4. The semiconductor device according to claim 1, characterized in that, Wherein the main portion comprises a first layer of silicon germanium doped with gallium to the first concentration and doped with boron to the third concentration, and wherein the terminal portion comprises a plurality of second layers of silicon germanium doped with gallium to the second concentration.

5. The semiconductor device according to claim 4, wherein Each of the plurality of second layers has the same crystal structure.

6. The semiconductor device according to claim 4, characterized in that, Wherein the plurality of second layers alternate between having a first crystal structure or a second crystal structure, the first crystal structure being different from the second crystal structure.

7. The semiconductor device according to claim 1, wherein, The main portion comprises a silicon germanium layer doped with gallium and boron, and the terminal portion comprises a plurality of silicon layers doped with gallium and a plurality of germanium layers doped with gallium, the plurality of silicon layers being doped with more gallium than the plurality of germanium layers.

8. The semiconductor device according to claim 1, wherein The epitaxial source / drain region has a plurality of facets that laterally extend beyond a plurality of sidewalls of the semiconductor substrate.

9. The semiconductor device according to claim 1, the semiconductor device comprising: An interlayer dielectric layer over the epitaxial source / drain region; A source / drain contact extending through the interlayer dielectric layer; And a silicide disposed between the source / drain contact and the terminal portion, the silicide comprising gallium.

10. A method for manufacturing a semiconductor device, characterized in that, Comprising: Forming a gate stack on a fin; Etching the fin to form a recess in the fin adjacent to the gate stack; Dispensing a plurality of epitaxial precursors during a first growth stage to form a first portion of an epitaxial source / drain region in the recess, the epitaxial precursors comprising a semiconductor material precursor and a gallium precursor, dispensing the gallium precursor at a first flow rate during the first growth stage, wherein the first portion comprises a semiconductor material doped with gallium and the semiconductor material is doped with gallium to a first concentration, the first concentration being less than the solid solubility of gallium in the semiconductor material; and During a second growth stage, dispense the plurality of epitaxial precursors to form a second portion of the epitaxial source / drain region over the first portion of the epitaxial source / drain region. During the second growth stage, dispense the gallium precursor at a second flow rate that is greater than the first flow rate. The second portion includes the semiconductor material doped with gallium to a second concentration that is greater than the solid solubility of gallium in the semiconductor material. The first portion has a first thickness, the second portion has a second thickness, and the second thickness of the second portion is less than the first thickness of the first portion.

11. The manufacturing method of the semiconductor device according to claim 10, characterized in that, The first portion includes a first layer that includes silicon germanium doped with gallium to the first concentration, and the second portion includes a second layer that includes silicon germanium doped with gallium to the second concentration.

12. The manufacturing method of the semiconductor device according to claim 10, characterized in that, The first portion includes a first layer of the semiconductor material doped with gallium to the first concentration, and dispensing the plurality of epitaxial precursors during the second growth stage includes: During the second growth stage, dispense the plurality of epitaxial precursors to form a plurality of second layers over the first layer.

13. The manufacturing method of the semiconductor device according to claim 12, wherein, The method further includes: during the second growth stage, grow a first subset of the plurality of second layers at a first temperature; during the second growth stage, grow a second subset of the plurality of second layers at a second temperature that is greater than the first temperature.

14. The manufacturing method of the semiconductor element according to claim 12, characterized in that, The first layer includes silicon germanium doped with gallium to the first concentration, a first subset of the plurality of second layers includes germanium doped with gallium to the second concentration, and the plurality of second layers includes silicon doped with gallium to a third concentration that is greater than the second concentration.

15. The manufacturing method of the semiconductor element according to claim 10, characterized in that, The plurality of epitaxial precursors further includes a boron precursor.

16. The manufacturing method of the semiconductor element according to claim 10, characterized in that, Further includes: Deposit an interlayer dielectric layer over the epitaxial source / drain region; Etch an opening in the interlayer dielectric layer that exposes the second portion of the epitaxial source / drain region; Form a silicide in the opening and over the second portion of the epitaxial source / drain region, the silicide including gallium; and Form a source / drain contact in the opening and over the silicide.

17. A method for manufacturing a semiconductor device, characterized in that, Includes: Form a gate stack on a fin; Etch the fin to form a recess in the fin adjacent to the gate stack; Dispense a plurality of semiconductor material precursors to form a first epitaxial layer in the recess; After dispensing the plurality of semiconductor material precursors, dispense a dopant precursor to form an impurity layer over the first epitaxial layer; After dispensing the dopant precursor, re-dispense the plurality of semiconductor material precursors to form a second epitaxial layer over the impurity layer; And Annealing is performed to diffuse at least a portion of the impurity layer into the first epitaxial layer and the second epitaxial layer, wherein the first epitaxial layer comprises a semiconductor material doped with gallium and the semiconductor material is doped with gallium to a first concentration, the second epitaxial layer comprises the semiconductor material doped with gallium to a second concentration, the first concentration is less than the solid solubility of gallium in the semiconductor material, the second concentration is greater than the solid solubility of gallium in the semiconductor material, wherein the first epitaxial layer has a first thickness, the second epitaxial layer has a second thickness, and the second thickness of the second epitaxial layer is less than the first thickness of the first epitaxial layer.

18. The method for manufacturing a semiconductor device according to claim 17, wherein, Wherein the plurality of semiconductor material precursors includes germane, wherein the dopant precursor is gallium chloride, and wherein after dispensing the dopant precursor, the impurity layer comprises a gallium monolayer terminated with chlorine.

19. The manufacturing method of the semiconductor device according to claim 18, characterized in that, The method further comprises: after dispensing the dopant precursor and before resuming dispensing of the plurality of semiconductor material precursors, dispensing a reducing agent on the impurity layer, the reducing agent removing the chlorine from the gallium monolayer.

20. The method for manufacturing a semiconductor device according to claim 18, characterized in that, Resuming dispensing of the plurality of semiconductor material precursors includes simultaneously dispensing a reducing agent and the plurality of semiconductor material precursors, the reducing agent removing the chlorine from the gallium monolayer.

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